Evan Cheng 1e249e3705 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8

2009-06-25 20:59:23 +00:00

..

Alpha

Fix Alpha test and support for private linkage.

2009-01-15 21:51:46 +00:00

ARM

ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.

2009-06-25 20:59:23 +00:00

CBackend

Fix an erroneous check for isFNeg; the FNeg case is handled

2009-06-04 23:43:29 +00:00

CellSPU

Add some generic expansion logic for SMULO and UMULO. Fixes UMULO

2009-06-16 06:58:29 +00:00

CPP

Fix code emission for conditional branches.

2009-05-04 19:10:38 +00:00

Generic

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

IA64

Add the private linkage.

2009-01-15 20:18:42 +00:00

Mips

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

MSP430

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

PowerPC

Add some generic expansion logic for SMULO and UMULO. Fixes UMULO

2009-06-16 06:58:29 +00:00

SPARC

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

Thumb

We should run these tests as well.

2009-06-24 21:36:26 +00:00

Thumb2

ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.

2009-06-25 20:59:23 +00:00

X86

unwind info not needed.

2009-06-24 19:48:04 +00:00

XCore

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00