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f6b47d2a4f
When we are scheduling the load and addi, if all other heuristic didn't take effect, we will try to schedule the addi before the load, to hide the latency, and avoid the true dependency added by RA. And this only take effects for Power9. Differential Revision: https://reviews.llvm.org/D61930 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361600 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
//===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCMachineScheduler.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
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cl::desc("Disable scheduling addi instruction before"
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"load for ppc"), cl::Hidden);
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bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone) const {
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if (DisableAddiLoadHeuristic)
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return false;
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auto isADDIInstr = [&] (const MachineInstr &Inst) {
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return Inst.getOpcode() == PPC::ADDI || Inst.getOpcode() == PPC::ADDI8;
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};
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SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
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SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
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if (isADDIInstr(*FirstCand.SU->getInstr()) &&
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SecondCand.SU->getInstr()->mayLoad()) {
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TryCand.Reason = Stall;
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return true;
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}
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if (FirstCand.SU->getInstr()->mayLoad() &&
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isADDIInstr(*SecondCand.SU->getInstr())) {
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TryCand.Reason = NoCand;
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return true;
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}
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return false;
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}
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void PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary *Zone) const {
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GenericScheduler::tryCandidate(Cand, TryCand, Zone);
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if (!Cand.isValid() || !Zone)
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return;
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// Add powerpc specific heuristic only when TryCand isn't selected or
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// selected as node order.
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if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
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return;
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// There are some benefits to schedule the ADDI before the load to hide the
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// latency, as RA may create a true dependency between the load and addi.
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if (biasAddiLoadCandidate(Cand, TryCand, *Zone))
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return;
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}
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void PPCPostRASchedStrategy::enterMBB(MachineBasicBlock *MBB) {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::enterMBB(MBB);
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}
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void PPCPostRASchedStrategy::leaveMBB() {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::leaveMBB();
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}
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void PPCPostRASchedStrategy::initialize(ScheduleDAGMI *Dag) {
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// Custom PPC PostRA specific initialization here.
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PostGenericScheduler::initialize(Dag);
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}
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SUnit *PPCPostRASchedStrategy::pickNode(bool &IsTopNode) {
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// Custom PPC PostRA specific scheduling here.
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return PostGenericScheduler::pickNode(IsTopNode);
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}
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