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c297159d2f
We still don't really have an equivalent of "AssertXExt" in DAG, so we don't exploit the guarantees on the receiving side yet, but this should produce conservatively correct code on iOS ABIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282069 91177308-0d34-0410-b5e6-96231b3b80d8
356 lines
12 KiB
C++
356 lines
12 KiB
C++
//===-- llvm/CodeGen/GlobalISel/MachineLegalizeHelper.cpp -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the MachineLegalizeHelper class to legalize
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/// individual instructions and the LegalizeMachineIR wrapper pass for the
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/// primary legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineLegalizeHelper.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineLegalizer.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <sstream>
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#define DEBUG_TYPE "legalize-mir"
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using namespace llvm;
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MachineLegalizeHelper::MachineLegalizeHelper(MachineFunction &MF)
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: MRI(MF.getRegInfo()) {
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MIRBuilder.setMF(MF);
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::legalizeInstrStep(MachineInstr &MI,
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const MachineLegalizer &Legalizer) {
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auto Action = Legalizer.getAction(MI, MRI);
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switch (std::get<0>(Action)) {
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case MachineLegalizer::Legal:
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return AlreadyLegal;
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case MachineLegalizer::Libcall:
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return libcall(MI);
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case MachineLegalizer::NarrowScalar:
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return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case MachineLegalizer::WidenScalar:
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return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case MachineLegalizer::Lower:
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return lower(MI, std::get<1>(Action), std::get<2>(Action));
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case MachineLegalizer::FewerElements:
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return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
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default:
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return UnableToLegalize;
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}
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::legalizeInstr(MachineInstr &MI,
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const MachineLegalizer &Legalizer) {
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SmallVector<MachineInstr *, 4> WorkList;
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MIRBuilder.recordInsertions(
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[&](MachineInstr *MI) { WorkList.push_back(MI); });
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WorkList.push_back(&MI);
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bool Changed = false;
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LegalizeResult Res;
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unsigned Idx = 0;
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do {
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Res = legalizeInstrStep(*WorkList[Idx], Legalizer);
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if (Res == UnableToLegalize) {
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MIRBuilder.stopRecordingInsertions();
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return UnableToLegalize;
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}
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Changed |= Res == Legalized;
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++Idx;
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} while (Idx < WorkList.size());
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MIRBuilder.stopRecordingInsertions();
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return Changed ? Legalized : AlreadyLegal;
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}
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void MachineLegalizeHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &VRegs) {
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unsigned Size = Ty.getSizeInBits();
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SmallVector<uint64_t, 4> Indexes;
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for (int i = 0; i < NumParts; ++i) {
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VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
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Indexes.push_back(i * Size);
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}
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MIRBuilder.buildExtract(VRegs, Indexes, Reg);
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::libcall(MachineInstr &MI) {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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unsigned Size = Ty.getSizeInBits();
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_FREM: {
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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Type *Ty = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
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auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
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auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
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const char *Name =
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TLI.getLibcallName(Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32);
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CLI.lowerCall(
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MIRBuilder, MachineOperand::CreateES(Name),
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{MI.getOperand(0).getReg(), Ty},
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{{MI.getOperand(1).getReg(), Ty}, {MI.getOperand(2).getReg(), Ty}});
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::narrowScalar(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD: {
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// Expand in terms of carry-setting/consuming G_ADDE instructions.
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
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NarrowTy.getSizeInBits();
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MIRBuilder.setInstr(MI);
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildConstant(CarryIn, 0);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
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Src2Regs[i], CarryIn);
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DstRegs.push_back(DstReg);
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Indexes.push_back(i * NarrowSize);
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CarryIn = CarryOut;
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy) {
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_MUL:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_XOR:
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case TargetOpcode::G_SUB: {
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
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MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(DstExt)
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.addUse(Src1Ext)
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.addUse(Src2Ext);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UDIV: {
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unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV
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? TargetOpcode::G_SEXT
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: TargetOpcode::G_ZEXT;
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unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
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MI.getOperand(1).getReg());
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unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
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MI.getOperand(2).getReg());
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unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(ResExt)
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.addUse(LHSExt)
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.addUse(RHSExt);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
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WideTy.getSizeInBits() &&
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"illegal to increase number of bytes loaded");
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
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**MI.memoperands_begin());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
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WideTy.getSizeInBits() &&
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"illegal to increase number of bytes modified by a store");
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(SrcExt, MI.getOperand(0).getReg());
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MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
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**MI.memoperands_begin());
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_CONSTANT: {
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildConstant(DstExt, MI.getOperand(1).getImm());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_FCONSTANT: {
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
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MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_BRCOND: {
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unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
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MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_ICMP: {
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assert(TypeIdx == 1 && "unable to legalize predicate");
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bool IsSigned = CmpInst::isSigned(
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
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unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
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if (IsSigned) {
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MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
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MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
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} else {
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MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
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MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
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}
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MIRBuilder.buildICmp(
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
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MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_GEP: {
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assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
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unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
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MI.getOperand(2).setReg(OffsetExt);
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return Legalized;
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}
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}
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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switch(MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_SREM:
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case TargetOpcode::G_UREM: {
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unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
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.addDef(QuotReg)
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.addUse(MI.getOperand(1).getReg())
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.addUse(MI.getOperand(2).getReg());
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unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
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MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
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ProdReg);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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MachineLegalizeHelper::LegalizeResult
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MachineLegalizeHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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unsigned DstReg = MI.getOperand(0).getReg();
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int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
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MIRBuilder.setInstr(MI);
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
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DstRegs.push_back(DstReg);
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Indexes.push_back(i * NarrowSize);
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}
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MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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