llvm/Disassembler at f759032ccd3709dcd7362b0ed51760ee4e47025a - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-01-11 23:16:20 +00:00

History

Tim Northover f52efce72d ARM: implement MRS/MSR (banked reg) system instructions.

These are system-only instructions for CPUs with virtualization
extensions, allowing a hypervisor easy access to all of the various
different AArch32 registers.

rdar://problem/17861345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-15 10:47:12 +00:00

AArch64

Condition codes AL and NV are invalid in the aliases that use

2014-06-10 13:11:35 +00:00

ARM

ARM: implement MRS/MSR (banked reg) system instructions.

2014-08-15 10:47:12 +00:00

Mips

[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions

2014-07-09 10:40:20 +00:00

PowerPC

Update disassembler test to check the full dccci/iccci form.