Martin Storsjo e9c83048fb [AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str ...

Differential Revision: https://reviews.llvm.org/D44355

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327316 91177308-0d34-0410-b5e6-96231b3b80d8

2018-03-12 18:47:43 +00:00

..

AArch64

[AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str

2018-03-12 18:47:43 +00:00

AMDGPU

[AMDGPU] Fix lowering enqueue kernel when kernel has no name

2018-03-12 16:34:06 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Fix for PR36577

2018-03-07 09:10:44 +00:00

AVR

[AVR] Remove the earlyclobber flag from LDDWRdYQ

2018-03-06 11:20:25 +00:00

BPF

bpf: New codegen testcases for 32-bit subregister support

2018-02-23 23:49:33 +00:00

Generic

Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""

2018-03-07 16:27:44 +00:00

Hexagon

[Hexagon] Fix typo in testcase

2018-03-12 18:29:47 +00:00

Inputs

…

Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[TLS] use emulated TLS if the target supports only this mode

2018-02-28 17:48:55 +00:00

MIR

[MIRParser] Accept overloaded intrinsic names w/o type suffixes

2018-02-28 23:51:49 +00:00

MSP430

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.

2018-03-01 22:32:25 +00:00

PowerPC

[PowerPC] fix tests to be independent of FP undef

2018-03-10 16:14:05 +00:00

RISCV

[RISCV] Update two tests after r326208

2018-02-28 08:20:47 +00:00

SPARC

Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"

2018-02-27 16:59:10 +00:00

SystemZ

[SystemZ] Fix test cases after r326613

2018-03-02 21:22:42 +00:00

Thumb

[ARM] Fix access to stack arguments when re-aligning SP in Armv6m

2018-03-02 15:47:14 +00:00

Thumb2

ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

2018-02-27 19:00:59 +00:00

WebAssembly

[WebAssembly] Add mechanisms for specifying an explicit import module name.

2018-02-09 23:13:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86][SSE] createVariablePermute - PSHUFB requires SSSE3 not just SSE3

2018-03-12 12:30:04 +00:00

XCore

[XCore] Return true in enableMultipleCopyHints().

2018-02-26 08:03:32 +00:00