Bill Wendling f88f21c5d4 Add another testcase for r71478. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73399 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-15 18:36:34 +00:00
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Alpha	Fix Alpha test and support for private linkage.	2009-01-15 21:51:46 +00:00
ARM	Part 1.	2009-06-15 08:28:29 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64	Add the private linkage.	2009-01-15 20:18:42 +00:00
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec	2009-06-07 01:07:55 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
X86	Add another testcase for r71478.	2009-06-15 18:36:34 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00