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7384652668
As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
559 lines
25 KiB
C++
559 lines
25 KiB
C++
//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Base ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <array>
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#include <cstdint>
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#define GET_INSTRINFO_HEADER
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#include "ARMGenInstrInfo.inc"
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namespace llvm {
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class ARMBaseRegisterInfo;
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class ARMSubtarget;
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class ARMBaseInstrInfo : public ARMGenInstrInfo {
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const ARMSubtarget &Subtarget;
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protected:
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// Can be only subclassed.
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explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
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unsigned LoadImmOpc, unsigned LoadOpc) const;
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/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
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/// and \p DefIdx.
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/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
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/// the list is modeled as <Reg:SubReg, SubIdx>.
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/// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
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/// two elements:
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/// - %1:sub1, sub0
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/// - %2<:0>, sub1
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///
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/// \returns true if it is possible to build such an input sequence
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/// with the pair \p MI, \p DefIdx. False otherwise.
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///
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/// \pre MI.isRegSequenceLike().
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bool getRegSequenceLikeInputs(
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const MachineInstr &MI, unsigned DefIdx,
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SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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/// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
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/// and \p DefIdx.
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/// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
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/// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
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/// - %1:sub1, sub0
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///
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/// \returns true if it is possible to build such an input sequence
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/// with the pair \p MI, \p DefIdx. False otherwise.
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///
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/// \pre MI.isExtractSubregLike().
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bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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RegSubRegPairAndIdx &InputReg) const override;
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/// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
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/// and \p DefIdx.
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/// \p [out] BaseReg and \p [out] InsertedReg contain
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/// the equivalent inputs of INSERT_SUBREG.
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/// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
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/// - BaseReg: %0:sub0
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/// - InsertedReg: %1:sub1, sub3
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///
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/// \returns true if it is possible to build such an input sequence
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/// with the pair \p MI, \p DefIdx. False otherwise.
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///
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/// \pre MI.isInsertSubregLike().
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bool
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getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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RegSubRegPair &BaseReg,
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RegSubRegPairAndIdx &InsertedReg) const override;
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/// Commutes the operands in the given instruction.
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/// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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///
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/// Do not call this method for a non-commutable instruction or for
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/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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/// Even though the instruction is commutable, the method may still
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/// fail to commute the operands, null pointer is returned in such cases.
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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public:
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// Return whether the target has an explicit NOP encoding.
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bool hasNOP() const;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineInstr &MI,
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LiveVariables *LV) const override;
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virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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const ARMSubtarget &getSubtarget() const { return Subtarget; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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const ScheduleDAG *DAG) const override;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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// Predication support.
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bool isPredicated(const MachineInstr &MI) const override;
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ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
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int PIdx = MI.findFirstPredOperandIdx();
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return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
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: ARMCC::AL;
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}
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Pred) const override;
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool DefinesPredicate(MachineInstr &MI,
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std::vector<MachineOperand> &Pred) const override;
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bool isPredicable(const MachineInstr &MI) const override;
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// CPSR defined in instruction
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static bool isCPSRDefined(const MachineInstr &MI);
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bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
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bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
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// Load, scaled register offset
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bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
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// Load, scaled register offset, not plus LSL2
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bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
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// Minus reg for ldstso addr mode
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bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
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// Scaled register offset in address mode 2
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bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
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// Load multiple, base reg in list
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bool isLDMBaseRegInList(const MachineInstr &MI) const;
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// get LDM variable defs size
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unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool KillSrc,
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const ARMSubtarget &Subtarget) const;
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void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, bool KillSrc,
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const ARMSubtarget &Subtarget) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr &Orig,
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const TargetRegisterInfo &TRI) const override;
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MachineInstr &
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duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
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const MachineInstr &Orig) const override;
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const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) const;
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bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
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const MachineRegisterInfo *MRI) const override;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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/// determine if two loads are loading from the same base address. It should
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/// only return true if the base pointers are the same and the only
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/// differences between the two addresses is the offset. It also returns the
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/// offsets by reference.
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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int64_t &Offset2) const override;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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/// should be scheduled togther. On some targets if two loads are loading from
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/// addresses in the same cache line, it's better if they are scheduled
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/// together. This function takes two integers that represent the load offsets
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const override;
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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unsigned ExtraT, MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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BranchProbability Probability) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override {
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return NumCycles == 1;
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}
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction to set the zero flag so
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/// that we can remove a "comparison with zero"; Remove a redundant CMP
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/// instruction if the flags can be updated in the same way by an earlier
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/// instruction such as SUB.
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bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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bool analyzeSelect(const MachineInstr &MI,
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SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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unsigned &FalseOp, bool &Optimizable) const override;
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MachineInstr *optimizeSelect(MachineInstr &MI,
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SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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bool) const override;
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/// FoldImmediate - 'Reg' is known to be defined by a move immediate
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/// instruction, try to fold the immediate into the use instruction.
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const override;
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unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr &MI) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const override;
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/// VFP/NEON execution domains.
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std::pair<uint16_t, uint16_t>
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getExecutionDomain(const MachineInstr &MI) const override;
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void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
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unsigned
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getPartialRegUpdateClearance(const MachineInstr &, unsigned,
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const TargetRegisterInfo *) const override;
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void breakPartialRegDependency(MachineInstr &, unsigned,
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const TargetRegisterInfo *TRI) const override;
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/// Get the number of addresses by LDM or VLDM or zero for unknown.
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unsigned getNumLDMAddresses(const MachineInstr &MI) const;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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int getVLDMDefCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getLDMDefCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getVSTMUseCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &UseMCID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getSTMUseCycle(const InstrItineraryData *ItinData,
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const MCInstrDesc &UseMCID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MCInstrDesc &DefMCID,
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unsigned DefIdx, unsigned DefAlign,
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const MCInstrDesc &UseMCID,
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unsigned UseIdx, unsigned UseAlign) const;
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int getOperandLatencyImpl(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MCInstrDesc &DefMCID, unsigned DefAdj,
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const MachineOperand &DefMO, unsigned Reg,
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const MachineInstr &UseMI, unsigned UseIdx,
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const MCInstrDesc &UseMCID, unsigned UseAdj) const;
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unsigned getPredicationCost(const MachineInstr &MI) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const override;
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bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
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const MachineRegisterInfo *MRI,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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const MachineInstr &DefMI,
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unsigned DefIdx) const override;
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/// verifyInstruction - Perform target specific instruction verification.
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
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void expandMEMCPY(MachineBasicBlock::iterator) const;
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private:
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/// Modeling special VFP / NEON fp MLA / MLS hazards.
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/// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
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/// MLx table.
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DenseMap<unsigned, unsigned> MLxEntryMap;
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/// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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/// stalls when scheduled together with fp MLA / MLS opcodes.
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SmallSet<unsigned, 16> MLxHazardOpcodes;
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public:
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/// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
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/// instruction.
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bool isFpMLxInstruction(unsigned Opcode) const {
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return MLxEntryMap.count(Opcode);
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}
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/// isFpMLxInstruction - This version also returns the multiply opcode and the
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/// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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/// the MLX instructions with an extra lane operand.
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bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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unsigned &AddSubOpc, bool &NegAcc,
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bool &HasLane) const;
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/// canCauseFpMLxStall - Return true if an instruction of the specified opcode
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/// will cause stalls when scheduled after (within 4-cycle window) a fp
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/// MLA / MLS instruction.
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bool canCauseFpMLxStall(unsigned Opcode) const {
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return MLxHazardOpcodes.count(Opcode);
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}
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/// Returns true if the instruction has a shift by immediate that can be
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/// executed in one cycle less.
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bool isSwiftFastImmShift(const MachineInstr *MI) const;
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/// Returns predicate register associated with the given frame instruction.
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unsigned getFramePred(const MachineInstr &MI) const {
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assert(isFrameInstr(MI));
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// Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
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// - argument declared in the pattern:
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// 0 - frame size
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// 1 - arg of CALLSEQ_START/CALLSEQ_END
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// 2 - predicate code (like ARMCC::AL)
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// - added by predOps:
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// 3 - predicate reg
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return MI.getOperand(3).getReg();
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}
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};
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/// Get the operands corresponding to the given \p Pred value. By default, the
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/// predicate register is assumed to be 0 (no register), but you can pass in a
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/// \p PredReg if that is not the case.
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static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
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unsigned PredReg = 0) {
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return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
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MachineOperand::CreateReg(PredReg, false)}};
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}
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/// Get the operand corresponding to the conditional code result. By default,
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/// this is 0 (no register).
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static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
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return MachineOperand::CreateReg(CCReg, false);
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|
}
|
|
|
|
/// Get the operand corresponding to the conditional code result for Thumb1.
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/// This operand will always refer to CPSR and it will have the Define flag set.
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|
/// You can optionally set the Dead flag by means of \p isDead.
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|
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
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|
return MachineOperand::CreateReg(ARM::CPSR,
|
|
/*Define*/ true, /*Implicit*/ false,
|
|
/*Kill*/ false, isDead);
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|
}
|
|
|
|
static inline
|
|
bool isUncondBranchOpcode(int Opc) {
|
|
return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
|
|
}
|
|
|
|
static inline
|
|
bool isCondBranchOpcode(int Opc) {
|
|
return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
|
|
}
|
|
|
|
static inline bool isJumpTableBranchOpcode(int Opc) {
|
|
return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
|
|
Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
|
|
Opc == ARM::t2BR_JT;
|
|
}
|
|
|
|
static inline
|
|
bool isIndirectBranchOpcode(int Opc) {
|
|
return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
|
|
}
|
|
|
|
static inline bool isPopOpcode(int Opc) {
|
|
return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
|
|
Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
|
|
Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
|
|
}
|
|
|
|
static inline bool isPushOpcode(int Opc) {
|
|
return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
|
|
Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
|
|
}
|
|
|
|
/// getInstrPredicate - If instruction is predicated, returns its predicate
|
|
/// condition, otherwise returns AL. It also returns the condition code
|
|
/// register by reference.
|
|
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
|
|
|
|
unsigned getMatchingCondBranchOpcode(unsigned Opc);
|
|
|
|
/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
|
|
/// opcode of the SSA instruction representing the conditional MI.
|
|
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
|
|
MachineInstr *&MI,
|
|
const MachineRegisterInfo &MRI);
|
|
|
|
/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
|
|
/// the instruction is encoded with an 'S' bit is determined by the optional
|
|
/// CPSR def operand.
|
|
unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
|
|
|
|
/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
|
|
/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
|
|
/// code.
|
|
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
const DebugLoc &dl, unsigned DestReg,
|
|
unsigned BaseReg, int NumBytes,
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
|
|
|
|
void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
const DebugLoc &dl, unsigned DestReg,
|
|
unsigned BaseReg, int NumBytes,
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
|
|
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
const DebugLoc &dl, unsigned DestReg,
|
|
unsigned BaseReg, int NumBytes,
|
|
const TargetInstrInfo &TII,
|
|
const ARMBaseRegisterInfo &MRI,
|
|
unsigned MIFlags = 0);
|
|
|
|
/// Tries to add registers to the reglist of a given base-updating
|
|
/// push/pop instruction to adjust the stack by an additional
|
|
/// NumBytes. This can save a few bytes per function in code-size, but
|
|
/// obviously generates more memory traffic. As such, it only takes
|
|
/// effect in functions being optimised for size.
|
|
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
|
|
MachineFunction &MF, MachineInstr *MI,
|
|
unsigned NumBytes);
|
|
|
|
/// rewriteARMFrameIndex / rewriteT2FrameIndex -
|
|
/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
|
|
/// offset could not be handled directly in MI, and return the left-over
|
|
/// portion by reference.
|
|
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const ARMBaseInstrInfo &TII);
|
|
|
|
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const ARMBaseInstrInfo &TII);
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
|