Alex Bradbury d25fc4439d [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero ... c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320799 91177308-0d34-0410-b5e6-96231b3b80d8		2017-12-15 10:20:51 +00:00
..
AsmParser	[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero	2017-12-15 10:20:51 +00:00
Disassembler	[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention	2017-12-13 09:57:25 +00:00
InstPrinter	[RISCV] Enable emission of alias instructions by default	2017-12-15 09:47:01 +00:00
MCTargetDesc
TargetInfo
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td
RISCVInstrFormatsC.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools	2017-12-13 12:46:55 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoC.td	[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero	2017-12-15 10:20:51 +00:00
RISCVInstrInfoD.td	[RISCV] Implement floating point assembler pseudo instructions	2017-12-13 11:37:19 +00:00
RISCVInstrInfoF.td	[RISCV] Implement floating point assembler pseudo instructions	2017-12-13 11:37:19 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
RISCVISelLowering.h
RISCVMCInstLower.cpp
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVTargetMachine.cpp
RISCVTargetMachine.h