mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-27 21:00:01 -04:00
Matt Arsenault
75448f1d3b
We have a lot of operand definition work essentially producing every valid permutation of operands to workaround builiding operand lists based on the instruction features. Apparently tablegen already has a mostly undocumented operator to concat dags which simplies this. Convert one simple place to use this. The BUF instruction definitions have much more complicated logic that can be totally rewritten now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312822 91177308-0d34-0410-b5e6-96231b3b80d8
1043 lines
49 KiB
TableGen
1043 lines
49 KiB
TableGen
//===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def FLATAtomic : ComplexPattern<i64, 3, "SelectFlatAtomic", [], [], -10>;
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def FLATOffset : ComplexPattern<i64, 3, "SelectFlatOffset<false>", [], [], -10>;
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def FLATOffsetSigned : ComplexPattern<i64, 3, "SelectFlatOffset<true>", [], [], -10>;
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def FLATSignedAtomic : ComplexPattern<i64, 3, "SelectFlatAtomicSigned", [], [], -10>;
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//===----------------------------------------------------------------------===//
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// FLAT classes
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//===----------------------------------------------------------------------===//
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class FLAT_Pseudo<string opName, dag outs, dag ins,
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string asmOps, list<dag> pattern=[]> :
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InstSI<outs, ins, "", pattern>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let FLAT = 1;
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0;
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let SchedRW = [WriteVMEM];
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string Mnemonic = opName;
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string AsmOperands = asmOps;
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bits<1> is_flat_global = 0;
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bits<1> is_flat_scratch = 0;
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bits<1> has_vdst = 1;
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// We need to distinguish having saddr and enabling saddr because
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// saddr is only valid for scratch and global instructions. Pre-gfx9
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// these bits were reserved, so we also don't necessarily want to
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// set these bits to the disabled value for the original flat
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// segment instructions.
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bits<1> has_saddr = 0;
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bits<1> enabled_saddr = 0;
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bits<7> saddr_value = 0;
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bits<1> has_vaddr = 1;
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bits<1> has_data = 1;
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bits<1> has_glc = 1;
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bits<1> glcValue = 0;
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let SubtargetPredicate = !if(is_flat_global, HasFlatGlobalInsts,
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!if(is_flat_scratch, HasFlatScratchInsts, HasFlatAddressSpace));
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// TODO: M0 if it could possibly access LDS (before gfx9? only)?
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let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
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// Internally, FLAT instruction are executed as both an LDS and a
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// Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
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// and are not considered done until both have been decremented.
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let VM_CNT = 1;
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let LGKM_CNT = !if(!or(is_flat_global, is_flat_scratch), 0, 1);
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}
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class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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Enc64 {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let TSFlags = ps.TSFlags;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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// encoding fields
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> saddr;
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bits<8> vdst;
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bits<1> slc;
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bits<1> glc;
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// Only valid on gfx9
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bits<1> lds = 0; // XXX - What does this actually do?
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// Segment, 00=flat, 01=scratch, 10=global, 11=reserved
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bits<2> seg = !if(ps.is_flat_global, 0b10,
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!if(ps.is_flat_scratch, 0b01, 0));
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// Signed offset. Highest bit ignored for flat and treated as 12-bit
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// unsigned for flat acceses.
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bits<13> offset;
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bits<1> nv = 0; // XXX - What does this actually do?
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// We don't use tfe right now, and it was removed in gfx9.
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bits<1> tfe = 0;
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// Only valid on GFX9+
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let Inst{12-0} = offset;
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let Inst{13} = lds;
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let Inst{15-14} = seg;
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let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
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let Inst{17} = slc;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x37; // Encoding.
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let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
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let Inst{47-40} = !if(ps.has_data, vdata, ?);
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let Inst{54-48} = !if(ps.has_saddr, !if(ps.enabled_saddr, saddr, 0x7f), 0);
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// 54-48 is reserved.
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let Inst{55} = nv; // nv on GFX9+, TFE before.
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let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
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}
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// TODO: Is exec allowed for saddr? The disabled value 0x7f is the
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// same encoding value as exec_hi, so it isn't possible to use that if
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// saddr is 32-bit (which isn't handled here yet).
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
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bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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opName,
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(outs regClass:$vdst),
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!con(
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!con(
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!con((ins VReg_64:$vaddr),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
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(ins GLC:$glc, slc:$slc)),
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" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
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let has_data = 0;
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let mayLoad = 1;
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let has_saddr = HasSaddr;
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let enabled_saddr = EnableSaddr;
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let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
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let maybeAtomic = 1;
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}
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class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
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bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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opName,
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(outs),
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!con(
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!con(
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!con((ins VReg_64:$vaddr, vdataClass:$vdata),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
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(ins GLC:$glc, slc:$slc)),
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" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
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let mayLoad = 0;
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let mayStore = 1;
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let has_vdst = 0;
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let has_saddr = HasSaddr;
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let enabled_saddr = EnableSaddr;
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let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
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let maybeAtomic = 1;
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}
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multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass> {
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let is_flat_global = 1 in {
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def "" : FLAT_Load_Pseudo<opName, regClass, 1, 1>;
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def _SADDR : FLAT_Load_Pseudo<opName, regClass, 1, 1, 1>;
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}
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}
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multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
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let is_flat_global = 1 in {
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def "" : FLAT_Store_Pseudo<opName, regClass, 1, 1>;
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def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1, 1>;
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}
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}
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class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
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bit EnableSaddr = 0>: FLAT_Pseudo<
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opName,
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(outs regClass:$vdst),
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!if(EnableSaddr,
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(ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
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(ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc)),
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" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc"> {
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let has_data = 0;
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let mayLoad = 1;
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let has_saddr = 1;
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let enabled_saddr = EnableSaddr;
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let has_vaddr = !if(EnableSaddr, 0, 1);
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let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
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let maybeAtomic = 1;
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}
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class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo<
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opName,
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(outs),
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!if(EnableSaddr,
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(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
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(ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc)),
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" "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc"> {
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let mayLoad = 0;
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let mayStore = 1;
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let has_vdst = 0;
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let has_saddr = 1;
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let enabled_saddr = EnableSaddr;
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let has_vaddr = !if(EnableSaddr, 0, 1);
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let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
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let maybeAtomic = 1;
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}
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multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass> {
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let is_flat_scratch = 1 in {
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def "" : FLAT_Scratch_Load_Pseudo<opName, regClass>;
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def _SADDR : FLAT_Scratch_Load_Pseudo<opName, regClass, 1>;
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}
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}
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multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
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let is_flat_scratch = 1 in {
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def "" : FLAT_Scratch_Store_Pseudo<opName, regClass>;
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def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>;
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}
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}
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class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []> :
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FLAT_Pseudo<opName, outs, ins, asm, pattern> {
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let mayLoad = 1;
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let mayStore = 1;
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let has_glc = 0;
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let glcValue = 0;
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let has_vdst = 0;
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let maybeAtomic = 1;
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}
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class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []>
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: FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> {
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let hasPostISelHook = 1;
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let has_vdst = 1;
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let glcValue = 1;
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let PseudoInstr = NAME # "_RTN";
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}
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multiclass FLAT_Atomic_Pseudo<
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string opName,
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RegisterClass vdst_rc,
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
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" $vaddr, $vdata$offset$slc">,
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AtomicNoRet <opName, 0> {
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let PseudoInstr = NAME;
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}
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
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" $vdst, $vaddr, $vdata$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <opName, 1>;
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}
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multiclass FLAT_Global_Atomic_Pseudo<
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string opName,
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RegisterClass vdst_rc,
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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" $vaddr, $vdata, off$offset$slc">,
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AtomicNoRet <opName, 0> {
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let has_saddr = 1;
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let PseudoInstr = NAME;
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}
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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" $vdst, $vaddr, $vdata, off$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <opName, 1> {
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let has_saddr = 1;
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}
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def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
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" $vaddr, $vdata$saddr$offset$slc">,
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AtomicNoRet <opName#"_saddr", 0> {
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR";
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}
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def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
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" $vdst, $vaddr, $vdata$saddr$offset glc$slc">,
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AtomicNoRet <opName#"_saddr", 1> {
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR_RTN";
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}
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}
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class flat_binary_atomic_op<SDNode atomic_op> : PatFrag<
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(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.FLAT_ADDRESS;}]
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>;
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def atomic_cmp_swap_flat : flat_binary_atomic_op<AMDGPUatomic_cmp_swap>;
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def atomic_swap_flat : flat_binary_atomic_op<atomic_swap>;
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def atomic_add_flat : flat_binary_atomic_op<atomic_load_add>;
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def atomic_and_flat : flat_binary_atomic_op<atomic_load_and>;
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def atomic_max_flat : flat_binary_atomic_op<atomic_load_max>;
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def atomic_min_flat : flat_binary_atomic_op<atomic_load_min>;
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def atomic_or_flat : flat_binary_atomic_op<atomic_load_or>;
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def atomic_sub_flat : flat_binary_atomic_op<atomic_load_sub>;
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def atomic_umax_flat : flat_binary_atomic_op<atomic_load_umax>;
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def atomic_umin_flat : flat_binary_atomic_op<atomic_load_umin>;
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def atomic_xor_flat : flat_binary_atomic_op<atomic_load_xor>;
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def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>;
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def atomic_dec_flat : flat_binary_atomic_op<SIatomic_dec>;
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//===----------------------------------------------------------------------===//
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// Flat Instructions
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//===----------------------------------------------------------------------===//
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def FLAT_LOAD_UBYTE : FLAT_Load_Pseudo <"flat_load_ubyte", VGPR_32>;
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def FLAT_LOAD_SBYTE : FLAT_Load_Pseudo <"flat_load_sbyte", VGPR_32>;
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def FLAT_LOAD_USHORT : FLAT_Load_Pseudo <"flat_load_ushort", VGPR_32>;
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def FLAT_LOAD_SSHORT : FLAT_Load_Pseudo <"flat_load_sshort", VGPR_32>;
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def FLAT_LOAD_DWORD : FLAT_Load_Pseudo <"flat_load_dword", VGPR_32>;
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def FLAT_LOAD_DWORDX2 : FLAT_Load_Pseudo <"flat_load_dwordx2", VReg_64>;
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def FLAT_LOAD_DWORDX4 : FLAT_Load_Pseudo <"flat_load_dwordx4", VReg_128>;
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def FLAT_LOAD_DWORDX3 : FLAT_Load_Pseudo <"flat_load_dwordx3", VReg_96>;
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def FLAT_STORE_BYTE : FLAT_Store_Pseudo <"flat_store_byte", VGPR_32>;
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def FLAT_STORE_SHORT : FLAT_Store_Pseudo <"flat_store_short", VGPR_32>;
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def FLAT_STORE_DWORD : FLAT_Store_Pseudo <"flat_store_dword", VGPR_32>;
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def FLAT_STORE_DWORDX2 : FLAT_Store_Pseudo <"flat_store_dwordx2", VReg_64>;
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def FLAT_STORE_DWORDX4 : FLAT_Store_Pseudo <"flat_store_dwordx4", VReg_128>;
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def FLAT_STORE_DWORDX3 : FLAT_Store_Pseudo <"flat_store_dwordx3", VReg_96>;
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let SubtargetPredicate = HasD16LoadStore in {
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def FLAT_LOAD_UBYTE_D16 : FLAT_Load_Pseudo <"flat_load_ubyte_d16", VGPR_32>;
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def FLAT_LOAD_UBYTE_D16_HI : FLAT_Load_Pseudo <"flat_load_ubyte_d16_hi", VGPR_32>;
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def FLAT_LOAD_SBYTE_D16 : FLAT_Load_Pseudo <"flat_load_sbyte_d16", VGPR_32>;
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def FLAT_LOAD_SBYTE_D16_HI : FLAT_Load_Pseudo <"flat_load_sbyte_d16_hi", VGPR_32>;
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def FLAT_LOAD_SHORT_D16 : FLAT_Load_Pseudo <"flat_load_short_d16", VGPR_32>;
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def FLAT_LOAD_SHORT_D16_HI : FLAT_Load_Pseudo <"flat_load_short_d16_hi", VGPR_32>;
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def FLAT_STORE_BYTE_D16_HI : FLAT_Store_Pseudo <"flat_store_byte_d16_hi", VGPR_32>;
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def FLAT_STORE_SHORT_D16_HI : FLAT_Store_Pseudo <"flat_store_short_d16_hi", VGPR_32>;
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}
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defm FLAT_ATOMIC_CMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap",
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VGPR_32, i32, atomic_cmp_swap_flat,
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v2i32, VReg_64>;
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defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap_x2",
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VReg_64, i64, atomic_cmp_swap_flat,
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v2i64, VReg_128>;
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defm FLAT_ATOMIC_SWAP : FLAT_Atomic_Pseudo <"flat_atomic_swap",
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VGPR_32, i32, atomic_swap_flat>;
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defm FLAT_ATOMIC_SWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_swap_x2",
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VReg_64, i64, atomic_swap_flat>;
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defm FLAT_ATOMIC_ADD : FLAT_Atomic_Pseudo <"flat_atomic_add",
|
|
VGPR_32, i32, atomic_add_flat>;
|
|
|
|
defm FLAT_ATOMIC_SUB : FLAT_Atomic_Pseudo <"flat_atomic_sub",
|
|
VGPR_32, i32, atomic_sub_flat>;
|
|
|
|
defm FLAT_ATOMIC_SMIN : FLAT_Atomic_Pseudo <"flat_atomic_smin",
|
|
VGPR_32, i32, atomic_min_flat>;
|
|
|
|
defm FLAT_ATOMIC_UMIN : FLAT_Atomic_Pseudo <"flat_atomic_umin",
|
|
VGPR_32, i32, atomic_umin_flat>;
|
|
|
|
defm FLAT_ATOMIC_SMAX : FLAT_Atomic_Pseudo <"flat_atomic_smax",
|
|
VGPR_32, i32, atomic_max_flat>;
|
|
|
|
defm FLAT_ATOMIC_UMAX : FLAT_Atomic_Pseudo <"flat_atomic_umax",
|
|
VGPR_32, i32, atomic_umax_flat>;
|
|
|
|
defm FLAT_ATOMIC_AND : FLAT_Atomic_Pseudo <"flat_atomic_and",
|
|
VGPR_32, i32, atomic_and_flat>;
|
|
|
|
defm FLAT_ATOMIC_OR : FLAT_Atomic_Pseudo <"flat_atomic_or",
|
|
VGPR_32, i32, atomic_or_flat>;
|
|
|
|
defm FLAT_ATOMIC_XOR : FLAT_Atomic_Pseudo <"flat_atomic_xor",
|
|
VGPR_32, i32, atomic_xor_flat>;
|
|
|
|
defm FLAT_ATOMIC_INC : FLAT_Atomic_Pseudo <"flat_atomic_inc",
|
|
VGPR_32, i32, atomic_inc_flat>;
|
|
|
|
defm FLAT_ATOMIC_DEC : FLAT_Atomic_Pseudo <"flat_atomic_dec",
|
|
VGPR_32, i32, atomic_dec_flat>;
|
|
|
|
defm FLAT_ATOMIC_ADD_X2 : FLAT_Atomic_Pseudo <"flat_atomic_add_x2",
|
|
VReg_64, i64, atomic_add_flat>;
|
|
|
|
defm FLAT_ATOMIC_SUB_X2 : FLAT_Atomic_Pseudo <"flat_atomic_sub_x2",
|
|
VReg_64, i64, atomic_sub_flat>;
|
|
|
|
defm FLAT_ATOMIC_SMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smin_x2",
|
|
VReg_64, i64, atomic_min_flat>;
|
|
|
|
defm FLAT_ATOMIC_UMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umin_x2",
|
|
VReg_64, i64, atomic_umin_flat>;
|
|
|
|
defm FLAT_ATOMIC_SMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smax_x2",
|
|
VReg_64, i64, atomic_max_flat>;
|
|
|
|
defm FLAT_ATOMIC_UMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umax_x2",
|
|
VReg_64, i64, atomic_umax_flat>;
|
|
|
|
defm FLAT_ATOMIC_AND_X2 : FLAT_Atomic_Pseudo <"flat_atomic_and_x2",
|
|
VReg_64, i64, atomic_and_flat>;
|
|
|
|
defm FLAT_ATOMIC_OR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_or_x2",
|
|
VReg_64, i64, atomic_or_flat>;
|
|
|
|
defm FLAT_ATOMIC_XOR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_xor_x2",
|
|
VReg_64, i64, atomic_xor_flat>;
|
|
|
|
defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
|
|
VReg_64, i64, atomic_inc_flat>;
|
|
|
|
defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
|
|
VReg_64, i64, atomic_dec_flat>;
|
|
|
|
let SubtargetPredicate = isCI in { // CI Only flat instructions : FIXME Only?
|
|
|
|
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
|
|
VGPR_32, f32, null_frag, v2f32, VReg_64>;
|
|
|
|
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2",
|
|
VReg_64, f64, null_frag, v2f64, VReg_128>;
|
|
|
|
defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin",
|
|
VGPR_32, f32>;
|
|
|
|
defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
|
|
VGPR_32, f32>;
|
|
|
|
defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
|
|
VReg_64, f64>;
|
|
|
|
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
|
|
VReg_64, f64>;
|
|
|
|
} // End SubtargetPredicate = isCI
|
|
|
|
let SubtargetPredicate = HasFlatGlobalInsts in {
|
|
defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
|
|
defm GLOBAL_LOAD_SBYTE : FLAT_Global_Load_Pseudo <"global_load_sbyte", VGPR_32>;
|
|
defm GLOBAL_LOAD_USHORT : FLAT_Global_Load_Pseudo <"global_load_ushort", VGPR_32>;
|
|
defm GLOBAL_LOAD_SSHORT : FLAT_Global_Load_Pseudo <"global_load_sshort", VGPR_32>;
|
|
defm GLOBAL_LOAD_DWORD : FLAT_Global_Load_Pseudo <"global_load_dword", VGPR_32>;
|
|
defm GLOBAL_LOAD_DWORDX2 : FLAT_Global_Load_Pseudo <"global_load_dwordx2", VReg_64>;
|
|
defm GLOBAL_LOAD_DWORDX3 : FLAT_Global_Load_Pseudo <"global_load_dwordx3", VReg_96>;
|
|
defm GLOBAL_LOAD_DWORDX4 : FLAT_Global_Load_Pseudo <"global_load_dwordx4", VReg_128>;
|
|
|
|
defm GLOBAL_LOAD_UBYTE_D16 : FLAT_Global_Load_Pseudo <"global_load_ubyte_d16", VGPR_32>;
|
|
defm GLOBAL_LOAD_UBYTE_D16_HI : FLAT_Global_Load_Pseudo <"global_load_ubyte_d16_hi", VGPR_32>;
|
|
defm GLOBAL_LOAD_SBYTE_D16 : FLAT_Global_Load_Pseudo <"global_load_sbyte_d16", VGPR_32>;
|
|
defm GLOBAL_LOAD_SBYTE_D16_HI : FLAT_Global_Load_Pseudo <"global_load_sbyte_d16_hi", VGPR_32>;
|
|
defm GLOBAL_LOAD_SHORT_D16 : FLAT_Global_Load_Pseudo <"global_load_short_d16", VGPR_32>;
|
|
defm GLOBAL_LOAD_SHORT_D16_HI : FLAT_Global_Load_Pseudo <"global_load_short_d16_hi", VGPR_32>;
|
|
|
|
defm GLOBAL_STORE_BYTE : FLAT_Global_Store_Pseudo <"global_store_byte", VGPR_32>;
|
|
defm GLOBAL_STORE_SHORT : FLAT_Global_Store_Pseudo <"global_store_short", VGPR_32>;
|
|
defm GLOBAL_STORE_DWORD : FLAT_Global_Store_Pseudo <"global_store_dword", VGPR_32>;
|
|
defm GLOBAL_STORE_DWORDX2 : FLAT_Global_Store_Pseudo <"global_store_dwordx2", VReg_64>;
|
|
defm GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
|
|
defm GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
|
|
|
|
defm GLOBAL_STORE_BYTE_D16_HI : FLAT_Global_Store_Pseudo <"global_store_byte_d16_hi", VGPR_32>;
|
|
defm GLOBAL_STORE_SHORT_D16_HI : FLAT_Global_Store_Pseudo <"global_store_short_d16_hi", VGPR_32>;
|
|
|
|
let is_flat_global = 1 in {
|
|
defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap",
|
|
VGPR_32, i32, AMDGPUatomic_cmp_swap_global,
|
|
v2i32, VReg_64>;
|
|
|
|
defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap_x2",
|
|
VReg_64, i64, AMDGPUatomic_cmp_swap_global,
|
|
v2i64, VReg_128>;
|
|
|
|
defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_swap",
|
|
VGPR_32, i32, atomic_swap_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_swap_x2",
|
|
VReg_64, i64, atomic_swap_global>;
|
|
|
|
defm GLOBAL_ATOMIC_ADD : FLAT_Global_Atomic_Pseudo <"global_atomic_add",
|
|
VGPR_32, i32, atomic_add_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SUB : FLAT_Global_Atomic_Pseudo <"global_atomic_sub",
|
|
VGPR_32, i32, atomic_sub_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_smin",
|
|
VGPR_32, i32, atomic_min_global>;
|
|
|
|
defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_umin",
|
|
VGPR_32, i32, atomic_umin_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_smax",
|
|
VGPR_32, i32, atomic_max_global>;
|
|
|
|
defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_umax",
|
|
VGPR_32, i32, atomic_umax_global>;
|
|
|
|
defm GLOBAL_ATOMIC_AND : FLAT_Global_Atomic_Pseudo <"global_atomic_and",
|
|
VGPR_32, i32, atomic_and_global>;
|
|
|
|
defm GLOBAL_ATOMIC_OR : FLAT_Global_Atomic_Pseudo <"global_atomic_or",
|
|
VGPR_32, i32, atomic_or_global>;
|
|
|
|
defm GLOBAL_ATOMIC_XOR : FLAT_Global_Atomic_Pseudo <"global_atomic_xor",
|
|
VGPR_32, i32, atomic_xor_global>;
|
|
|
|
defm GLOBAL_ATOMIC_INC : FLAT_Global_Atomic_Pseudo <"global_atomic_inc",
|
|
VGPR_32, i32, atomic_inc_global>;
|
|
|
|
defm GLOBAL_ATOMIC_DEC : FLAT_Global_Atomic_Pseudo <"global_atomic_dec",
|
|
VGPR_32, i32, atomic_dec_global>;
|
|
|
|
defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_add_x2",
|
|
VReg_64, i64, atomic_add_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_sub_x2",
|
|
VReg_64, i64, atomic_sub_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smin_x2",
|
|
VReg_64, i64, atomic_min_global>;
|
|
|
|
defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umin_x2",
|
|
VReg_64, i64, atomic_umin_global>;
|
|
|
|
defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smax_x2",
|
|
VReg_64, i64, atomic_max_global>;
|
|
|
|
defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umax_x2",
|
|
VReg_64, i64, atomic_umax_global>;
|
|
|
|
defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_and_x2",
|
|
VReg_64, i64, atomic_and_global>;
|
|
|
|
defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_or_x2",
|
|
VReg_64, i64, atomic_or_global>;
|
|
|
|
defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_xor_x2",
|
|
VReg_64, i64, atomic_xor_global>;
|
|
|
|
defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_inc_x2",
|
|
VReg_64, i64, atomic_inc_global>;
|
|
|
|
defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_dec_x2",
|
|
VReg_64, i64, atomic_dec_global>;
|
|
} // End is_flat_global = 1
|
|
|
|
} // End SubtargetPredicate = HasFlatGlobalInsts
|
|
|
|
|
|
let SubtargetPredicate = HasFlatScratchInsts in {
|
|
defm SCRATCH_LOAD_UBYTE : FLAT_Scratch_Load_Pseudo <"scratch_load_ubyte", VGPR_32>;
|
|
defm SCRATCH_LOAD_SBYTE : FLAT_Scratch_Load_Pseudo <"scratch_load_sbyte", VGPR_32>;
|
|
defm SCRATCH_LOAD_USHORT : FLAT_Scratch_Load_Pseudo <"scratch_load_ushort", VGPR_32>;
|
|
defm SCRATCH_LOAD_SSHORT : FLAT_Scratch_Load_Pseudo <"scratch_load_sshort", VGPR_32>;
|
|
defm SCRATCH_LOAD_DWORD : FLAT_Scratch_Load_Pseudo <"scratch_load_dword", VGPR_32>;
|
|
defm SCRATCH_LOAD_DWORDX2 : FLAT_Scratch_Load_Pseudo <"scratch_load_dwordx2", VReg_64>;
|
|
defm SCRATCH_LOAD_DWORDX3 : FLAT_Scratch_Load_Pseudo <"scratch_load_dwordx3", VReg_96>;
|
|
defm SCRATCH_LOAD_DWORDX4 : FLAT_Scratch_Load_Pseudo <"scratch_load_dwordx4", VReg_128>;
|
|
|
|
defm SCRATCH_LOAD_UBYTE_D16 : FLAT_Scratch_Load_Pseudo <"scratch_load_ubyte_d16", VGPR_32>;
|
|
defm SCRATCH_LOAD_UBYTE_D16_HI : FLAT_Scratch_Load_Pseudo <"scratch_load_ubyte_d16_hi", VGPR_32>;
|
|
defm SCRATCH_LOAD_SBYTE_D16 : FLAT_Scratch_Load_Pseudo <"scratch_load_sbyte_d16", VGPR_32>;
|
|
defm SCRATCH_LOAD_SBYTE_D16_HI : FLAT_Scratch_Load_Pseudo <"scratch_load_sbyte_d16_hi", VGPR_32>;
|
|
defm SCRATCH_LOAD_SHORT_D16 : FLAT_Scratch_Load_Pseudo <"scratch_load_short_d16", VGPR_32>;
|
|
defm SCRATCH_LOAD_SHORT_D16_HI : FLAT_Scratch_Load_Pseudo <"scratch_load_short_d16_hi", VGPR_32>;
|
|
|
|
defm SCRATCH_STORE_BYTE : FLAT_Scratch_Store_Pseudo <"scratch_store_byte", VGPR_32>;
|
|
defm SCRATCH_STORE_SHORT : FLAT_Scratch_Store_Pseudo <"scratch_store_short", VGPR_32>;
|
|
defm SCRATCH_STORE_DWORD : FLAT_Scratch_Store_Pseudo <"scratch_store_dword", VGPR_32>;
|
|
defm SCRATCH_STORE_DWORDX2 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx2", VReg_64>;
|
|
defm SCRATCH_STORE_DWORDX3 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx3", VReg_96>;
|
|
defm SCRATCH_STORE_DWORDX4 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx4", VReg_128>;
|
|
|
|
defm SCRATCH_STORE_BYTE_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_byte_d16_hi", VGPR_32>;
|
|
defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_short_d16_hi", VGPR_32>;
|
|
|
|
} // End SubtargetPredicate = HasFlatScratchInsts
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Flat Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
|
|
(ld node:$ptr), [{
|
|
auto const AS = cast<MemSDNode>(N)->getAddressSpace();
|
|
return AS == AMDGPUASI.FLAT_ADDRESS ||
|
|
AS == AMDGPUASI.GLOBAL_ADDRESS ||
|
|
AS == AMDGPUASI.CONSTANT_ADDRESS;
|
|
}]>;
|
|
|
|
class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
auto const AS = cast<MemSDNode>(N)->getAddressSpace();
|
|
return AS == AMDGPUASI.FLAT_ADDRESS ||
|
|
AS == AMDGPUASI.GLOBAL_ADDRESS;
|
|
}]>;
|
|
|
|
def atomic_flat_load : flat_ld <atomic_load>;
|
|
def flat_load : flat_ld <load>;
|
|
def flat_az_extloadi8 : flat_ld <az_extloadi8>;
|
|
def flat_sextloadi8 : flat_ld <sextloadi8>;
|
|
def flat_az_extloadi16 : flat_ld <az_extloadi16>;
|
|
def flat_sextloadi16 : flat_ld <sextloadi16>;
|
|
|
|
def atomic_flat_store : flat_st <atomic_store>;
|
|
def flat_store : flat_st <store>;
|
|
def flat_truncstorei8 : flat_st <truncstorei8>;
|
|
def flat_truncstorei16 : flat_st <truncstorei16>;
|
|
|
|
// Patterns for global loads with no offset.
|
|
class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
(vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))),
|
|
(inst $vaddr, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
(vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))),
|
|
(inst $vaddr, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
(vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))),
|
|
(inst $vaddr, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
(node vt:$data, (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)),
|
|
(inst $vaddr, $data, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
(node vt:$data, (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)),
|
|
(inst $vaddr, $data, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
// atomic store follows atomic binop convention so the address comes
|
|
// first.
|
|
(node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data),
|
|
(inst $vaddr, $data, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatStoreSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
|
|
// atomic store follows atomic binop convention so the address comes
|
|
// first.
|
|
(node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data),
|
|
(inst $vaddr, $data, $offset, 0, $slc)
|
|
>;
|
|
|
|
class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
|
|
ValueType data_vt = vt> : Pat <
|
|
(vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),
|
|
(inst $vaddr, $data, $offset, $slc)
|
|
>;
|
|
|
|
class FlatSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
|
|
ValueType data_vt = vt> : Pat <
|
|
(vt (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),
|
|
(inst $vaddr, $data, $offset, $slc)
|
|
>;
|
|
|
|
let Predicates = [HasFlatAddressSpace] in {
|
|
|
|
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
|
|
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
|
|
def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_USHORT, flat_load, i16>;
|
|
def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_DWORDX2, flat_load, v2i32>;
|
|
def : FlatLoadPat <FLAT_LOAD_DWORDX4, flat_load, v4i32>;
|
|
|
|
def : FlatLoadAtomicPat <FLAT_LOAD_DWORD, atomic_flat_load, i32>;
|
|
def : FlatLoadAtomicPat <FLAT_LOAD_DWORDX2, atomic_flat_load, i64>;
|
|
|
|
def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i32>;
|
|
def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei16, i32>;
|
|
def : FlatStorePat <FLAT_STORE_DWORD, flat_store, i32>;
|
|
def : FlatStorePat <FLAT_STORE_DWORDX2, flat_store, v2i32>;
|
|
def : FlatStorePat <FLAT_STORE_DWORDX4, flat_store, v4i32>;
|
|
|
|
def : FlatStoreAtomicPat <FLAT_STORE_DWORD, atomic_flat_store, i32>;
|
|
def : FlatStoreAtomicPat <FLAT_STORE_DWORDX2, atomic_flat_store, i64>;
|
|
|
|
def : FlatAtomicPat <FLAT_ATOMIC_ADD_RTN, atomic_add_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_INC_RTN, atomic_inc_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_DEC_RTN, atomic_dec_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_AND_RTN, atomic_and_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_OR_RTN, atomic_or_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_RTN, AMDGPUatomic_cmp_swap_global, i32, v2i32>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
|
|
|
|
def : FlatAtomicPat <FLAT_ATOMIC_ADD_X2_RTN, atomic_add_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SUB_X2_RTN, atomic_sub_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_INC_X2_RTN, atomic_inc_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_DEC_X2_RTN, atomic_dec_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_AND_X2_RTN, atomic_and_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SMAX_X2_RTN, atomic_max_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
|
|
def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
|
|
|
|
def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;
|
|
def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
|
|
} // End Predicates = [HasFlatAddressSpace]
|
|
|
|
let Predicates = [HasFlatGlobalInsts], AddedComplexity = 10 in {
|
|
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i16>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i16>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_USHORT, az_extloadi16_global, i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_SSHORT, sextloadi16_global, i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_USHORT, global_load, i16>;
|
|
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_DWORD, global_load, i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_DWORDX2, global_load, v2i32>;
|
|
def : FlatLoadSignedPat <GLOBAL_LOAD_DWORDX4, global_load, v4i32>;
|
|
|
|
def : FlatLoadAtomicPat <GLOBAL_LOAD_DWORD, global_atomic_load, i32>;
|
|
def : FlatLoadAtomicPat <GLOBAL_LOAD_DWORDX2, global_atomic_load, i64>;
|
|
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_BYTE, truncstorei8_global, i32>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_BYTE, truncstorei8_global, i16>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_SHORT, truncstorei16_global, i32>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_SHORT, global_store, i16>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_DWORD, global_store, i32>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_DWORDX2, global_store, v2i32>;
|
|
def : FlatStoreSignedPat <GLOBAL_STORE_DWORDX4, global_store, v4i32>;
|
|
|
|
def : FlatStoreSignedAtomicPat <GLOBAL_STORE_DWORD, global_store_atomic, i32>;
|
|
def : FlatStoreSignedAtomicPat <GLOBAL_STORE_DWORDX2, global_store_atomic, i64>;
|
|
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_ADD_RTN, atomic_add_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_INC_RTN, atomic_inc_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_DEC_RTN, atomic_dec_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_AND_RTN, atomic_and_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_OR_RTN, atomic_or_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_CMPSWAP_RTN, AMDGPUatomic_cmp_swap_global, i32, v2i32>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
|
|
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_ADD_X2_RTN, atomic_add_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SUB_X2_RTN, atomic_sub_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_INC_X2_RTN, atomic_inc_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_DEC_X2_RTN, atomic_dec_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_AND_X2_RTN, atomic_and_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SMAX_X2_RTN, atomic_max_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
|
|
def : FlatSignedAtomicPat <GLOBAL_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
|
|
|
|
} // End Predicates = [HasFlatGlobalInsts]
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
|
|
FLAT_Real <op, ps>,
|
|
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
|
|
let AssemblerPredicate = isCIOnly;
|
|
let DecoderNamespace="CI";
|
|
}
|
|
|
|
def FLAT_LOAD_UBYTE_ci : FLAT_Real_ci <0x8, FLAT_LOAD_UBYTE>;
|
|
def FLAT_LOAD_SBYTE_ci : FLAT_Real_ci <0x9, FLAT_LOAD_SBYTE>;
|
|
def FLAT_LOAD_USHORT_ci : FLAT_Real_ci <0xa, FLAT_LOAD_USHORT>;
|
|
def FLAT_LOAD_SSHORT_ci : FLAT_Real_ci <0xb, FLAT_LOAD_SSHORT>;
|
|
def FLAT_LOAD_DWORD_ci : FLAT_Real_ci <0xc, FLAT_LOAD_DWORD>;
|
|
def FLAT_LOAD_DWORDX2_ci : FLAT_Real_ci <0xd, FLAT_LOAD_DWORDX2>;
|
|
def FLAT_LOAD_DWORDX4_ci : FLAT_Real_ci <0xe, FLAT_LOAD_DWORDX4>;
|
|
def FLAT_LOAD_DWORDX3_ci : FLAT_Real_ci <0xf, FLAT_LOAD_DWORDX3>;
|
|
|
|
def FLAT_STORE_BYTE_ci : FLAT_Real_ci <0x18, FLAT_STORE_BYTE>;
|
|
def FLAT_STORE_SHORT_ci : FLAT_Real_ci <0x1a, FLAT_STORE_SHORT>;
|
|
def FLAT_STORE_DWORD_ci : FLAT_Real_ci <0x1c, FLAT_STORE_DWORD>;
|
|
def FLAT_STORE_DWORDX2_ci : FLAT_Real_ci <0x1d, FLAT_STORE_DWORDX2>;
|
|
def FLAT_STORE_DWORDX4_ci : FLAT_Real_ci <0x1e, FLAT_STORE_DWORDX4>;
|
|
def FLAT_STORE_DWORDX3_ci : FLAT_Real_ci <0x1f, FLAT_STORE_DWORDX3>;
|
|
|
|
multiclass FLAT_Real_Atomics_ci <bits<7> op, FLAT_Pseudo ps> {
|
|
def _ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
|
|
def _RTN_ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
|
|
}
|
|
|
|
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_ci <0x30, FLAT_ATOMIC_SWAP>;
|
|
defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_ci <0x31, FLAT_ATOMIC_CMPSWAP>;
|
|
defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_ci <0x32, FLAT_ATOMIC_ADD>;
|
|
defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_ci <0x33, FLAT_ATOMIC_SUB>;
|
|
defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_ci <0x35, FLAT_ATOMIC_SMIN>;
|
|
defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_ci <0x36, FLAT_ATOMIC_UMIN>;
|
|
defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_ci <0x37, FLAT_ATOMIC_SMAX>;
|
|
defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_ci <0x38, FLAT_ATOMIC_UMAX>;
|
|
defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_ci <0x39, FLAT_ATOMIC_AND>;
|
|
defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_ci <0x3a, FLAT_ATOMIC_OR>;
|
|
defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_ci <0x3b, FLAT_ATOMIC_XOR>;
|
|
defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_ci <0x3c, FLAT_ATOMIC_INC>;
|
|
defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_ci <0x3d, FLAT_ATOMIC_DEC>;
|
|
defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_ci <0x50, FLAT_ATOMIC_SWAP_X2>;
|
|
defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_ci <0x51, FLAT_ATOMIC_CMPSWAP_X2>;
|
|
defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_ci <0x52, FLAT_ATOMIC_ADD_X2>;
|
|
defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_ci <0x53, FLAT_ATOMIC_SUB_X2>;
|
|
defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_ci <0x55, FLAT_ATOMIC_SMIN_X2>;
|
|
defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_ci <0x56, FLAT_ATOMIC_UMIN_X2>;
|
|
defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_ci <0x57, FLAT_ATOMIC_SMAX_X2>;
|
|
defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_ci <0x58, FLAT_ATOMIC_UMAX_X2>;
|
|
defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_ci <0x59, FLAT_ATOMIC_AND_X2>;
|
|
defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_ci <0x5a, FLAT_ATOMIC_OR_X2>;
|
|
defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_ci <0x5b, FLAT_ATOMIC_XOR_X2>;
|
|
defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_ci <0x5c, FLAT_ATOMIC_INC_X2>;
|
|
defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_ci <0x5d, FLAT_ATOMIC_DEC_X2>;
|
|
|
|
// CI Only flat instructions
|
|
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Real_Atomics_ci <0x3e, FLAT_ATOMIC_FCMPSWAP>;
|
|
defm FLAT_ATOMIC_FMIN : FLAT_Real_Atomics_ci <0x3f, FLAT_ATOMIC_FMIN>;
|
|
defm FLAT_ATOMIC_FMAX : FLAT_Real_Atomics_ci <0x40, FLAT_ATOMIC_FMAX>;
|
|
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Real_Atomics_ci <0x5e, FLAT_ATOMIC_FCMPSWAP_X2>;
|
|
defm FLAT_ATOMIC_FMIN_X2 : FLAT_Real_Atomics_ci <0x5f, FLAT_ATOMIC_FMIN_X2>;
|
|
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
|
|
FLAT_Real <op, ps>,
|
|
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
|
|
let AssemblerPredicate = isVI;
|
|
let DecoderNamespace="VI";
|
|
}
|
|
|
|
multiclass FLAT_Real_AllAddr_vi<bits<7> op> {
|
|
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME)>;
|
|
def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
|
|
}
|
|
|
|
def FLAT_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
|
|
def FLAT_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
|
|
def FLAT_LOAD_USHORT_vi : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
|
|
def FLAT_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
|
|
def FLAT_LOAD_DWORD_vi : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
|
|
def FLAT_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;
|
|
def FLAT_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, FLAT_LOAD_DWORDX4>;
|
|
def FLAT_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, FLAT_LOAD_DWORDX3>;
|
|
|
|
def FLAT_STORE_BYTE_vi : FLAT_Real_vi <0x18, FLAT_STORE_BYTE>;
|
|
def FLAT_STORE_BYTE_D16_HI_vi : FLAT_Real_vi <0x19, FLAT_STORE_BYTE_D16_HI>;
|
|
def FLAT_STORE_SHORT_vi : FLAT_Real_vi <0x1a, FLAT_STORE_SHORT>;
|
|
def FLAT_STORE_SHORT_D16_HI_vi : FLAT_Real_vi <0x1b, FLAT_STORE_SHORT_D16_HI>;
|
|
def FLAT_STORE_DWORD_vi : FLAT_Real_vi <0x1c, FLAT_STORE_DWORD>;
|
|
def FLAT_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, FLAT_STORE_DWORDX2>;
|
|
def FLAT_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
|
|
def FLAT_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
|
|
|
|
def FLAT_LOAD_UBYTE_D16_vi : FLAT_Real_vi <0x20, FLAT_LOAD_UBYTE_D16>;
|
|
def FLAT_LOAD_UBYTE_D16_HI_vi : FLAT_Real_vi <0x21, FLAT_LOAD_UBYTE_D16_HI>;
|
|
def FLAT_LOAD_SBYTE_D16_vi : FLAT_Real_vi <0x22, FLAT_LOAD_SBYTE_D16>;
|
|
def FLAT_LOAD_SBYTE_D16_HI_vi : FLAT_Real_vi <0x23, FLAT_LOAD_SBYTE_D16_HI>;
|
|
def FLAT_LOAD_SHORT_D16_vi : FLAT_Real_vi <0x24, FLAT_LOAD_SHORT_D16>;
|
|
def FLAT_LOAD_SHORT_D16_HI_vi : FLAT_Real_vi <0x25, FLAT_LOAD_SHORT_D16_HI>;
|
|
|
|
multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
|
|
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
|
|
def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
|
|
}
|
|
|
|
multiclass FLAT_Global_Real_Atomics_vi<bits<7> op> :
|
|
FLAT_Real_AllAddr_vi<op> {
|
|
def _RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
|
|
def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
|
|
}
|
|
|
|
|
|
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
|
|
defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
|
|
defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
|
|
defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
|
|
defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;
|
|
defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_vi <0x45, FLAT_ATOMIC_UMIN>;
|
|
defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_vi <0x46, FLAT_ATOMIC_SMAX>;
|
|
defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_vi <0x47, FLAT_ATOMIC_UMAX>;
|
|
defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_vi <0x48, FLAT_ATOMIC_AND>;
|
|
defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_vi <0x49, FLAT_ATOMIC_OR>;
|
|
defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_vi <0x4a, FLAT_ATOMIC_XOR>;
|
|
defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_vi <0x4b, FLAT_ATOMIC_INC>;
|
|
defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_vi <0x4c, FLAT_ATOMIC_DEC>;
|
|
defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_vi <0x60, FLAT_ATOMIC_SWAP_X2>;
|
|
defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_vi <0x61, FLAT_ATOMIC_CMPSWAP_X2>;
|
|
defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_vi <0x62, FLAT_ATOMIC_ADD_X2>;
|
|
defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_vi <0x63, FLAT_ATOMIC_SUB_X2>;
|
|
defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_vi <0x64, FLAT_ATOMIC_SMIN_X2>;
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defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_vi <0x65, FLAT_ATOMIC_UMIN_X2>;
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defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_vi <0x66, FLAT_ATOMIC_SMAX_X2>;
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defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_vi <0x67, FLAT_ATOMIC_UMAX_X2>;
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defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_vi <0x68, FLAT_ATOMIC_AND_X2>;
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defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_vi <0x69, FLAT_ATOMIC_OR_X2>;
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defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_vi <0x6a, FLAT_ATOMIC_XOR_X2>;
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defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_vi <0x6b, FLAT_ATOMIC_INC_X2>;
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defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_vi <0x6c, FLAT_ATOMIC_DEC_X2>;
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defm GLOBAL_LOAD_UBYTE : FLAT_Real_AllAddr_vi <0x10>;
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defm GLOBAL_LOAD_SBYTE : FLAT_Real_AllAddr_vi <0x11>;
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defm GLOBAL_LOAD_USHORT : FLAT_Real_AllAddr_vi <0x12>;
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defm GLOBAL_LOAD_SSHORT : FLAT_Real_AllAddr_vi <0x13>;
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defm GLOBAL_LOAD_DWORD : FLAT_Real_AllAddr_vi <0x14>;
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defm GLOBAL_LOAD_DWORDX2 : FLAT_Real_AllAddr_vi <0x15>;
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defm GLOBAL_LOAD_DWORDX3 : FLAT_Real_AllAddr_vi <0x16>;
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defm GLOBAL_LOAD_DWORDX4 : FLAT_Real_AllAddr_vi <0x17>;
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defm GLOBAL_LOAD_UBYTE_D16 : FLAT_Real_AllAddr_vi <0x20>;
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defm GLOBAL_LOAD_UBYTE_D16_HI : FLAT_Real_AllAddr_vi <0x21>;
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defm GLOBAL_LOAD_SBYTE_D16 : FLAT_Real_AllAddr_vi <0x22>;
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defm GLOBAL_LOAD_SBYTE_D16_HI : FLAT_Real_AllAddr_vi <0x23>;
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defm GLOBAL_LOAD_SHORT_D16 : FLAT_Real_AllAddr_vi <0x24>;
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defm GLOBAL_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x25>;
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defm GLOBAL_STORE_BYTE : FLAT_Real_AllAddr_vi <0x18>;
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defm GLOBAL_STORE_BYTE_D16_HI : FLAT_Real_AllAddr_vi <0x19>;
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defm GLOBAL_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>;
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defm GLOBAL_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x1b>;
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defm GLOBAL_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
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defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
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defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
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defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
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defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Real_Atomics_vi <0x40>;
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defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Real_Atomics_vi <0x41>;
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defm GLOBAL_ATOMIC_ADD : FLAT_Global_Real_Atomics_vi <0x42>;
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defm GLOBAL_ATOMIC_SUB : FLAT_Global_Real_Atomics_vi <0x43>;
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defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Real_Atomics_vi <0x44>;
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defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Real_Atomics_vi <0x45>;
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defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Real_Atomics_vi <0x46>;
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defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Real_Atomics_vi <0x47>;
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defm GLOBAL_ATOMIC_AND : FLAT_Global_Real_Atomics_vi <0x48>;
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defm GLOBAL_ATOMIC_OR : FLAT_Global_Real_Atomics_vi <0x49>;
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defm GLOBAL_ATOMIC_XOR : FLAT_Global_Real_Atomics_vi <0x4a>;
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defm GLOBAL_ATOMIC_INC : FLAT_Global_Real_Atomics_vi <0x4b>;
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defm GLOBAL_ATOMIC_DEC : FLAT_Global_Real_Atomics_vi <0x4c>;
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defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Real_Atomics_vi <0x60>;
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defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Real_Atomics_vi <0x61>;
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defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Real_Atomics_vi <0x62>;
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defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Real_Atomics_vi <0x63>;
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defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Real_Atomics_vi <0x64>;
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defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Real_Atomics_vi <0x65>;
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defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Real_Atomics_vi <0x66>;
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defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Real_Atomics_vi <0x67>;
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defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Real_Atomics_vi <0x68>;
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defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Real_Atomics_vi <0x69>;
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defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Real_Atomics_vi <0x6a>;
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defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Real_Atomics_vi <0x6b>;
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defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Real_Atomics_vi <0x6c>;
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defm SCRATCH_LOAD_UBYTE : FLAT_Real_AllAddr_vi <0x10>;
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defm SCRATCH_LOAD_SBYTE : FLAT_Real_AllAddr_vi <0x11>;
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defm SCRATCH_LOAD_USHORT : FLAT_Real_AllAddr_vi <0x12>;
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defm SCRATCH_LOAD_SSHORT : FLAT_Real_AllAddr_vi <0x13>;
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defm SCRATCH_LOAD_DWORD : FLAT_Real_AllAddr_vi <0x14>;
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defm SCRATCH_LOAD_DWORDX2 : FLAT_Real_AllAddr_vi <0x15>;
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defm SCRATCH_LOAD_DWORDX3 : FLAT_Real_AllAddr_vi <0x16>;
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defm SCRATCH_LOAD_DWORDX4 : FLAT_Real_AllAddr_vi <0x17>;
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defm SCRATCH_STORE_BYTE : FLAT_Real_AllAddr_vi <0x18>;
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defm SCRATCH_STORE_BYTE_D16_HI : FLAT_Real_AllAddr_vi <0x19>;
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defm SCRATCH_LOAD_UBYTE_D16 : FLAT_Real_AllAddr_vi <0x20>;
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defm SCRATCH_LOAD_UBYTE_D16_HI : FLAT_Real_AllAddr_vi <0x21>;
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defm SCRATCH_LOAD_SBYTE_D16 : FLAT_Real_AllAddr_vi <0x22>;
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defm SCRATCH_LOAD_SBYTE_D16_HI : FLAT_Real_AllAddr_vi <0x23>;
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defm SCRATCH_LOAD_SHORT_D16 : FLAT_Real_AllAddr_vi <0x24>;
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defm SCRATCH_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x25>;
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defm SCRATCH_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>;
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defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x1b>;
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defm SCRATCH_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
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defm SCRATCH_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
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defm SCRATCH_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
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defm SCRATCH_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
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