mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Matt Arsenault
2e48864110
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
7.2 KiB
LLVM
199 lines
7.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; Test that non-entry function frame indices are expanded properly to
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; give an index relative to the scratch wave offset register
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; Materialize into a mov. Make sure there isn't an unnecessary copy.
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; GCN-LABEL: {{^}}func_mov_fi_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN: s_sub_u32 s6, s5, s4
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; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
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; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_mov_fi_i32() #0 {
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%alloca = alloca i32
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store volatile i32* %alloca, i32* addrspace(3)* undef
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ret void
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}
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; Materialize into an add of a constant offset from the FI.
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; FIXME: Should be able to merge adds
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; GCN-LABEL: {{^}}func_add_constant_to_fi_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN: s_sub_u32 s6, s5, s4
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; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
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; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
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; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_add_constant_to_fi_i32() #0 {
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%alloca = alloca [2 x i32], align 4
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%gep0 = getelementptr inbounds [2 x i32], [2 x i32]* %alloca, i32 0, i32 1
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store volatile i32* %gep0, i32* addrspace(3)* undef
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ret void
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}
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; A user the materialized frame index can't be meaningfully folded
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; into.
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; GCN-LABEL: {{^}}func_other_fi_user_i32:
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; GCN: s_sub_u32 s6, s5, s4
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; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
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; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
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; GCN-NEXT: v_mul_lo_i32 v0, v0, 9
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_other_fi_user_i32() #0 {
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%alloca = alloca [2 x i32], align 4
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%ptrtoint = ptrtoint [2 x i32]* %alloca to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, i32 addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_store_private_arg_i32_ptr:
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; GCN: v_mov_b32_e32 v1, 15{{$}}
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; GCN: buffer_store_dword v1, v0, s[0:3], s4 offen{{$}}
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define void @func_store_private_arg_i32_ptr(i32* %ptr) #0 {
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store volatile i32 15, i32* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr:
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; GCN: s_waitcnt
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; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], s4 offen{{$}}
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define void @func_load_private_arg_i32_ptr(i32* %ptr) #0 {
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%val = load volatile i32, i32* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:
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; GCN: s_waitcnt
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4
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; GCN-NEXT: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6
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; GCN-NEXT: v_add_i32_e64 [[ADD:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]]
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; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, [[ADD]]
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 }* byval %arg0) #0 {
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%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1
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%load1 = load i32, i32* %gep1
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store volatile i32* %gep1, i32* addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_value:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s5, s32
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; GCN-NEXT: buffer_load_ubyte v0, off, s[0:3], s5
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; GCN_NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4
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define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 }* byval %arg0) #0 {
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%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1
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%load0 = load i8, i8* %gep0
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%load1 = load i32, i32* %gep1
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store volatile i8 %load0, i8 addrspace(3)* undef
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store volatile i32 %load1, i32 addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_nonentry_block:
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; GCN: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4
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; GCN: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6
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; GCN: v_add_i32_e64 [[ADD:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]]
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; GCN: s_and_saveexec_b64
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; GCN: v_add_i32_e32 v0, vcc, 4, [[ADD]]
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; GCN: buffer_load_dword v1, v1, s[0:3], s4 offen offset:4
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; GCN: ds_write_b32
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define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 }* byval %arg0, i32 %arg2) #0 {
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %bb, label %ret
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bb:
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%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1
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%load1 = load volatile i32, i32* %gep1
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store volatile i32* %gep1, i32* addrspace(3)* undef
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br label %ret
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ret:
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ret void
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}
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; Added offset can't be used with VOP3 add
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; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32:
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; GCN: s_sub_u32 s6, s5, s4
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; GCN-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
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; GCN-DAG: s_movk_i32 s6, 0x204
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; GCN: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]]
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; GCN: v_mul_lo_i32 v0, v0, 9
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; GCN: ds_write_b32 v0, v0
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define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
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%alloca0 = alloca [128 x i32], align 4
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%alloca1 = alloca [8 x i32], align 4
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%gep0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca0, i32 0, i32 65
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%gep1 = getelementptr inbounds [8 x i32], [8 x i32]* %alloca1, i32 0, i32 0
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store volatile i32 7, i32* %gep0
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%ptrtoint = ptrtoint i32* %gep1 to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, i32 addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live:
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; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4
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; GCN-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6
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; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204
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; GCN: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
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; GCN: v_mul_lo_i32 v0, v0, 9
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; GCN: ds_write_b32 v0, v0
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define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
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%alloca0 = alloca [128 x i32], align 4
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%alloca1 = alloca [8 x i32], align 4
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%vcc = call i64 asm sideeffect "; def $0", "={VCC}"()
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%gep0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca0, i32 0, i32 65
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%gep1 = getelementptr inbounds [8 x i32], [8 x i32]* %alloca1, i32 0, i32 0
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store volatile i32 7, i32* %gep0
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call void asm sideeffect "; use $0", "{VCC}"(i64 %vcc)
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%ptrtoint = ptrtoint i32* %gep1 to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, i32 addrspace(3)* undef
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ret void
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}
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declare void @func(<4 x float>* nocapture) #0
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; undef flag not preserved in eliminateFrameIndex when handling the
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; stores in the middle block.
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; GCN-LABEL: {{^}}undefined_stack_store_reg:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
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; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
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; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:
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define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
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bb:
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%tmp = alloca <4 x float>, align 16
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%tmp2 = insertelement <4 x float> undef, float %arg, i32 0
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store <4 x float> %tmp2, <4 x float>* undef
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%tmp3 = icmp eq i32 %arg1, 0
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br i1 %tmp3, label %bb4, label %bb5
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bb4:
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call void @func(<4 x float>* nonnull undef)
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store <4 x float> %tmp2, <4 x float>* %tmp, align 16
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call void @func(<4 x float>* nonnull %tmp)
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br label %bb5
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bb5:
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ret void
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}
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attributes #0 = { nounwind }
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