mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Diana Picus
a479e53b55
We lower to a sequence consisting of: - MOVi 0 into a register - VCMPS to do the actual comparison and set the VFP flags - FMSTAT to move the flags out of the VFP unit - MOVCCi to either use the "zero register" that we have previously set with the MOVi, or move 1 into the result register, based on the values of the flags As was the case with soft-float, for some predicates (one, ueq) we actually need two comparisons instead of just one. When that happens, we generate two VCMPS-FMSTAT-MOVCCi sequences and chain them by means of using the result of the first MOVCCi as the "zero register" for the second one. This is a bit overkill, since one comparison followed by two non-flag-setting conditional moves should be enough. In any case, the backend manages to CSE one of the comparisons away so it doesn't matter much. Note that unlike SelectionDAG and FastISel, we always use VCMPS, and not VCMPES. This makes the code a lot simpler, and it also seems correct since the LLVM Lang Ref defines simple true/false returns if the operands are QNaN's. For SNaN's, even VCMPS throws an Invalid Operand exception, so they won't be slipping through unnoticed. Implementation-wise, this introduces a template so we can share the same code that we use for handling integer comparisons, since the only differences are in the details (exact opcodes to be used etc). Hopefully this will be easy to extend to s64 G_FCMP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307365 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.4 KiB
LLVM
82 lines
2.4 KiB
LLVM
; RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
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; RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-AEABI
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; RUN: llc -mtriple arm-linux-gnu- -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-DEFAULT
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define arm_aapcscc float @test_frem_float(float %x, float %y) {
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; CHECK-LABEL: test_frem_float:
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; CHECK: blx fmodf
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%r = frem float %x, %y
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ret float %r
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}
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define arm_aapcscc double @test_frem_double(double %x, double %y) {
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; CHECK-LABEL: test_frem_double:
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; CHECK: blx fmod
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%r = frem double %x, %y
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ret double %r
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}
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declare float @llvm.pow.f32(float %x, float %y)
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define arm_aapcscc float @test_fpow_float(float %x, float %y) {
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; CHECK-LABEL: test_fpow_float:
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; CHECK: blx powf
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%r = call float @llvm.pow.f32(float %x, float %y)
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ret float %r
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}
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declare double @llvm.pow.f64(double %x, double %y)
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define arm_aapcscc double @test_fpow_double(double %x, double %y) {
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; CHECK-LABEL: test_fpow_double:
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; CHECK: blx pow
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%r = call double @llvm.pow.f64(double %x, double %y)
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ret double %r
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}
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define arm_aapcscc float @test_add_float(float %x, float %y) {
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; CHECK-LABEL: test_add_float:
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; HARD: vadd.f32
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; SOFT-AEABI: blx __aeabi_fadd
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; SOFT-DEFAULT: blx __addsf3
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%r = fadd float %x, %y
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ret float %r
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}
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define arm_aapcscc double @test_add_double(double %x, double %y) {
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; CHECK-LABEL: test_add_double:
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; HARD: vadd.f64
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; SOFT-AEABI: blx __aeabi_dadd
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; SOFT-DEFAULT: blx __adddf3
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%r = fadd double %x, %y
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ret double %r
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}
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define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) {
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; CHECK-LABEL: test_cmp_float_ogt
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; HARD: vcmp.f32
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; HARD: vmrs APSR_nzcv, fpscr
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; HARD-NEXT: movgt
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; SOFT-AEABI: blx __aeabi_fcmpgt
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; SOFT-DEFAULT: blx __gtsf2
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entry:
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%v = fcmp ogt float %x, %y
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) {
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; CHECK-LABEL: test_cmp_float_one
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; HARD: vcmp.f32
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; HARD: vmrs APSR_nzcv, fpscr
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; HARD: movgt
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; HARD-NOT: vcmp
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; HARD: movmi
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; SOFT-AEABI-DAG: blx __aeabi_fcmpgt
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; SOFT-AEABI-DAG: blx __aeabi_fcmplt
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; SOFT-DEFAULT-DAG: blx __gtsf2
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; SOFT-DEFAULT-DAG: blx __ltsf2
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entry:
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%v = fcmp one float %x, %y
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%r = zext i1 %v to i32
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ret i32 %r
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}
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