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https://github.com/RPCS3/llvm.git
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Igor Breger
54b8b993d1
Summary: Support vector type G_INSERT legalization/selection. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305989 91177308-0d34-0410-b5e6-96231b3b80d8
177 lines
5.8 KiB
YAML
177 lines
5.8 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
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--- |
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define void @test_insert_128_idx0() {
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ret void
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}
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define void @test_insert_128_idx0_undef() {
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ret void
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}
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define void @test_insert_128_idx1() {
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ret void
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}
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define void @test_insert_128_idx1_undef() {
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ret void
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}
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...
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---
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name: test_insert_128_idx0
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# ALL-LABEL: name: test_insert_128_idx0
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0 = COPY %ymm0
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# AVX-NEXT: %1 = COPY %xmm1
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# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 0
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# AVX-NEXT: %ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit %ymm0
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#
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# AVX512VL: %0 = COPY %ymm0
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# AVX512VL-NEXT: %1 = COPY %xmm1
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# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 0
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# AVX512VL-NEXT: %ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = COPY %ymm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_128_idx0_undef
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# ALL-LABEL: name: test_insert_128_idx0_undef
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %1 = COPY %xmm1
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# ALL-NEXT: undef %2.sub_xmm = COPY %1
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# ALL-NEXT: %ymm0 = COPY %2
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# ALL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_128_idx1
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# ALL-LABEL: name: test_insert_128_idx1
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0 = COPY %ymm0
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# AVX-NEXT: %1 = COPY %xmm1
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# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
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# AVX-NEXT: %ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit %ymm0
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#
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# AVX512VL: %0 = COPY %ymm0
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# AVX512VL-NEXT: %1 = COPY %xmm1
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# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
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# AVX512VL-NEXT: %ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = COPY %ymm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_128_idx1_undef
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# ALL-LABEL: name: test_insert_128_idx1_undef
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0 = IMPLICIT_DEF
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# AVX-NEXT: %1 = COPY %xmm1
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# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
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# AVX-NEXT: %ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit %ymm0
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#
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# AVX512VL: %0 = IMPLICIT_DEF
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# AVX512VL-NEXT: %1 = COPY %xmm1
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# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
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# AVX512VL-NEXT: %ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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