mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Gadi Haber
b123fd02f9
This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target. We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling. The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792. Information includes latency, number of micro-Ops and used ports by each HSW instruction. Please expect some performance fluctuations due to code alignment effects. Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud Differential Revision: https://reviews.llvm.org/D36663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311879 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
4.3 KiB
LLVM
127 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx | FileCheck %s -check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s -check-prefix=X64
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%struct.AA = type { i24, [4 x i8] }
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@obj = external local_unnamed_addr global %struct.AA, align 8
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@var_27 = external local_unnamed_addr constant i8, align 1
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@var_2 = external local_unnamed_addr constant i16, align 2
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@var_24 = external local_unnamed_addr constant i64, align 8
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@var_310 = external local_unnamed_addr global i64, align 8
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@var_50 = external local_unnamed_addr global i64, align 8
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@var_205 = external local_unnamed_addr global i8, align 1
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@var_218 = external local_unnamed_addr global i8, align 1
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define void @foo() local_unnamed_addr {
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; X86-LABEL: foo:
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; X86: # BB#0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: .Lcfi0:
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: pushl %ebx
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; X86-NEXT: .Lcfi1:
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; X86-NEXT: .cfi_def_cfa_offset 12
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; X86-NEXT: pushl %edi
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; X86-NEXT: .Lcfi2:
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; X86-NEXT: .cfi_def_cfa_offset 16
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; X86-NEXT: pushl %esi
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; X86-NEXT: .Lcfi3:
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; X86-NEXT: .cfi_def_cfa_offset 20
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; X86-NEXT: .Lcfi4:
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; X86-NEXT: .cfi_offset %esi, -20
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; X86-NEXT: .Lcfi5:
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; X86-NEXT: .cfi_offset %edi, -16
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; X86-NEXT: .Lcfi6:
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; X86-NEXT: .cfi_offset %ebx, -12
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; X86-NEXT: .Lcfi7:
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; X86-NEXT: .cfi_offset %ebp, -8
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; X86-NEXT: movsbl var_27, %eax
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; X86-NEXT: movl var_310, %ecx
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; X86-NEXT: imull %eax, %ecx
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; X86-NEXT: movl obj, %esi
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; X86-NEXT: addl var_24, %ecx
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; X86-NEXT: movzwl var_2, %edi
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; X86-NEXT: andl $4194303, %esi # imm = 0x3FFFFF
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; X86-NEXT: leal (%esi,%esi), %edx
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; X86-NEXT: subl %eax, %edx
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; X86-NEXT: movl %edx, %ebx
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; X86-NEXT: subl %edi, %ebx
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; X86-NEXT: imull %ebx, %ecx
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; X86-NEXT: addl $-1437483407, %ecx # imm = 0xAA51BE71
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; X86-NEXT: movl $9, %edi
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; X86-NEXT: xorl %ebp, %ebp
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; X86-NEXT: shldl %cl, %edi, %ebp
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; X86-NEXT: shlxl %ecx, %edi, %edi
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; X86-NEXT: testb $32, %cl
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; X86-NEXT: cmovnel %edi, %ebp
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; X86-NEXT: movl $0, %ecx
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; X86-NEXT: cmovnel %ecx, %edi
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; X86-NEXT: movl %ebp, var_50+4
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; X86-NEXT: cmpl %esi, %ebx
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; X86-NEXT: setge var_205
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; X86-NEXT: imull %eax, %edx
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; X86-NEXT: movl %edi, var_50
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; X86-NEXT: movb %dl, var_218
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # BB#0: # %entry
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; X64-NEXT: movsbl {{.*}}(%rip), %eax
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; X64-NEXT: movl {{.*}}(%rip), %ecx
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; X64-NEXT: imull %eax, %ecx
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; X64-NEXT: movl {{.*}}(%rip), %edx
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; X64-NEXT: addl {{.*}}(%rip), %ecx
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; X64-NEXT: movzwl {{.*}}(%rip), %r8d
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; X64-NEXT: andl $4194303, %edx # imm = 0x3FFFFF
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; X64-NEXT: leal (%rdx,%rdx), %edi
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; X64-NEXT: subl %eax, %edi
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; X64-NEXT: movl %edi, %esi
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; X64-NEXT: subl %r8d, %esi
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; X64-NEXT: imull %esi, %ecx
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; X64-NEXT: addl $-1437483407, %ecx # imm = 0xAA51BE71
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; X64-NEXT: movl $9, %r8d
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; X64-NEXT: cmpl %edx, %esi
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; X64-NEXT: setge {{.*}}(%rip)
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; X64-NEXT: shlxq %rcx, %r8, %rcx
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; X64-NEXT: imull %eax, %edi
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; X64-NEXT: movq %rcx, {{.*}}(%rip)
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; X64-NEXT: movb %dil, {{.*}}(%rip)
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; X64-NEXT: retq
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entry:
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%bf.load = load i32, i32* bitcast (%struct.AA* @obj to i32*), align 8
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%bf.clear = shl i32 %bf.load, 1
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%add = and i32 %bf.clear, 8388606
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%0 = load i8, i8* @var_27, align 1
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%conv5 = sext i8 %0 to i32
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%sub = sub nsw i32 %add, %conv5
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%1 = load i16, i16* @var_2, align 2
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%conv6 = zext i16 %1 to i32
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%sub7 = sub nsw i32 %sub, %conv6
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%conv8 = sext i32 %sub7 to i64
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%2 = load i64, i64* @var_24, align 8
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%3 = load i64, i64* @var_310, align 8
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%conv9 = sext i8 %0 to i64
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%mul = mul i64 %3, %conv9
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%add10 = add i64 %mul, %2
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%mul11 = mul i64 %add10, %conv8
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%sub12 = add i64 %mul11, 8662905354777116273
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%shl = shl i64 9, %sub12
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store i64 %shl, i64* @var_50, align 8
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%bf.clear14 = and i32 %bf.load, 4194303
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%add21 = shl nuw nsw i32 %bf.clear14, 1
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%sub23 = sub nsw i32 %add21, %conv5
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%sub25 = sub nsw i32 %sub23, %conv6
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%cmp = icmp sge i32 %sub25, %bf.clear14
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%conv30 = zext i1 %cmp to i8
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store i8 %conv30, i8* @var_205, align 1
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%mul43 = mul nsw i32 %sub, %conv5
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%conv44 = trunc i32 %mul43 to i8
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store i8 %conv44, i8* @var_218, align 1
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ret void
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}
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