Hal Finkel fa55969acb PPC: Allocate RS spill slot for unaligned i64 load/store ... This fixes another bug found by llvm-stress! If we happen to be doing an i64 load or store into a stack slot that has less than a 4-byte alignment, then the frame-index elimination may need to use an indexed load or store instruction (because the offset may not be a multiple of 4, a requirement of the STD/LD instructions). The extra register needed to hold the offset comes from the register scavenger, and it is possible that the scavenger will need to use an emergency spill slot. As a result, we need to make sure that a spill slot is allocated when doing an i64 load/store into a less-than-4-byte-aligned stack slot. Because test cases for things like this tend to be fairly fragile, I've concatenated a few small bugpoint-reduced test cases together to form the regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185907 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-09 06:34:51 +00:00
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Bindings/Ocaml	Convert an OCaml binding grep test to FileCheck	2013-07-08 14:14:22 +00:00
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CodeGen	PPC: Allocate RS spill slot for unaligned i64 load/store	2013-07-09 06:34:51 +00:00
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MC	CEHCK->CHECK typo fix.	2013-07-08 21:47:33 +00:00
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Other	llvm/test/Other/llvm-cov.test: It requires +Asserts to let XFAILed.	2013-07-08 08:44:24 +00:00
TableGen
tools	Revert: Fix wrong code offset for unwind code SET_FPREG.	2013-07-08 04:48:34 +00:00
Transforms	InstCombine: Fold X-C1 <u 2 -> (X & -2) == C1	2013-07-08 11:53:08 +00:00
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CMakeLists.txt	llvm/test/CMakeLists.txt: Add llvm-cov in "check-clang".	2013-07-08 08:44:36 +00:00
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