Logo
Explore Help
Sign In
RPCS3/llvm
1
0
Fork 0
You've already forked llvm
mirror of https://github.com/RPCS3/llvm.git synced 2026-08-28 05:10:05 -04:00
Code Issues Packages Projects Releases 10 Wiki Activity
Files
fa7848b1a02f2b36fc12786bbffd1c8a68866ca2
llvm/test/CodeGen/Mips/mirparser
T
History
Simon Dardis 2bdc7ff150 [mips] Correct predicates for loads, bit manipulation instructions and some pseudos
Additionally, correct the definition of the rdhwr instruction.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D48216


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335162 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-20 19:59:58 +00:00
..
target-flags-pic-mxgot-tls.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
target-flags-pic-o32.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
target-flags-pic.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
target-flags-static-tls.mir
[mips] Correct predicates for loads, bit manipulation instructions and some pseudos
2018-06-20 19:59:58 +00:00
Powered by Gitea Version: 1.26.2 Page: 179ms Template: 1ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API