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6ccfc507dc
have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
426 B
LLVM
16 lines
426 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
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define void @b(i32 %x) nounwind optsize {
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entry:
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; CHECK: b
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; CHECK: mov r2, sp
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; CHECK: mls r0, r0, r1, r2
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; CHECK: mov sp, r0
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%0 = mul i32 %x, 24 ; <i32> [#uses=1]
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%vla = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1]
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call arm_aapcscc void @a(i8* %vla) nounwind optsize
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ret void
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}
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declare void @a(i8*) optsize
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