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a3ac88d8ab
LLVM is able to merge identical static const globals, GCC isn't, and this caused some bloat in the generated data. This has a marginal effect on PPC, shrinking the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger reduction. This should speed up the register allocator as well by reducing the dcache footprint for this static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22879 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
//===- InstrInfoEmitter.h - Generate a Instruction Set Desc. ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef INSTRINFO_EMITTER_H
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#define INSTRINFO_EMITTER_H
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#include "TableGenBackend.h"
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#include <vector>
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#include <map>
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namespace llvm {
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class StringInit;
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class IntInit;
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class ListInit;
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struct CodeGenInstruction;
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class InstrInfoEmitter : public TableGenBackend {
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RecordKeeper &Records;
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public:
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InstrInfoEmitter(RecordKeeper &R) : Records(R) {}
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// run - Output the instruction set description, returning true on failure.
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void run(std::ostream &OS);
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// runEnums - Print out enum values for all of the instructions.
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void runEnums(std::ostream &OS);
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private:
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void printDefList(const std::vector<Record*> &Uses, unsigned Num,
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std::ostream &OS) const;
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<ListInit*, unsigned> &ListNumbers,
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std::ostream &OS);
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void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
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std::ostream &OS);
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};
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} // End llvm namespace
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#endif
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