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Add some notes to the README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
818 lines
33 KiB
TableGen
818 lines
33 KiB
TableGen
//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces used by SelectionDAG
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// instruction selection generators.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Constraint definitions.
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//
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// Note that the semantics of these constraints are hard coded into tblgen. To
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// modify or add constraints, you have to hack tblgen.
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//
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class SDTypeConstraint<int opnum> {
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int OperandNum = opnum;
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}
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// SDTCisVT - The specified operand has exactly this VT.
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class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
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ValueType VT = vt;
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}
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class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisInt - The specified operand is has integer type.
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class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisFP - The specified operand is has floating point type.
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class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisSameAs - The two specified operands have identical types.
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class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
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// smaller than the 'Other' operand.
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class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
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int BigOperandNum = BigOp;
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}
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/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
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/// vector types, and that ThisOp is the result of
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/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
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/// has.
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class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
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: SDTypeConstraint<ThisOp> {
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int OtherOpNum = OtherOp;
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}
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/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
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/// type as the element type of OtherOp, which is a vector type.
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class SDTCisEltOfVec<int ThisOp, int OtherOp>
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: SDTypeConstraint<ThisOp> {
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int OtherOpNum = OtherOp;
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}
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Profile definitions.
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//
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// These use the constraints defined above to describe the type requirements of
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// the various nodes. These are not hard coded into tblgen, allowing targets to
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// add their own if needed.
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//
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// SDTypeProfile - This profile describes the type requirements of a Selection
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// DAG node.
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class SDTypeProfile<int numresults, int numoperands,
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list<SDTypeConstraint> constraints> {
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int NumResults = numresults;
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int NumOperands = numoperands;
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list<SDTypeConstraint> Constraints = constraints;
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}
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// Builtin profiles.
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def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
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def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
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def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
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def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
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def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
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def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
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]>;
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def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
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]>;
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def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
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]>;
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def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
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SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
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]>;
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def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
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]>;
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def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
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SDTCisSameAs<0, 1>, SDTCisInt<0>
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]>;
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def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
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SDTCisSameAs<0, 1>, SDTCisFP<0>
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]>;
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def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
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SDTCisFP<0>, SDTCisInt<1>
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]>;
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def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
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SDTCisInt<0>, SDTCisFP<1>
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]>;
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def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
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SDTCisVTSmallerThanOp<2, 1>
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]>;
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def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
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SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
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]>;
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def SDTSelect : SDTypeProfile<1, 3, [ // select
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SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
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]>;
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def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
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SDTCisVT<5, OtherVT>
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]>;
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def SDTBr : SDTypeProfile<0, 1, [ // br
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SDTCisVT<0, OtherVT>
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]>;
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def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
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SDTCisInt<0>, SDTCisVT<1, OtherVT>
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]>;
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def SDTBrind : SDTypeProfile<0, 1, [ // brind
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SDTCisPtrTy<0>
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]>;
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def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
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def SDTLoad : SDTypeProfile<1, 1, [ // load
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SDTCisPtrTy<1>
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]>;
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def SDTStore : SDTypeProfile<0, 2, [ // store
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SDTCisPtrTy<1>
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]>;
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def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
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SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
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]>;
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def SDTVecShuffle : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
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]>;
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def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
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SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
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]>;
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def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
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SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
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]>;
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class SDCallSeqStart<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 1, constraints>;
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class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 2, constraints>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Properties.
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//
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// Note: These are hard coded into tblgen.
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//
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class SDNodeProperty;
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def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
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def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
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def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
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def SDNPOutFlag : SDNodeProperty; // Write a flag result
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def SDNPInFlag : SDNodeProperty; // Read a flag operand
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def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
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def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
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def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
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def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
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//===----------------------------------------------------------------------===//
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// Selection DAG Node definitions.
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//
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class SDNode<string opcode, SDTypeProfile typeprof,
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list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
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string Opcode = opcode;
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string SDClass = sdclass;
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list<SDNodeProperty> Properties = props;
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SDTypeProfile TypeProfile = typeprof;
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}
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def set;
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def implicit;
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def parallel;
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def node;
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def srcvalue;
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def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
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def fpimm : SDNode<"ISD::TargetConstantFP",
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SDTFPLeaf, [], "ConstantFPSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
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def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
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def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
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def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
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def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
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"ConstantPoolSDNode">;
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def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
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"ConstantPoolSDNode">;
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def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
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"JumpTableSDNode">;
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def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
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"JumpTableSDNode">;
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def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
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"FrameIndexSDNode">;
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def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
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"FrameIndexSDNode">;
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def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
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"ExternalSymbolSDNode">;
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def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
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"ExternalSymbolSDNode">;
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def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
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[SDNPCommutative, SDNPAssociative]>;
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def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
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def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
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def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
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def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
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def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
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def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
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def and : SDNode<"ISD::AND" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
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[SDNPCommutative, SDNPOutFlag]>;
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def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
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def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
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[SDNPOutFlag]>;
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def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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[SDNPOutFlag, SDNPInFlag]>;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
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def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
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def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
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def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
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def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
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def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
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def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
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def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
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def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
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def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
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def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
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def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
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def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
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def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
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def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
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def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
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def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
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def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
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def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
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def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
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def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
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def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
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def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
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def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
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def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
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def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
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def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
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def select : SDNode<"ISD::SELECT" , SDTSelect>;
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def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
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def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
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def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
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def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
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def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
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def trap : SDNode<"ISD::TRAP" , SDTNone,
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[SDNPHasChain, SDNPSideEffect]>;
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// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
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// and truncst (see below).
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def ld : SDNode<"ISD::LOAD" , SDTLoad,
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[SDNPHasChain, SDNPMayLoad]>;
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def st : SDNode<"ISD::STORE" , SDTStore,
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[SDNPHasChain, SDNPMayStore]>;
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def ist : SDNode<"ISD::STORE" , SDTIStore,
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[SDNPHasChain, SDNPMayStore]>;
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def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
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def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
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def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
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[]>;
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def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
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SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
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def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
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def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
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SDTypeProfile<1, 2, []>>;
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def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
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SDTypeProfile<1, 3, []>>;
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// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
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// these internally. Don't reference these directly.
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def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
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SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain]>;
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def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
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SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
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[SDNPHasChain]>;
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def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
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SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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class CondCode; // ISD::CondCode enums
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def SETOEQ : CondCode; def SETOGT : CondCode;
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def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
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def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
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def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
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def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
|
|
|
|
def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
|
|
def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Selection DAG Node Transformation Functions.
|
|
//
|
|
// This mechanism allows targets to manipulate nodes in the output DAG once a
|
|
// match has been formed. This is typically used to manipulate immediate
|
|
// values.
|
|
//
|
|
class SDNodeXForm<SDNode opc, code xformFunction> {
|
|
SDNode Opcode = opc;
|
|
code XFormFunction = xformFunction;
|
|
}
|
|
|
|
def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Selection DAG Pattern Fragments.
|
|
//
|
|
// Pattern fragments are reusable chunks of dags that match specific things.
|
|
// They can take arguments and have C++ predicates that control whether they
|
|
// match. They are intended to make the patterns for common instructions more
|
|
// compact and readable.
|
|
//
|
|
|
|
/// PatFrag - Represents a pattern fragment. This can match something on the
|
|
/// DAG, frame a single node to multiply nested other fragments.
|
|
///
|
|
class PatFrag<dag ops, dag frag, code pred = [{}],
|
|
SDNodeXForm xform = NOOP_SDNodeXForm> {
|
|
dag Operands = ops;
|
|
dag Fragment = frag;
|
|
code Predicate = pred;
|
|
SDNodeXForm OperandTransform = xform;
|
|
}
|
|
|
|
// PatLeaf's are pattern fragments that have no operands. This is just a helper
|
|
// to define immediates and other common things concisely.
|
|
class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
|
|
: PatFrag<(ops), frag, pred, xform>;
|
|
|
|
// Leaf fragments.
|
|
|
|
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
|
|
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
|
|
|
|
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
|
|
def immAllOnesV: PatLeaf<(build_vector), [{
|
|
return ISD::isBuildVectorAllOnes(N);
|
|
}]>;
|
|
def immAllOnesV_bc: PatLeaf<(bitconvert), [{
|
|
return ISD::isBuildVectorAllOnes(N);
|
|
}]>;
|
|
def immAllZerosV: PatLeaf<(build_vector), [{
|
|
return ISD::isBuildVectorAllZeros(N);
|
|
}]>;
|
|
def immAllZerosV_bc: PatLeaf<(bitconvert), [{
|
|
return ISD::isBuildVectorAllZeros(N);
|
|
}]>;
|
|
|
|
|
|
|
|
// Other helper fragments.
|
|
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
|
|
def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
|
|
def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
|
|
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
|
|
|
|
// load fragments.
|
|
def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::NON_EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
|
|
// extending load fragments.
|
|
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i1;
|
|
return false;
|
|
}]>;
|
|
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i8;
|
|
return false;
|
|
}]>;
|
|
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i16;
|
|
return false;
|
|
}]>;
|
|
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i32;
|
|
return false;
|
|
}]>;
|
|
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::f32;
|
|
return false;
|
|
}]>;
|
|
def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::f64;
|
|
return false;
|
|
}]>;
|
|
|
|
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i1;
|
|
return false;
|
|
}]>;
|
|
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i8;
|
|
return false;
|
|
}]>;
|
|
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i16;
|
|
return false;
|
|
}]>;
|
|
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i32;
|
|
return false;
|
|
}]>;
|
|
|
|
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i1;
|
|
return false;
|
|
}]>;
|
|
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i8;
|
|
return false;
|
|
}]>;
|
|
def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i16;
|
|
return false;
|
|
}]>;
|
|
def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
LD->getMemoryVT() == MVT::i32;
|
|
return false;
|
|
}]>;
|
|
|
|
// store fragments.
|
|
def store : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return !ST->isTruncatingStore() &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
|
|
// truncstore fragments.
|
|
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
|
|
(st node:$val, node:$ptr), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
|
return false;
|
|
}]>;
|
|
|
|
// indexed store fragments.
|
|
def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
!ST->isTruncatingStore();
|
|
}
|
|
return false;
|
|
}]>;
|
|
|
|
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
|
|
}
|
|
return false;
|
|
}]>;
|
|
|
|
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
|
(ist node:$val, node:$ptr, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return !ST->isTruncatingStore() &&
|
|
(AM == ISD::POST_INC || AM == ISD::POST_DEC);
|
|
}
|
|
return false;
|
|
}]>;
|
|
|
|
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
|
|
}
|
|
return false;
|
|
}]>;
|
|
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
(ist node:$val, node:$base, node:$offset), [{
|
|
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
|
|
}
|
|
return false;
|
|
}]>;
|
|
|
|
// setcc convenience fragments.
|
|
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETOEQ)>;
|
|
def setogt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETOGT)>;
|
|
def setoge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETOGE)>;
|
|
def setolt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETOLT)>;
|
|
def setole : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETOLE)>;
|
|
def setone : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETONE)>;
|
|
def seto : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETO)>;
|
|
def setuo : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETUO)>;
|
|
def setueq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETUEQ)>;
|
|
def setugt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETUGT)>;
|
|
def setuge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETUGE)>;
|
|
def setult : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETULT)>;
|
|
def setule : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETULE)>;
|
|
def setune : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETUNE)>;
|
|
def seteq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETEQ)>;
|
|
def setgt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETGT)>;
|
|
def setge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETGE)>;
|
|
def setlt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETLT)>;
|
|
def setle : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETLE)>;
|
|
def setne : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETNE)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Selection DAG Pattern Support.
|
|
//
|
|
// Patterns are what are actually matched against the target-flavored
|
|
// instruction selection DAG. Instructions defined by the target implicitly
|
|
// define patterns in most cases, but patterns can also be explicitly added when
|
|
// an operation is defined by a sequence of instructions (e.g. loading a large
|
|
// immediate value on RISC targets that do not support immediates as large as
|
|
// their GPRs).
|
|
//
|
|
|
|
class Pattern<dag patternToMatch, list<dag> resultInstrs> {
|
|
dag PatternToMatch = patternToMatch;
|
|
list<dag> ResultInstrs = resultInstrs;
|
|
list<Predicate> Predicates = []; // See class Instruction in Target.td.
|
|
int AddedComplexity = 0; // See class Instruction in Target.td.
|
|
}
|
|
|
|
// Pat - A simple (but common) form of a pattern, which produces a simple result
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// not needing a full list.
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class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
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//===----------------------------------------------------------------------===//
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// Complex pattern definitions.
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//
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class CPAttribute;
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// Pass the parent Operand as root to CP function rather
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// than the root of the sub-DAG
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def CPAttrParentAsRoot : CPAttribute;
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// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
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// in C++. NumOperands is the number of operands returned by the select function;
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// SelectFunc is the name of the function used to pattern match the max. pattern;
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// RootNodes are the list of possible root nodes of the sub-dags to match.
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// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
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//
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class ComplexPattern<ValueType ty, int numops, string fn,
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list<SDNode> roots = [], list<SDNodeProperty> props = [],
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list<CPAttribute> attrs = []> {
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ValueType Ty = ty;
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int NumOperands = numops;
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string SelectFunc = fn;
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list<SDNode> RootNodes = roots;
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list<SDNodeProperty> Properties = props;
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list<CPAttribute> Attributes = attrs;
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}
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//===----------------------------------------------------------------------===//
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// Dwarf support.
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//
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def SDT_dwarf_loc : SDTypeProfile<0, 3,
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[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
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def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
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