Vincent Lejeune fd49dac48f R600: Fix JUMP handling so that MachineInstr verification can occur ... This allows R600 Target to use the newly created -verify-misched llc flag git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176819 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-11 18:15:06 +00:00
..
AArch64	Test case hygiene.	2013-03-09 18:25:40 +00:00
ARM	Remove date from test case file name. The PR number provides a unique ID already.	2013-03-11 03:49:23 +00:00
CPP
Generic
Hexagon	Hexagon: Add patterns for zero extended loads from i1->i64.	2013-03-08 14:15:15 +00:00
MBlaze
Mips	Test case hygiene.	2013-03-09 18:25:40 +00:00
MSP430
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	Test case hygiene.	2013-03-09 18:25:40 +00:00
R600	R600: Fix JUMP handling so that MachineInstr verification can occur	2013-03-11 18:15:06 +00:00
SI
SPARC
Thumb	llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.	2013-03-05 02:18:52 +00:00
Thumb2	SDAG: Handle scalarizing an extend of a <1 x iN> vector.	2013-03-07 05:47:54 +00:00
X86	llvm/test/CodeGen/X86/handle-move.ll: Mark it as XFAIL:cygming. Investigating.	2013-03-11 16:30:26 +00:00
XCore