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798 lines
26 KiB
C++
798 lines
26 KiB
C++
//=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///\file
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/// This pass is used to reduce the size of instructions where applicable.
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///
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/// TODO: Implement microMIPS64 support.
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "micromips-reduce-size"
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#define MICROMIPS_SIZE_REDUCE_NAME "MicroMips instruction size reduce pass"
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STATISTIC(NumReduced, "Number of instructions reduced (32-bit to 16-bit ones, "
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"or two instructions into one");
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namespace {
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/// Order of operands to transfer
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// TODO: Will be extended when additional optimizations are added
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enum OperandTransfer {
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OT_NA, ///< Not applicable
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OT_OperandsAll, ///< Transfer all operands
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OT_Operands02, ///< Transfer operands 0 and 2
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OT_Operand2, ///< Transfer just operand 2
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OT_OperandsXOR, ///< Transfer operands for XOR16
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OT_OperandsLwp, ///< Transfer operands for LWP
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OT_OperandsSwp, ///< Transfer operands for SWP
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OT_OperandsMovep, ///< Transfer operands for MOVEP
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};
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/// Reduction type
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// TODO: Will be extended when additional optimizations are added
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enum ReduceType {
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RT_TwoInstr, ///< Reduce two instructions into one instruction
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RT_OneInstr ///< Reduce one instruction into a smaller instruction
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};
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// Information about immediate field restrictions
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struct ImmField {
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ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
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ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
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int8_t ImmFieldOperand)
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: ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
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HBound(HBound) {}
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int8_t ImmFieldOperand; // Immediate operand, -1 if it does not exist
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uint8_t Shift; // Shift value
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int16_t LBound; // Low bound of the immediate operand
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int16_t HBound; // High bound of the immediate operand
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};
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/// Information about operands
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// TODO: Will be extended when additional optimizations are added
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struct OpInfo {
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OpInfo(enum OperandTransfer TransferOperands)
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: TransferOperands(TransferOperands) {}
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OpInfo() : TransferOperands(OT_NA) {}
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enum OperandTransfer
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TransferOperands; ///< Operands to transfer to the new instruction
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};
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// Information about opcodes
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struct OpCodes {
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OpCodes(unsigned WideOpc, unsigned NarrowOpc)
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: WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}
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unsigned WideOpc; ///< Wide opcode
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unsigned NarrowOpc; ///< Narrow opcode
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};
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typedef struct ReduceEntryFunArgs ReduceEntryFunArgs;
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/// ReduceTable - A static table with information on mapping from wide
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/// opcodes to narrow
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struct ReduceEntry {
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enum ReduceType eRType; ///< Reduction type
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bool (*ReduceFunction)(
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ReduceEntryFunArgs *Arguments); ///< Pointer to reduce function
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struct OpCodes Ops; ///< All relevant OpCodes
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struct OpInfo OpInf; ///< Characteristics of operands
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struct ImmField Imm; ///< Characteristics of immediate field
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ReduceEntry(enum ReduceType RType, struct OpCodes Op,
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bool (*F)(ReduceEntryFunArgs *Arguments), struct OpInfo OpInf,
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struct ImmField Imm)
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: eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
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unsigned NarrowOpc() const { return Ops.NarrowOpc; }
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unsigned WideOpc() const { return Ops.WideOpc; }
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int16_t LBound() const { return Imm.LBound; }
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int16_t HBound() const { return Imm.HBound; }
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uint8_t Shift() const { return Imm.Shift; }
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int8_t ImmField() const { return Imm.ImmFieldOperand; }
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enum OperandTransfer TransferOperands() const {
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return OpInf.TransferOperands;
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}
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enum ReduceType RType() const { return eRType; }
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// operator used by std::equal_range
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bool operator<(const unsigned int r) const { return (WideOpc() < r); }
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// operator used by std::equal_range
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friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
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return (r < re.WideOpc());
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}
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};
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// Function arguments for ReduceFunction
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struct ReduceEntryFunArgs {
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MachineInstr *MI; // Instruction
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const ReduceEntry &Entry; // Entry field
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MachineBasicBlock::instr_iterator
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&NextMII; // Iterator to next instruction in block
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ReduceEntryFunArgs(MachineInstr *argMI, const ReduceEntry &argEntry,
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MachineBasicBlock::instr_iterator &argNextMII)
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: MI(argMI), Entry(argEntry), NextMII(argNextMII) {}
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};
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typedef llvm::SmallVector<ReduceEntry, 32> ReduceEntryVector;
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class MicroMipsSizeReduce : public MachineFunctionPass {
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public:
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static char ID;
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MicroMipsSizeReduce();
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static const MipsInstrInfo *MipsII;
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const MipsSubtarget *Subtarget;
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bool runOnMachineFunction(MachineFunction &MF) override;
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llvm::StringRef getPassName() const override {
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return "microMIPS instruction size reduction pass";
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}
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private:
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/// Reduces width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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/// Attempts to reduce MI, returns true on success.
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bool ReduceMI(const MachineBasicBlock::instr_iterator &MII,
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MachineBasicBlock::instr_iterator &NextMII);
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// Attempts to reduce LW/SW instruction into LWSP/SWSP,
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// returns true on success.
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static bool ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce two LW/SW instructions into LWP/SWP instruction,
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// returns true on success.
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static bool ReduceXWtoXWP(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce LBU/LHU instruction into LBU16/LHU16,
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// returns true on success.
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static bool ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce SB/SH instruction into SB16/SH16,
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// returns true on success.
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static bool ReduceSXtoSX16(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce two MOVE instructions into MOVEP instruction,
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// returns true on success.
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static bool ReduceMoveToMovep(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce arithmetic instructions, returns true on success.
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static bool ReduceArithmeticInstructions(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce ADDIU into ADDIUSP instruction,
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// returns true on success.
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static bool ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce ADDIU into ADDIUR1SP instruction,
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// returns true on success.
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static bool ReduceADDIUToADDIUR1SP(ReduceEntryFunArgs *Arguments);
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// Attempts to reduce XOR into XOR16 instruction,
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// returns true on success.
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static bool ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments);
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// Changes opcode of an instruction, replaces an instruction with a
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// new one, or replaces two instructions with a new instruction
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// depending on their order i.e. if these are consecutive forward
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// or consecutive backward
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static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry,
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MachineInstr *MI2 = nullptr,
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bool ConsecutiveForward = true);
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// Table with transformation rules for each instruction.
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static ReduceEntryVector ReduceTable;
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};
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char MicroMipsSizeReduce::ID = 0;
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const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
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// This table must be sorted by WideOpc as a main criterion and
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// ReduceType as a sub-criterion (when wide opcodes are the same).
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ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {
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// ReduceType, OpCodes, ReduceFunction,
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// OpInfo(TransferOperands),
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// ImmField(Shift, LBound, HBound, ImmFieldPosition)
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{RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
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ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
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{RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
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OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
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{RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
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ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
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{RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
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ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
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{RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
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OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
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{RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
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OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
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{RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
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ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
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{RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
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ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
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{RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
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OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
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{RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
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OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
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{RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
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{RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_TwoInstr, OpCodes(Mips::LW16_MM, Mips::LWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
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{RT_TwoInstr, OpCodes(Mips::LW_MM, Mips::LWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
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{RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_TwoInstr, OpCodes(Mips::MOVE16_MM, Mips::MOVEP_MM), ReduceMoveToMovep,
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OpInfo(OT_OperandsMovep), ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,
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OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
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{RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,
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OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
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{RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,
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OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
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{RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,
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OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
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{RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_TwoInstr, OpCodes(Mips::SW, Mips::SWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
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{RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_TwoInstr, OpCodes(Mips::SW16_MM, Mips::SWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
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{RT_TwoInstr, OpCodes(Mips::SW_MM, Mips::SWP_MM), ReduceXWtoXWP,
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OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
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{RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
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OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
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OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
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} // end anonymous namespace
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INITIALIZE_PASS(MicroMipsSizeReduce, DEBUG_TYPE, MICROMIPS_SIZE_REDUCE_NAME,
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false, false)
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// Returns true if the machine operand MO is register SP.
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static bool IsSP(const MachineOperand &MO) {
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if (MO.isReg() && ((MO.getReg() == Mips::SP)))
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return true;
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return false;
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}
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// Returns true if the machine operand MO is register $16, $17, or $2-$7.
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static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
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if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
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return true;
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return false;
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}
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// Returns true if the machine operand MO is register $0, $17, or $2-$7.
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static bool isMMSourceRegister(const MachineOperand &MO) {
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if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
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return true;
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return false;
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}
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// Returns true if the operand Op is an immediate value
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// and writes the immediate value into variable Imm.
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static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {
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if (!MI->getOperand(Op).isImm())
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return false;
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Imm = MI->getOperand(Op).getImm();
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return true;
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}
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// Returns true if the value is a valid immediate for ADDIUSP.
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static bool AddiuspImmValue(int64_t Value) {
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int64_t Value2 = Value >> 2;
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if (((Value & (int64_t)maskTrailingZeros<uint64_t>(2)) == Value) &&
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((Value2 >= 2 && Value2 <= 257) || (Value2 >= -258 && Value2 <= -3)))
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return true;
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return false;
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}
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// Returns true if the variable Value has the number of least-significant zero
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// bits equal to Shift and if the shifted value is between the bounds.
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static bool InRange(int64_t Value, unsigned short Shift, int LBound,
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int HBound) {
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int64_t Value2 = Value >> Shift;
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if (((Value & (int64_t)maskTrailingZeros<uint64_t>(Shift)) == Value) &&
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(Value2 >= LBound) && (Value2 < HBound))
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return true;
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return false;
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}
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// Returns true if immediate operand is in range.
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static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {
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int64_t offset;
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if (!GetImm(MI, Entry.ImmField(), offset))
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return false;
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if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
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return false;
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return true;
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}
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// Returns true if MI can be reduced to lwp/swp instruction
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static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
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const ReduceEntry &Entry) {
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if (ReduceToLwp &&
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!(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM ||
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MI->getOpcode() == Mips::LW16_MM))
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return false;
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if (!ReduceToLwp &&
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!(MI->getOpcode() == Mips::SW || MI->getOpcode() == Mips::SW_MM ||
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MI->getOpcode() == Mips::SW16_MM))
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return false;
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unsigned reg = MI->getOperand(0).getReg();
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if (reg == Mips::RA)
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return false;
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if (!ImmInRange(MI, Entry))
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return false;
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if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
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return false;
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return true;
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}
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// Returns true if the registers Reg1 and Reg2 are consecutive
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static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
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static SmallVector<unsigned, 31> Registers = {
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Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
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Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,
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Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
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Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
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Mips::SP, Mips::FP, Mips::RA};
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for (uint8_t i = 0; i < Registers.size() - 1; i++) {
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if (Registers[i] == Reg1) {
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if (Registers[i + 1] == Reg2)
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return true;
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else
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return false;
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}
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}
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return false;
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}
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// Returns true if registers and offsets are consecutive
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static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) {
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int64_t Offset1, Offset2;
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if (!GetImm(MI1, 2, Offset1))
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return false;
|
|
if (!GetImm(MI2, 2, Offset2))
|
|
return false;
|
|
|
|
unsigned Reg1 = MI1->getOperand(0).getReg();
|
|
unsigned Reg2 = MI2->getOperand(0).getReg();
|
|
|
|
return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
|
|
}
|
|
|
|
MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
|
|
|
|
bool MicroMipsSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII,
|
|
MachineBasicBlock::instr_iterator &NextMII) {
|
|
|
|
MachineInstr *MI = &*MII;
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
// Search the table.
|
|
ReduceEntryVector::const_iterator Start = std::begin(ReduceTable);
|
|
ReduceEntryVector::const_iterator End = std::end(ReduceTable);
|
|
|
|
std::pair<ReduceEntryVector::const_iterator,
|
|
ReduceEntryVector::const_iterator>
|
|
Range = std::equal_range(Start, End, Opcode);
|
|
|
|
if (Range.first == Range.second)
|
|
return false;
|
|
|
|
for (ReduceEntryVector::const_iterator Entry = Range.first;
|
|
Entry != Range.second; ++Entry) {
|
|
ReduceEntryFunArgs Arguments(&(*MII), *Entry, NextMII);
|
|
if (((*Entry).ReduceFunction)(&Arguments))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!ImmInRange(MI, Entry))
|
|
return false;
|
|
|
|
if (!IsSP(MI->getOperand(1)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceXWtoXWP(ReduceEntryFunArgs *Arguments) {
|
|
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
MachineBasicBlock::instr_iterator &NextMII = Arguments->NextMII;
|
|
const MachineBasicBlock::instr_iterator &E =
|
|
Arguments->MI->getParent()->instr_end();
|
|
|
|
if (NextMII == E)
|
|
return false;
|
|
|
|
MachineInstr *MI1 = Arguments->MI;
|
|
MachineInstr *MI2 = &*NextMII;
|
|
|
|
// ReduceToLwp = true/false - reduce to LWP/SWP instruction
|
|
bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
|
|
(MI1->getOpcode() == Mips::LW_MM) ||
|
|
(MI1->getOpcode() == Mips::LW16_MM);
|
|
|
|
if (!CheckXWPInstr(MI1, ReduceToLwp, Entry))
|
|
return false;
|
|
|
|
if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
|
|
return false;
|
|
|
|
unsigned Reg1 = MI1->getOperand(1).getReg();
|
|
unsigned Reg2 = MI2->getOperand(1).getReg();
|
|
|
|
if (Reg1 != Reg2)
|
|
return false;
|
|
|
|
bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
|
|
bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
|
|
|
|
if (!(ConsecutiveForward || ConsecutiveBackward))
|
|
return false;
|
|
|
|
NextMII = std::next(NextMII);
|
|
return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
|
|
ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(1)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(2)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(
|
|
ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!ImmInRange(MI, Entry))
|
|
return false;
|
|
|
|
if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
int64_t ImmValue;
|
|
if (!GetImm(MI, Entry.ImmField(), ImmValue))
|
|
return false;
|
|
|
|
if (!AddiuspImmValue(ImmValue))
|
|
return false;
|
|
|
|
if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!ImmInRange(MI, Entry))
|
|
return false;
|
|
|
|
if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(1)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceSXtoSX16(ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!ImmInRange(MI, Entry))
|
|
return false;
|
|
|
|
if (!isMMSourceRegister(MI->getOperand(0)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(1)))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
// Returns true if Reg can be a source register
|
|
// of MOVEP instruction
|
|
static bool IsMovepSrcRegister(unsigned Reg) {
|
|
|
|
if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 ||
|
|
Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 ||
|
|
Reg == Mips::S3 || Reg == Mips::S4)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
// Returns true if Reg can be a destination register
|
|
// of MOVEP instruction
|
|
static bool IsMovepDestinationReg(unsigned Reg) {
|
|
|
|
if (Reg == Mips::A0 || Reg == Mips::A1 || Reg == Mips::A2 ||
|
|
Reg == Mips::A3 || Reg == Mips::S5 || Reg == Mips::S6)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
// Returns true if the registers can be a pair of destination
|
|
// registers in MOVEP instruction
|
|
static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) {
|
|
|
|
if ((R0 == Mips::A0 && R1 == Mips::S5) ||
|
|
(R0 == Mips::A0 && R1 == Mips::S6) ||
|
|
(R0 == Mips::A0 && R1 == Mips::A1) ||
|
|
(R0 == Mips::A0 && R1 == Mips::A2) ||
|
|
(R0 == Mips::A0 && R1 == Mips::A3) ||
|
|
(R0 == Mips::A1 && R1 == Mips::A2) ||
|
|
(R0 == Mips::A1 && R1 == Mips::A3) ||
|
|
(R0 == Mips::A2 && R1 == Mips::A3))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceMoveToMovep(ReduceEntryFunArgs *Arguments) {
|
|
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
MachineBasicBlock::instr_iterator &NextMII = Arguments->NextMII;
|
|
const MachineBasicBlock::instr_iterator &E =
|
|
Arguments->MI->getParent()->instr_end();
|
|
|
|
if (NextMII == E)
|
|
return false;
|
|
|
|
MachineInstr *MI1 = Arguments->MI;
|
|
MachineInstr *MI2 = &*NextMII;
|
|
|
|
unsigned RegDstMI1 = MI1->getOperand(0).getReg();
|
|
unsigned RegSrcMI1 = MI1->getOperand(1).getReg();
|
|
|
|
if (!IsMovepSrcRegister(RegSrcMI1))
|
|
return false;
|
|
|
|
if (!IsMovepDestinationReg(RegDstMI1))
|
|
return false;
|
|
|
|
if (MI2->getOpcode() != Entry.WideOpc())
|
|
return false;
|
|
|
|
unsigned RegDstMI2 = MI2->getOperand(0).getReg();
|
|
unsigned RegSrcMI2 = MI2->getOperand(1).getReg();
|
|
|
|
if (!IsMovepSrcRegister(RegSrcMI2))
|
|
return false;
|
|
|
|
bool ConsecutiveForward;
|
|
if (IsMovepDestinationRegPair(RegDstMI1, RegDstMI2)) {
|
|
ConsecutiveForward = true;
|
|
} else if (IsMovepDestinationRegPair(RegDstMI2, RegDstMI1)) {
|
|
ConsecutiveForward = false;
|
|
} else
|
|
return false;
|
|
|
|
NextMII = std::next(NextMII);
|
|
return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments) {
|
|
|
|
MachineInstr *MI = Arguments->MI;
|
|
const ReduceEntry &Entry = Arguments->Entry;
|
|
|
|
if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(1)) ||
|
|
!isMMThreeBitGPRegister(MI->getOperand(2)))
|
|
return false;
|
|
|
|
if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
|
|
!(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
|
|
return false;
|
|
|
|
return ReplaceInstruction(MI, Entry);
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
|
|
E = MBB.instr_end();
|
|
MachineBasicBlock::instr_iterator NextMII;
|
|
|
|
// Iterate through the instructions in the basic block
|
|
for (; MII != E; MII = NextMII) {
|
|
NextMII = std::next(MII);
|
|
MachineInstr *MI = &*MII;
|
|
|
|
// Don't reduce bundled instructions or pseudo operations
|
|
if (MI->isBundle() || MI->isTransient())
|
|
continue;
|
|
|
|
// Try to reduce 32-bit instruction into 16-bit instruction
|
|
Modified |= ReduceMI(MII, NextMII);
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
|
|
const ReduceEntry &Entry,
|
|
MachineInstr *MI2,
|
|
bool ConsecutiveForward) {
|
|
|
|
enum OperandTransfer OpTransfer = Entry.TransferOperands();
|
|
|
|
LLVM_DEBUG(dbgs() << "Converting 32-bit: " << *MI);
|
|
++NumReduced;
|
|
|
|
if (OpTransfer == OT_OperandsAll) {
|
|
MI->setDesc(MipsII->get(Entry.NarrowOpc()));
|
|
LLVM_DEBUG(dbgs() << " to 16-bit: " << *MI);
|
|
return true;
|
|
} else {
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
|
|
switch (OpTransfer) {
|
|
case OT_Operand2:
|
|
MIB.add(MI->getOperand(2));
|
|
break;
|
|
case OT_Operands02: {
|
|
MIB.add(MI->getOperand(0));
|
|
MIB.add(MI->getOperand(2));
|
|
break;
|
|
}
|
|
case OT_OperandsXOR: {
|
|
if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
|
|
MIB.add(MI->getOperand(0));
|
|
MIB.add(MI->getOperand(1));
|
|
MIB.add(MI->getOperand(2));
|
|
} else {
|
|
MIB.add(MI->getOperand(0));
|
|
MIB.add(MI->getOperand(2));
|
|
MIB.add(MI->getOperand(1));
|
|
}
|
|
break;
|
|
}
|
|
case OT_OperandsMovep:
|
|
case OT_OperandsLwp:
|
|
case OT_OperandsSwp: {
|
|
if (ConsecutiveForward) {
|
|
MIB.add(MI->getOperand(0));
|
|
MIB.add(MI2->getOperand(0));
|
|
MIB.add(MI->getOperand(1));
|
|
if (OpTransfer == OT_OperandsMovep)
|
|
MIB.add(MI2->getOperand(1));
|
|
else
|
|
MIB.add(MI->getOperand(2));
|
|
} else { // consecutive backward
|
|
MIB.add(MI2->getOperand(0));
|
|
MIB.add(MI->getOperand(0));
|
|
MIB.add(MI2->getOperand(1));
|
|
if (OpTransfer == OT_OperandsMovep)
|
|
MIB.add(MI->getOperand(1));
|
|
else
|
|
MIB.add(MI2->getOperand(2));
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "and converting 32-bit: " << *MI2
|
|
<< " to: " << *MIB);
|
|
|
|
MBB.erase_instr(MI);
|
|
MBB.erase_instr(MI2);
|
|
return true;
|
|
}
|
|
default:
|
|
llvm_unreachable("Unknown operand transfer!");
|
|
}
|
|
|
|
// Transfer MI flags.
|
|
MIB.setMIFlags(MI->getFlags());
|
|
|
|
LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB);
|
|
MBB.erase_instr(MI);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
|
|
|
|
// TODO: Add support for the subtarget microMIPS32R6.
|
|
if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
|
|
Subtarget->hasMips32r6())
|
|
return false;
|
|
|
|
MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
|
|
|
|
bool Modified = false;
|
|
MachineFunction::iterator I = MF.begin(), E = MF.end();
|
|
|
|
for (; I != E; ++I)
|
|
Modified |= ReduceMBB(*I);
|
|
return Modified;
|
|
}
|
|
|
|
/// Returns an instance of the MicroMips size reduction pass.
|
|
FunctionPass *llvm::createMicroMipsSizeReducePass() {
|
|
return new MicroMipsSizeReduce();
|
|
}
|