Juergen Ributzka c9bc145e31 [FastISel][AArch64] Add vector support to argument lowering. ... Lower the first 8 vector arguments too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217850 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-16 00:25:30 +00:00
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AArch64	[FastISel][AArch64] Add vector support to argument lowering.	2014-09-16 00:25:30 +00:00
ARM	[ARM] Add Thumb-2 code size optimization regression test for LSR (register).	2014-09-11 10:45:50 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Add a regression test to sanity check the PBQP allocator.	2014-09-03 18:04:10 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add mips32 r1 to the list of supported targets for Mips fast-isel	2014-09-15 20:30:25 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
R600	R600/SI: Prefer selecting more e64 instruction forms.	2014-09-15 17:15:02 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	Check-label a bit more specific	2014-09-03 13:32:08 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] As a follow-up to r217819, don't check for VSELECT legality now	2014-09-16 00:24:42 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00