Craig Topper fe2aed677b [X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use v16i16 instead. ...

BWI supports shifting by word amounts. Even if VLX isn't support we can still widen to v32i16 and extract the lower half. For SKX its preferrable to not use 512-bit vector if we can.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321059 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-19 06:59:10 +00:00

..

AArch64

update_mir_test_checks: Accept IR as input as well as MIR

2017-12-19 00:49:04 +00:00

AMDGPU

[Memcpy Loop Lowering] Remove the fixed int8 lowering.

2017-12-18 15:31:14 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Adjust test checks

2017-12-18 10:08:03 +00:00

AVR

[AVR] Fix two CodeGen tests

2017-12-09 07:51:43 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Hexagon

[Hexagon] Cache loads to select to avoid traversing mutating DAG

2017-12-18 23:13:27 +00:00

Inputs

…

Lanai

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

Mips

Reland "[mips] Fix the target specific instruction verifier"

2017-12-18 15:56:40 +00:00

MIR

[YAML] Add support for non-printable characters

2017-12-18 17:38:03 +00:00

MSP430

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Nios2

[Nios2] final infrastructure to provide compilation of a return from a function

2017-12-07 12:35:02 +00:00

NVPTX

[Memcpy Loop Lowering] Remove the fixed int8 lowering.

2017-12-18 15:31:14 +00:00

PowerPC

[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.

2017-12-18 19:21:56 +00:00

RISCV

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

SPARC

Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion

2017-12-11 22:25:04 +00:00

SystemZ

[MachineOperand][MIR] Add isRenamable to MachineOperand.

2017-12-12 17:53:59 +00:00

Thumb

[ARM] Add tests for D34515

2017-12-15 09:24:46 +00:00

Thumb2

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

WebAssembly

[WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors

2017-12-15 00:17:10 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use v16i16 instead.

2017-12-19 06:59:10 +00:00

XCore

[MC] Suppress .Lcfi labels when emitting textual assembly

2017-10-10 00:57:36 +00:00