mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-26 22:26:16 +00:00
75dd57a8f0
There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
6.4 KiB
TableGen
150 lines
6.4 KiB
TableGen
//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This describes the calling conventions for the PowerPC 32- and 64-bit
|
|
// architectures.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// CCIfSubtarget - Match if the current subtarget has a feature F.
|
|
class CCIfSubtarget<string F, CCAction A>
|
|
: CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Return Value Calling Convention
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Return-value convention for PowerPC
|
|
def RetCC_PPC : CallingConv<[
|
|
// On PPC64, integer return values are always promoted to i64
|
|
CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
|
|
|
|
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
|
CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
|
|
CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
|
|
|
|
CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
|
|
CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
|
|
|
|
// Vector types are always returned in V2.
|
|
CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
|
|
]>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// PowerPC System V Release 4 32-bit ABI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def CC_PPC32_SVR4_Common : CallingConv<[
|
|
// The ABI requires i64 to be passed in two adjacent registers with the first
|
|
// register having an odd register number.
|
|
CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
|
|
|
|
// The first 8 integer arguments are passed in integer registers.
|
|
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
|
|
|
// Make sure the i64 words from a long double are either both passed in
|
|
// registers or both passed on the stack.
|
|
CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
|
|
|
|
// FP values are passed in F1 - F8.
|
|
CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
|
|
|
|
// Split arguments have an alignment of 8 bytes on the stack.
|
|
CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
|
|
|
|
CCIfType<[i32], CCAssignToStack<4, 4>>,
|
|
|
|
// Floats are stored in double precision format, thus they have the same
|
|
// alignment and size as doubles.
|
|
CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
|
|
|
|
// Vectors get 16-byte stack slots that are 16-byte aligned.
|
|
CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
|
|
]>;
|
|
|
|
// This calling convention puts vector arguments always on the stack. It is used
|
|
// to assign vector arguments which belong to the variable portion of the
|
|
// parameter list of a variable argument function.
|
|
def CC_PPC32_SVR4_VarArg : CallingConv<[
|
|
CCDelegateTo<CC_PPC32_SVR4_Common>
|
|
]>;
|
|
|
|
// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
|
|
// put vector arguments in vector registers before putting them on the stack.
|
|
def CC_PPC32_SVR4 : CallingConv<[
|
|
// The first 12 Vector arguments are passed in AltiVec registers.
|
|
CCIfType<[v16i8, v8i16, v4i32, v4f32],
|
|
CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
|
|
|
|
CCDelegateTo<CC_PPC32_SVR4_Common>
|
|
]>;
|
|
|
|
// Helper "calling convention" to handle aggregate by value arguments.
|
|
// Aggregate by value arguments are always placed in the local variable space
|
|
// of the caller. This calling convention is only used to assign those stack
|
|
// offsets in the callers stack frame.
|
|
//
|
|
// Still, the address of the aggregate copy in the callers stack frame is passed
|
|
// in a GPR (or in the parameter list area if all GPRs are allocated) from the
|
|
// caller to the callee. The location for the address argument is assigned by
|
|
// the CC_PPC32_SVR4 calling convention.
|
|
//
|
|
// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
|
|
// not passed by value.
|
|
|
|
def CC_PPC32_SVR4_ByVal : CallingConv<[
|
|
CCIfByVal<CCPassByVal<4, 4>>,
|
|
|
|
CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
|
|
]>;
|
|
|
|
def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
|
|
V28, V29, V30, V31)>;
|
|
|
|
def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
|
|
R21, R22, R23, R24, R25, R26, R27, R28,
|
|
R29, R30, R31, F14, F15, F16, F17, F18,
|
|
F19, F20, F21, F22, F23, F24, F25, F26,
|
|
F27, F28, F29, F30, F31, CR2, CR3, CR4
|
|
)>;
|
|
|
|
def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
|
|
|
|
def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
|
|
R21, R22, R23, R24, R25, R26, R27, R28,
|
|
R29, R30, R31, F14, F15, F16, F17, F18,
|
|
F19, F20, F21, F22, F23, F24, F25, F26,
|
|
F27, F28, F29, F30, F31, CR2, CR3, CR4
|
|
)>;
|
|
|
|
def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
|
|
|
|
def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
|
|
X21, X22, X23, X24, X25, X26, X27, X28,
|
|
X29, X30, X31, F14, F15, F16, F17, F18,
|
|
F19, F20, F21, F22, F23, F24, F25, F26,
|
|
F27, F28, F29, F30, F31, CR2, CR3, CR4
|
|
)>;
|
|
|
|
def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
|
|
|
|
def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
|
|
X21, X22, X23, X24, X25, X26, X27, X28,
|
|
X29, X30, X31, F14, F15, F16, F17, F18,
|
|
F19, F20, F21, F22, F23, F24, F25, F26,
|
|
F27, F28, F29, F30, F31, CR2, CR3, CR4
|
|
)>;
|
|
|
|
|
|
def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
|
|
|
|
def CSR_NoRegs : CalleeSavedRegs<(add)>;
|
|
|