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In certain cases it is possible that transient instructions such as %reg = IMPLICIT_DEF as a single instruction in a basic block to reach the MipsHazardSchedule pass. This patch teaches MipsHazardSchedule to properly look through such cases. Reviewers: vkalintiris, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D27209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289529 91177308-0d34-0410-b5e6-96231b3b80d8