Mikael Holmen 78cae93022 Skip DBG instr in OptimizePHIs when looking for dead PHI cycles ...

Summary:
Changed use_instructions() to use_nodbg_instructions() when
building an instruction set.

We don't want the presence of debug info to affect the code
we generate.

Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl

Reviewed By: aprantl

Subscribers: aprantl, llvm-commits

Differential Revision: https://reviews.llvm.org/D40882

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320010 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-07 07:01:21 +00:00

..

AArch64

[AArch64] Add patterns to replace fsub fmul with fma fneg.

2017-12-06 22:48:36 +00:00

AMDGPU

AMDGPU Tests: Change a case to be run with -O0

2017-12-06 17:40:09 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM][AArch64][DAG] Reenable post-legalize store merge

2017-12-06 15:30:13 +00:00

AVR

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Hexagon

[Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically

2017-12-06 22:41:49 +00:00

Inputs

…

Lanai

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

Mips

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

MIR

Skip DBG instr in OptimizePHIs when looking for dead PHI cycles

2017-12-07 07:01:21 +00:00

MSP430

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.

2017-12-06 17:50:05 +00:00

PowerPC

Add REQUIRES asserts in combine_loads_from_build_pair.ll

2017-12-05 15:26:01 +00:00

RISCV

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SPARC

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SystemZ

[SystemZ] Bugfix in expandRxSBG()

2017-12-06 13:53:24 +00:00

Thumb

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb2

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

WebAssembly

[WebAssembly] Don't try to emit size information for unsized types

2017-12-07 00:14:30 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86][AVX512] Tag mask reg op instruction scheduler classes

2017-12-06 19:36:00 +00:00

XCore

[MC] Suppress .Lcfi labels when emitting textual assembly

2017-10-10 00:57:36 +00:00