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Summary: This class maintains the same logic as the original RetireControlUnit. This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb, courbet Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47244 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333292 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
3.2 KiB
C++
89 lines
3.2 KiB
C++
//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file simulates the hardware responsible for retiring instructions.
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///
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//===----------------------------------------------------------------------===//
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#include "RetireControlUnit.h"
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#include "DispatchStage.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM)
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
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// Check if the scheduling model provides extra information about the machine
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// processor. If so, then use that information to set the reorder buffer size
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// and the maximum number of instructions retired per cycle.
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if (SM.hasExtraProcessorInfo()) {
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const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
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if (EPI.ReorderBufferSize)
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AvailableSlots = EPI.ReorderBufferSize;
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MaxRetirePerCycle = EPI.MaxRetirePerCycle;
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}
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assert(AvailableSlots && "Invalid reorder buffer size!");
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Queue.resize(AvailableSlots);
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}
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::reserveSlot(const InstRef &IR,
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unsigned NumMicroOps) {
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assert(isAvailable(NumMicroOps));
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unsigned NormalizedQuantity =
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std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
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// Zero latency instructions may have zero mOps. Artificially bump this
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// value to 1. Although zero latency instructions don't consume scheduler
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// resources, they still consume one slot in the retire queue.
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NormalizedQuantity = std::max(NormalizedQuantity, 1U);
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unsigned TokenID = NextAvailableSlotIdx;
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Queue[NextAvailableSlotIdx] = {IR, NormalizedQuantity, false};
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NextAvailableSlotIdx += NormalizedQuantity;
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NextAvailableSlotIdx %= Queue.size();
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AvailableSlots -= NormalizedQuantity;
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return TokenID;
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}
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const RetireControlUnit::RUToken &RetireControlUnit::peekCurrentToken() const {
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return Queue[CurrentInstructionSlotIdx];
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}
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void RetireControlUnit::consumeCurrentToken() {
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const RetireControlUnit::RUToken &Current = peekCurrentToken();
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assert(Current.NumSlots && "Reserved zero slots?");
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assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
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// Update the slot index to be the next item in the circular queue.
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CurrentInstructionSlotIdx += Current.NumSlots;
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CurrentInstructionSlotIdx %= Queue.size();
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AvailableSlots += Current.NumSlots;
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}
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void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
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assert(Queue.size() > TokenID);
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assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
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Queue[TokenID].Executed = true;
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}
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#ifndef NDEBUG
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void RetireControlUnit::dump() const {
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dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
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<< ", Available Slots=" << AvailableSlots << " }\n";
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}
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#endif
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} // namespace mca
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