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fce447566a
Summary: This patch transforms the Scheduler class into the ExecuteStage. Most of the logic remains. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47246 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334679 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
2.6 KiB
C++
96 lines
2.6 KiB
C++
//===--------------------- Backend.cpp --------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// Implementation of class Backend which emulates an hardware OoO backend.
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///
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//===----------------------------------------------------------------------===//
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#include "Backend.h"
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#include "FetchStage.h"
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#include "HWEventListener.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/Debug.h"
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namespace mca {
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#define DEBUG_TYPE "llvm-mca"
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using namespace llvm;
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void Backend::addEventListener(HWEventListener *Listener) {
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if (Listener)
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Listeners.insert(Listener);
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}
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void Backend::run() {
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while (Fetch->isReady() || !Dispatch->isReady())
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runCycle(Cycles++);
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}
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void Backend::runCycle(unsigned Cycle) {
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notifyCycleBegin(Cycle);
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// Update the stages before we do any processing for this cycle.
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InstRef IR;
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Retire->preExecute(IR);
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Dispatch->preExecute(IR);
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Execute->preExecute(IR);
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// Fetch instructions and dispatch them to the hardware.
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while (Fetch->execute(IR)) {
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if (!Dispatch->execute(IR))
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break;
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Execute->execute(IR);
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Fetch->postExecute(IR);
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}
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notifyCycleEnd(Cycle);
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}
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void Backend::notifyCycleBegin(unsigned Cycle) {
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LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
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for (HWEventListener *Listener : Listeners)
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Listener->onCycleBegin();
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}
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void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
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for (HWEventListener *Listener : Listeners)
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Listener->onInstructionEvent(Event);
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}
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void Backend::notifyStallEvent(const HWStallEvent &Event) {
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for (HWEventListener *Listener : Listeners)
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Listener->onStallEvent(Event);
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}
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void Backend::notifyResourceAvailable(const ResourceRef &RR) {
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LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
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<< RR.second << "]\n");
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for (HWEventListener *Listener : Listeners)
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Listener->onResourceAvailable(RR);
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}
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void Backend::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
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for (HWEventListener *Listener : Listeners)
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Listener->onReservedBuffers(Buffers);
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}
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void Backend::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
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for (HWEventListener *Listener : Listeners)
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Listener->onReleasedBuffers(Buffers);
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}
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void Backend::notifyCycleEnd(unsigned Cycle) {
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LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
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for (HWEventListener *Listener : Listeners)
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Listener->onCycleEnd();
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}
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} // namespace mca.
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