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Summary: This class maintains the same logic as the original RetireControlUnit. This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb, courbet Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47244 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333292 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.8 KiB
C++
57 lines
1.8 KiB
C++
//===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines the retire stage of an instruction pipeline.
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/// The RetireStage represents the process logic that interacts with the
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/// simulated RetireControlUnit hardware.
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///
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//===----------------------------------------------------------------------===//
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#include "RetireStage.h"
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#include "Backend.h"
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#include "HWEventListener.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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void RetireStage::preExecute(const InstRef &IR) {
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if (RCU.isEmpty())
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return;
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const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
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unsigned NumRetired = 0;
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while (!RCU.isEmpty()) {
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if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
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break;
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const RetireControlUnit::RUToken &Current = RCU.peekCurrentToken();
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if (!Current.Executed)
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break;
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RCU.consumeCurrentToken();
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notifyInstructionRetired(Current.IR);
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NumRetired++;
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}
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}
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void RetireStage::notifyInstructionRetired(const InstRef &IR) {
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LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
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SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
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const InstrDesc &Desc = IR.getInstruction()->getDesc();
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for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
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PRF.removeRegisterWrite(*WS.get(), FreedRegs, !Desc.isZeroLatency());
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Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
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}
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} // namespace mca
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