3 Commits

Author	SHA1	Message	Date
Andrew Kaylor	c7ca1302cf	Add optimization bisect opt-in calls for AMDGPU passes ... Differential Revision: http://reviews.llvm.org/D19450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267485 91177308-0d34-0410-b5e6-96231b3b80d8	2016-04-25 22:23:44 +00:00
Tom Stellard	98ef447825	AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions ... Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260765 91177308-0d34-0410-b5e6-96231b3b80d8	2016-02-12 23:45:29 +00:00
Tom Stellard	6a0d02e088	AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions ... Summary: We were previously selecting all constant loads to SMRD instructions and legalizing the SMRDs with non-uniform addresses during the SIFixSGPRCopesPass. This new solution is more simple and also generates much better code, because the instruction selector is able to take advantage of all the MUBUF addressing modes that are legalization pass wasn't able to. We also no longer need to generate v_add_* instructions when we have a uniform pointer and a non-uniform offset, as this is now folded into the MUBUF instruction during instruction selection. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15425 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255672 91177308-0d34-0410-b5e6-96231b3b80d8	2015-12-15 20:55:55 +00:00