17 Commits

Author SHA1 Message Date
Chandler Carruth
e3e43d9d57 Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 11:49:48 +00:00
Francis Visoiu Mistrih
ae1c853358 [LegacyPassManager] Remove TargetMachine constructors
This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
  `getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
  `addRequired<TargetPassConfig>` and call
  `getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18 17:21:13 +00:00
Matt Arsenault
33eb1b078c AMDGPU: Cleanup control flow intrinsics
Move backend internal intrinsics along with the rest of the
normal intrinsics, and use the Intrinsic::getDeclaration
API instead of manually constructing the type list.

It's surprising this was working before. fdiv.fast had
the wrong number of parameters. The control flow intrinsic
declaration attributes were not being applied, and
their types were inconsistent. The actual IR use types
did not match the declaration, and were closer to the
types used for the patterns. The brcond lowering
was changing the types, so introduce new nodes for those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298119 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-17 20:41:45 +00:00
Matt Arsenault
27f4f2f4bc AMDGPU: Support v2i16/v2f16 packed operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296396 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-27 22:15:25 +00:00
Matt Arsenault
982ff7f443 AMDGPU: Improve nsw/nuw/exact when promoting uniform i16 ops
These were simply preserving the flags of the original operation,
which was too conservative in most cases and incorrect for mul.

nsw/nuw may be needed for some combines to cleanup messes when
intermediate sext_inregs are introduced later.

Tested valid combinations with alive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293776 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01 16:25:23 +00:00
Eugene Zelenko
68c521d030 [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292623 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-20 17:52:16 +00:00
Matt Arsenault
a8dff18ebc AMDGPU: Allow rcp and rsq usage with f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290302 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:05:44 +00:00
Matt Arsenault
9bdddbab7d AMDGPU: Fix crash on i16 constant expression
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-06 23:18:06 +00:00
Konstantin Zhuravlyov
fbd12bbb90 [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283558 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-07 14:39:53 +00:00
Konstantin Zhuravlyov
2d50d3f3c9 [AMDGPU] Promote uniform (i1, i16] operations to i32
Differential Revision: https://reviews.llvm.org/D25302


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283555 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-07 14:22:58 +00:00
Konstantin Zhuravlyov
bb3823e630 [AMDGPU] Promote uniform i16 bitreverse intrinsic to i32
Differential Revision: https://reviews.llvm.org/D25121


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283415 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-06 02:20:46 +00:00
Konstantin Zhuravlyov
1e8f5fd9f8 [AMDGPU] Sign extend AShr when promoting (instead of zero extending)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283130 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-03 18:29:01 +00:00
Mehdi Amini
67f335d992 Use StringRef in Pass/PassManager APIs (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283004 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-01 02:56:57 +00:00
Konstantin Zhuravlyov
f9bcd7b189 [AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions
Differential Revision: https://reviews.llvm.org/D24125



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282624 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-28 20:05:39 +00:00
Matt Arsenault
f799c706db AMDGPU: Use rcp for fdiv 1, x with fpmath metadata
Using rcp should be OK for safe math usually, so this
should not be replacing the original fdiv.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276823 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-26 23:25:44 +00:00
Matt Arsenault
63be72069d AMDGPU: Change fdiv lowering based on !fpmath metadata
If 2.5 ulp is acceptable, denormals are not required, and
isn't a reciprocal which will already be handled, replace
with a faster fdiv.

Simplify the lowering tests by using per function
subtarget features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276051 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-19 23:16:53 +00:00
Matt Arsenault
11c2d4bf28 AMDGPU: Add stub custom CodeGenPrepare pass
This will do various things including ones
CodeGenPrepare does, but with knowledge of uniform
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273657 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 07:07:55 +00:00