68 Commits

Author SHA1 Message Date
Guy Blank
6f26a8e23e [X86] Add xgetbv/xsetbv intrinsics to non-windows platforms
Differential Revision: https://reviews.llvm.org/D21958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278782 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 06:41:00 +00:00
David Majnemer
543ae79447 [X86] Don't model UD2/UD2B as a terminator
A UD2 might make its way into the program via a call to @llvm.trap.
Obviously, calls are not terminators.  However, we modeled the X86
instruction, UD2, as a terminator.  Later on, this confuses the epilogue
insertion machinery which results in the epilogue getting inserted
before the UD2.  For some platforms, like x64, the result is a
violation of the ABI.

Instead, model UD2/UD2B as a side effecting instruction which may
observe memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278144 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-09 17:55:12 +00:00
Zvi Rackover
a72116dbfd test commit: remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273094 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-18 19:13:38 +00:00
Craig Topper
db96b37522 [X86] Remove many operands that represent memory stores from outs to ins. These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263354 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-13 02:56:31 +00:00
Craig Topper
a57544039b [X86] Mark LDS/LES as not being allowed in 64-bit mode.
Their opcodes are used as part of the VEX prefix in 64-bit mode. Clearly the disassembler implicitly decoded them as AVX instructions in 64-bit mode, but I think the AsmParser would have encoded them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258793 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-26 06:10:15 +00:00
Craig Topper
5205089191 [X86] Use PS instead of TB for instructions that have PD/XS/XD variations. Use OpSize32 on an instruction that has an OpSize16 variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256918 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-06 06:18:41 +00:00
Asaf Badouh
7b8bd88d45 [X86][PKU] Add {RD,WR}PKRU intrinsics
Differential Revision: http://reviews.llvm.org/D15808

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 08:31:13 +00:00
Asaf Badouh
5c7343b3a6 [X86][PKU] Add {RD,WR}PKRU encoding
Differential Revision: http://reviews.llvm.org/D15711

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-24 08:25:00 +00:00
Amjad Aboud
9889174ead Implemented Support of IA interrupt and exception handlers:
http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html

Differential Revision: http://reviews.llvm.org/D15567

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256155 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21 14:07:14 +00:00
Amjad Aboud
8e03ab46f2 [X86] Add XSAVE intrinsic family
Add intrinsics for the
  XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64)
  XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64)
  XSAVEC instructions (XSAVEC/XSAVEC64)
  XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64)

Differential Revision: http://reviews.llvm.org/D13012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250029 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-12 11:47:46 +00:00
Craig Topper
e446a19cc1 [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250012 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-12 04:17:55 +00:00
Craig Topper
a9d6f4a14a [X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.
This also fixes a bug where negative immediates below -128 were not being reported as errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249989 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-11 18:27:24 +00:00
Craig Topper
3e7edda4aa [X86] Add register use/def for wrmsr and rdmsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228515 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-07 23:36:51 +00:00
Craig Topper
e15d286e83 [X86] Add GETSEC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-07 23:36:36 +00:00
Craig Topper
20d15157e4 [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228283 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 08:51:06 +00:00
Craig Topper
b8fa51de42 [X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 08:51:02 +00:00
Craig Topper
97494e9718 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 11:03:57 +00:00
Alex Rosenberg
8da9a6686a Use a different encoding for debugtrap on PS4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-26 19:09:27 +00:00
Michael Liao
d3c452a506 [X86] Clean up whitespace as well as minor coding style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-04 05:20:33 +00:00
Reid Kleckner
f2cdc0b1e9 X86: cpuid and xgetbv write to 32-bit registers, not 64-bit
This fixes an issue where MS inline assembly containing xgetbv wouldn't
be marked as clobbering EAX:EDX. Test for that forthcoming on the Clang
side.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-04 16:58:25 +00:00
Robert Khasanov
375a68ca15 [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216163 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:34:12 +00:00
Andrea Di Biagio
e6cfdc8471 [X86] Add support for builtin to read performance monitoring counters.
This patch adds support for a new builtin instruction called
__builtin_ia32_rdpmc.

Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can
be used to read performance monitoring counters. It takes as input the index
of the performance counter to read, and returns the value of the specified
performance counter as a 64-bit number.

Calls to this new builtin will map to instruction RDPMC.
The index in input to the builtin call is moved to register %ECX. The result
of the builtin call is the value of the specified performance counter (RDPMC
would return that quantity in registers RDX:RAX).

This patch:
 - Adds builtin int_x86_rdpmc as a GCCBuiltin;
 - Adds a new x86 DAG node called 'RDPMC_DAG';
 - Teaches how to lower this new builtin;
 - Adds an ISel pattern to select instruction RDPMC;
 - Fixes the definition of instruction RDPMC adding %RAX and %RDX as
   implicit definitions, and adding %ECX as implicit use;
 - Adds a LLVM test to verify that the new builtin is correctly selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212049 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-30 17:14:21 +00:00
Andrea Di Biagio
35f9e1aa49 [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.
This patch:
- Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and
   'int_x86_rdtscp') as GCCBuiltin intrinsics;
- Teaches the backend how to lower the two new builtins;
- Introduces a common function to lower READCYCLECOUNTER dag nodes
  and the two new rdtsc/rdtscp intrinsics;
- Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll'
  correctly verifies that both READCYCLECOUNTER and the two new intrinsics
  work fine for both 64bit and 32bit Subtargets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207127 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 17:18:27 +00:00
Craig Topper
74be63b014 [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 05:08:25 +00:00
Craig Topper
ecb903c1b5 [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:50:27 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Craig Topper
17e2af6928 Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 08:18:29 +00:00
Craig Topper
6b6dfa5c5a Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-02 09:25:09 +00:00
Craig Topper
312eec7ecb Simplify some x86 format classes and remove some ambiguities in their application.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-01 08:17:56 +00:00
Reid Kleckner
1386d3f885 x86: add implicit defs for cpuid
This avoids miscompiling MS inline asm in LLVM where we have to infer
clobbers.  Test case forthcoming in Clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200279 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 02:08:22 +00:00
David Woodhouse
0ff018e500 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199809 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:55 +00:00
Craig Topper
3039306b76 Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 08:16:57 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 07:41:20 +00:00
David Woodhouse
1c75f15a60 [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
David Woodhouse
a493812047 [x86] Add OpSize16 to instructions that need it
This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:40 +00:00
Craig Topper
29d56f68c6 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04 22:29:41 +00:00
Craig Topper
a7133ee752 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 18:20:48 +00:00
Eric Christopher
75a8b23e10 [x86] Rename In32BitMode predicate to Not64BitMode
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 02:04:49 +00:00
Craig Topper
418eb3df74 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:47:52 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:52:28 +00:00
Kay Tiong Khoo
c92cc5d918 fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:52:25 +00:00
Kay Tiong Khoo
49bbb35dfc fixed to disassemble with tab after mnemonic rather than space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:17:58 +00:00
Jakob Stoklund Olesen
eab5f7678b Add a catch-all WriteSystem SchedWrite type.
This is used for all the expensive system instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 23:09:50 +00:00
Kay Tiong Khoo
86494d7991 *fixed disassembly of some i386 system insts with intel syntax
*added file for test cases for i386 intel syntax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 19:46:36 +00:00
Dan Gohman
a6063c6e29 Rename @llvm.debugger to @llvm.debugtrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 18:58:10 +00:00
Dan Gohman
d4347e1af9 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 00:19:32 +00:00
Preston Gurd
3d142e58ef Adds Intel Atom scheduling latencies to X86InstrSystem.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 19:26:37 +00:00
Bill Wendling
e060eb8916 Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
Patch by Kay Tiong Khoo!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 07:37:27 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Devang Patel
c16d96f6f4 Fix asm string wrt variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09 21:32:02 +00:00