For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286377 91177308-0d34-0410-b5e6-96231b3b80d8
If the result of the find is only used to compare against end(), just
use is_contained instead.
No functionality change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278433 91177308-0d34-0410-b5e6-96231b3b80d8
Floating point instructions use general purpose registers, so the few
instructions that can put floating point immediates into registers are,
in fact, integer instruction. Use them explicitly instead of having
pseudo-instructions specifically for dealing with floating point values.
Simplify the constant loading instructions (from sdata) to have only two:
one for 32-bit values and one for 64-bit values: CONST32 and CONST64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278244 91177308-0d34-0410-b5e6-96231b3b80d8
Consider this case:
vreg1 = A2_zxth vreg0 (1)
...
vreg2 = A2_zxth vreg1 (2)
Redundant instruction elimination could delete the instruction (1)
because the user (2) only cares about the low 16 bits. Then it could
delete (2) because the input is already zero-extended. The problem
is that the properties allowing each individual instruction to be
deleted depend on the existence of the other instruction, so either
one can be deleted, but not both.
The existing check for this situation in RIE was insufficient. The
fix is to update all dependent cells when an instruction is removed
(replaced via COPY) in RIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276792 91177308-0d34-0410-b5e6-96231b3b80d8
Change the bit simplifier to generate REG_SEQUENCE instructions in
addition to COPY, which will handle cases of word insert/extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276787 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid implicit iterator conversions from MachineInstrBundleIterator to
MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr&
over MachineInstr* and switching to range-based for loops.
There's a long tail of API cleanup here, but I'm planning to leave the
rest to the Hexagon maintainers. HexagonInstrInfo defines many of its
own predicates, and most of them still take MachineInstr*. Some of
those actually check for nullptr, so I didn't feel comfortable changing
them to MachineInstr& en masse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275142 91177308-0d34-0410-b5e6-96231b3b80d8
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250868 91177308-0d34-0410-b5e6-96231b3b80d8
