Commit Graph

1613 Commits

Author SHA1 Message Date
Simon Pilgrim
72a3a14d8b [SelectionDAG] Added support for EXTRACT_SUBVECTOR/CONCAT_VECTORS demandedelts in ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 22:10:58 +00:00
Simon Pilgrim
bacfc66c2e [SelectionDAG] Add VECTOR_SHUFFLE support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302993 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 19:57:10 +00:00
Craig Topper
a7f9de4432 [ValueTracking] Remove const_casts on several calls to computeKnownBits and ComputeSignBit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 17:22:16 +00:00
Craig Topper
d49344495d [KnownBits] Add bit counting methods to KnownBits struct and use them where possible
This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 17:20:30 +00:00
Simon Pilgrim
43d171f539 Use SDValue::getOperand() helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 13:20:24 +00:00
Simon Pilgrim
7d572e564a Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302784 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11 10:03:05 +00:00
Amara Emerson
8f1f7ce9d1 Introduce experimental generic intrinsics for horizontal vector reductions.
- This change allows targets to opt-in to using them instead of the log2
  shufflevector algorithm.
- The SLP and Loop vectorizers have the common code to do shuffle reductions
  factored out into LoopUtils, and now have a unified interface for generating
  reductions regardless of the preference of the target. LoopUtils now uses TTI
  to determine what kind of reductions the target wants to handle.
- For CodeGen, basic legalization support is added.

Differential Revision: https://reviews.llvm.org/D30086



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302514 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:43:25 +00:00
Craig Topper
ace8b39f82 [KnownBits] Add wrapper methods for setting and clear all bits in the underlying APInts in KnownBits.
This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown.

Differential Revision: https://reviews.llvm.org/D32637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302262 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-05 17:36:09 +00:00
Craig Topper
9e4ad9cbb5 [SelectionDAG] Improve known bits support for CTPOP.
This is based on the same concept from ValueTracking's version of computeKnownBits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302110 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-04 04:33:27 +00:00
Craig Topper
f78221855b [KnownBits] Add zext, sext, and trunc methods to KnownBits
This patch adds zext, sext, and trunc methods to KnownBits and uses them where possible.

Differential Revision: https://reviews.llvm.org/D32784

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-03 22:07:25 +00:00
Simon Pilgrim
ed79276e6b [SelectionDAG] Improve support for promotion of <1 x fX> floating point argument types (PR31088)
PR31088 demonstrated that we were assuming that only integers require promotion from <1 x iX> types, when in fact float types may require it as well - in this case half floats.

This patch adds support for extension/truncation for both integer and float types.

Differential Revision: https://reviews.llvm.org/D32391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301910 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-02 10:33:08 +00:00
Craig Topper
4e5c5db786 [SelectionDAG] Use known ones to provide a better bound for the known zeros for CTTZ/CTLZ operations.
This is the SelectionDAG version of D32521. If know where at least one 1 is located in the input to these intrinsics we can place an upper bound on the number of bits needed to represent the count and thus increase the number of known zeros in the output.

I think we can also refine this further for CTTZ_UNDEF/CTLZ_UNDEF by assuming that the answer will never be BitWidth. I've left this out for now because it caused other test failures across multiple targets. Usually because of turning ADD into OR based on this new information.

I'll fix CTPOP in a future patch.

Differential Revision: https://reviews.llvm.org/D32692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301806 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-01 16:08:06 +00:00
Amara Emerson
195d3fa988 Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.
This removes BinaryWithFlagsSDNode, and flags are now all passed by value.

Differential Revision: https://reviews.llvm.org/D32527



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-01 15:17:51 +00:00
Amaury Sechet
bcb9816097 Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry
Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility.

Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer

Subscribers: igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D29872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301775 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-30 19:24:09 +00:00
Craig Topper
c07d5e69ae [APInt] Replace calls to setBits with more specific calls to setBitsFrom and setLowBits where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301768 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-30 07:44:58 +00:00
Craig Topper
8b69610574 [KnownBits] Add methods for determining if the known bits represent a negative/nonnegative number and add methods for changing the negative/nonnegative state
Summary: This patch adds isNegative, isNonNegative for querying whether the sign bit is known. It also adds makeNegative and makeNonNegative for controlling the sign bit.

Reviewers: RKSimon, spatel, davide

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-29 16:43:11 +00:00
Craig Topper
78b412f427 [APInt] Add clearSignBit method. Use it and setSignBit in a few places. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301656 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 16:58:05 +00:00
Simon Pilgrim
053e5ff4f2 [DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ASHR and INSERT_VECTOR_ELT (reapplied)
Reapplied r299221 after fix for nondeterminism in ThinLTO builder (rL301599), with extra check for implicit truncation of inserted element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 13:21:18 +00:00
Craig Topper
955683a5c6 [ValueTracking] Convert computeKnownBitsFromRangeMetadata to use KnownBits struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 06:28:56 +00:00
Craig Topper
8b430f87e6 [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits
This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently.

This is largely a mechanical transformation from KnownZero to Known.Zero.

Differential Revision: https://reviews.llvm.org/D32569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301620 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 05:31:46 +00:00
Craig Topper
cdfc3cbcb5 [SelectionDAG] Use various APInt methods to reduce temporary APInt creation
This patch uses various APInt methods to reduce the number of temporary APInts. These were all found while working through converting SelectionDAG's computeKnownBits to also use the KnownBits struct recently added to the ValueTracking version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301618 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 04:57:59 +00:00
Craig Topper
a7fa95c0e5 [APInt] Use inplace shift methods where possible. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 03:36:24 +00:00
Craig Topper
58c7fe69d0 [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for computeKnownBits
This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit.

Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch.

I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases.

Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with.

Differential Revision: https://reviews.llvm.org/D32376

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301432 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-26 16:39:58 +00:00
Sanjay Patel
0f75548f9f [DAG] add FIXME comments for splat detection; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301403 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-26 13:27:57 +00:00
Sanjay Patel
2b2adc9567 [DAG] fix formatting of isConstantSplat(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301366 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-25 23:33:28 +00:00
Simon Pilgrim
5c072c6410 [SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301303 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-25 12:29:07 +00:00
Renato Golin
d907744fff Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."
This reverts commit r301105, 4, 3 and 1, as a follow up of the previous
revert, which broke even more bots.

For reference:
Revert "[APInt] Use operator<<= where possible. NFC"
Revert "[APInt] Use operator<<= instead of shl where possible. NFC"
Revert "[APInt] Use ashInPlace where possible."

PR32754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 12:15:30 +00:00
Craig Topper
e3ba850127 [APInt] Use operator<<= where possible. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301104 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 05:43:02 +00:00
Craig Topper
1ea7b69466 [APInt] Use ashInPlace where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301101 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 03:45:59 +00:00
Benjamin Kramer
4b3567dbfc [Recycler] Add asan/msan annotations.
This enables use after free and uninit memory checking for memory
returned by a recycler. SelectionDAG currently relies on the opcode of a
free'd node being ISD::DELETED_NODE, so poke a hole in the asan poison
for SDNode opcodes. This means that we won't find some issues, but only
in SDag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300868 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 18:29:37 +00:00
Yaxun Liu
1baa360f32 CodeGen: Let frame index value type match alloca addr space
Recently alloca address space has been added to data layout. Due to this
change, pointer returned by alloca may have different size as pointer in
address space 0.

However, currently the value type of frame index is assumed to be of the
same size as pointer in address space 0.

This patch fixes that.

Most targets assume alloca returning pointer in address space 0, which
is the default alloca address space. Therefore it is NFC for them.

AMDGCN target with amdgiz environment requires this change since it
assumes alloca returning pointer to addr space 5 and its size is 32,
which is different from the size of pointer in addr space 0 which is 64.

Differential Revision: https://reviews.llvm.org/D32021


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300864 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 18:15:34 +00:00
Craig Topper
54f0462d2b [APInt] Rename getSignBit to getSignMask
getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask.

Differential Revision: https://reviews.llvm.org/D32108



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300856 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 16:56:25 +00:00
Amara Emerson
780f89d961 [MVT][SVE] Scalable vector MVTs (1/3)
This patch adds a few helper functions to obtain new vector
value types based on existing ones without needing to care
about whether they are scalable or not.

I've confined their use to a few common locations right now,
and targets that don't have scalable vectors should never
need to care about these.

Patch by Graham Hunter.

Differential Revision: https://reviews.llvm.org/D32017



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300838 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 13:08:17 +00:00
Galina Kistanova
6b92d164d6 Temporarily revert r299221 to fix nondeterminism in ThinLTO builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300783 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 23:16:14 +00:00
Craig Topper
3bebc1eb2e [APInt] Cast calls to add/sub/mul overflow methods to void if only their overflow bool out param is used.
This is preparation for a clang change to improve the [[nodiscard]] warning to not be ignored on methods that return a class marked [[nodiscard]] that are defined in the class itself. See D32207.

We should consider adding wrapper methods to APInt that return the overflow flag directly and discard the APInt result. This would eliminate the void casts and the need to create a bool before the call to pass to the out param.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 21:09:45 +00:00
Craig Topper
df22034939 [APInt] Use lshrInPlace to replace lshr where possible
This patch uses lshrInPlace to replace code where the object that lshr is called on is being overwritten with the result.

This adds an lshrInPlace(const APInt &) version as well.

Differential Revision: https://reviews.llvm.org/D32155




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-18 17:14:21 +00:00
Jonas Paulsson
ff14b9ebc7 [SelectionDAG] NFC patch removing a redundant check.
Since the BUILD_VECTOR has already been checked by
isBuildVectorOfConstantSDNodes() in SelectionDAG::getNode() for a
SIGN_EXTEND_INREG, it can be assumed that Op is always either undef or a
ConstantSDNode, and Ops.size() will always equal VT.getVectorNumElements().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299647 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 13:00:37 +00:00
Jonas Paulsson
4a035b600a [DAGCombiner] Don't make a BUILD_VECTOR with operands of illegal type.
When DAGCombiner visits a SIGN_EXTEND_INREG of a BUILD_VECTOR with
constant operands, a new BUILD_VECTOR node will be created transformed
constants.

Llvm-stress found a case where the new BUILD_VECTOR had constant operands
of an illegal type, because the (legal) element type is in fact not a legal
scalar type.

This patch changes this so that the new BUILD_VECTOR has the same operand
type as the old one.

Review: Eli Friedman, Nirav Dave
https://bugs.llvm.org//show_bug.cgi?id=32422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:45:37 +00:00
Simon Pilgrim
40593e05da [DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ASHR and INSERT_VECTOR_ELT
Followup to D31311

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299221 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31 14:21:50 +00:00
Simon Pilgrim
9fc191fd45 [DAGCombiner] Add vector demanded elements support to ComputeNumSignBits
Currently ComputeNumSignBits returns the minimum number of sign bits for all elements of vector data, when we may only be interested in one/some of the elements.

This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original ComputeNumSignBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.

I've only added support for BUILD_VECTOR and EXTRACT_VECTOR_ELT so far, all others will default to demanding all elements but can be updated in due course.

Followup to D25691.

Differential Revision: https://reviews.llvm.org/D31311

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299219 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31 13:54:09 +00:00
Simon Pilgrim
07898901df [DAGCombiner] Add vector demanded elements support to computeKnownBitsForTargetNode
Follow up to D25691, this sets up the plumbing necessary to support vector demanded elements support in known bits calculations in target nodes.

Differential Revision: https://reviews.llvm.org/D31249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299201 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31 11:24:16 +00:00
Ahmed Bougacha
04dea7e088 [CodeGen] Pass SDAG an ORE, and replace FastISel stats with remarks.
In the long-term, we want to replace statistics with something
finer-grained that lets us gather per-function data.
Remarks are that replacement.

Create an ORE instance in SelectionDAGISel, and pass it to
SelectionDAG.

SelectionDAG was used so that we can emit remarks from all
SelectionDAG-related code, including TargetLowering and DAGCombiner.
This isn't used in the current patch but Adam tells me he's interested
for the fp-contract combines.

Use the ORE instance to emit FastISel failures as remarks (instead of
the mix of dbgs() dumps and statistics that we currently have).

Eventually, we want to have an API that tells us whether remarks are
enabled (http://llvm.org/PR32352) so that we don't emit expensive
remarks (in this case, dumping IR) when it's not needed.  For now, use
'isEnabled' as a crude replacement.

This does mean that the replacement for '-fast-isel-verbose' is now
'-pass-remarks-missed=isel'.  Additionally, clang users also need to
enable remark diagnostics, using '-Rpass-missed=isel'.

This also removes '-fast-isel-verbose2': there are no static statistics
that we want to only enable in asserts builds, so we can always use
the remarks regardless of the build type.

Differential Revision: https://reviews.llvm.org/D31405

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299093 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-30 17:49:58 +00:00
Sanjay Patel
bdb8cec802 [DAG] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298950 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-28 22:25:25 +00:00
Simon Pilgrim
a31a2f7e7b Apply clang-format as commented in D31311. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298751 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-24 23:47:41 +00:00
Simon Pilgrim
33e1fb27fd Fix constant folding of fp2int to large integers
We make the assumption in most of our constant folding code that a fp2int will target an integer of 128-bits or less, calling the APFloat::convertToInteger with only uint64_t[2] of raw bits for the result.

Fuzz testing (PR24662) showed that we don't handle other cases at all, resulting in stack overflows and all sorts of crashes.

This patch uses the APSInt version of APFloat::convertToInteger instead to better handle such cases.

Differential Revision: https://reviews.llvm.org/D31074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298226 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-19 16:50:25 +00:00
Nirav Dave
11fdc7845a Make library calls sensitive to regparm module flag (Fixes PR3997).
Reviewers: mkuper, rnk

Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D27050

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298179 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-18 00:44:07 +00:00
Eli Friedman
87552d6290 [SelectionDAG] Remove redundant stores more aggressively.
Handle TokenFactors more aggressively in
SDValue::reachesChainWithoutSideEffects.  This isn't really a
very effective change anymore because of other changes to
chain handling, but it's a cheap check, and the expanded
comments are still useful.

It might be possible to loosen the hasOneUse() requirement with a
deeper analysis, but a naive implementation of that check would be
expensive.

Differential Revision: https://reviews.llvm.org/D29845




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298156 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-17 22:15:50 +00:00
Simon Pilgrim
20afc5b611 [SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298108 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-17 17:45:36 +00:00
Craig Topper
01c2f41249 [CodeGen] Use APInt::setLowBits/setHighBits/setBitsFrom in more places
This patch replaces ORs with getHighBits/getLowBits etc. with setLowBits/setHighBits/setBitsFrom.

In a few of the places we weren't ORing, but the KnownZero/KnownOne vectors were already initialized to zero. We exploit this in most places already there were just some that were inconsistent.

Differential Revision: https://reviews.llvm.org/D30965




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297860 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-15 16:53:53 +00:00
Simon Pilgrim
a1d8ce502d [SelectionDAG] Support BUILD_VECTOR implicit truncation in SelectionDAG::ComputeNumSignBits (PR32273)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297852 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-15 16:22:24 +00:00