Matthew Simpson 6523b45d2e [ARM/AArch64] Support wide interleaved accesses ...

This patch teaches (ARM|AArch64)ISelLowering.cpp to match illegal vector types
to interleaved access intrinsics as long as the types are multiples of the
vector register width. A "wide" access will now be mapped to multiple
interleave intrinsics similar to the way in which non-interleaved accesses with
illegal types are legalized into multiple accesses. I'll update the associated
TTI costs (in getInterleavedMemoryOpCost) as a follow-on.

Differential Revision: https://reviews.llvm.org/D29466

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296750 91177308-0d34-0410-b5e6-96231b3b80d8

2017-03-02 15:11:20 +00:00

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interleaved-accesses-extract-user.ll

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interleaved-accesses.ll

[ARM/AArch64] Support wide interleaved accesses

2017-03-02 15:11:20 +00:00

lit.local.cfg

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