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64ed61ca6b
We now emit the compiler generated divide by zero check that was needed for the MSVC routines. We construct a psuedo-instruction for the DBZ check as the operation requires splitting up the BB. For the 64-bit operations, we need to custom expand the node as we need to insert the DBZ check and then emit the libcall to the appropriate name. Because this is target specific, it seemed better to reproduce the expansion operation from the target-agnostic type legalization rather than sink this there to avoid the duplication. The division library calls now match MSVC semantically. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248561 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.0 KiB
LLVM
50 lines
1.0 KiB
LLVM
; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
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; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
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define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = sdiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: sdiv32:
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; CHECK: cbz r0
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; CHECK: bl __rt_sdiv
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
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entry:
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%div = udiv i32 %divident, %divisor
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ret i32 %div
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}
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; CHECK-LABEL: udiv32:
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; CHECK: cbz r0
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; CHECK: bl __rt_udiv
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = sdiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: sdiv64:
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; CHECK: orr.w r12, r0, r1
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; CHECK-NEXT: cbz r12
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; CHECK: bl __rt_sdiv64
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; CHECK: udf.w #249
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define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
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entry:
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%div = udiv i64 %divident, %divisor
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ret i64 %div
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}
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; CHECK-LABEL: udiv64:
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; CHECK: orr.w r12, r0, r1
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; CHECK-NEXT: cbz r12
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; CHECK: bl __rt_udiv64
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; CHECK: udf.w #249
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