Alex Lorenz eecbba2d64 Fix PR 24724 - The implicit register verifier shouldn't assume certain operand ...

order.

The implicit register verifier in the MIR parser should only check if the
instruction's default implicit operands are present in the instruction. It
should not check the order in which they occur.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247283 91177308-0d34-0410-b5e6-96231b3b80d8

2015-09-10 14:04:34 +00:00

..

AArch64

MIR Serialization: Use the global value syntax for global value memory operands.

2015-08-20 00:20:03 +00:00

AMDGPU

MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

2015-08-13 23:10:16 +00:00

ARM

MIR Serialization: Serialize the '.cfi_same_value' CFI directive.

2015-08-14 21:55:58 +00:00

Generic

MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

2015-08-13 23:10:16 +00:00

Mips

MIR Serialization: Change syntax for the call entry pseudo source values.

2015-08-20 00:12:57 +00:00

NVPTX

MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

2015-08-13 23:10:16 +00:00

PowerPC

Fix PR 24724 - The implicit register verifier shouldn't assume certain operand

2015-09-10 14:04:34 +00:00

X86

Fix PR 24724 - The implicit register verifier shouldn't assume certain operand

2015-09-10 14:04:34 +00:00

lit.local.cfg

Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).

2015-05-27 18:02:19 +00:00