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- Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
14 lines
431 B
LLVM
14 lines
431 B
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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%struct.int32x4_t = type { <4 x i32> }
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define arm_apcscc void @t() nounwind {
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entry:
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; CHECK: vmov.I64 q15, #0
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; CHECK: vmov.32 d30[0], r0
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; CHECK: vmov q0, q15
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%tmp = alloca %struct.int32x4_t, align 16
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call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
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ret void
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}
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