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a007516937
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12 and z13. This scheduler optimizes decoder grouping and balances processor resources (including side steering the FPd unit instructions). The SystemZHazardRecognizer keeps track of the scheduling state, which can be dumped with -debug-only=misched. Reviers: Ulrich Weigand, Andrew Trick. https://reviews.llvm.org/D17260 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284704 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.1 KiB
TableGen
71 lines
2.1 KiB
TableGen
//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Scheduler resources
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// These three resources are used to express decoder grouping rules.
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// The number of decoder slots needed by an instructions is normally
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// one. For a cracked instruction (BeginGroup && !EndGroup) it is
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// two. Expanded instructions (BeginGroup && EndGroup) group alone.
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def GroupAlone : SchedWrite;
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def BeginGroup : SchedWrite;
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def EndGroup : SchedWrite;
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// Latencies, to make code a bit neater. If more than one resource is
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// used for an instruction, the greatest latency (not the sum) will be
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// output by Tablegen. Therefore, in such cases one of these resources
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// is needed.
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def Lat2 : SchedWrite;
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def Lat3 : SchedWrite;
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def Lat4 : SchedWrite;
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def Lat5 : SchedWrite;
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def Lat6 : SchedWrite;
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def Lat7 : SchedWrite;
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def Lat8 : SchedWrite;
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def Lat9 : SchedWrite;
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def Lat10 : SchedWrite;
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def Lat11 : SchedWrite;
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def Lat12 : SchedWrite;
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def Lat15 : SchedWrite;
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def Lat20 : SchedWrite;
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def Lat30 : SchedWrite;
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// Fixed-point
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def FXa : SchedWrite;
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def FXb : SchedWrite;
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def FXU : SchedWrite;
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// Load/store unit
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def LSU : SchedWrite;
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// Model a return without latency, otherwise if-converter will model
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// extra cost and abort (currently there is an assert that checks that
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// all instructions have at least one uop).
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def LSU_lat1 : SchedWrite;
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// Floating point unit (zEC12 and earlier)
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def FPU : SchedWrite;
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// Vector sub units (z13)
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def VecBF : SchedWrite;
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def VecDF : SchedWrite;
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def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
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def VecMul : SchedWrite;
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def VecStr : SchedWrite;
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def VecXsPm : SchedWrite;
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// Virtual branching unit
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def VBU : SchedWrite;
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include "SystemZScheduleZ13.td"
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include "SystemZScheduleZEC12.td"
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include "SystemZScheduleZ196.td"
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