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https://github.com/RPCSX/llvm.git
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acc2c1d71d
Summary: In SelectionDAG, when a store is immediately chained to another store to the same address, elide the first store as it has no observable effects. This is causes small improvements dealing with intrinsics lowered to stores. Test notes: * Many testcases overwrite store addresses multiple times and needed minor changes, mainly making stores volatile to prevent the optimization from optimizing the test away. * Many X86 test cases optimized out instructions associated with associated with va_start. * Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has dependencies to check and can probably be removed and potentially replaced with another test. Reviewers: rnk, john.brawn Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33206 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303198 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.3 KiB
LLVM
50 lines
1.3 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
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target triple = "msp430---elf"
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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declare void @llvm.va_copy(i8*, i8*) nounwind
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define void @va_start(i16 %a, ...) nounwind {
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entry:
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; CHECK-LABEL: va_start:
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; CHECK: sub.w #2, r1
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%vl = alloca i8*, align 2
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%vl1 = bitcast i8** %vl to i8*
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; CHECK-NEXT: mov.w r1, [[REG:r[0-9]+]]
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; CHECK-NEXT: add.w #6, [[REG]]
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; CHECK-NEXT: mov.w [[REG]], 0(r1)
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call void @llvm.va_start(i8* %vl1)
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call void @llvm.va_end(i8* %vl1)
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ret void
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}
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define i16 @va_arg(i8* %vl) nounwind {
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entry:
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; CHECK-LABEL: va_arg:
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%vl.addr = alloca i8*, align 2
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store i8* %vl, i8** %vl.addr, align 2
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; CHECK: mov.w r12, [[REG:r[0-9]+]]
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; CHECK-NEXT: add.w #2, [[REG]]
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; CHECK-NEXT: mov.w [[REG]], 0(r1)
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%0 = va_arg i8** %vl.addr, i16
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; CHECK-NEXT: mov.w 0(r12), r12
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ret i16 %0
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}
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define void @va_copy(i8* %vl) nounwind {
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entry:
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; CHECK-LABEL: va_copy:
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%vl.addr = alloca i8*, align 2
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%vl2 = alloca i8*, align 2
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; CHECK: mov.w r12, 2(r1)
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store i8* %vl, i8** %vl.addr, align 2
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%0 = bitcast i8** %vl2 to i8*
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%1 = bitcast i8** %vl.addr to i8*
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; CHECK-NEXT: mov.w r12, 0(r1)
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call void @llvm.va_copy(i8* %0, i8* %1)
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ret void
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}
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