Hal Finkel f606a6ed99 [PowerPC] Enable interleaved-access vectorization ...

This adds a basic cost model for interleaved-access vectorization (and a better
default for shuffles), and enables interleaved-access vectorization by default.
The relevant difference from the default cost model for interleaved-access
vectorization, is that on PPC, the shuffles that end up being used are *much*
cheaper than modeling the process with insert/extract pairs (which are
quite expensive, especially on older cores).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246824 91177308-0d34-0410-b5e6-96231b3b80d8

2015-09-04 00:10:41 +00:00

..

agg-interleave-a2.ll

[PowerPC] Always use aggressive interleaving on the A2

2015-09-03 23:23:00 +00:00

large-loop-rdx.ll

Do not restrict interleaved unrolling to small loops, depending on the target.

2015-03-06 23:12:04 +00:00

lit.local.cfg

…

small-loop-rdx.ll

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

stride-vectorization.ll

[PowerPC] Enable interleaved-access vectorization

2015-09-04 00:10:41 +00:00

vsx-tsvc-s173.ll

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00