#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
#
#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING V4FMADDPS (V4FMADDPS-512-1)
{
ICLASS:      V4FMADDPS
CPL:         3
CATEGORY:    AVX512_4FMAPS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4FMAPS_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: N
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32
IFORM:       V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING V4FMADDSS (V4FMADDSS-128-1)
{
ICLASS:      V4FMADDSS
CPL:         3
CATEGORY:    AVX512_4FMAPS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4FMAPS_SCALAR
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: N
ATTRIBUTES:  DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32
IFORM:       V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING V4FNMADDPS (V4FNMADDPS-512-1)
{
ICLASS:      V4FNMADDPS
CPL:         3
CATEGORY:    AVX512_4FMAPS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4FMAPS_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: N
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32
IFORM:       V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING V4FNMADDSS (V4FNMADDSS-128-1)
{
ICLASS:      V4FNMADDSS
CPL:         3
CATEGORY:    AVX512_4FMAPS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4FMAPS_SCALAR
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: N
ATTRIBUTES:  DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32
IFORM:       V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VP4DPWSSD (VP4DPWSSD-512-1)
{
ICLASS:      VP4DPWSSD
CPL:         3
CATEGORY:    AVX512_4VNNIW
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4VNNIW_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: N
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 
PATTERN:    EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:i16
IFORM:       VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512
}


# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1)
{
ICLASS:      VP4DPWSSDS
CPL:         3
CATEGORY:    AVX512_4VNNIW
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4VNNIW_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: N
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 
PATTERN:    EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:i16
IFORM:       VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512
}


