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#Copyright (c) 2016 Intel Corporation
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KNC_VMODRM()::
 MOD=0b00 KNC_VSIB()             | 
 MOD=0b01 KNC_VSIB() MEMDISP8()  | 
 MOD=0b10 KNC_VSIB() MEMDISP32() | 


KNC_VSIB()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE()  | INDEX=KNC_VSIB_INDEX()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE()  | INDEX=KNC_VSIB_INDEX()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE()  | INDEX=KNC_VSIB_INDEX()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE()  | INDEX=KNC_VSIB_INDEX()  SCALE=8  


xed_reg_enum_t KNC_VSIB_INDEX()::
VEXDEST4=0 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_ZMM0
VEXDEST4=0 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_ZMM1
VEXDEST4=0 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_ZMM2
VEXDEST4=0 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_ZMM3
VEXDEST4=0 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_ZMM4
VEXDEST4=0 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_ZMM5
VEXDEST4=0 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_ZMM6
VEXDEST4=0 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_ZMM7
VEXDEST4=0 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_ZMM8
VEXDEST4=0 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_ZMM9
VEXDEST4=0 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_ZMM10
VEXDEST4=0 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_ZMM11
VEXDEST4=0 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_ZMM12
VEXDEST4=0 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_ZMM13
VEXDEST4=0 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_ZMM14
VEXDEST4=0 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_ZMM15
VEXDEST4=1 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_ZMM16
VEXDEST4=1 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_ZMM17
VEXDEST4=1 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_ZMM18
VEXDEST4=1 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_ZMM19
VEXDEST4=1 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_ZMM20
VEXDEST4=1 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_ZMM21
VEXDEST4=1 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_ZMM22
VEXDEST4=1 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_ZMM23
VEXDEST4=1 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_ZMM24
VEXDEST4=1 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_ZMM25
VEXDEST4=1 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_ZMM26
VEXDEST4=1 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_ZMM27
VEXDEST4=1 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_ZMM28
VEXDEST4=1 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_ZMM29
VEXDEST4=1 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_ZMM30
VEXDEST4=1 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_ZMM31


KNC_VSIB_BASE()::
REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()

# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8  and DISP32 
REXB=0 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()

REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()

# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8  and DISP32 
REXB=1 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()

REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()



  
  



