#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
#
#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1)
{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
IFORM:       VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}


# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1)
{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
IFORM:       VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}

{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}


# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1)
{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPMADD52HUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1)
{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
IFORM:       VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}


# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1)
{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
IFORM:       VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}

{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}


# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1)
{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPMADD52LUQ
CPL:         3
CATEGORY:    IFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_IFMA_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


