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#Copyright (c) 2016 Intel Corporation
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# VGPRy_N is used by AMD XOP only but the lower level stuff is used by HSW NI

xed_reg_enum_t VGPRy_N()::   
EOSZ=1 | OUTREG=VGPR32_N() 
EOSZ=2 | OUTREG=VGPR32_N()
EOSZ=3 | OUTREG=VGPR64_N() 

xed_reg_enum_t VGPR32_N()::
mode16 | OUTREG=VGPR32_N_32()
mode32 | OUTREG=VGPR32_N_32()
mode64 | OUTREG=VGPR32_N_64()

xed_reg_enum_t VGPR32_B()::
mode16 | OUTREG=VGPR32_B_32()
mode32 | OUTREG=VGPR32_B_32()
mode64 | OUTREG=VGPR32_B_64()

xed_reg_enum_t VGPR32_R()::
mode16 | OUTREG=VGPR32_R_32()
mode32 | OUTREG=VGPR32_R_32()
mode64 | OUTREG=VGPR32_R_64()






xed_reg_enum_t VGPR32_N_32():: # IGNORES UPPER BIT  (VEXDEST3) IN 32b mode
VEXDEST210=7   | OUTREG=XED_REG_EAX
VEXDEST210=6   | OUTREG=XED_REG_ECX
VEXDEST210=5   | OUTREG=XED_REG_EDX
VEXDEST210=4   | OUTREG=XED_REG_EBX
VEXDEST210=3   | OUTREG=XED_REG_ESP
VEXDEST210=2   | OUTREG=XED_REG_EBP
VEXDEST210=1   | OUTREG=XED_REG_ESI
VEXDEST210=0   | OUTREG=XED_REG_EDI

xed_reg_enum_t VGPR32_N_64():: # IGNORES UPPER BIT  (VEXDEST3) IN 32b mode
VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_EAX
VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_ECX
VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_EDX
VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_EBX
VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_ESP
VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_EBP
VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_ESI
VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_EDI
VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8D
VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9D
VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10D
VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11D
VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12D
VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13D
VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14D
VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15D


xed_reg_enum_t VGPR64_N()::
VEXDEST3=1 VEXDEST210=7  | OUTREG=XED_REG_RAX
VEXDEST3=1 VEXDEST210=6  | OUTREG=XED_REG_RCX
VEXDEST3=1 VEXDEST210=5  | OUTREG=XED_REG_RDX
VEXDEST3=1 VEXDEST210=4  | OUTREG=XED_REG_RBX
VEXDEST3=1 VEXDEST210=3  | OUTREG=XED_REG_RSP
VEXDEST3=1 VEXDEST210=2  | OUTREG=XED_REG_RBP
VEXDEST3=1 VEXDEST210=1  | OUTREG=XED_REG_RSI
VEXDEST3=1 VEXDEST210=0  | OUTREG=XED_REG_RDI
VEXDEST3=0 VEXDEST210=7  | OUTREG=XED_REG_R8
VEXDEST3=0 VEXDEST210=6  | OUTREG=XED_REG_R9
VEXDEST3=0 VEXDEST210=5  | OUTREG=XED_REG_R10
VEXDEST3=0 VEXDEST210=4  | OUTREG=XED_REG_R11
VEXDEST3=0 VEXDEST210=3  | OUTREG=XED_REG_R12
VEXDEST3=0 VEXDEST210=2  | OUTREG=XED_REG_R13
VEXDEST3=0 VEXDEST210=1  | OUTREG=XED_REG_R14
VEXDEST3=0 VEXDEST210=0  | OUTREG=XED_REG_R15


###########

xed_reg_enum_t VGPR32_R_32():: # IGNORES  (REXR) IN 32b mode
REG=0   | OUTREG=XED_REG_EAX
REG=1   | OUTREG=XED_REG_ECX
REG=2   | OUTREG=XED_REG_EDX
REG=3   | OUTREG=XED_REG_EBX
REG=4   | OUTREG=XED_REG_ESP
REG=5   | OUTREG=XED_REG_EBP
REG=6   | OUTREG=XED_REG_ESI
REG=7   | OUTREG=XED_REG_EDI


xed_reg_enum_t VGPR32_R_64()::
REXR=0 REG=0  | OUTREG=XED_REG_EAX
REXR=0 REG=1  | OUTREG=XED_REG_ECX
REXR=0 REG=2  | OUTREG=XED_REG_EDX
REXR=0 REG=3  | OUTREG=XED_REG_EBX
REXR=0 REG=4  | OUTREG=XED_REG_ESP
REXR=0 REG=5  | OUTREG=XED_REG_EBP
REXR=0 REG=6  | OUTREG=XED_REG_ESI
REXR=0 REG=7  | OUTREG=XED_REG_EDI
REXR=1 REG=0  | OUTREG=XED_REG_R8D
REXR=1 REG=1  | OUTREG=XED_REG_R9D
REXR=1 REG=2  | OUTREG=XED_REG_R10D
REXR=1 REG=3  | OUTREG=XED_REG_R11D
REXR=1 REG=4  | OUTREG=XED_REG_R12D
REXR=1 REG=5  | OUTREG=XED_REG_R13D
REXR=1 REG=6  | OUTREG=XED_REG_R14D
REXR=1 REG=7  | OUTREG=XED_REG_R15D

xed_reg_enum_t VGPR64_R()::
REXR=0 REG=0  | OUTREG=XED_REG_RAX
REXR=0 REG=1  | OUTREG=XED_REG_RCX
REXR=0 REG=2  | OUTREG=XED_REG_RDX
REXR=0 REG=3  | OUTREG=XED_REG_RBX
REXR=0 REG=4  | OUTREG=XED_REG_RSP
REXR=0 REG=5  | OUTREG=XED_REG_RBP
REXR=0 REG=6  | OUTREG=XED_REG_RSI
REXR=0 REG=7  | OUTREG=XED_REG_RDI
REXR=1 REG=0  | OUTREG=XED_REG_R8
REXR=1 REG=1  | OUTREG=XED_REG_R9
REXR=1 REG=2  | OUTREG=XED_REG_R10
REXR=1 REG=3  | OUTREG=XED_REG_R11
REXR=1 REG=4  | OUTREG=XED_REG_R12
REXR=1 REG=5  | OUTREG=XED_REG_R13
REXR=1 REG=6  | OUTREG=XED_REG_R14
REXR=1 REG=7  | OUTREG=XED_REG_R15


###################

xed_reg_enum_t VGPR32_B_32()::  # IGNORES  (REXB) IN 32b mode
RM=0   | OUTREG=XED_REG_EAX
RM=1   | OUTREG=XED_REG_ECX
RM=2   | OUTREG=XED_REG_EDX
RM=3   | OUTREG=XED_REG_EBX
RM=4   | OUTREG=XED_REG_ESP
RM=5   | OUTREG=XED_REG_EBP
RM=6   | OUTREG=XED_REG_ESI
RM=7   | OUTREG=XED_REG_EDI


xed_reg_enum_t VGPR32_B_64()::
REXB=0 RM=0  | OUTREG=XED_REG_EAX
REXB=0 RM=1  | OUTREG=XED_REG_ECX
REXB=0 RM=2  | OUTREG=XED_REG_EDX
REXB=0 RM=3  | OUTREG=XED_REG_EBX
REXB=0 RM=4  | OUTREG=XED_REG_ESP
REXB=0 RM=5  | OUTREG=XED_REG_EBP
REXB=0 RM=6  | OUTREG=XED_REG_ESI
REXB=0 RM=7  | OUTREG=XED_REG_EDI
REXB=1 RM=0  | OUTREG=XED_REG_R8D
REXB=1 RM=1  | OUTREG=XED_REG_R9D
REXB=1 RM=2  | OUTREG=XED_REG_R10D
REXB=1 RM=3  | OUTREG=XED_REG_R11D
REXB=1 RM=4  | OUTREG=XED_REG_R12D
REXB=1 RM=5  | OUTREG=XED_REG_R13D
REXB=1 RM=6  | OUTREG=XED_REG_R14D
REXB=1 RM=7  | OUTREG=XED_REG_R15D

xed_reg_enum_t VGPR64_B()::
REXB=0 RM=0  | OUTREG=XED_REG_RAX
REXB=0 RM=1  | OUTREG=XED_REG_RCX
REXB=0 RM=2  | OUTREG=XED_REG_RDX
REXB=0 RM=3  | OUTREG=XED_REG_RBX
REXB=0 RM=4  | OUTREG=XED_REG_RSP
REXB=0 RM=5  | OUTREG=XED_REG_RBP
REXB=0 RM=6  | OUTREG=XED_REG_RSI
REXB=0 RM=7  | OUTREG=XED_REG_RDI
REXB=1 RM=0  | OUTREG=XED_REG_R8
REXB=1 RM=1  | OUTREG=XED_REG_R9
REXB=1 RM=2  | OUTREG=XED_REG_R10
REXB=1 RM=3  | OUTREG=XED_REG_R11
REXB=1 RM=4  | OUTREG=XED_REG_R12
REXB=1 RM=5  | OUTREG=XED_REG_R13
REXB=1 RM=6  | OUTREG=XED_REG_R14
REXB=1 RM=7  | OUTREG=XED_REG_R15


