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#Copyright (c) 2016 Intel Corporation
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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING VADDPD (VADDPD-512-1)
{
ICLASS:      VADDPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VADDPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VADDPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VADDPS (VADDPS-512-1)
{
ICLASS:      VADDPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VADDPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VADDPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VADDSD (VADDSD-128-1)
{
ICLASS:      VADDSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VADDSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VADDSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VADDSS (VADDSS-128-1)
{
ICLASS:      VADDSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VADDSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VADDSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VALIGND (VALIGND-512-1)
{
ICLASS:      VALIGND
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VALIGND
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VALIGNQ (VALIGNQ-512-1)
{
ICLASS:      VALIGNQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VALIGNQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VBLENDMPD (VBLENDMPD-512-1)
{
ICLASS:      VBLENDMPD
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MASK_AS_CONTROL 
PATTERN:    EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VBLENDMPD
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VBLENDMPS (VBLENDMPS-512-1)
{
ICLASS:      VBLENDMPS
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MASK_AS_CONTROL 
PATTERN:    EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VBLENDMPS
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1)
{
ICLASS:      VBROADCASTF32X4
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32
IFORM:       VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1)
{
ICLASS:      VBROADCASTF64X4
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64
IFORM:       VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1)
{
ICLASS:      VBROADCASTI32X4
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32
IFORM:       VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1)
{
ICLASS:      VBROADCASTI64X4
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64
IFORM:       VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VBROADCASTSD (VBROADCASTSD-512-1)
{
ICLASS:      VBROADCASTSD
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 
PATTERN:    EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_TUPLE1()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64
IFORM:       VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VBROADCASTSD (VBROADCASTSD-512-2)
{
ICLASS:      VBROADCASTSD
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64
IFORM:       VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512
}


# EMITTING VBROADCASTSS (VBROADCASTSS-512-1)
{
ICLASS:      VBROADCASTSS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 
PATTERN:    EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_TUPLE1()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32
IFORM:       VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VBROADCASTSS (VBROADCASTSS-512-2)
{
ICLASS:      VBROADCASTSS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32
IFORM:       VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512
}


# EMITTING VCMPPD (VCMPPD-512-1)
{
ICLASS:      VCMPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VCMPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VCMPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VCMPPS (VCMPPS-512-1)
{
ICLASS:      VCMPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VCMPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VCMPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VCMPSD (VCMPSD-128-1)
{
ICLASS:      VCMPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VCMPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VCMPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VCMPSS (VCMPSS-128-1)
{
ICLASS:      VCMPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VCMPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VCMPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VCOMISD (VCOMISD-128-1)
{
ICLASS:      VCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64
IFORM:       VCOMISD_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCOMISD_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_SCALAR 
PATTERN:    EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64
IFORM:       VCOMISD_XMMf64_MEMf64_AVX512
}


# EMITTING VCOMISS (VCOMISS-128-1)
{
ICLASS:      VCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32
IFORM:       VCOMISS_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCOMISS_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_SCALAR 
PATTERN:    EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32
IFORM:       VCOMISS_XMMf32_MEMf32_AVX512
}


# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1)
{
ICLASS:      VCOMPRESSPD
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
IFORM:       VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2)
{
ICLASS:      VCOMPRESSPD
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
IFORM:       VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1)
{
ICLASS:      VCOMPRESSPS
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
IFORM:       VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2)
{
ICLASS:      VCOMPRESSPS
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
IFORM:       VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1)
{
ICLASS:      VCVTDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 
PATTERN:    EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512
}


# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1)
{
ICLASS:      VCVTDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512
}


# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1)
{
ICLASS:      VCVTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTPD2PS (VCVTPD2PS-512-1)
{
ICLASS:      VCVTPD2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1)
{
ICLASS:      VCVTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTPH2PS (VCVTPH2PS-512-1)
{
ICLASS:      VCVTPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16
IFORM:       VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1)
{
ICLASS:      VCVTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2PD (VCVTPS2PD-512-1)
{
ICLASS:      VCVTPS2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 
PATTERN:    EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2PH (VCVTPS2PH-512-1)
{
ICLASS:      VCVTPS2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
IFORM:       VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VCVTPS2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
IFORM:       VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
}


# EMITTING VCVTPS2PH (VCVTPS2PH-512-2)
{
ICLASS:      VCVTPS2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E11NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
IFORM:       VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512
}


# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1)
{
ICLASS:      VCVTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTSD2SI (VCVTSD2SI-128-1)
{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM:       VCVTSD2SI_GPR32i32_MEMf64_AVX512
}


# EMITTING VCVTSD2SI (VCVTSD2SI-128-2)
{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
IFORM:       VCVTSD2SI_GPR64i64_MEMf64_AVX512
}


# EMITTING VCVTSD2SS (VCVTSD2SS-128-1)
{
ICLASS:      VCVTSD2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VCVTSD2USI (VCVTSD2USI-128-1)
{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM:       VCVTSD2USI_GPR32u32_MEMf64_AVX512
}


# EMITTING VCVTSD2USI (VCVTSD2USI-128-2)
{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
IFORM:       VCVTSD2USI_GPR64u64_MEMf64_AVX512
}


# EMITTING VCVTSI2SD (VCVTSI2SD-128-1)
{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
IFORM:       VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
}


# EMITTING VCVTSI2SD (VCVTSI2SD-128-2)
{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64
IFORM:       VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512
}


# EMITTING VCVTSI2SS (VCVTSI2SS-128-1)
{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
IFORM:       VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
}


# EMITTING VCVTSI2SS (VCVTSI2SS-128-2)
{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64
IFORM:       VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
}


# EMITTING VCVTSS2SD (VCVTSS2SD-128-1)
{
ICLASS:      VCVTSS2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VCVTSS2SI (VCVTSS2SI-128-1)
{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM:       VCVTSS2SI_GPR32i32_MEMf32_AVX512
}


# EMITTING VCVTSS2SI (VCVTSS2SI-128-2)
{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
IFORM:       VCVTSS2SI_GPR64i64_MEMf32_AVX512
}


# EMITTING VCVTSS2USI (VCVTSS2USI-128-1)
{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM:       VCVTSS2USI_GPR32u32_MEMf32_AVX512
}


# EMITTING VCVTSS2USI (VCVTSS2USI-128-2)
{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
IFORM:       VCVTSS2USI_GPR64u64_MEMf32_AVX512
}


# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1)
{
ICLASS:      VCVTTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTTPD2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1)
{
ICLASS:      VCVTTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
}

{
ICLASS:      VCVTTPD2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1)
{
ICLASS:      VCVTTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1)
{
ICLASS:      VCVTTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1)
{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM:       VCVTTSD2SI_GPR32i32_MEMf64_AVX512
}


# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2)
{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
IFORM:       VCVTTSD2SI_GPR64i64_MEMf64_AVX512
}


# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1)
{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM:       VCVTTSD2USI_GPR32u32_MEMf64_AVX512
}


# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2)
{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 
PATTERN:    EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
IFORM:       VCVTTSD2USI_GPR64u64_MEMf64_AVX512
}


# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1)
{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM:       VCVTTSS2SI_GPR32i32_MEMf32_AVX512
}


# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2)
{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
IFORM:       VCVTTSS2SI_GPR64i64_MEMf32_AVX512
}


# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1)
{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM:       VCVTTSS2USI_GPR32u32_MEMf32_AVX512
}


# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2)
{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 
PATTERN:    EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
IFORM:       VCVTTSS2USI_GPR64u64_MEMf32_AVX512
}


# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1)
{
ICLASS:      VCVTUDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
IFORM:       VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 
PATTERN:    EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512
}


# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1)
{
ICLASS:      VCVTUDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512
}


# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1)
{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
}


# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2)
{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512
}


# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1)
{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
}


# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2)
{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_GPR_READER 
PATTERN:    EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
}


# EMITTING VDIVPD (VDIVPD-512-1)
{
ICLASS:      VDIVPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VDIVPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VDIVPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VDIVPS (VDIVPS-512-1)
{
ICLASS:      VDIVPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VDIVPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VDIVPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VDIVSD (VDIVSD-128-1)
{
ICLASS:      VDIVSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VDIVSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VDIVSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VDIVSS (VDIVSS-128-1)
{
ICLASS:      VDIVSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VDIVSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VDIVSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VEXPANDPD (VEXPANDPD-512-1)
{
ICLASS:      VEXPANDPD
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
IFORM:       VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VEXPANDPD (VEXPANDPD-512-2)
{
ICLASS:      VEXPANDPD
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VEXPANDPS (VEXPANDPS-512-1)
{
ICLASS:      VEXPANDPS
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
IFORM:       VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VEXPANDPS (VEXPANDPS-512-2)
{
ICLASS:      VEXPANDPS
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1)
{
ICLASS:      VEXTRACTF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
IFORM:       VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}


# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2)
{
ICLASS:      VEXTRACTF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
IFORM:       VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
}


# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1)
{
ICLASS:      VEXTRACTF64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b
IFORM:       VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}


# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2)
{
ICLASS:      VEXTRACTF64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b
IFORM:       VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
}


# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1)
{
ICLASS:      VEXTRACTI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b
IFORM:       VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}


# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2)
{
ICLASS:      VEXTRACTI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b
IFORM:       VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
}


# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1)
{
ICLASS:      VEXTRACTI64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b
IFORM:       VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}


# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2)
{
ICLASS:      VEXTRACTI64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b
IFORM:       VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
}


# EMITTING VEXTRACTPS (VEXTRACTPS-128-1)
{
ICLASS:      VEXTRACTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 UIMM8() 
OPERANDS:    REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b
IFORM:       VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VEXTRACTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_STORE 
PATTERN:    EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128    NOEVSR  ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
OPERANDS:    MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b
IFORM:       VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512
}


# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1)
{
ICLASS:      VFIXUPIMMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1)
{
ICLASS:      VFIXUPIMMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1)
{
ICLASS:      VFIXUPIMMSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1)
{
ICLASS:      VFIXUPIMMSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VFIXUPIMMSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VFMADD132PD (VFMADD132PD-512-1)
{
ICLASS:      VFMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADD132PS (VFMADD132PS-512-1)
{
ICLASS:      VFMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMADD132SD (VFMADD132SD-128-1)
{
ICLASS:      VFMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMADD132SS (VFMADD132SS-128-1)
{
ICLASS:      VFMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMADD213PD (VFMADD213PD-512-1)
{
ICLASS:      VFMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADD213PS (VFMADD213PS-512-1)
{
ICLASS:      VFMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMADD213SD (VFMADD213SD-128-1)
{
ICLASS:      VFMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMADD213SS (VFMADD213SS-128-1)
{
ICLASS:      VFMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMADD231PD (VFMADD231PD-512-1)
{
ICLASS:      VFMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADD231PS (VFMADD231PS-512-1)
{
ICLASS:      VFMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMADD231SD (VFMADD231SD-128-1)
{
ICLASS:      VFMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMADD231SS (VFMADD231SS-128-1)
{
ICLASS:      VFMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1)
{
ICLASS:      VFMADDSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1)
{
ICLASS:      VFMADDSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1)
{
ICLASS:      VFMADDSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1)
{
ICLASS:      VFMADDSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1)
{
ICLASS:      VFMADDSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMADDSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1)
{
ICLASS:      VFMADDSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMADDSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB132PD (VFMSUB132PD-512-1)
{
ICLASS:      VFMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB132PS (VFMSUB132PS-512-1)
{
ICLASS:      VFMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB132SD (VFMSUB132SD-128-1)
{
ICLASS:      VFMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB132SS (VFMSUB132SS-128-1)
{
ICLASS:      VFMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB213PD (VFMSUB213PD-512-1)
{
ICLASS:      VFMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB213PS (VFMSUB213PS-512-1)
{
ICLASS:      VFMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB213SD (VFMSUB213SD-128-1)
{
ICLASS:      VFMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB213SS (VFMSUB213SS-128-1)
{
ICLASS:      VFMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB231PD (VFMSUB231PD-512-1)
{
ICLASS:      VFMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB231PS (VFMSUB231PS-512-1)
{
ICLASS:      VFMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUB231SD (VFMSUB231SD-128-1)
{
ICLASS:      VFMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFMSUB231SS (VFMSUB231SS-128-1)
{
ICLASS:      VFMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1)
{
ICLASS:      VFMSUBADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1)
{
ICLASS:      VFMSUBADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1)
{
ICLASS:      VFMSUBADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1)
{
ICLASS:      VFMSUBADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1)
{
ICLASS:      VFMSUBADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFMSUBADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1)
{
ICLASS:      VFMSUBADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFMSUBADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD132PD (VFNMADD132PD-512-1)
{
ICLASS:      VFNMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD132PS (VFNMADD132PS-512-1)
{
ICLASS:      VFNMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD132SD (VFNMADD132SD-128-1)
{
ICLASS:      VFNMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD132SS (VFNMADD132SS-128-1)
{
ICLASS:      VFNMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD213PD (VFNMADD213PD-512-1)
{
ICLASS:      VFNMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD213PS (VFNMADD213PS-512-1)
{
ICLASS:      VFNMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD213SD (VFNMADD213SD-128-1)
{
ICLASS:      VFNMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD213SS (VFNMADD213SS-128-1)
{
ICLASS:      VFNMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD231PD (VFNMADD231PD-512-1)
{
ICLASS:      VFNMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMADD231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD231PS (VFNMADD231PS-512-1)
{
ICLASS:      VFNMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMADD231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMADD231SD (VFNMADD231SD-128-1)
{
ICLASS:      VFNMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMADD231SS (VFNMADD231SS-128-1)
{
ICLASS:      VFNMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1)
{
ICLASS:      VFNMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB132PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1)
{
ICLASS:      VFNMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB132PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1)
{
ICLASS:      VFNMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1)
{
ICLASS:      VFNMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1)
{
ICLASS:      VFNMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB213PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1)
{
ICLASS:      VFNMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB213PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1)
{
ICLASS:      VFNMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1)
{
ICLASS:      VFNMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1)
{
ICLASS:      VFNMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VFNMSUB231PD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1)
{
ICLASS:      VFNMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VFNMSUB231PS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1)
{
ICLASS:      VFNMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VFNMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1)
{
ICLASS:      VFNMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VFNMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VGATHERDPD (VGATHERDPD-512-1)
{
ICLASS:      VGATHERDPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64
IFORM:       VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VGATHERDPS (VGATHERDPS-512-1)
{
ICLASS:      VGATHERDPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f32
IFORM:       VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512
}


# EMITTING VGATHERQPD (VGATHERQPD-512-1)
{
ICLASS:      VGATHERQPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64
IFORM:       VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VGATHERQPS (VGATHERQPS-512-1)
{
ICLASS:      VGATHERQPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32
IFORM:       VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512
}


# EMITTING VGETEXPPD (VGETEXPPD-512-1)
{
ICLASS:      VGETEXPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VGETEXPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VGETEXPPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VGETEXPPS (VGETEXPPS-512-1)
{
ICLASS:      VGETEXPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VGETEXPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VGETEXPPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VGETEXPSD (VGETEXPSD-128-1)
{
ICLASS:      VGETEXPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VGETEXPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VGETEXPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VGETEXPSS (VGETEXPSS-128-1)
{
ICLASS:      VGETEXPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VGETEXPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VGETEXPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VGETMANTPD (VGETMANTPD-512-1)
{
ICLASS:      VGETMANTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VGETMANTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VGETMANTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
}


# EMITTING VGETMANTPS (VGETMANTPS-512-1)
{
ICLASS:      VGETMANTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VGETMANTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VGETMANTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
}


# EMITTING VGETMANTSD (VGETMANTSD-128-1)
{
ICLASS:      VGETMANTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VGETMANTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VGETMANTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VGETMANTSS (VGETMANTSS-128-1)
{
ICLASS:      VGETMANTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VGETMANTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VGETMANTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1)
{
ICLASS:      VINSERTF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VINSERTF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b
IFORM:       VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1)
{
ICLASS:      VINSERTF64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
IFORM:       VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512
}

{
ICLASS:      VINSERTF64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b
IFORM:       VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1)
{
ICLASS:      VINSERTI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
IFORM:       VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512
}

{
ICLASS:      VINSERTI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b
IFORM:       VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1)
{
ICLASS:      VINSERTI64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512
}

{
ICLASS:      VINSERTI64X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_TUPLE4 
PATTERN:    EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_TUPLE4()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b
IFORM:       VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VINSERTPS (VINSERTPS-128-1)
{
ICLASS:      VINSERTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 MASK=0 UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VINSERTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_TUPLE1 
PATTERN:    EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0 MASK=0 UIMM8()  ESIZE_32_BITS() NELEM_TUPLE1()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VMAXPD (VMAXPD-512-1)
{
ICLASS:      VMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMAXPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VMAXPS (VMAXPS-512-1)
{
ICLASS:      VMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMAXPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VMAXSD (VMAXSD-128-1)
{
ICLASS:      VMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VMAXSS (VMAXSS-128-1)
{
ICLASS:      VMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VMINPD (VMINPD-512-1)
{
ICLASS:      VMINPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMINPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMINPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VMINPS (VMINPS-512-1)
{
ICLASS:      VMINPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMINPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMINPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VMINSD (VMINSD-128-1)
{
ICLASS:      VMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VMINSS (VMINSS-128-1)
{
ICLASS:      VMINSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMINSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMINSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VMOVAPD (VMOVAPD-512-1)
{
ICLASS:      VMOVAPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VMOVAPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
IFORM:       VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VMOVAPD (VMOVAPD-512-2)
{
ICLASS:      VMOVAPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
IFORM:       VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VMOVAPD (VMOVAPD-512-3)
{
ICLASS:      VMOVAPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
IFORM:       VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VMOVAPS (VMOVAPS-512-1)
{
ICLASS:      VMOVAPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VMOVAPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
IFORM:       VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VMOVAPS (VMOVAPS-512-2)
{
ICLASS:      VMOVAPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
IFORM:       VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VMOVAPS (VMOVAPS-512-3)
{
ICLASS:      VMOVAPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
IFORM:       VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VMOVD (VMOVD-128-1)
{
ICLASS:      VMOVD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
IFORM:       VMOVD_XMMu32_GPR32u32_AVX512
}

{
ICLASS:      VMOVD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER 
PATTERN:    EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
IFORM:       VMOVD_XMMu32_MEMu32_AVX512
}


# EMITTING VMOVD (VMOVD-128-2)
{
ICLASS:      VMOVD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
IFORM:       VMOVD_GPR32u32_XMMu32_AVX512
}

{
ICLASS:      VMOVD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_STORE 
PATTERN:    EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
OPERANDS:    MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
IFORM:       VMOVD_MEMu32_XMMu32_AVX512
}


# EMITTING VMOVDDUP (VMOVDDUP-512-1)
{
ICLASS:      VMOVDDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VMOVDDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MOVDDUP 
PATTERN:    EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_MOVDDUP()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
IFORM:       VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VMOVDQA32 (VMOVDQA32-512-1)
{
ICLASS:      VMOVDQA32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VMOVDQA32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
IFORM:       VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VMOVDQA32 (VMOVDQA32-512-2)
{
ICLASS:      VMOVDQA32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VMOVDQA32 (VMOVDQA32-512-3)
{
ICLASS:      VMOVDQA32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VMOVDQA64 (VMOVDQA64-512-1)
{
ICLASS:      VMOVDQA64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VMOVDQA64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
IFORM:       VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VMOVDQA64 (VMOVDQA64-512-2)
{
ICLASS:      VMOVDQA64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VMOVDQA64 (VMOVDQA64-512-3)
{
ICLASS:      VMOVDQA64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1
REAL_OPCODE: Y
ATTRIBUTES:   REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VMOVDQU32 (VMOVDQU32-512-1)
{
ICLASS:      VMOVDQU32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VMOVDQU32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
IFORM:       VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VMOVDQU32 (VMOVDQU32-512-2)
{
ICLASS:      VMOVDQU32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VMOVDQU32 (VMOVDQU32-512-3)
{
ICLASS:      VMOVDQU32
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VMOVDQU64 (VMOVDQU64-512-1)
{
ICLASS:      VMOVDQU64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VMOVDQU64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
IFORM:       VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VMOVDQU64 (VMOVDQU64-512-2)
{
ICLASS:      VMOVDQU64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VMOVDQU64 (VMOVDQU64-512-3)
{
ICLASS:      VMOVDQU64
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VMOVHLPS (VMOVHLPS-128-1)
{
ICLASS:      VMOVHLPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E7NM128
REAL_OPCODE: Y
PATTERN:    EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32
IFORM:       VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512
}


# EMITTING VMOVHPD (VMOVHPD-128-1)
{
ICLASS:      VMOVHPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64
IFORM:       VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512
}


# EMITTING VMOVHPD (VMOVHPD-128-2)
{
ICLASS:      VMOVHPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64
IFORM:       VMOVHPD_MEMf64_XMMf64_AVX512
}


# EMITTING VMOVHPS (VMOVHPS-128-1)
{
ICLASS:      VMOVHPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_TUPLE2 
PATTERN:    EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_TUPLE2()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32
IFORM:       VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512
}


# EMITTING VMOVHPS (VMOVHPS-128-2)
{
ICLASS:      VMOVHPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_TUPLE2 
PATTERN:    EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_TUPLE2()
OPERANDS:    MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32
IFORM:       VMOVHPS_MEMf32_XMMf32_AVX512
}


# EMITTING VMOVLHPS (VMOVLHPS-128-1)
{
ICLASS:      VMOVLHPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E7NM128
REAL_OPCODE: Y
PATTERN:    EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32
IFORM:       VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512
}


# EMITTING VMOVLPD (VMOVLPD-128-1)
{
ICLASS:      VMOVLPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512
}


# EMITTING VMOVLPD (VMOVLPD-128-2)
{
ICLASS:      VMOVLPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    MEM0:w:q:f64 REG0=XMM_R3():r:q:f64
IFORM:       VMOVLPD_MEMf64_XMMf64_AVX512
}


# EMITTING VMOVLPS (VMOVLPS-128-1)
{
ICLASS:      VMOVLPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_TUPLE2 
PATTERN:    EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_TUPLE2()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32
IFORM:       VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512
}


# EMITTING VMOVLPS (VMOVLPS-128-2)
{
ICLASS:      VMOVLPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_TUPLE2 
PATTERN:    EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_TUPLE2()
OPERANDS:    MEM0:w:q:f32 REG0=XMM_R3():r:q:f32
IFORM:       VMOVLPS_MEMf32_XMMf32_AVX512
}


# EMITTING VMOVNTDQ (VMOVNTDQ-512-1)
{
ICLASS:      VMOVNTDQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1NF
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
PATTERN:    EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32
IFORM:       VMOVNTDQ_MEMu32_ZMMu32_AVX512
}


# EMITTING VMOVNTDQA (VMOVNTDQA-512-1)
{
ICLASS:      VMOVNTDQA
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1NF
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
PATTERN:    EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32
IFORM:       VMOVNTDQA_ZMMu32_MEMu32_AVX512
}


# EMITTING VMOVNTPD (VMOVNTPD-512-1)
{
ICLASS:      VMOVNTPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1NF
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
PATTERN:    EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64
IFORM:       VMOVNTPD_MEMf64_ZMMf64_AVX512
}


# EMITTING VMOVNTPS (VMOVNTPS-512-1)
{
ICLASS:      VMOVNTPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E1NF
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX  REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
PATTERN:    EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32
IFORM:       VMOVNTPS_MEMf32_ZMMf32_AVX512
}


# EMITTING VMOVQ (VMOVQ-128-1)
{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64
IFORM:       VMOVQ_XMMu64_GPR64u64_AVX512
}

{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER 
PATTERN:    EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS:    REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
IFORM:       VMOVQ_XMMu64_MEMu64_AVX512
}


# EMITTING VMOVQ (VMOVQ-128-2)
{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1  mode64  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64
IFORM:       VMOVQ_GPR64u64_XMMu64_AVX512
}

{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_STORE 
PATTERN:    EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()
OPERANDS:    MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
IFORM:       VMOVQ_MEMu64_XMMu64_AVX512
}


# EMITTING VMOVQ (VMOVQ-128-3)
{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64
IFORM:       VMOVQ_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
IFORM:       VMOVQ_XMMu64_MEMu64_AVX512
}


# EMITTING VMOVQ (VMOVQ-128-4)
{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64
IFORM:       VMOVQ_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VMOVQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR 
PATTERN:    EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
IFORM:       VMOVQ_MEMu64_XMMu64_AVX512
}


# EMITTING VMOVSD (VMOVSD-128-1)
{
ICLASS:      VMOVSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
IFORM:       VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VMOVSD (VMOVSD-128-2)
{
ICLASS:      VMOVSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
IFORM:       VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512
}


# EMITTING VMOVSD (VMOVSD-128-3)
{
ICLASS:      VMOVSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}


# EMITTING VMOVSD (VMOVSD-128-4)
{
ICLASS:      VMOVSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64
IFORM:       VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}


# EMITTING VMOVSHDUP (VMOVSHDUP-512-1)
{
ICLASS:      VMOVSHDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VMOVSHDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
IFORM:       VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VMOVSLDUP (VMOVSLDUP-512-1)
{
ICLASS:      VMOVSLDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VMOVSLDUP
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
IFORM:       VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VMOVSS (VMOVSS-128-1)
{
ICLASS:      VMOVSS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32
IFORM:       VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VMOVSS (VMOVSS-128-2)
{
ICLASS:      VMOVSS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
IFORM:       VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512
}


# EMITTING VMOVSS (VMOVSS-128-3)
{
ICLASS:      VMOVSS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}


# EMITTING VMOVSS (VMOVSS-128-4)
{
ICLASS:      VMOVSS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32
IFORM:       VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}


# EMITTING VMOVUPD (VMOVUPD-512-1)
{
ICLASS:      VMOVUPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VMOVUPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
IFORM:       VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VMOVUPD (VMOVUPD-512-2)
{
ICLASS:      VMOVUPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
IFORM:       VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VMOVUPD (VMOVUPD-512-3)
{
ICLASS:      VMOVUPD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
IFORM:       VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512
}


# EMITTING VMOVUPS (VMOVUPS-512-1)
{
ICLASS:      VMOVUPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VMOVUPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
IFORM:       VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VMOVUPS (VMOVUPS-512-2)
{
ICLASS:      VMOVUPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
IFORM:       VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VMOVUPS (VMOVUPS-512-3)
{
ICLASS:      VMOVUPS
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
IFORM:       VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512
}


# EMITTING VMULPD (VMULPD-512-1)
{
ICLASS:      VMULPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMULPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VMULPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VMULPS (VMULPS-512-1)
{
ICLASS:      VMULPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMULPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VMULPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VMULSD (VMULSD-128-1)
{
ICLASS:      VMULSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMULSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VMULSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VMULSS (VMULSS-128-1)
{
ICLASS:      VMULSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMULSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VMULSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VPABSD (VPABSD-512-1)
{
ICLASS:      VPABSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
IFORM:       VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512
}

{
ICLASS:      VPABSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512
}


# EMITTING VPABSQ (VPABSQ-512-1)
{
ICLASS:      VPABSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64
IFORM:       VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512
}

{
ICLASS:      VPABSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
IFORM:       VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512
}


# EMITTING VPADDD (VPADDD-512-1)
{
ICLASS:      VPADDD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPADDD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPADDQ (VPADDQ-512-1)
{
ICLASS:      VPADDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPADDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPANDD (VPANDD-512-1)
{
ICLASS:      VPANDD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPANDD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPANDND (VPANDND-512-1)
{
ICLASS:      VPANDND
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPANDND
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPANDNQ (VPANDNQ-512-1)
{
ICLASS:      VPANDNQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPANDNQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPANDQ (VPANDQ-512-1)
{
ICLASS:      VPANDQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPANDQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPBLENDMD (VPBLENDMD-512-1)
{
ICLASS:      VPBLENDMD
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MASK_AS_CONTROL 
PATTERN:    EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPBLENDMD
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPBLENDMQ (VPBLENDMQ-512-1)
{
ICLASS:      VPBLENDMQ
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MASK_AS_CONTROL 
PATTERN:    EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPBLENDMQ
CPL:         3
CATEGORY:    BLEND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPBROADCASTD (VPBROADCASTD-512-1)
{
ICLASS:      VPBROADCASTD
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 
PATTERN:    EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_TUPLE1()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32
IFORM:       VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VPBROADCASTD (VPBROADCASTD-512-2)
{
ICLASS:      VPBROADCASTD
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32
IFORM:       VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512
}


# EMITTING VPBROADCASTD (VPBROADCASTD-512-3)
{
ICLASS:      VPBROADCASTD
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
IFORM:       VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
}


# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1)
{
ICLASS:      VPBROADCASTQ
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 
PATTERN:    EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_TUPLE1()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64
IFORM:       VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2)
{
ICLASS:      VPBROADCASTQ
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64
IFORM:       VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512
}


# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3)
{
ICLASS:      VPBROADCASTQ
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  mode64  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64
IFORM:       VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
}


# EMITTING VPCMPD (VPCMPD-512-1)
{
ICLASS:      VPCMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b
IFORM:       VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512
}

{
ICLASS:      VPCMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512
}


# EMITTING VPCMPEQD (VPCMPEQD-512-1)
{
ICLASS:      VPCMPEQD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPCMPEQD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPCMPEQQ (VPCMPEQQ-512-1)
{
ICLASS:      VPCMPEQQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPCMPEQQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPCMPGTD (VPCMPGTD-512-1)
{
ICLASS:      VPCMPGTD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
IFORM:       VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512
}

{
ICLASS:      VPCMPGTD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512
}


# EMITTING VPCMPGTQ (VPCMPGTQ-512-1)
{
ICLASS:      VPCMPGTQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
IFORM:       VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512
}

{
ICLASS:      VPCMPGTQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM:       VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512
}


# EMITTING VPCMPQ (VPCMPQ-512-1)
{
ICLASS:      VPCMPQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b
IFORM:       VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512
}

{
ICLASS:      VPCMPQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512
}


# EMITTING VPCMPUD (VPCMPUD-512-1)
{
ICLASS:      VPCMPUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPCMPUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPCMPUQ (VPCMPUQ-512-1)
{
ICLASS:      VPCMPUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPCMPUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0 UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1)
{
ICLASS:      VPCOMPRESSD
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2)
{
ICLASS:      VPCOMPRESSD
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1)
{
ICLASS:      VPCOMPRESSQ
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2)
{
ICLASS:      VPCOMPRESSQ
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPERMD (VPERMD-512-1)
{
ICLASS:      VPERMD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPERMD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPERMI2D (VPERMI2D-512-1)
{
ICLASS:      VPERMI2D
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPERMI2D
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPERMI2PD (VPERMI2PD-512-1)
{
ICLASS:      VPERMI2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VPERMI2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VPERMI2PS (VPERMI2PS-512-1)
{
ICLASS:      VPERMI2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VPERMI2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VPERMI2Q (VPERMI2Q-512-1)
{
ICLASS:      VPERMI2Q
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPERMI2Q
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPERMILPD (VPERMILPD-512-1)
{
ICLASS:      VPERMILPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VPERMILPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
}


# EMITTING VPERMILPD (VPERMILPD-512-2)
{
ICLASS:      VPERMILPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VPERMILPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VPERMILPS (VPERMILPS-512-1)
{
ICLASS:      VPERMILPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VPERMILPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
}


# EMITTING VPERMILPS (VPERMILPS-512-2)
{
ICLASS:      VPERMILPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VPERMILPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VPERMPD (VPERMPD-512-1)
{
ICLASS:      VPERMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VPERMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
}


# EMITTING VPERMPD (VPERMPD-512-2)
{
ICLASS:      VPERMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VPERMPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VPERMPS (VPERMPS-512-1)
{
ICLASS:      VPERMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VPERMPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VPERMQ (VPERMQ-512-1)
{
ICLASS:      VPERMQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPERMQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPERMQ (VPERMQ-512-2)
{
ICLASS:      VPERMQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPERMQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPERMT2D (VPERMT2D-512-1)
{
ICLASS:      VPERMT2D
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPERMT2D
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPERMT2PD (VPERMT2PD-512-1)
{
ICLASS:      VPERMT2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VPERMT2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VPERMT2PS (VPERMT2PS-512-1)
{
ICLASS:      VPERMT2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VPERMT2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VPERMT2Q (VPERMT2Q-512-1)
{
ICLASS:      VPERMT2Q
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPERMT2Q
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPEXPANDD (VPEXPANDD-512-1)
{
ICLASS:      VPEXPANDD
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
IFORM:       VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VPEXPANDD (VPEXPANDD-512-2)
{
ICLASS:      VPEXPANDD
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPEXPANDQ (VPEXPANDQ-512-1)
{
ICLASS:      VPEXPANDQ
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
IFORM:       VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VPEXPANDQ (VPEXPANDQ-512-2)
{
ICLASS:      VPEXPANDQ
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPGATHERDD (VPGATHERDD-512-1)
{
ICLASS:      VPGATHERDD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u32
IFORM:       VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512
}


# EMITTING VPGATHERDQ (VPGATHERDQ-512-1)
{
ICLASS:      VPGATHERDQ
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64
IFORM:       VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
}


# EMITTING VPGATHERQD (VPGATHERQD-512-1)
{
ICLASS:      VPGATHERQD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32
IFORM:       VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512
}


# EMITTING VPGATHERQQ (VPGATHERQQ-512-1)
{
ICLASS:      VPGATHERQQ
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64
IFORM:       VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
}


# EMITTING VPMAXSD (VPMAXSD-512-1)
{
ICLASS:      VPMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
IFORM:       VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
}

{
ICLASS:      VPMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
}


# EMITTING VPMAXSQ (VPMAXSQ-512-1)
{
ICLASS:      VPMAXSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
IFORM:       VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
}

{
ICLASS:      VPMAXSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM:       VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
}


# EMITTING VPMAXUD (VPMAXUD-512-1)
{
ICLASS:      VPMAXUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPMAXUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPMAXUQ (VPMAXUQ-512-1)
{
ICLASS:      VPMAXUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPMAXUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPMINSD (VPMINSD-512-1)
{
ICLASS:      VPMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
IFORM:       VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
}

{
ICLASS:      VPMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
}


# EMITTING VPMINSQ (VPMINSQ-512-1)
{
ICLASS:      VPMINSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
IFORM:       VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
}

{
ICLASS:      VPMINSQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM:       VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
}


# EMITTING VPMINUD (VPMINUD-512-1)
{
ICLASS:      VPMINUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPMINUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPMINUQ (VPMINUQ-512-1)
{
ICLASS:      VPMINUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPMINUQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPMOVDB (VPMOVDB-512-1)
{
ICLASS:      VPMOVDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVDB (VPMOVDB-512-2)
{
ICLASS:      VPMOVDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVDW (VPMOVDW-512-1)
{
ICLASS:      VPMOVDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVDW (VPMOVDW-512-2)
{
ICLASS:      VPMOVDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVQB (VPMOVQB-512-1)
{
ICLASS:      VPMOVQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVQB (VPMOVQB-512-2)
{
ICLASS:      VPMOVQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 
PATTERN:    EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
OPERANDS:    MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVQD (VPMOVQD-512-1)
{
ICLASS:      VPMOVQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVQD (VPMOVQD-512-2)
{
ICLASS:      VPMOVQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVQW (VPMOVQW-512-1)
{
ICLASS:      VPMOVQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVQW (VPMOVQW-512-2)
{
ICLASS:      VPMOVQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVSDB (VPMOVSDB-512-1)
{
ICLASS:      VPMOVSDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32
IFORM:       VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512
}


# EMITTING VPMOVSDB (VPMOVSDB-512-2)
{
ICLASS:      VPMOVSDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32
IFORM:       VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512
}


# EMITTING VPMOVSDW (VPMOVSDW-512-1)
{
ICLASS:      VPMOVSDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32
IFORM:       VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512
}


# EMITTING VPMOVSDW (VPMOVSDW-512-2)
{
ICLASS:      VPMOVSDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32
IFORM:       VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512
}


# EMITTING VPMOVSQB (VPMOVSQB-512-1)
{
ICLASS:      VPMOVSQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
IFORM:       VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSQB (VPMOVSQB-512-2)
{
ICLASS:      VPMOVSQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 
PATTERN:    EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
OPERANDS:    MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
IFORM:       VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSQD (VPMOVSQD-512-1)
{
ICLASS:      VPMOVSQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
IFORM:       VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSQD (VPMOVSQD-512-2)
{
ICLASS:      VPMOVSQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
IFORM:       VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSQW (VPMOVSQW-512-1)
{
ICLASS:      VPMOVSQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
IFORM:       VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSQW (VPMOVSQW-512-2)
{
ICLASS:      VPMOVSQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
IFORM:       VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512
}


# EMITTING VPMOVSXBD (VPMOVSXBD-512-1)
{
ICLASS:      VPMOVSXBD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
IFORM:       VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512
}

{
ICLASS:      VPMOVSXBD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_8_BITS() NELEM_QUARTERMEM()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
IFORM:       VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512
}


# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1)
{
ICLASS:      VPMOVSXBQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
IFORM:       VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
}

{
ICLASS:      VPMOVSXBQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 
PATTERN:    EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_8_BITS() NELEM_EIGHTHMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
IFORM:       VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
}


# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1)
{
ICLASS:      VPMOVSXDQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
}

{
ICLASS:      VPMOVSXDQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALFMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32
IFORM:       VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
}


# EMITTING VPMOVSXWD (VPMOVSXWD-512-1)
{
ICLASS:      VPMOVSXWD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
IFORM:       VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512
}

{
ICLASS:      VPMOVSXWD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
IFORM:       VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512
}


# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1)
{
ICLASS:      VPMOVSXWQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
IFORM:       VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
}

{
ICLASS:      VPMOVSXWQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_16_BITS() NELEM_QUARTERMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
IFORM:       VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
}


# EMITTING VPMOVUSDB (VPMOVUSDB-512-1)
{
ICLASS:      VPMOVUSDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVUSDB (VPMOVUSDB-512-2)
{
ICLASS:      VPMOVUSDB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVUSDW (VPMOVUSDW-512-1)
{
ICLASS:      VPMOVUSDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
IFORM:       VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVUSDW (VPMOVUSDW-512-2)
{
ICLASS:      VPMOVUSDW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512
}


# EMITTING VPMOVUSQB (VPMOVUSQB-512-1)
{
ICLASS:      VPMOVUSQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVUSQB (VPMOVUSQB-512-2)
{
ICLASS:      VPMOVUSQB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 
PATTERN:    EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_EIGHTHMEM()
OPERANDS:    MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVUSQD (VPMOVUSQD-512-1)
{
ICLASS:      VPMOVUSQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVUSQD (VPMOVUSQD-512-2)
{
ICLASS:      VPMOVUSQD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_32_BITS() NELEM_HALFMEM()
OPERANDS:    MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVUSQW (VPMOVUSQW-512-1)
{
ICLASS:      VPMOVUSQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
IFORM:       VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVUSQW (VPMOVUSQW-512-2)
{
ICLASS:      VPMOVUSQW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_QUARTERMEM()
OPERANDS:    MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512
}


# EMITTING VPMOVZXBD (VPMOVZXBD-512-1)
{
ICLASS:      VPMOVZXBD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
IFORM:       VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512
}

{
ICLASS:      VPMOVZXBD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_8_BITS() NELEM_QUARTERMEM()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
IFORM:       VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512
}


# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1)
{
ICLASS:      VPMOVZXBQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
IFORM:       VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
}

{
ICLASS:      VPMOVZXBQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 
PATTERN:    EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_8_BITS() NELEM_EIGHTHMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
IFORM:       VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
}


# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1)
{
ICLASS:      VPMOVZXDQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
}

{
ICLASS:      VPMOVZXDQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_HALFMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32
IFORM:       VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
}


# EMITTING VPMOVZXWD (VPMOVZXWD-512-1)
{
ICLASS:      VPMOVZXWD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
IFORM:       VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512
}

{
ICLASS:      VPMOVZXWD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 
PATTERN:    EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_16_BITS() NELEM_HALFMEM()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
IFORM:       VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512
}


# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1)
{
ICLASS:      VPMOVZXWQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512    NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
IFORM:       VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
}

{
ICLASS:      VPMOVZXWQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 
PATTERN:    EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512    NOEVSR  ESIZE_16_BITS() NELEM_QUARTERMEM()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
IFORM:       VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
}


# EMITTING VPMULDQ (VPMULDQ-512-1)
{
ICLASS:      VPMULDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
IFORM:       VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512
}

{
ICLASS:      VPMULDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512
}


# EMITTING VPMULLD (VPMULLD-512-1)
{
ICLASS:      VPMULLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPMULLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPMULUDQ (VPMULUDQ-512-1)
{
ICLASS:      VPMULUDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPMULUDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPORD (VPORD-512-1)
{
ICLASS:      VPORD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPORD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPORQ (VPORQ-512-1)
{
ICLASS:      VPORQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPORQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPROLD (VPROLD-512-1)
{
ICLASS:      VPROLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPROLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPROLQ (VPROLQ-512-1)
{
ICLASS:      VPROLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPROLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPROLVD (VPROLVD-512-1)
{
ICLASS:      VPROLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPROLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPROLVQ (VPROLVQ-512-1)
{
ICLASS:      VPROLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPROLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPRORD (VPRORD-512-1)
{
ICLASS:      VPRORD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPRORD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPRORQ (VPRORQ-512-1)
{
ICLASS:      VPRORQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPRORQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPRORVD (VPRORVD-512-1)
{
ICLASS:      VPRORVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPRORVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPRORVQ (VPRORVQ-512-1)
{
ICLASS:      VPRORVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPRORVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSCATTERDD (VPSCATTERDD-512-1)
{
ICLASS:      VPSCATTERDD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32
IFORM:       VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512
}


# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1)
{
ICLASS:      VPSCATTERDQ
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
}


# EMITTING VPSCATTERQD (VPSCATTERQD-512-1)
{
ICLASS:      VPSCATTERQD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
IFORM:       VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512
}


# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1)
{
ICLASS:      VPSCATTERQQ
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
IFORM:       VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
}


# EMITTING VPSHUFD (VPSHUFD-512-1)
{
ICLASS:      VPSHUFD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHUFD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPSLLD (VPSLLD-512-1)
{
ICLASS:      VPSLLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
IFORM:       VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
}

{
ICLASS:      VPSLLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
IFORM:       VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSLLD (VPSLLD-512-2)
{
ICLASS:      VPSLLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSLLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPSLLQ (VPSLLQ-512-1)
{
ICLASS:      VPSLLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
IFORM:       VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
}

{
ICLASS:      VPSLLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
IFORM:       VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSLLQ (VPSLLQ-512-2)
{
ICLASS:      VPSLLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPSLLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPSLLVD (VPSLLVD-512-1)
{
ICLASS:      VPSLLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSLLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSLLVQ (VPSLLVQ-512-1)
{
ICLASS:      VPSLLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSLLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSRAD (VPSRAD-512-1)
{
ICLASS:      VPSRAD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
IFORM:       VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
}

{
ICLASS:      VPSRAD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
IFORM:       VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSRAD (VPSRAD-512-2)
{
ICLASS:      VPSRAD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSRAD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPSRAQ (VPSRAQ-512-1)
{
ICLASS:      VPSRAQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
IFORM:       VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
}

{
ICLASS:      VPSRAQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
IFORM:       VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSRAQ (VPSRAQ-512-2)
{
ICLASS:      VPSRAQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPSRAQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPSRAVD (VPSRAVD-512-1)
{
ICLASS:      VPSRAVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSRAVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSRAVQ (VPSRAVQ-512-1)
{
ICLASS:      VPSRAVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSRAVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSRLD (VPSRLD-512-1)
{
ICLASS:      VPSRLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
IFORM:       VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
}

{
ICLASS:      VPSRLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
IFORM:       VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSRLD (VPSRLD-512-2)
{
ICLASS:      VPSRLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSRLD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
}


# EMITTING VPSRLQ (VPSRLQ-512-1)
{
ICLASS:      VPSRLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
IFORM:       VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
}

{
ICLASS:      VPSRLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_MEM128 
PATTERN:    EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_MEM128()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
IFORM:       VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSRLQ (VPSRLQ-512-2)
{
ICLASS:      VPSRLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPSRLQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
}


# EMITTING VPSRLVD (VPSRLVD-512-1)
{
ICLASS:      VPSRLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSRLVD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSRLVQ (VPSRLVQ-512-1)
{
ICLASS:      VPSRLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSRLVQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSUBD (VPSUBD-512-1)
{
ICLASS:      VPSUBD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSUBD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSUBQ (VPSUBQ-512-1)
{
ICLASS:      VPSUBQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSUBQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPTERNLOGD (VPTERNLOGD-512-1)
{
ICLASS:      VPTERNLOGD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPTERNLOGD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1)
{
ICLASS:      VPTERNLOGQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPTERNLOGQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPTESTMD (VPTESTMD-512-1)
{
ICLASS:      VPTESTMD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPTESTMD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPTESTMQ (VPTESTMQ-512-1)
{
ICLASS:      VPTESTMQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPTESTMQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPTESTNMD (VPTESTNMD-512-1)
{
ICLASS:      VPTESTNMD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPTESTNMD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPTESTNMQ (VPTESTNMQ-512-1)
{
ICLASS:      VPTESTNMQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1    ZEROING=0 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPTESTNMQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ZEROING=0  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1)
{
ICLASS:      VPUNPCKHDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPUNPCKHDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1)
{
ICLASS:      VPUNPCKHQDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPUNPCKHQDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1)
{
ICLASS:      VPUNPCKLDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPUNPCKLDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1)
{
ICLASS:      VPUNPCKLQDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPUNPCKLQDQ
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPXORD (VPXORD-512-1)
{
ICLASS:      VPXORD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPXORD
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPXORQ (VPXORQ-512-1)
{
ICLASS:      VPXORQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPXORQ
CPL:         3
CATEGORY:    LOGICAL
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VRCP14PD (VRCP14PD-512-1)
{
ICLASS:      VRCP14PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VRCP14PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VRCP14PS (VRCP14PS-512-1)
{
ICLASS:      VRCP14PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VRCP14PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VRCP14SD (VRCP14SD-128-1)
{
ICLASS:      VRCP14SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VRCP14SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VRCP14SS (VRCP14SS-128-1)
{
ICLASS:      VRCP14SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VRCP14SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1)
{
ICLASS:      VRNDSCALEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
}


# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1)
{
ICLASS:      VRNDSCALEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
}


# EMITTING VRNDSCALESD (VRNDSCALESD-128-1)
{
ICLASS:      VRNDSCALESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1   UIMM8()  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VRNDSCALESS (VRNDSCALESS-128-1)
{
ICLASS:      VRNDSCALESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0   UIMM8()  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VRSQRT14PD (VRSQRT14PD-512-1)
{
ICLASS:      VRSQRT14PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VRSQRT14PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VRSQRT14PS (VRSQRT14PS-512-1)
{
ICLASS:      VRSQRT14PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VRSQRT14PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VRSQRT14SD (VRSQRT14SD-128-1)
{
ICLASS:      VRSQRT14SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VRSQRT14SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VRSQRT14SS (VRSQRT14SS-128-1)
{
ICLASS:      VRSQRT14SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VRSQRT14SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VSCALEFPD (VSCALEFPD-512-1)
{
ICLASS:      VSCALEFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VSCALEFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VSCALEFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VSCALEFPS (VSCALEFPS-512-1)
{
ICLASS:      VSCALEFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VSCALEFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VSCALEFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VSCALEFSD (VSCALEFSD-128-1)
{
ICLASS:      VSCALEFSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSCALEFSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSCALEFSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VSCALEFSS (VSCALEFSS-128-1)
{
ICLASS:      VSCALEFSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSCALEFSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSCALEFSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VSCATTERDPD (VSCATTERDPD-512-1)
{
ICLASS:      VSCATTERDPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
IFORM:       VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
}


# EMITTING VSCATTERDPS (VSCATTERDPS-512-1)
{
ICLASS:      VSCATTERDPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32
IFORM:       VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512
}


# EMITTING VSCATTERQPD (VSCATTERQPD-512-1)
{
ICLASS:      VSCATTERQPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
IFORM:       VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
}


# EMITTING VSCATTERQPS (VSCATTERQPS-512-1)
{
ICLASS:      VSCATTERQPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E12
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
IFORM:       VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512
}


# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1)
{
ICLASS:      VSHUFF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VSHUFF32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1)
{
ICLASS:      VSHUFF64X2
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VSHUFF64X2
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1)
{
ICLASS:      VSHUFI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VSHUFI32X4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1)
{
ICLASS:      VSHUFI64X2
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VSHUFI64X2
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VSHUFPD (VSHUFPD-512-1)
{
ICLASS:      VSHUFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
IFORM:       VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
}

{
ICLASS:      VSHUFPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
}


# EMITTING VSHUFPS (VSHUFPS-512-1)
{
ICLASS:      VSHUFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
IFORM:       VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
}

{
ICLASS:      VSHUFPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM:       VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
}


# EMITTING VSQRTPD (VSQRTPD-512-1)
{
ICLASS:      VSQRTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VSQRTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VSQRTPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512
}


# EMITTING VSQRTPS (VSQRTPS-512-1)
{
ICLASS:      VSQRTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VSQRTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VSQRTPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512
}


# EMITTING VSQRTSD (VSQRTSD-128-1)
{
ICLASS:      VSQRTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSQRTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSQRTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VSQRTSS (VSQRTSS-128-1)
{
ICLASS:      VSQRTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSQRTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSQRTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VSUBPD (VSUBPD-512-1)
{
ICLASS:      VSUBPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VSUBPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VSUBPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VSUBPS (VSUBPS-512-1)
{
ICLASS:      VSUBPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VSUBPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VSUBPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VSUBSD (VSUBSD-128-1)
{
ICLASS:      VSUBSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSUBSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VSUBSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VSUBSS (VSUBSS-128-1)
{
ICLASS:      VSUBSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSUBSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VSUBSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VUCOMISD (VUCOMISD-128-1)
{
ICLASS:      VUCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64
IFORM:       VUCOMISD_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VUCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VUCOMISD_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VUCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_SCALAR 
PATTERN:    EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1  NOEVSR  ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64
IFORM:       VUCOMISD_XMMf64_MEMf64_AVX512
}


# EMITTING VUCOMISS (VUCOMISS-128-1)
{
ICLASS:      VUCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32
IFORM:       VUCOMISS_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VUCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VUCOMISS_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VUCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-mod of-0 af-0 sf-0 ]
ATTRIBUTES:  MXCSR SIMD_SCALAR DISP8_SCALAR 
PATTERN:    EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32
IFORM:       VUCOMISS_XMMf32_MEMf32_AVX512
}


# EMITTING VUNPCKHPD (VUNPCKHPD-512-1)
{
ICLASS:      VUNPCKHPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VUNPCKHPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VUNPCKHPS (VUNPCKHPS-512-1)
{
ICLASS:      VUNPCKHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VUNPCKHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VUNPCKLPD (VUNPCKLPD-512-1)
{
ICLASS:      VUNPCKLPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
IFORM:       VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
}

{
ICLASS:      VUNPCKLPD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
}


# EMITTING VUNPCKLPS (VUNPCKLPS-512-1)
{
ICLASS:      VUNPCKLPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VUNPCKLPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512F_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
}


AVX_INSTRUCTIONS()::
# EMITTING KANDNW (KANDNW-256-1)
{
ICLASS:      KANDNW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x42 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


# EMITTING KANDW (KANDW-256-1)
{
ICLASS:      KANDW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x41 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


# EMITTING KMOVW (KMOVW-128-1)
{
ICLASS:      KMOVW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K21
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x90 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16
IFORM:       KMOVW_MASKmskw_MASKu16_AVX512
}

{
ICLASS:      KMOVW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K21
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL=0  W0  NOVSR 
OPERANDS:    REG0=MASK_R():w:mskw MEM0:r:wrd:u16
IFORM:       KMOVW_MASKmskw_MEMu16_AVX512
}


# EMITTING KMOVW (KMOVW-128-2)
{
ICLASS:      KMOVW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K21
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL=0  W0  NOVSR 
OPERANDS:    MEM0:w:wrd:u16 REG0=MASK_R():r:mskw
IFORM:       KMOVW_MEMu16_MASKmskw_AVX512
}


# EMITTING KMOVW (KMOVW-128-3)
{
ICLASS:      KMOVW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K21
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x92 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR 
OPERANDS:    REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
IFORM:       KMOVW_MASKmskw_GPR32u32_AVX512
}


# EMITTING KMOVW (KMOVW-128-4)
{
ICLASS:      KMOVW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x93 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
IFORM:       KMOVW_GPR32u32_MASKmskw_AVX512
}


# EMITTING KNOTW (KNOTW-128-1)
{
ICLASS:      KNOTW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x44 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
IFORM:       KNOTW_MASKmskw_MASKmskw_AVX512
}


# EMITTING KORTESTW (KORTESTW-128-1)
{
ICLASS:      KORTESTW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
FLAGS:       MUST [ cf-mod zf-mod  pf-0 of-0 af-0 sf-0 ]
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x98 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W0  NOVSR 
OPERANDS:    REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
IFORM:       KORTESTW_MASKmskw_MASKmskw_AVX512
}


# EMITTING KORW (KORW-256-1)
{
ICLASS:      KORW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x45 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KORW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


# EMITTING KSHIFTLW (KSHIFTLW-128-1)
{
ICLASS:      KSHIFTLW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x32 V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W1  NOVSR UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
IFORM:       KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512
}


# EMITTING KSHIFTRW (KSHIFTRW-128-1)
{
ICLASS:      KSHIFTRW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x30 V66 V0F3A MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=0  W1  NOVSR UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
IFORM:       KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512
}


# EMITTING KUNPCKBW (KUNPCKBW-256-1)
{
ICLASS:      KUNPCKBW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x4B V66 V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


# EMITTING KXNORW (KXNORW-256-1)
{
ICLASS:      KXNORW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x46 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


# EMITTING KXORW (KXORW-256-1)
{
ICLASS:      KXORW
CPL:         3
CATEGORY:    KMASK
EXTENSION:   AVX512VEX
ISA_SET:     AVX512F_KOP
EXCEPTIONS:     AVX512-K20
REAL_OPCODE: Y
ATTRIBUTES:  KMASK 
PATTERN:    VV1 0x47 VNP V0F MOD[0b11] MOD=3  REG[rrr] RM[nnn]  VL=1  W0   
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
IFORM:       KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512
}


