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#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
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#      http://www.apache.org/licenses/LICENSE-2.0
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# These bind the operand deciders that control the encoding
SEQUENCE ISA_BINDINGS
   FIXUP_EOSZ_ENC_BIND()
   FIXUP_EASZ_ENC_BIND()
   ASZ_NONTERM_BIND()  
   INSTRUCTIONS_BIND()     # not calling tree splitter! GSSE instructions must set VEXVALID=1
   OSZ_NONTERM_ENC_BIND()   # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously)
   PREFIX_ENC_BIND() 
   VEXED_REX_BIND()

# These emit the bits and bytes that make up the encoding
SEQUENCE ISA_EMIT
   PREFIX_ENC_EMIT() 
   VEXED_REX_EMIT()
   INSTRUCTIONS_EMIT()

VEXED_REX()::
VEXVALID=4 -> KNC_EVEX_ENC() 


#################################################
SEQUENCE KNC_EVEX_ENC_BIND
	 # R,X,B R map (byte 1)
	 # W, vvvv, L, pp  (byte 2)
	 # NR, sss, V', kkk ( byte 3)
	 EVEX_62_REXR_ENC_BIND
	 EVEX_REXX_ENC_BIND
	 EVEX_REXB_ENC_BIND
	 EVEX_REXRR_ENC_BIND
	 EVEX_MAP_ENC_BIND
	 EVEX_REXW_VVVV_ENC_BIND
	 EVEX_ESCVL_ENC_BIND
	 EVEX_BYTE3_ENC_BIND

	 
SEQUENCE KNC_EVEX_ENC_EMIT
	 EVEX_62_REXR_ENC_EMIT
	 EVEX_REXX_ENC_EMIT
	 EVEX_REXB_ENC_EMIT
	 EVEX_REXRR_ENC_EMIT
	 EVEX_MAP_ENC_EMIT
	 EVEX_REXW_VVVV_ENC_EMIT
	 EVEX_ESCVL_ENC_EMIT
	 EVEX_BYTE3_ENC_EMIT


EVEX_62_REXR_ENC()::
mode64 REXR=1 -> 0x62 0b0
mode64 REXR=0 -> 0x62 0b1
mode32 REXR=1 -> error
mode32 REXR=0 -> 0x62 0b1

EVEX_REXX_ENC()::
mode64 REXX=1 -> 0b0
mode64 REXX=0 -> 0b1
mode32 REXX=1 -> error
mode32 REXX=0 -> 0b1

EVEX_REXB_ENC()::
mode64 REXB=1 -> 0b0
mode64 REXB=0 -> 0b1
mode32 REXB=1 -> error
mode32 REXB=0 -> 0b1

EVEX_REXRR_ENC()::
mode64 REXRR=1 -> 0b0
mode64 REXRR=0 -> 0b1
mode32 REXRR=1 -> error
mode32 REXRR=0 -> 0b1

EVEX_MAP_ENC()::
MAP=0  -> 0b0000
MAP=1  -> 0b0001
MAP=2  -> 0b0010
MAP=3  -> 0b0011

EVEX_REXW_VVVV_ENC()::
mode64 REXW[w] VEXDEST3[u]   VEXDEST210[ddd] -> w u_ddd
mode32 REXW[w] VEXDEST3[u]=1 VEXDEST210[ddd] -> w u_ddd
mode32 REXW[w] VEXDEST3[u]=0 VEXDEST210[ddd] -> error

#include the required zero bit before the pp bits
EVEX_ESCVL_ENC()::
 VNP -> 0b000
 V66 -> 0b001
 VF3 -> 0b010
 VF2 -> 0b011

EVEX_BYTE3_ENC()::
NR[n] SWIZ[sss] VEXDEST4=0 MASK[kkk] -> n_sss 1_ kkk
NR[n] SWIZ[sss] VEXDEST4=1 MASK[kkk] -> n_sss 0_ kkk

