#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
SEQUENCE UISA_VMODRM_ZMM_BIND
   VMODRM_MOD_ENCODE_BIND()  # FROM HSW
   VSIB_ENC_BASE_BIND()      # FROM HSW
   UISA_ENC_INDEX_ZMM_BIND()
   VSIB_ENC_SCALE_BIND() # FROM HSW
   VSIB_ENC_BIND()       # FROM HSW
   SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA
   SEGMENT_ENCODE_BIND()         # FROM BASE ISA
   DISP_NT_BIND()        # FROM BASE ISA
SEQUENCE UISA_VMODRM_YMM_BIND
   VMODRM_MOD_ENCODE_BIND()  # FROM HSW
   VSIB_ENC_BASE_BIND()      # FROM HSW
   UISA_ENC_INDEX_YMM_BIND()
   VSIB_ENC_SCALE_BIND()   # FROM HSW
   VSIB_ENC_BIND()         # FROM HSW
   SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA
   SEGMENT_ENCODE_BIND()         # FROM BASE ISA
   DISP_NT_BIND()          # FROM BASE ISA
SEQUENCE UISA_VMODRM_XMM_BIND
   VMODRM_MOD_ENCODE_BIND()  # FROM HSW
   VSIB_ENC_BASE_BIND()      # FROM HSW
   UISA_ENC_INDEX_XMM_BIND()
   VSIB_ENC_SCALE_BIND()   # FROM HSW
   VSIB_ENC_BIND()         # FROM HSW
   SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA
   SEGMENT_ENCODE_BIND()         # FROM BASE ISA
   DISP_NT_BIND()          # FROM BASE ISA

# For now, ignoring the difference in x/y/zmm for the index register. Could
#  split these.
SEQUENCE UISA_VMODRM_ZMM_EMIT
   VSIB_ENC_EMIT()
   DISP_NT_EMIT()
SEQUENCE UISA_VMODRM_YMM_EMIT
   VSIB_ENC_EMIT()
   DISP_NT_EMIT()
SEQUENCE UISA_VMODRM_XMM_EMIT
   VSIB_ENC_EMIT()
   DISP_NT_EMIT()

######################################



UISA_ENC_INDEX_ZMM()::
INDEX=XED_REG_ZMM0   -> VEXDEST4=0 REXX=0 SIBINDEX=0 
INDEX=XED_REG_ZMM1   -> VEXDEST4=0 REXX=0 SIBINDEX=1 
INDEX=XED_REG_ZMM2   -> VEXDEST4=0 REXX=0 SIBINDEX=2 
INDEX=XED_REG_ZMM3   -> VEXDEST4=0 REXX=0 SIBINDEX=3 
INDEX=XED_REG_ZMM4   -> VEXDEST4=0 REXX=0 SIBINDEX=4 
INDEX=XED_REG_ZMM5   -> VEXDEST4=0 REXX=0 SIBINDEX=5 
INDEX=XED_REG_ZMM6   -> VEXDEST4=0 REXX=0 SIBINDEX=6 
INDEX=XED_REG_ZMM7   -> VEXDEST4=0 REXX=0 SIBINDEX=7 
INDEX=XED_REG_ZMM8   -> VEXDEST4=0 REXX=1 SIBINDEX=0 
INDEX=XED_REG_ZMM9   -> VEXDEST4=0 REXX=1 SIBINDEX=1 
INDEX=XED_REG_ZMM10  -> VEXDEST4=0 REXX=1 SIBINDEX=2 
INDEX=XED_REG_ZMM11  -> VEXDEST4=0 REXX=1 SIBINDEX=3 
INDEX=XED_REG_ZMM12  -> VEXDEST4=0 REXX=1 SIBINDEX=4 
INDEX=XED_REG_ZMM13  -> VEXDEST4=0 REXX=1 SIBINDEX=5 
INDEX=XED_REG_ZMM14  -> VEXDEST4=0 REXX=1 SIBINDEX=6 
INDEX=XED_REG_ZMM15  -> VEXDEST4=0 REXX=1 SIBINDEX=7 
INDEX=XED_REG_ZMM16  -> VEXDEST4=1 REXX=0 SIBINDEX=0 
INDEX=XED_REG_ZMM17  -> VEXDEST4=1 REXX=0 SIBINDEX=1 
INDEX=XED_REG_ZMM18  -> VEXDEST4=1 REXX=0 SIBINDEX=2 
INDEX=XED_REG_ZMM19  -> VEXDEST4=1 REXX=0 SIBINDEX=3 
INDEX=XED_REG_ZMM20  -> VEXDEST4=1 REXX=0 SIBINDEX=4 
INDEX=XED_REG_ZMM21  -> VEXDEST4=1 REXX=0 SIBINDEX=5 
INDEX=XED_REG_ZMM22  -> VEXDEST4=1 REXX=0 SIBINDEX=6 
INDEX=XED_REG_ZMM23  -> VEXDEST4=1 REXX=0 SIBINDEX=7 
INDEX=XED_REG_ZMM24  -> VEXDEST4=1 REXX=1 SIBINDEX=0 
INDEX=XED_REG_ZMM25  -> VEXDEST4=1 REXX=1 SIBINDEX=1 
INDEX=XED_REG_ZMM26  -> VEXDEST4=1 REXX=1 SIBINDEX=2 
INDEX=XED_REG_ZMM27  -> VEXDEST4=1 REXX=1 SIBINDEX=3 
INDEX=XED_REG_ZMM28  -> VEXDEST4=1 REXX=1 SIBINDEX=4 
INDEX=XED_REG_ZMM29  -> VEXDEST4=1 REXX=1 SIBINDEX=5 
INDEX=XED_REG_ZMM30  -> VEXDEST4=1 REXX=1 SIBINDEX=6 
INDEX=XED_REG_ZMM31  -> VEXDEST4=1 REXX=1 SIBINDEX=7 
UISA_ENC_INDEX_YMM()::
INDEX=XED_REG_YMM0   -> VEXDEST4=0 REXX=0 SIBINDEX=0 
INDEX=XED_REG_YMM1   -> VEXDEST4=0 REXX=0 SIBINDEX=1 
INDEX=XED_REG_YMM2   -> VEXDEST4=0 REXX=0 SIBINDEX=2 
INDEX=XED_REG_YMM3   -> VEXDEST4=0 REXX=0 SIBINDEX=3 
INDEX=XED_REG_YMM4   -> VEXDEST4=0 REXX=0 SIBINDEX=4 
INDEX=XED_REG_YMM5   -> VEXDEST4=0 REXX=0 SIBINDEX=5 
INDEX=XED_REG_YMM6   -> VEXDEST4=0 REXX=0 SIBINDEX=6 
INDEX=XED_REG_YMM7   -> VEXDEST4=0 REXX=0 SIBINDEX=7 
INDEX=XED_REG_YMM8   -> VEXDEST4=0 REXX=1 SIBINDEX=0 
INDEX=XED_REG_YMM9   -> VEXDEST4=0 REXX=1 SIBINDEX=1 
INDEX=XED_REG_YMM10  -> VEXDEST4=0 REXX=1 SIBINDEX=2 
INDEX=XED_REG_YMM11  -> VEXDEST4=0 REXX=1 SIBINDEX=3 
INDEX=XED_REG_YMM12  -> VEXDEST4=0 REXX=1 SIBINDEX=4 
INDEX=XED_REG_YMM13  -> VEXDEST4=0 REXX=1 SIBINDEX=5 
INDEX=XED_REG_YMM14  -> VEXDEST4=0 REXX=1 SIBINDEX=6 
INDEX=XED_REG_YMM15  -> VEXDEST4=0 REXX=1 SIBINDEX=7 
INDEX=XED_REG_YMM16  -> VEXDEST4=1 REXX=0 SIBINDEX=0 
INDEX=XED_REG_YMM17  -> VEXDEST4=1 REXX=0 SIBINDEX=1 
INDEX=XED_REG_YMM18  -> VEXDEST4=1 REXX=0 SIBINDEX=2 
INDEX=XED_REG_YMM19  -> VEXDEST4=1 REXX=0 SIBINDEX=3 
INDEX=XED_REG_YMM20  -> VEXDEST4=1 REXX=0 SIBINDEX=4 
INDEX=XED_REG_YMM21  -> VEXDEST4=1 REXX=0 SIBINDEX=5 
INDEX=XED_REG_YMM22  -> VEXDEST4=1 REXX=0 SIBINDEX=6 
INDEX=XED_REG_YMM23  -> VEXDEST4=1 REXX=0 SIBINDEX=7 
INDEX=XED_REG_YMM24  -> VEXDEST4=1 REXX=1 SIBINDEX=0 
INDEX=XED_REG_YMM25  -> VEXDEST4=1 REXX=1 SIBINDEX=1 
INDEX=XED_REG_YMM26  -> VEXDEST4=1 REXX=1 SIBINDEX=2 
INDEX=XED_REG_YMM27  -> VEXDEST4=1 REXX=1 SIBINDEX=3 
INDEX=XED_REG_YMM28  -> VEXDEST4=1 REXX=1 SIBINDEX=4 
INDEX=XED_REG_YMM29  -> VEXDEST4=1 REXX=1 SIBINDEX=5 
INDEX=XED_REG_YMM30  -> VEXDEST4=1 REXX=1 SIBINDEX=6 
INDEX=XED_REG_YMM31  -> VEXDEST4=1 REXX=1 SIBINDEX=7 
UISA_ENC_INDEX_XMM()::
INDEX=XED_REG_XMM0   -> VEXDEST4=0 REXX=0 SIBINDEX=0 
INDEX=XED_REG_XMM1   -> VEXDEST4=0 REXX=0 SIBINDEX=1 
INDEX=XED_REG_XMM2   -> VEXDEST4=0 REXX=0 SIBINDEX=2 
INDEX=XED_REG_XMM3   -> VEXDEST4=0 REXX=0 SIBINDEX=3 
INDEX=XED_REG_XMM4   -> VEXDEST4=0 REXX=0 SIBINDEX=4 
INDEX=XED_REG_XMM5   -> VEXDEST4=0 REXX=0 SIBINDEX=5 
INDEX=XED_REG_XMM6   -> VEXDEST4=0 REXX=0 SIBINDEX=6 
INDEX=XED_REG_XMM7   -> VEXDEST4=0 REXX=0 SIBINDEX=7 
INDEX=XED_REG_XMM8   -> VEXDEST4=0 REXX=1 SIBINDEX=0 
INDEX=XED_REG_XMM9   -> VEXDEST4=0 REXX=1 SIBINDEX=1 
INDEX=XED_REG_XMM10  -> VEXDEST4=0 REXX=1 SIBINDEX=2 
INDEX=XED_REG_XMM11  -> VEXDEST4=0 REXX=1 SIBINDEX=3 
INDEX=XED_REG_XMM12  -> VEXDEST4=0 REXX=1 SIBINDEX=4 
INDEX=XED_REG_XMM13  -> VEXDEST4=0 REXX=1 SIBINDEX=5 
INDEX=XED_REG_XMM14  -> VEXDEST4=0 REXX=1 SIBINDEX=6 
INDEX=XED_REG_XMM15  -> VEXDEST4=0 REXX=1 SIBINDEX=7 
INDEX=XED_REG_XMM16  -> VEXDEST4=1 REXX=0 SIBINDEX=0 
INDEX=XED_REG_XMM17  -> VEXDEST4=1 REXX=0 SIBINDEX=1 
INDEX=XED_REG_XMM18  -> VEXDEST4=1 REXX=0 SIBINDEX=2 
INDEX=XED_REG_XMM19  -> VEXDEST4=1 REXX=0 SIBINDEX=3 
INDEX=XED_REG_XMM20  -> VEXDEST4=1 REXX=0 SIBINDEX=4 
INDEX=XED_REG_XMM21  -> VEXDEST4=1 REXX=0 SIBINDEX=5 
INDEX=XED_REG_XMM22  -> VEXDEST4=1 REXX=0 SIBINDEX=6 
INDEX=XED_REG_XMM23  -> VEXDEST4=1 REXX=0 SIBINDEX=7 
INDEX=XED_REG_XMM24  -> VEXDEST4=1 REXX=1 SIBINDEX=0 
INDEX=XED_REG_XMM25  -> VEXDEST4=1 REXX=1 SIBINDEX=1 
INDEX=XED_REG_XMM26  -> VEXDEST4=1 REXX=1 SIBINDEX=2 
INDEX=XED_REG_XMM27  -> VEXDEST4=1 REXX=1 SIBINDEX=3 
INDEX=XED_REG_XMM28  -> VEXDEST4=1 REXX=1 SIBINDEX=4 
INDEX=XED_REG_XMM29  -> VEXDEST4=1 REXX=1 SIBINDEX=5 
INDEX=XED_REG_XMM30  -> VEXDEST4=1 REXX=1 SIBINDEX=6 
INDEX=XED_REG_XMM31  -> VEXDEST4=1 REXX=1 SIBINDEX=7 



 



