#BEGIN_LEGAL
#
#Copyright (c) 2017 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
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#END_LEGAL


INSTRUCTIONS()::
{
ICLASS    : FADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP

PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}

{
ICLASS    : FCOM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87STATUS:w:SUPP

COMMENT   : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org)
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87STATUS:w:SUPP
IFORM     : FCOM_ST0_X87_DCD0
}


{
ICLASS    : FCOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}

{
ICLASS    : FCOMP
ATTRIBUTES: NOTSX
COMMENT   : UNDOC ALIASES
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
IFORM     : FCOMP_ST0_X87_DCD1

PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
IFORM     : FCOMP_ST0_X87_DED0
}


{
ICLASS    : FSUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80  REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80  REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP

PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem80real   REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP

PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP

COMMENT   : UNDOC ALIASES
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
IFORM     : FSTP_X87_ST0_DFD0

PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
IFORM     : FSTP_X87_ST0_DFD1
}

{
ICLASS    : FSTPNCE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
COMMENT   : UNDOC ALIASES - empty top of stack behavior differs from FSTP.
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}



{
ICLASS    : FLDENV
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM()
OPERANDS  : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM()
OPERANDS  : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDCW
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FNSTENV
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM()
OPERANDS  : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM()
OPERANDS  : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FNSTCW
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80  REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FXCH
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80   REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FXCH
ATTRIBUTES: NOTSX
CPL       : 3
COMMENT   : UNDOC ALIAS
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80   REG2=XED_REG_X87STATUS:w:SUPP
IFORM     : FXCH_ST0_X87_DFC1

PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80   REG2=XED_REG_X87STATUS:w:SUPP
IFORM     : FXCH_ST0_X87_DDC1
}



{
ICLASS    : FNOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP X87_CONTROL NOTSX
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]
OPERANDS  :
}
{
ICLASS    : FCHS
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FABS
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FTST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FXAM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLD1
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDL2T
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDL2E
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDPI
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDLG2
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDLN2
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLDZ
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]
OPERANDS  : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : F2XM1
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FYL2X
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FPTAN
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     :   MUST [ fc0-u   fc1-mod fc2-mod fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FPATAN
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]
OPERANDS  : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FXTRACT
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FPREM1
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDECSTP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]
OPERANDS  : REG0=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FINCSTP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]
OPERANDS  : REG0=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FPREM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FYL2XP1
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSQRT
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSINCOS
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     :   MUST [ fc0-u   fc1-mod fc2-mod fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FRNDINT
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSCALE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSIN
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     :   MUST [ fc0-u   fc1-mod fc2-mod fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOS
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     :   MUST [ fc0-u   fc1-mod fc2-mod fc3-u   ]
PATTERN   : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]
OPERANDS  : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FICOM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FICOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u  ]
PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [ zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVBE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [ cf-tst zf-tst  fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVU
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [ pf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FUCOMPP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:r:SUPP:f80  REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FILD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : SSE3
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80  REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVNB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [  cf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVNE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [  zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVNBE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [  cf-tst zf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCMOVNU
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FCMOV
EXTENSION : X87
ISA_SET   : FCMOV
FLAGS     : MUST [  pf-tst fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FNCLEX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010]
OPERANDS  : REG0=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FNINIT
CPL       : 3
ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011]
OPERANDS  : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP  REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSETPM287_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100]
OPERANDS  :
COMMENT   : UNDOC
}
{
ICLASS    : FENI8087_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000]
OPERANDS  :
COMMENT   : UNDOC
}
{
ICLASS    : FDISI8087_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001]
COMMENT   : UNDOC
OPERANDS  :
}


{
ICLASS    : FUCOMI
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ISA_SET   : PPRO
FLAGS     : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOMI
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ISA_SET   : PPRO
FLAGS     : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0   fc1-mod ]
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80  REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FSUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FLD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTTP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : SSE3
ATTRIBUTES :  NOTSX
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80  REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FRSTOR
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM()
OPERANDS  : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM()
OPERANDS  : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP
}
{
ICLASS    : FNSAVE
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM()
OPERANDS  : MEM0:w:mem94 \
            REG0=XED_REG_X87CONTROL:rw:SUPP  \
            REG1=XED_REG_X87TAG:rw:SUPP  \
            REG3=XED_REG_X87STATUS:rw:SUPP

PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM()
OPERANDS  : MEM0:w:mem108  \
            REG0=XED_REG_X87CONTROL:rw:SUPP  \
            REG1=XED_REG_X87TAG:rw:SUPP  \
            REG3=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FNSTSW
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_NOWAIT  X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FFREE
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP
}
{
ICLASS    : FST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80  REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FUCOM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80  REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FUCOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FIADD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIMUL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FICOM
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FICOMP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISUBR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIDIV
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIDIVR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FADDP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
}
{
ICLASS    : FMULP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
}
{
ICLASS    : FCOMPP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001]
OPERANDS  : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FSUBRP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.

}
{
ICLASS    : FSUBP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
}
{
ICLASS    : FDIVRP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.

}
{
ICLASS    : FDIVP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
COMMENT   : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
}
{
ICLASS    : FILD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  :  REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : SSE3
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FIST
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FBLD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FILD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int  REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FBSTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80  REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FISTP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
FLAGS     : MUST [ fc0-u   fc1-mod fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FFREEP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP
COMMENT   : UNDOC
}
{
ICLASS    : FNSTSW
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000]
OPERANDS  : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP
}
{
ICLASS    : FUCOMIP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ISA_SET   : PPRO
FLAGS     : MUST [ zf-mod pf-mod cf-mod  af-0 sf-0 of-0 fc1-mod ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80   REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : FCOMIP
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ISA_SET   : PPRO
FLAGS     : MUST [ zf-mod pf-mod cf-mod  af-0 sf-0 of-0 fc1-mod ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80  REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
}
{
ICLASS    : ADD_LOCK
DISASM    : add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADD_LOCK_MEMb_IMMb_80r0
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADD_MEMb_IMMb_80r0
}



{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : ADD_GPR8_IMMb_80r0
}



{
ICLASS    : OR_LOCK
DISASM    : or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : OR_LOCK_MEMb_IMMb_80r1
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE 
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : OR_MEMb_IMMb_80r1
}


{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : OR_GPR8_IMMb_80r1
}



{
ICLASS    : ADC_LOCK
DISASM    : adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADC_LOCK_MEMb_IMMb_80r2
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADC_MEMb_IMMb_80r2
}

{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : ADC_GPR8_IMMb_80r2
}


{
ICLASS    : SBB_LOCK
DISASM    : sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SBB_LOCK_MEMb_IMMb_80r3
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SBB_MEMb_IMMb_80r3
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : SBB_GPR8_IMMb_80r3
}



{
ICLASS    : AND_LOCK
DISASM    : and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : AND_LOCK_MEMb_IMMb_80r4
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE 
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : AND_MEMb_IMMb_80r4
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : AND_GPR8_IMMb_80r4
}

{
ICLASS    : SUB_LOCK
DISASM    : sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SUB_LOCK_MEMb_IMMb_80r5
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SUB_MEMb_IMMb_80r5
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : SUB_GPR8_IMMb_80r5
}





{
ICLASS    : XOR_LOCK
DISASM    : xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : XOR_LOCK_MEMb_IMMb_80r6
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : XOR_MEMb_IMMb_80r6
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : XOR_GPR8_IMMb_80r6
}

{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()
OPERANDS  : MEM0:r:b IMM0:r:b:i8
IFORM     : CMP_MEMb_IMMb_80r7

PATTERN   : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():r IMM0:r:b:i8
IFORM     : CMP_GPR8_IMMb_80r7
}
{
ICLASS    : ADD_LOCK
DISASM    : add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}


{
ICLASS    : OR_LOCK
DISASM    : or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}

{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKABLE 
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}




{
ICLASS    : ADC_LOCK
DISASM    : adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}


{
ICLASS    : SBB_LOCK
DISASM    : sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}




{
ICLASS    : AND_LOCK
DISASM    : and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE 
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}

{
ICLASS    : SUB_LOCK
DISASM    : sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE 
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}



{
ICLASS    : XOR_LOCK
DISASM    : xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE 
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:z 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:z
}



{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz()
OPERANDS  : MEM0:r:v IMM0:r:z
PATTERN   : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():r IMM0:r:z
}

{
ICLASS    : ADD_LOCK
DISASM    : add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADD_LOCK_MEMb_IMMb_82r0
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADD_MEMb_IMMb_82r0
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : ADD_GPR8_IMMb_82r0
}


{
ICLASS    : OR_LOCK
DISASM    : or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : OR_LOCK_MEMb_IMMb_82r1
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : OR_MEMb_IMMb_82r1
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : OR_GPR8_IMMb_82r1
}



{
ICLASS    : ADC_LOCK
DISASM    : adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADC_LOCK_MEMb_IMMb_82r2
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : ADC_MEMb_IMMb_82r2
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : ADC_GPR8_IMMb_82r2
}



{
ICLASS    : SBB_LOCK
DISASM    : sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SBB_LOCK_MEMb_IMMb_82r3
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SBB_MEMb_IMMb_82r3
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : SBB_GPR8_IMMb_82r3
}


{
ICLASS    : AND_LOCK
DISASM    :  and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : AND_LOCK_MEMb_IMMb_82r4
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : AND_MEMb_IMMb_82r4
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : AND_GPR8_IMMb_82r4
}



{
ICLASS    : SUB_LOCK
DISASM    :  sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SUB_LOCK_MEMb_IMMb_82r5
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b:i8 
IFORM     : SUB_MEMb_IMMb_82r5
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:i8
IFORM     : SUB_GPR8_IMMb_82r5
}


{
ICLASS    : XOR_LOCK
DISASM    :  xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : XOR_LOCK_MEMb_IMMb_82r6
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:b IMM0:r:b 
IFORM     : XOR_MEMb_IMMb_82r6
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : XOR_GPR8_IMMb_82r6
}

{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()
OPERANDS  : MEM0:r:b IMM0:r:b:i8
IFORM     : CMP_MEMb_IMMb_82r7

PATTERN   : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()
OPERANDS  : REG0=GPR8_B():r IMM0:r:b:i8
IFORM     : CMP_GPR8_IMMb_82r7
}

{
ICLASS    : ADD_LOCK
DISASM    :  add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : OR_LOCK
DISASM    :  or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : ADC_LOCK
DISASM    :  adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : SBB_LOCK
DISASM    :  sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : AND_LOCK
DISASM    :  and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : SUB_LOCK
DISASM    :  sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : XOR_LOCK
DISASM    :  xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b:i8 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:i8
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()
OPERANDS  : MEM0:r:v IMM0:r:b:i8

PATTERN   : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_B():r IMM0:r:b:i8
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM()
OPERANDS  : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP

PATTERN   : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64()
OPERANDS  : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP
IFORM     : POP_GPRv_8F
}


{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod  cf-mod ], IMMx MUST [ of-u  cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}
{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod  cf-mod ], IMMx MUST [ of-u  cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b

PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}

{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod  cf-mod ], IMMx MUST [ of-u  cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}

{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod  cf-mod ], IMMx MUST [ of-u  cf-mod ]
PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
# 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b
}

{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod  cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : ROR_MEMb_ONE

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : ROR_GPR8_ONE
}

{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod  cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : ROR_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : ROR_GPRv_ONE
}


{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u  cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}

{
ICLASS    : ROR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u  cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL

PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}





{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod  cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()  ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : ROL_MEMb_ONE
PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : ROL_GPR8_ONE
}

{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod  cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : ROL_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : ROL_GPRv_ONE
}
{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : ROL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u  cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL

PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}

#################




{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
IFORM     : SHL_MEMb_IMMb_C0r4

PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : SHL_GPR8_IMMb_C0r4
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
IFORM     : SHL_MEMb_IMMb_C0r6

PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
IFORM     : SHL_GPR8_IMMb_C0r6
}
{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : BYTEOP
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:b IMM0:r:b
PATTERN   : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b
}

{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b

PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b

PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b
IFORM     : SHL_MEMv_IMMb_C1r4

PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
IFORM     : SHL_GPRv_IMMb_C1r4
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b
PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b
IFORM     : SHL_MEMv_IMMb_C1r6

PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
IFORM     : SHL_GPRv_IMMb_C1r6
}
{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rw:v IMM0:r:b
PATTERN   : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod cf-tst cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : RCL_MEMb_ONE

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : RCL_GPR8_ONE
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod cf-tst cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : RCR_MEMb_ONE

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : RCR_GPR8_ONE
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : SHL_MEMb_ONE_D0r4

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : SHL_GPR8_ONE_D0r4

PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : SHL_MEMb_ONE_D0r6

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : SHL_GPR8_ONE_D0r6
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : SHR_MEMb_ONE

PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : SHR_GPR8_ONE
}

{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:b IMM0:r:b:IMPL
IFORM     : SAR_MEMb_ONE
PATTERN   : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()
OPERANDS  : REG0=GPR8_B():rw IMM0:r:b:IMPL
IFORM     : SAR_GPR8_ONE
}
{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod cf-tst cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : RCL_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : RCL_GPRv_ONE
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod cf-tst cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : RCR_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : RCR_GPRv_ONE
}

{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : SHR_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : SHR_GPRv_ONE
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : SHL_MEMv_ONE_D1r6

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : SHL_GPRv_ONE_D1r6

PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : SHL_MEMv_ONE_D1r4

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : SHL_GPRv_ONE_D1r4
}


{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : IMPLICIT_ONE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()
OPERANDS  : MEM0:rw:v IMM0:r:b:IMPL
IFORM     : SAR_MEMv_ONE

PATTERN   : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b:IMPL
IFORM     : SAR_GPRv_ONE
}
{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
IFORM     : SHL_MEMb_CL_D2r4

PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
IFORM     : SHL_GPR8_CL_D2r4
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
IFORM     : SHL_MEMb_CL_D2r6

PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
IFORM     : SHL_GPR8_CL_D2r6
}
{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
PATTERN   : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
}

{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
}
{
ICLASS    : RCL
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
}
{
ICLASS    : RCR
CPL       : 3
CATEGORY  : ROTATE
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u cf-tst cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
IFORM     : SHL_MEMv_CL_D3r4
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
IFORM     : SHL_GPRv_CL_D3r4
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
}
{
ICLASS    : SHR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
IFORM     : SHL_MEMv_CL_D3r6
}
{
ICLASS    : SHL
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
IFORM     : SHL_GPRv_CL_D3r6
}
{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
}
{
ICLASS    : SAR
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8()
OPERANDS  : MEM0:r:b IMM0:r:b:i8
IFORM     : TEST_MEMb_IMMb_F6r0

PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8()
OPERANDS  : MEM0:r:b IMM0:r:b:i8
IFORM     : TEST_MEMb_IMMb_F6r1

PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():r IMM0:r:b:i8
IFORM     : TEST_GPR8_IMMb_F6r0

PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
OPERANDS  : REG0=GPR8_B():r IMM0:r:b:i8
IFORM     : TEST_GPR8_IMMb_F6r1
}

{
ICLASS    : NOT_LOCK
DISASM    :  not
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : NOT
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : NOT
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw
}
{
ICLASS    : NEG_LOCK
DISASM    :  neg
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : NEG
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : NEG
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw
}
{
ICLASS    : MUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP
PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP
}
{
ICLASS    : IMUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP

PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP
}
{
ICLASS    : DIV
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=XED_REG_AX:rw:SUPP
PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP
}
{
ICLASS    : IDIV
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
PATTERN   : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=XED_REG_AX:rw:SUPP
PATTERN   : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()
OPERANDS  : MEM0:r:v IMM0:r:z
IFORM     : TEST_MEMv_IMMz_F7r0

PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz()
OPERANDS  : MEM0:r:v IMM0:r:z
IFORM     : TEST_MEMv_IMMz_F7r1

PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():r IMM0:r:z
IFORM     : TEST_GPRv_IMMz_F7r0

PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():r IMM0:r:z
IFORM     : TEST_GPRv_IMMz_F7r1
}
{
ICLASS    : NOT_LOCK
DISASM    :  not
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : NOT
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : NOT
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw
}
{
ICLASS    : NEG_LOCK
DISASM    :  neg
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : NEG
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : NEG
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw
}
{
ICLASS    : MUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP
}
{
ICLASS    : MUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP
}
{
ICLASS    : IMUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP

PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP
}
{
ICLASS    : DIV
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
}
{
ICLASS    : IDIV
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
PATTERN   : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
PATTERN   : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
}
{
ICLASS    : INC_LOCK
DISASM    :  inc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : INC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : INC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw
}
{
ICLASS    : DEC_LOCK
DISASM    :  dec
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : DEC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b 
}
{
ICLASS    : DEC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw
}
{
ICLASS    : INC_LOCK
DISASM    :  inc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : INC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : INC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw
IFORM     : INC_GPRv_FFr0
}
{
ICLASS    : DEC_LOCK
DISASM    :  dec
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : DEC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v 
}
{
ICLASS    : DEC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw
IFORM     : DEC_GPRv_FFr1
}
{
ICLASS    : CALL_NEAR
DISASM_INTEL: call
DISASM_ATTSV: call
CPL       : 3
CATEGORY  : CALL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0xE8 not64 BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP
PATTERN   : 0xE8 mode64  BRDISP32() DF64() FORCE64()
OPERANDS  : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn]  DF64() IMMUNE66_LOOP64() MODRM()
OPERANDS  : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn]  DF64() IMMUNE66_LOOP64()
OPERANDS  : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP
}
{
ICLASS    : JMP
CPL       : 3
CATEGORY  : UNCOND_BR
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM()
OPERANDS  : MEM0:r:v REG0=rIP():w:SUPP
PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64()
OPERANDS  : REG0=GPRv_B():r REG1=rIP():w:SUPP
}
{
ICLASS    : JMP_FAR
DISASM_INTEL: jmp far
DISASM_ATTSV: ljmp
CPL       : 3
ATTRIBUTES : FAR_XFER NOTSX
CATEGORY  : UNCOND_BR
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:p2 REG0=rIP():w:SUPP
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM()
OPERANDS  : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP

PATTERN   : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64()
OPERANDS  : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP
IFORM     : PUSH_GPRv_FFr6
}
{
ICLASS    : SLDT
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE NOTSX
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP

PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP
}
{
ICLASS    : STR
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE NOTSX
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:w:w REG0=XED_REG_TR:r:SUPP

PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP
}
{
ICLASS    : LLDT
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES : PROTECTED_MODE RING0 NOTSX
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP

PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP
}
{
ICLASS    : LTR
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES : PROTECTED_MODE RING0 NOTSX
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:r:w REG0=XED_REG_TR:w:SUPP

PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP
}
{
ICLASS    : VERR
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:r:w
COMMENT   : reads a selector
}
{
ICLASS    : VERR
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPR16_B():r
COMMENT   : reads a selector
}
{
ICLASS    : VERW
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:w
COMMENT   : reads a selector
}
{
ICLASS    : VERW
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPR16_B():r
COMMENT   : reads a selector
}
{
ICLASS    : LGDT
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES: NOTSX
COMMENT   : 66 is OSZ; F2/F3 ignored

PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010]  RM[nnn] mode64 FORCE64() MODRM() 
OPERANDS  : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010]  RM[nnn] not64 MODRM() 
OPERANDS  : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP
}
{
ICLASS    : SMSW
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
COMMENT   : 66 is OSZ; F2/F3 ignored

PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:w:w REG0=XED_REG_CR0:r:SUPP
}
{
ICLASS    : SMSW
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
COMMENT   : 66 is OSZ; F2/F3 ignored

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP
}
{
ICLASS    : LMSW
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES: RING0 NOTSX
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:r:w REG0=XED_REG_CR0:w:SUPP
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP
}
{
ICLASS    : BT
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:r:v IMM0:r:b
}
{
ICLASS    : BT
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u  af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():r IMM0:r:b
}
{
ICLASS    : BTS_LOCK
DISASM    :  bts
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTS
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTS
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : BTR_LOCK
DISASM    :  btr
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}
{
ICLASS    : BTC_LOCK
DISASM    :  btc
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTC
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix
OPERANDS  : MEM0:rw:v IMM0:r:b 
}
{
ICLASS    : BTC
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rw IMM0:r:b
}

# NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66
# on VMXON. It should be (and is) a VMXON.  VMCLEAR is required to
# "not have" f2/f3; osz_refining_prefix handles this.

{
ICLASS    : VMCLEAR
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()
OPERANDS  : MEM0:r:q
}
{
ICLASS    : VMPTRLD
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]

PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix  MODRM()
OPERANDS  : MEM0:r:q
}
{
ICLASS    : VMPTRST
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]

PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()
OPERANDS  : MEM0:w:q
}


{
ICLASS    : VMXON
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: PROTECTED_MODE NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]

PATTERN   : 0x0F 0xC7  MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()
OPERANDS  : MEM0:r:q
}
{
ICLASS    : CMPXCHG8B_LOCK
DISASM    :  cmpxchg8b
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : PENTIUMREAL
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix
OPERANDS  : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix
OPERANDS  : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 
}
{
ICLASS    : CMPXCHG8B
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : PENTIUMREAL
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix
OPERANDS  : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix
OPERANDS  : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 
}
{
ICLASS    : CMPXCHG16B_LOCK
DISASM    :  cmpxchg16b
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : LONGMODE
ISA_SET   : CMPXCHG16B
ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64  rexw_prefix IMMUNE66() MODRM() lock_prefix
OPERANDS  : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP 
}
{
ICLASS    : CMPXCHG16B
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : LONGMODE
ISA_SET   : CMPXCHG16B
ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64  rexw_prefix IMMUNE66() MODRM() nolock_prefix
OPERANDS  : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP 
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP

PATTERN   : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR8_B():w IMM0:r:b
IFORM     : MOV_GPR8_IMMb_C6r0
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP HLE_REL_ABLE
PATTERN   : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:b IMM0:r:b 
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_B():w IMM0:r:z
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : HLE_REL_ABLE
PATTERN   : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()
OPERANDS  : MEM0:w:v IMM0:r:z 
}
{
ICLASS    : PSRLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u16 IMM0:r:b
}
{
ICLASS    : PSRAW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:i16 IMM0:r:b
}
{
ICLASS    : PSLLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u16 IMM0:r:b
}
{
ICLASS    : PSRLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u16 IMM0:r:b
}
{
ICLASS    : PSRAW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:i16 IMM0:r:b
}
{
ICLASS    : PSLLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u16 IMM0:r:b
}
{
ICLASS    : PSRLD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u32 IMM0:r:b
}
{
ICLASS    : PSRAD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:i32 IMM0:r:b
}
{
ICLASS    : PSLLD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u32 IMM0:r:b
}
{
ICLASS    : PSRLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u32 IMM0:r:b
}
{
ICLASS    : PSRAD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:i32 IMM0:r:b
}
{
ICLASS    : PSLLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u32 IMM0:r:b
}
{
ICLASS    : PSRLQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u64 IMM0:r:b
}
{
ICLASS    : PSLLQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_B():rw:q:u64 IMM0:r:b
}
{
ICLASS    : PSRLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u64 IMM0:r:b
}
{
ICLASS    : PSRLDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u128 IMM0:r:b
}
{
ICLASS    : PSLLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u64 IMM0:r:b
}
{
ICLASS    : PSLLDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_B():rw:dq:u128 IMM0:r:b
}
{
ICLASS    : FXSAVE
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : FXSAVE
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX
PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b000] RM[nnn]  no_refining_prefix norexw_prefix MODRM()
OPERANDS  : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP
}
{
ICLASS    : FXRSTOR
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : FXSAVE
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn]   no_refining_prefix norexw_prefix MODRM()
OPERANDS  : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP
}
{
ICLASS    : FXSAVE64
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : FXSAVE64
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX
PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b000] RM[nnn]  no_refining_prefix rexw_prefix MODRM()
OPERANDS  : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP
}
{
ICLASS    : FXRSTOR64
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : FXSAVE64
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn]   no_refining_prefix rexw_prefix MODRM()
OPERANDS  : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP
}





{
ICLASS    : LDMXCSR
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : SSEMXCSR
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES :  MXCSR
PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn]  no_refining_prefix MODRM()
OPERANDS  : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP
}
{
ICLASS    : STMXCSR
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
ISA_SET   : SSEMXCSR
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES :  MXCSR_RD
PATTERN   : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix  MODRM()
OPERANDS  : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP
}
{
ICLASS    : PREFETCHNTA
CPL       : 3
CATEGORY  : PREFETCH
ATTRIBUTES: PREFETCH NONTEMPORAL
EXTENSION : SSE
ISA_SET   : SSE_PREFETCH
PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : PREFETCHT0
CPL       : 3
CATEGORY  : PREFETCH
ATTRIBUTES: PREFETCH
EXTENSION : SSE
ISA_SET   : SSE_PREFETCH
PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : PREFETCHT1
CPL       : 3
CATEGORY  : PREFETCH
ATTRIBUTES: PREFETCH
EXTENSION : SSE
ISA_SET   : SSE_PREFETCH
PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : PREFETCHT2
CPL       : 3
CATEGORY  : PREFETCH
ATTRIBUTES: PREFETCH
EXTENSION : SSE
ISA_SET   : SSE_PREFETCH
PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:r:mprefetch
}



{
ICLASS    : NOP
CPL       : 3
UNAME     : NOP0F18
CATEGORY  : WIDENOP
ATTRIBUTES: NOP
EXTENSION : BASE
ISA_SET   : FAT_NOP

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r0

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r1

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r2

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r3


PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v
IFORM     : NOP_MEMv_0F18r4

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r4

PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v
IFORM     : NOP_MEMv_0F18r5

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r5

PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v
IFORM     : NOP_MEMv_0F18r6

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r6

PATTERN   : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v
IFORM     : NOP_MEMv_0F18r7

PATTERN   : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS  : REG0=GPRv_B():r
IFORM     : NOP_GPRv_0F18r7
}
{
ICLASS    : NOP
UNAME     : NOP0F19
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F19

PATTERN   : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F19
}
{
ICLASS    : NOP
CPL       : 3
UNAME     : NOP0F1A
CATEGORY  : WIDENOP
ATTRIBUTES: NOP
EXTENSION : BASE
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1A

PATTERN   : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1A
}
{
ICLASS    : NOP
UNAME     : NOP0F1B
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1B

PATTERN   : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1B
}
{
ICLASS    : NOP
UNAME     : NOP0F1C
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1C

PATTERN   : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1C
}
{
ICLASS    : NOP
UNAME     : NOP0F1D
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1D

PATTERN   : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1D
}
{
ICLASS    : NOP
UNAME     : NOP0F1E
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1E

PATTERN   : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1E
}

{
ICLASS    : NOP
UNAME     : NOP0F1F
CPL       : 3
CATEGORY  : WIDENOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : FAT_NOP
PATTERN   : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
IFORM     : NOP_MEMv_GPRv_0F1F
PATTERN   : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : NOP_GPRv_GPRv_0F1F
}
{
ICLASS    : VMCALL
CPL       : 3
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : VMLAUNCH
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : VMRESUME
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
COMMENT   : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
FLAGS     : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : VMXOFF
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES: NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ]

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : SGDT
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()
OPERANDS  : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()
OPERANDS  : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP
}
{
ICLASS    : LIDT
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES: RING0 NOTSX
COMMENT   : 66 is OSZ; F2/F3 ignored
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() 
OPERANDS  : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() 
OPERANDS  : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP
}
{
ICLASS    : MONITOR
CPL       : 0
CATEGORY  : MISC
EXTENSION : SSE3
ATTRIBUTES: RING0 NOTSX

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32
OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP 

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16
OPERANDS  : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP 

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64
OPERANDS  : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP

PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32
OPERANDS  : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
}
{
ICLASS    : MWAIT
CPL       : 0
CATEGORY  : MISC
EXTENSION : SSE3
ATTRIBUTES: RING0 NOTSX
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix
OPERANDS  : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP
}
{
ICLASS    : SIDT
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES: NOTSX
COMMENT   : 66 is OSZ; F2/F3 ignored
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() 
OPERANDS  : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP
}
{
ICLASS    : SIDT
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
COMMENT   : 66 is OSZ; F2/F3 ignored
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()
OPERANDS  : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP
}
{
ICLASS    : INVLPG
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX
PATTERN   : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 
OPERANDS  : MEM0:r:b
}
{
ICLASS    : SWAPGS
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : LONGMODE
ATTRIBUTES: RING0 NOTSX
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 
OPERANDS  :
}
{
ICLASS    : RDTSCP
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : RDTSCP
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] 
OPERANDS  : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP
}
{
ICLASS    : SFENCE
CPL       : 3
CATEGORY  : MISC
EXTENSION : SSE
ATTRIBUTES: IGNORES_OSFXSR
PATTERN   : 0x0F 0xAE  MOD[0b11] MOD=3 REG[0b111] RM[nnn]  no_refining_prefix
OPERANDS  :
}
{
ICLASS    : CLFLUSH
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MISC
EXTENSION : CLFSH
ISA_SET   : CLFSH
PATTERN   : 0x0F 0xAE  MOD[mm] MOD!=3 REG[0b111] RM[nnn]  no_refining_prefix MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : LFENCE
CPL       : 3
CATEGORY  : MISC
EXTENSION : SSE2
ISA_SET   : SSE2
ATTRIBUTES: IGNORES_OSFXSR
PATTERN   : 0x0F 0xAE  MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : MFENCE
CPL       : 3
CATEGORY  : MISC
EXTENSION : SSE2
ISA_SET   : SSE2
ATTRIBUTES: IGNORES_OSFXSR
PATTERN   : 0x0F 0xAE  MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix
OPERANDS  :
}
{
ICLASS    : MOVHLPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32
}
{
ICLASS    : MOVLPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:q:f32 MEM0:r:q:f32
}
{
ICLASS    : MOVLHPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32
}
{
ICLASS    : MOVHPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:q:f32 MEM0:r:q:f32
}
{
ICLASS    : ADD_LOCK
DISASM    :  add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : ADD_GPR8_GPR8_00
}



{
ICLASS    : ADD_LOCK
DISASM    :  add
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : ADD_GPRv_GPRv_01
}



{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : ADD_GPR8_GPR8_02
}



{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : ADD_GPRv_GPRv_03
}

{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x04 SIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
}
{
ICLASS    : ADD
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x05 SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x06 not64
OPERANDS  : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0x07 not64
OPERANDS  : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
}

{
ICLASS    : OR_LOCK
DISASM    :  or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : OR_GPR8_GPR8_08
}




{
ICLASS    : OR_LOCK
DISASM    :  or
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : OR_GPRv_GPRv_09
}



{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : OR_GPR8_GPR8_0A
}



{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : OR_GPRv_GPRv_0B
}



{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x0C UIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b
}
{
ICLASS    : OR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x0D SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x0E not64
OPERANDS  : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}


{
ICLASS    : ADC_LOCK
DISASM    : adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : ADC_GPR8_GPR8_10
}



{
ICLASS    : ADC_LOCK
DISASM    :  adc
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : ADC_GPRv_GPRv_11
}



{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : ADC_GPR8_GPR8_12
}



{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]

PATTERN   : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : ADC_GPRv_GPRv_13
}





{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x14 SIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
}
{
ICLASS    : ADC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x15 SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x16 not64
OPERANDS  : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0x17 not64
COMMENT   : Inhibits all interrupts until after next instr
OPERANDS  : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
}
{
ICLASS    : SBB_LOCK
DISASM    :  sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : SBB_GPR8_GPR8_18
}






{
ICLASS    : SBB_LOCK
DISASM    :  sbb
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]

PATTERN   : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : SBB_GPRv_GPRv_19
}


{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : SBB_GPR8_GPR8_1A

PATTERN   : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : SBB_GPRv_GPRv_1B

PATTERN   : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x1C SIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
}
{
ICLASS    : SBB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
PATTERN   : 0x1D SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x1E not64
OPERANDS  : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0x1F not64
OPERANDS  : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
}



{
ICLASS    : AND_LOCK
DISASM    :  and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : AND_GPR8_GPR8_20
}



{
ICLASS    : AND_LOCK
DISASM    :  and
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : AND_GPRv_GPRv_21
}



{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : AND_GPR8_GPR8_22

PATTERN   : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : AND_GPRv_GPRv_23

PATTERN   : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x24 SIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
}
{
ICLASS    : AND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x25 SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : DAA
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x27 not64
OPERANDS  : REG0=XED_REG_AL:rw:SUPP
}



{
ICLASS    : SUB_LOCK
DISASM    :  sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : SUB_GPR8_GPR8_28
}


{
ICLASS    : SUB_LOCK
DISASM    :  sub
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : SUB_GPRv_GPRv_29
}



{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : SUB_GPR8_GPR8_2A
PATTERN   : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : SUB_GPRv_GPRv_2B

PATTERN   : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x2C SIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
}
{
ICLASS    : SUB
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x2D SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : DAS
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ]
PATTERN   : 0x2F not64
OPERANDS  : REG0=XED_REG_AL:rw:SUPP
}

{
ICLASS    : XOR_LOCK
DISASM    :  xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():r 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():r
IFORM     : XOR_GPR8_GPR8_30
}





{
ICLASS    : XOR_LOCK
DISASM    :  xor
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]

PATTERN   : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
IFORM     : XOR_GPRv_GPRv_31
}



{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():rw REG1=GPR8_B():r
IFORM     : XOR_GPR8_GPR8_32

PATTERN   : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():rw MEM0:r:b
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
IFORM     : XOR_GPRv_GPRv_33

PATTERN   : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x34 UIMM8()
OPERANDS  : REG0=XED_REG_AL:rw:IMPL IMM0:r:b
}
{
ICLASS    : XOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x35 SIMMz()
OPERANDS  : REG0=OrAX():rw:IMPL IMM0:r:z
}
{
ICLASS    : AAA
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ]
PATTERN   : 0x37 not64
OPERANDS  : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=GPR8_R():r

PATTERN   : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=GPR8_R():r
IFORM     : CMP_GPR8_GPR8_38
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
PATTERN   : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
IFORM     : CMP_GPRv_GPRv_39
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():r MEM0:r:b
PATTERN   : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():r REG1=GPR8_B():r
IFORM     : CMP_GPR8_GPR8_3A
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():r MEM0:r:v
PATTERN   : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():r REG1=GPRv_B():r
IFORM     : CMP_GPRv_GPRv_3B
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x3C SIMM8()
OPERANDS  : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8
}
{
ICLASS    : CMP
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x3D SIMMz()
OPERANDS  : REG0=OrAX():r:IMPL IMM0:r:z
}
{
ICLASS    : AAS
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ]
PATTERN   : 0x3F not64
OPERANDS  : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
}
{
ICLASS    : INC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0b0100_0 SRM[rrr] not64
OPERANDS  : REG0=GPRv_SB():rw
IFORM     : INC_GPRv_40
}
{
ICLASS    : DEC
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
PATTERN   : 0b0100_1 SRM[rrr] not64
OPERANDS  : REG0=GPRv_SB():rw
IFORM     : DEC_GPRv_48
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0b0101_0 SRM[rrr] DF64()
OPERANDS  : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP
IFORM     : PUSH_GPRv_50
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0b0101_1 SRM[rrr] DF64()
OPERANDS  : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP
IFORM     : POP_GPRv_51
}
{
ICLASS    : PUSHA
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I186
PATTERN   : 0x60 EOSZ=1 not64
OPERANDS  : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP
}
{
ICLASS    : PUSHAD
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x60 EOSZ=2 not64
OPERANDS  : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP
}
{
ICLASS    : POPA
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I186
PATTERN   : 0x61 EOSZ=1 not64
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP
COMMENT   : eSP value on the stack is ignored! 2008-08-14
}
{
ICLASS    : POPAD
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x61 EOSZ=2 not64
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP
COMMENT   : eSP value on the stack is ignored! 2008-08-14
}
{
ICLASS    : BOUND
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ATTRIBUTES: EXCEPTION_BR
ISA_SET   : I186
PATTERN   : 0x62 mode16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():r MEM0:r:a16
PATTERN   : 0x62 mode32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():r MEM0:r:a32
}
{
ICLASS    : ARPL
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
OPERANDS  : MEM0:rw:w REG0=GPR16_R():r
}
{
ICLASS    : ARPL
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES: PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64
OPERANDS  : REG0=GPR16_B():rw REG1=GPR16_R():r
}
{
ICLASS    : MOVSXD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : LONGMODE
PATTERN   : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:d
}
{
ICLASS    : MOVSXD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : LONGMODE
PATTERN   : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64
OPERANDS  : REG0=GPRv_R():w REG1=GPR32_B():r
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I186
PATTERN   : 0x68 DF64() SIMMz()
OPERANDS  : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : IMUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz()
OPERANDS  : REG0=GPRv_R():w MEM0:r:v IMM0:r:z

PATTERN   : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz()
OPERANDS  : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I186
PATTERN   : 0x6A DF64() SIMM8()
OPERANDS  : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : IMUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I186
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8()
OPERANDS  : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8

PATTERN   : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8()
OPERANDS  : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8
}


{
ICLASS    : REP_INSB
DISASM    : insb
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES :REP   fixed_base0  NOTSX BYTEOP
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6C repe
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0x6C repne
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 
}

{
ICLASS    : INSB
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : fixed_base0  NOTSX BYTEOP
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6C norep
OPERANDS  : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
}


{
ICLASS    : REP_INSW
DISASM    : insw
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : REP  fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6D EOSZ=1 repe
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0x6D EOSZ=1 repne
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : INSW
DISASM    : insw
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6D EOSZ=1 norep
OPERANDS  : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
}


{
ICLASS    : REP_INSD
DISASM    : insd
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :REP  fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6D EOSZ=2 repe
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6D EOSZ=3 repe
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6D EOSZ=2 repne
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6D EOSZ=3 repne
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 
}

{
ICLASS    : INSD
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6D EOSZ=2 norep
OPERANDS  : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP

PATTERN   : 0x6D EOSZ=3 norep
OPERANDS  : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
}


{
ICLASS    : REP_OUTSB
DISASM    : outsb
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES :REP  fixed_base0 NOTSX BYTEOP
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6E repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0x6E repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}

{
ICLASS    : OUTSB
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : fixed_base0 NOTSX BYTEOP
FLAGS     : READONLY [ iopl-tst df-tst ]

PATTERN   : 0x6E norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}


{
ICLASS    : REP_OUTSW
DISASM    : outsw
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES :REP  fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6F EOSZ=1 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0x6F EOSZ=1 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}

{
ICLASS    : OUTSW
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]
PATTERN   : 0x6F EOSZ=1 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}


{
ICLASS    : REP_OUTSD
DISASM    : outsd
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :REP  fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]

PATTERN   : 0x6F EOSZ=2 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6F EOSZ=3 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6F EOSZ=2 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 

PATTERN   : 0x6F EOSZ=3 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : OUTSD
CPL       : 3
CATEGORY  : IOSTRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : fixed_base0 NOTSX
FLAGS     : READONLY [ iopl-tst df-tst ]

PATTERN   : 0x6F EOSZ=2 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP

PATTERN   : 0x6F EOSZ=3 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}


{
ICLASS    : JO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x70 not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x71 not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x72 not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x73 not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x74 not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x75 not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8  REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x76 not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x77 not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x78 not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x79 not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7A not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7B not64  BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7C not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7D not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7E not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN   : 0x7F not64 BRANCH_HINT() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:b REG0=GPR8_R():r
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():r REG1=GPR8_R():r
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
}
{
ICLASS    : XCHG
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():rw 
PATTERN   : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():rw 
}
{
ICLASS    : XCHG
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():rw
}


{
ICLASS    : XCHG
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
PATTERN   : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():rw 
PATTERN   : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():rw 
}
{
ICLASS    : XCHG
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():rw
}


{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP
EXTENSION : BASE
ISA_SET   : I86

PATTERN   : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w REG1=GPR8_R():r
IFORM     : MOV_GPR8_GPR8_88
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP HLE_REL_ABLE
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b REG0=GPR8_R():r 
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : HLE_REL_ABLE
PATTERN   : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:v REG0=GPRv_R():r 
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():w REG1=GPRv_R():r
IFORM     : MOV_GPRv_GPRv_89
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPR8_R():w MEM0:r:b

PATTERN   : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_R():w REG1=GPR8_B():r
IFORM     : MOV_GPR8_GPR8_8A
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:v
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w REG1=GPRv_B():r
IFORM     : MOV_GPRv_GPRv_8B
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:w REG0=SEG():r
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():w REG1=SEG():r
}
{
ICLASS    : LEA
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT()
OPERANDS  : REG0=GPRv_R():w AGEN:r
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
COMMENT   : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
PATTERN   : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=SEG_MOV():w MEM0:r:w
IFORM     : MOV_SEG_MEMw
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
COMMENT   : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
PATTERN   : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=SEG_MOV():w REG1=GPR16_B():r
IFORM     : MOV_SEG_GPR16
}



{
ICLASS    : NOP
UNAME     : NOP90
CPL       : 3
CATEGORY  : NOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : I86
PATTERN   : 0b1001_0 SRM[0b000] SRM=0  not_refining_f3 norexb_prefix
OPERANDS  :
IFORM     : NOP_90
}
{
ICLASS    : PAUSE
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MISC
EXTENSION : PAUSE
ISA_SET   : PAUSE
PATTERN   : 0b1001_0 SRM[0b000] SRM=0  refining_f3 P4=1
OPERANDS  :
COMMENT   : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4
}
{
ICLASS    : NOP
CPL       : 3
CATEGORY  : NOP
EXTENSION : BASE
ATTRIBUTES: NOP
ISA_SET   : I86
PATTERN   : 0b1001_0 SRM[0b000] SRM=0  refining_f3 P4=0
OPERANDS  :
IFORM     : NOP_90
COMMENT   : This is the encoding of PAUSE on pre-P4 systems

}

{
ICLASS    : XCHG
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86

PATTERN   : 0b1001_0 SRM[rrr] SRM!=0
OPERANDS  : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL

PATTERN   : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix
OPERANDS  : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL
}
{
ICLASS    : CBW
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x98 EOSZ=1
OPERANDS  : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP
}
{
ICLASS    : CDQE
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : LONGMODE
PATTERN   : 0x98 EOSZ=3 mode64 rexw_prefix
OPERANDS  : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP
}
{
ICLASS    : CWDE
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x98 EOSZ=2
OPERANDS  : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP
}
{
ICLASS    : CWD
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x99 EOSZ=1
OPERANDS  : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP
}
{
ICLASS    : CQO
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : LONGMODE
PATTERN   : 0x99 EOSZ=3 mode64 rexw_prefix
OPERANDS  : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP
}
{
ICLASS    : CDQ
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x99 EOSZ=2
OPERANDS  : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP
}
{
ICLASS    : CALL_FAR
DISASM_INTEL    : call far
DISASM_ATTSV    : lcall
CPL       : 3
CATEGORY  : CALL
ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET   : I86

COMMENT   : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)

PATTERN   : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS  : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP

PATTERN   : 0x9A not64 BRDISPz() UIMM16()
OPERANDS  : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP
}
{
ICLASS    : FWAIT
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES : X87_CONTROL NOTSX
PATTERN   : 0x9B
OPERANDS  :
}
{
ICLASS    : PUSHF
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ id-tst  vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
PATTERN   : 0x9C DF64() EOSZ=1
OPERANDS  : REG0=XED_REG_STACKPUSH:w:w:SUPP
}
{
ICLASS    : PUSHFD
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
PATTERN   : 0x9C DF64() EOSZ=2 not64
OPERANDS  : REG0=XED_REG_STACKPUSH:w:d:SUPP
}
{
ICLASS    : PUSHFQ
CPL       : 3
CATEGORY  : PUSH
EXTENSION : LONGMODE
FLAGS     : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
PATTERN   : 0x9C DF64() EOSZ=3 mode64
OPERANDS  : REG0=XED_REG_STACKPUSH:w:q:SUPP
}
{
ICLASS    : POPF
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0x9D DF64() EOSZ=1
OPERANDS  : REG0=XED_REG_STACKPOP:r:w:SUPP
}
{
ICLASS    : POPFD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0x9D DF64() EOSZ=2 not64
OPERANDS  : REG0=XED_REG_STACKPOP:r:d:SUPP
}
{
ICLASS    : POPFQ
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : POP
EXTENSION : LONGMODE
FLAGS     : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0x9D DF64() EOSZ=3 mode64
OPERANDS  : REG0=XED_REG_STACKPOP:r:q:SUPP
}
{
ICLASS    : SAHF
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : LAHF
FLAGS     : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ]
PATTERN   : 0x9E
OPERANDS  : REG0=XED_REG_AH:r:SUPP
}
{
ICLASS    : LAHF
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : LAHF
FLAGS     : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ]
PATTERN   : 0x9F
OPERANDS  : REG0=XED_REG_AH:w:SUPP
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 BYTEOP
PATTERN   : 0xA0 MEMDISPv()   OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0
PATTERN   : 0xA1 MEMDISPv() OVERRIDE_SEG0()
OPERANDS  : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 BYTEOP
PATTERN   : 0xA2 MEMDISPv()  OVERRIDE_SEG0()
OPERANDS  : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0
PATTERN   : 0xA3 MEMDISPv() OVERRIDE_SEG0()
OPERANDS  : MEM0:w:v REG0=OrAX():r:IMPL  SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
}


{
ICLASS    : REP_MOVSB
DISASM    : movsb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP  fixed_base0 fixed_base1 BYTEOP
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA4 repe OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 

PATTERN   : 0xA4 repne OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP  MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : MOVSB
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA4 norep OVERRIDE_SEG1()
OPERANDS  : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP  MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
}



{
ICLASS    : REP_MOVSW
DISASM    : movsw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP  fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=1 repe OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 

PATTERN   : 0xA5 EOSZ=1 repne OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : MOVSW
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=1 norep  OVERRIDE_SEG1()
OPERANDS  : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
}



{
ICLASS    : REP_MOVSD
DISASM    : movsd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :REP  fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=2 repe OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 

PATTERN   : 0xA5 EOSZ=2 repne OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : MOVSD
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=2 norep OVERRIDE_SEG1()
OPERANDS  : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
}


{
ICLASS    : REP_MOVSQ
DISASM    : movsq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES :REP  fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=3 repe OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 

PATTERN   : 0xA5 EOSZ=3 repne OVERRIDE_SEG1()
OPERANDS  : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}

{
ICLASS    : MOVSQ
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : fixed_base0 fixed_base1
FLAGS     : READONLY [ df-tst ]

PATTERN   : 0xA5 EOSZ=3 norep OVERRIDE_SEG1()
OPERANDS  : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
}


{
ICLASS    : REPE_CMPSB
DISASM    : cmpsb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP
FLAGS     :  MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA6 repe OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_CMPSB
DISASM    : cmpsb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP
FLAGS     :  MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA6 repne OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}

{
ICLASS    : CMPSB
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :  fixed_base0 fixed_base1 BYTEOP
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0xA6 norep OVERRIDE_SEG0()
OPERANDS  : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
}


{
ICLASS    : REPE_CMPSW
DISASM    : cmpsw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=1 repe OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_CMPSW
DISASM    : cmpsw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=1 repne OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}

{
ICLASS    : CMPSW
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :  fixed_base0 fixed_base1
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xA7 EOSZ=1 norep OVERRIDE_SEG0()
OPERANDS  : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
}




{
ICLASS    : REPE_CMPSD
DISASM    : cmpsd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=2 repe OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_CMPSD
DISASM    : cmpsd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=2 repne OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}


{
ICLASS    : CMPSD
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :  fixed_base0 fixed_base1
FLAGS     : MUST  [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0xA7 EOSZ=2 norep OVERRIDE_SEG0()
OPERANDS  : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
}


{
ICLASS    : REPE_CMPSQ
DISASM    : cmpsq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=3 repe OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_CMPSQ
DISASM    : cmpsq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : REP  fixed_base0 fixed_base1
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]

PATTERN   : 0xA7 EOSZ=3 repne OVERRIDE_SEG0()
OPERANDS  : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 
}
{
ICLASS    : CMPSQ
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES :  fixed_base0 fixed_base1
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xA7 EOSZ=3 norep OVERRIDE_SEG0()
OPERANDS  : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
}


{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0xA8 SIMM8()
OPERANDS  : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8
}
{
ICLASS    : TEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
PATTERN   : 0xA9 SIMMz()
OPERANDS  : REG0=OrAX():r:IMPL IMM0:r:z
}

{
ICLASS    : REP_STOSB
DISASM    : stosb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP  fixed_base0 BYTEOP
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAA repe
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAA repne
OPERANDS  : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : STOSB
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 BYTEOP
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAA norep
OPERANDS  : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP
}



{
ICLASS    : REP_STOSW
DISASM    : stosw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP   fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=1 repe
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAB EOSZ=1 repne
OPERANDS  : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : STOSW
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=1 norep
OPERANDS  : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP
}




{
ICLASS    : REP_STOSD
DISASM    : stosd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :REP  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=2 repe
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAB EOSZ=2 repne
OPERANDS  : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : STOSD
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=2 norep
OPERANDS  : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP
}




{
ICLASS    : REP_STOSQ
DISASM    : stosq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES :REP  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=3 repe
OPERANDS  : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAB EOSZ=3 repne
OPERANDS  : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : STOSQ
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAB EOSZ=3 norep
OPERANDS  : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP
}




{
ICLASS    : REP_LODSB
DISASM    : lodsb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP  fixed_base0 BYTEOP
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAC repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAC repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : LODSB
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0 BYTEOP
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAC norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}




{
ICLASS    : REP_LODSW
DISASM    : lodsw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :REP  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=1 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAD EOSZ=1 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : LODSW
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=1 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}




{
ICLASS    : REP_LODSD
DISASM    : lodsd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :REP  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=2 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAD EOSZ=2 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : LODSD
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=2 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}



{
ICLASS    : REP_LODSQ
DISASM    : lodsq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES :REP  fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=3 repe OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
PATTERN   : 0xAD EOSZ=3 repne OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : LODSQ
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : fixed_base0
FLAGS     : READONLY [ df-tst ]
PATTERN   : 0xAD EOSZ=3 norep OVERRIDE_SEG0()
OPERANDS  : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
}



{
ICLASS    : REPE_SCASB
DISASM    : scasb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0 BYTEOP
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAE repe
OPERANDS  : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_SCASB
DISASM    : scasb
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0 BYTEOP
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAE repne
OPERANDS  : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}

{
ICLASS    : SCASB
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :  fixed_base0 BYTEOP
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xAE norep
OPERANDS  : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
}




{
ICLASS    : REPE_SCASW
DISASM    : scasw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=1 repe
OPERANDS  : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_SCASW
DISASM    : scasw
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : REP  fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=1 repne
OPERANDS  : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : SCASW
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES :  fixed_base0
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xAF EOSZ=1 norep
OPERANDS  : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
}




{
ICLASS    : REPE_SCASD
DISASM    : scasd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : REP fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=2 repe
OPERANDS  : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_SCASD
DISASM    : scasd
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : REP  fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=2 repne
OPERANDS  : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : SCASD
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES :  fixed_base0
FLAGS     :  MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xAF EOSZ=2 norep
OPERANDS  : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
}




{
ICLASS    : REPE_SCASQ
DISASM    : scasq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : REP fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=3 repe
OPERANDS  : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : REPNE_SCASQ
DISASM    : scasq
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES : REP  fixed_base0
FLAGS     : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
PATTERN   : 0xAF EOSZ=3 repne
OPERANDS  : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 
}
{
ICLASS    : SCASQ
CPL       : 3
CATEGORY  : STRINGOP
EXTENSION : LONGMODE
ATTRIBUTES :  fixed_base0
FLAGS     : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0xAF EOSZ=3 norep
OPERANDS  : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
}




{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
ATTRIBUTES : BYTEOP
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0b1011_0 SRM[rrr] UIMM8()
OPERANDS  : REG0=GPR8_SB():w IMM0:r:b
# i had to come up with a partial nibble name
IFORM     : MOV_GPR8_IMMb_D0
}
{
ICLASS    : MOV
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0b1011_1 SRM[rrr] UIMMv()
OPERANDS  : REG0=GPRv_SB():w IMM0:r:v
}
{
ICLASS    : RET_NEAR
DISASM    : ret
CPL       : 3
CATEGORY  : RET
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64()
OPERANDS  : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : RET_NEAR
DISASM    : ret
CPL       : 3
CATEGORY  : RET
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0xC3 DF64() IMMUNE66_LOOP64()
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : LES
CPL       : 3
CATEGORY  : SEGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
OPERANDS  : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP
}
{
ICLASS    : LDS
CPL       : 3
CATEGORY  : SEGOP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
OPERANDS  : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP
}
{
ICLASS    : ENTER
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
PATTERN   : 0xC8 DF64() UIMM16() UIMM8_1()
OPERANDS  : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP
}
{
ICLASS    : LEAVE
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : I186
ATTRIBUTES : fixed_base0
PATTERN   : 0xC9 DF64()
# Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of
#    the initial copy of rBP to rSP as part of the LEAVE's execution.
OPERANDS  : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP
}
{
ICLASS    : RET_FAR
DISASM_INTEL: ret far
DISASM_ATTSV: lcall
CPL       : 3
CATEGORY  : RET
ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET   : I86
COMMENT   : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented)
PATTERN   : 0xCA UIMM16() 
OPERANDS  : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : RET_FAR
DISASM_INTEL: ret far
DISASM_ATTSV: lcall
CPL       : 3
CATEGORY  : RET
ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xCB 
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : INT3
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ]
PATTERN   : 0xCC
OPERANDS  : REG0=rIP():w:SUPP
}
{
ICLASS    : INT
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ]
PATTERN   : 0xCD UIMM8()
OPERANDS  : IMM0:r:b REG0=rIP():w:SUPP
}
{
ICLASS    : INTO
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ]
PATTERN   : 0xCE not64
OPERANDS  : REG0=XED_REG_EIP:w:SUPP
}
{
ICLASS    : IRET
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : RET
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0xCF EOSZ=1
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : IRETD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : RET
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0xCF EOSZ=2
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
}
{
ICLASS    : IRETQ
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : RET
EXTENSION : LONGMODE
FLAGS     : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN   : 0xCF EOSZ=3 mode64
# FIXME: This is only an approximate width for the stack pops
OPERANDS  : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=XED_REG_RIP:w:SUPP
}
{
ICLASS    : AAM
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
PATTERN   : 0xD4 not64 SIMM8()
OPERANDS  : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP
}
{
ICLASS    : AAD
CPL       : 3
CATEGORY  : DECIMAL
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
PATTERN   : 0xD5 not64 SIMM8()
OPERANDS  : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
}
{
ICLASS    : SALC
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ cf-tst ]
PATTERN   : 0xD6 not64
OPERANDS  : REG0=XED_REG_AL:w:SUPP
COMMENT   : UNDOC - "The Undocumented PC", 2nd ed 1997, says it is present on all Intel CPUs of that time.
}
{
ICLASS    : XLAT
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : fixed_base0
PATTERN   : 0xD7 OVERRIDE_SEG0()
OPERANDS  : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP  INDEX=XED_REG_AL:r:SUPP  REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP
}


{
ICLASS    : LOOPNE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0xE0 MODEP5=1  REP=0  DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
PATTERN   : 0xE0 MODEP5=1  REP=2  DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
PATTERN   : 0xE0 MODEP5=0         DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP

COMMENT   : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC 
PATTERN   : 0xE1 MODEP5=1 REP=2  DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
}
{
ICLASS    : LOOPE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
PATTERN   : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
PATTERN   : 0xE1 MODEP5=0       DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP

COMMENT   : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC 
PATTERN   : 0xE0 MODEP5=1 REP=3  DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
}



{
ICLASS    : LOOP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64()
OPERANDS  : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
}

{
ICLASS    : JCXZ
COMMENT   : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0xE3 eamode16 BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP
}
{
ICLASS    : JECXZ
COMMENT   : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0xE3 eamode32 not64 BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP
PATTERN   : 0xE3 eamode32 mode64 BRDISP8() FORCE64()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
}
{
ICLASS    : JRCXZ
COMMENT   : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : LONGMODE
PATTERN   : 0xE3 eamode64 BRDISP8() FORCE64()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
}

{
ICLASS    : IN
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP NOTSX
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xE4 UIMM8() IMMUNE_REXW()
OPERANDS  : REG0=XED_REG_AL:w:IMPL IMM0:r:b
}
{
ICLASS    : IN
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xE5 UIMM8() IMMUNE_REXW()
OPERANDS  : REG0=OeAX():w:IMPL IMM0:r:b
}

{
ICLASS    : OUT
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX BYTEOP
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xE6 UIMM8() IMMUNE_REXW()
OPERANDS  : IMM0:r:b REG0=XED_REG_AL:r:IMPL
}

{
ICLASS    : OUT
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xE7 UIMM8() IMMUNE_REXW()
OPERANDS  : IMM0:r:b REG0=OeAX():r:IMPL
}

{
ICLASS    : JMP
CPL       : 3
CATEGORY  : UNCOND_BR
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0xE9 not64 BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
PATTERN   : 0xE9 mode64 FORCE64() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
{
ICLASS    : JMP_FAR
DISASM_INTEL: jmp far
DISASM_ATTSV: ljmp
CPL       : 3
CATEGORY  : UNCOND_BR
ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xEA not64 BRDISPz() UIMM16()
OPERANDS  : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP
}
{
ICLASS    : JMP
CPL       : 3
CATEGORY  : UNCOND_BR
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xEB not64 BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
PATTERN   : 0xEB mode64 FORCE64() BRDISP8()
OPERANDS  : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
}
{
ICLASS    : IN
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xEC IMMUNE_REXW()
OPERANDS  : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL
}
{
ICLASS    : IN
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xED IMMUNE_REXW()
OPERANDS  : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL
}
{
ICLASS    : OUT
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xEE IMMUNE_REXW()
OPERANDS  : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL
}
{
ICLASS    : OUT
CPL       : 3
CATEGORY  : IO
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ iopl-tst ]
PATTERN   : 0xEF IMMUNE_REXW()
OPERANDS  : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL
}
{
ICLASS    : INT1
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xF1
OPERANDS  : REG0=rIP():w:SUPP
COMMENT   : UNDOC by Intel, but in AMD's opcode map
}
{
ICLASS    : HLT
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ATTRIBUTES : RING0 NOTSX
ISA_SET   : I86
PATTERN   : 0xF4
OPERANDS  :
}
{
ICLASS    : CMC
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ cf-tst cf-mod ]
PATTERN   : 0xF5
OPERANDS  :
}
{
ICLASS    : CLC
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ cf-0 ]
PATTERN   : 0xF8
OPERANDS  :
}
{
ICLASS    : STC
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ cf-1 ]
PATTERN   : 0xF9
OPERANDS  :
}
{
ICLASS    : CLI
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ vif-mod iopl-tst if-mod ]
PATTERN   : 0xFA
OPERANDS  :
}
{
ICLASS    : STI
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
COMMENT   : Inhibits all interrupts until after next instr
FLAGS     : MUST [ vif-mod iopl-tst if-mod ]
PATTERN   : 0xFB
OPERANDS  :
}
{
ICLASS    : CLD
ATTRIBUTES: NOTSX_COND
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ df-0 ]
PATTERN   : 0xFC
OPERANDS  :
}
{
ICLASS    : STD
ATTRIBUTES: NOTSX_COND
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ df-1 ]
PATTERN   : 0xFD
OPERANDS  :
}
{
ICLASS    : LAR
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES : PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
COMMENT   : LAR only sometimes writes its destination register.
PATTERN   : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:w
PATTERN   : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : LSL
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286PROTECTED
ATTRIBUTES : PROTECTED_MODE
FLAGS     : MUST [ zf-mod ]
PATTERN   : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:w

PATTERN   : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRz_B():r
}
{
ICLASS    : SYSCALL
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : SYSCALL
EXTENSION : LONGMODE
ISA_SET   : LONGMODE
FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0x05 mode64 FORCE64()
OPERANDS  : REG0=XED_REG_RIP:w:SUPP
COMMENT   : 32B VERSION IS ONLY SUPPORTED ON AMD
}
{
ICLASS    : CLTS
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I286REAL
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x06
OPERANDS  :
}
{
ICLASS    : SYSRET
CPL       : 0
CATEGORY  : SYSRET
ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
EXTENSION : LONGMODE
ISA_SET   : LONGMODE
FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0x07 mode64 eosz64
OPERANDS  : REG0=XED_REG_RIP:w:SUPP
PATTERN   : 0x0F 0x07 mode64 eosz32
OPERANDS  : REG0=XED_REG_EIP:w:SUPP
COMMENT   : 32B VERSION IS ONLY SUPPORTED ON AMD
}
{
ICLASS    : MOVUPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4M
ATTRIBUTES : 
PATTERN   : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps

PATTERN   : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
IFORM     : MOVUPS_XMMps_XMMps_0F10

PATTERN   : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:ps REG0=XMM_R():r:ps

PATTERN   : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_B():w:ps REG1=XMM_R():r:ps
IFORM     : MOVUPS_XMMps_XMMps_0F11
}
{
ICLASS    : MOVLPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  no_refining_prefix MODRM()
OPERANDS  : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32
}
{
ICLASS    : UNPCKLPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:dq
PATTERN   : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:q
}
{
ICLASS    : UNPCKHPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:dq
PATTERN   : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq
}
{
ICLASS    : MOVHPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  no_refining_prefix MODRM()
OPERANDS  : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32
}
{
ICLASS    : MOVSS
CPL       : 3
ATTRIBUTES : simd_scalar 
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
PATTERN   : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:f32 MEM0:r:ss

PATTERN   : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
IFORM     : MOVSS_XMMss_XMMss_0F10

PATTERN   : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : MEM0:w:ss REG0=XMM_R():r:ss

PATTERN   : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_B():w:ss REG1=XMM_R():r:ss
IFORM     : MOVSS_XMMss_XMMss_0F11
}
{
ICLASS    : MOVSLDUP
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps
PATTERN   : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MOVSHDUP
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps
PATTERN   : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MOVUPD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4M
ATTRIBUTES : 
PATTERN   : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:pd MEM0:r:pd

PATTERN   : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
IFORM     : MOVUPD_XMMpd_XMMpd_0F10

PATTERN   : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:pd REG0=XMM_R():r:pd

PATTERN   : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_B():w:pd REG1=XMM_R():r:pd
IFORM     : MOVUPD_XMMpd_XMMpd_0F11
}
{
ICLASS    : MOVLPD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:sd MEM0:r:q
PATTERN   : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:q REG0=XMM_R():r:sd
}
{
ICLASS    : UNPCKLPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:dq
PATTERN   : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:q
}
{
ICLASS    : UNPCKHPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64   REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:dq
PATTERN   : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:q
}
{
ICLASS    : MOVHPD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:sd MEM0:r:q
PATTERN   : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:q REG0=XMM_R():r:sd
}
{
ICLASS    : MOVSD_XMM
DISASM    : movsd
CPL       : 3
ATTRIBUTES : simd_scalar 
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
PATTERN   : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:f64 MEM0:r:sd

PATTERN   : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:sd REG1=XMM_B():r:sd
IFORM     : MOVSD_XMM_XMMsd_XMMsd_0F10

PATTERN   : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : MEM0:w:sd REG0=XMM_R():r:sd

PATTERN   : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_B():w:sd REG1=XMM_R():r:sd
IFORM     : MOVSD_XMM_XMMsd_XMMsd_0F11
}
{
ICLASS    : MOVDDUP
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:q
PATTERN   : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:q
}

{
ICLASS    : MOV_CR
DISASM    : mov
CPL       : 0
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : RING0 NOTSX
COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
PATTERN   : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
OPERANDS  : REG0=CR_R():w REG1=GPR32_B():r

PATTERN   : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
OPERANDS  : REG0=CR_R():w REG1=GPR64_B():r
}

{
ICLASS    : MOV_CR
DISASM    : mov
CPL       : 0
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : RING0
COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
PATTERN   : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
OPERANDS  : REG0=GPR32_B():w REG1=CR_R():r

PATTERN   : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
OPERANDS  : REG0=GPR64_B():w REG1=CR_R():r
}

{
ICLASS    : MOV_DR
DISASM    : mov
CPL       : 0
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : RING0 NOTSX
COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() not64
OPERANDS  : REG0=DR_R():w REG1=GPR32_B():r

PATTERN   : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() mode64
OPERANDS  : REG0=DR_R():w REG1=GPR64_B():r
}

{
ICLASS    : MOV_DR
DISASM    : mov
CPL       : 0
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES : RING0
COMMENT   :  MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() not64
OPERANDS  : REG0=GPR32_B():w REG1=DR_R():r

PATTERN   : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() mode64
OPERANDS  : REG0=GPR64_B():w REG1=DR_R():r
}


{
ICLASS    : WRMSR
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : PENTIUMREAL
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x30
OPERANDS  : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP
}
{
ICLASS    : RDTSC
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : PENTIUMREAL
PATTERN   : 0x0F 0x31
OPERANDS  : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP
}
{
ICLASS    : RDMSR
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : PENTIUMREAL
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x32
OPERANDS  : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP
}
{
ICLASS    : RDPMC
CPL       : 3
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : RDPMC
PATTERN   : 0x0F 0x33
OPERANDS  : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP
}
{
ICLASS    : SYSENTER
CPL       : 3
CATEGORY  : SYSCALL
EXTENSION : BASE
ISA_SET   : PPRO
ATTRIBUTES: PROTECTED_MODE NOTSX
FLAGS     : MUST [ vm-0 rf-0 if-0 ]
PATTERN   : 0x0F 0x34
OPERANDS  : REG0=rIP():w:SUPP
COMMENT   : AMD does not document support for this in 64b mode
}
{
ICLASS    : SYSEXIT
CPL       : 0
CATEGORY  : SYSRET
EXTENSION : BASE
ISA_SET   : PPRO
ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
PATTERN   : 0x0F 0x35
OPERANDS  : REG0=rIP():w:SUPP
COMMENT   : AMD does not document support for this in 64b mode
}
{
ICLASS    : CMOVO
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ of-tst ]
PATTERN   : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNO
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ of-tst ]
PATTERN   : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVB
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ cf-tst ]
PATTERN   : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNB
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ cf-tst ]
PATTERN   : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVZ
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNZ
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVBE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ cf-tst zf-tst ]
PATTERN   : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNBE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ cf-tst zf-tst ]
PATTERN   : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
PATTERN   : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : MOVMSKPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():w REG1=XMM_B():r:ps
}
{
ICLASS    : SQRTPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps
PATTERN   : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
}
{
ICLASS    : RSQRTPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps
PATTERN   : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
}
{
ICLASS    : RCPPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps
PATTERN   : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
}
{
ICLASS    : ANDPS
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : ANDNPS
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : ORPS
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : XORPS
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : SQRTSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ss MEM0:r:ss
PATTERN   : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
}
{
ICLASS    : RSQRTSS
CPL       : 3
ATTRIBUTES : simd_scalar 
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
PATTERN   : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ss MEM0:r:ss
PATTERN   : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
}
{
ICLASS    : RCPSS
CPL       : 3
ATTRIBUTES : simd_scalar 
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_5
PATTERN   : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ss MEM0:r:ss
PATTERN   : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
}
{
ICLASS    : MOVMSKPD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=GPR32_R():w REG1=XMM_B():r:pd
}
{
ICLASS    : SQRTPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:pd MEM0:r:pd
PATTERN   : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
}
{
ICLASS    : ANDPD
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : ANDNPD
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : ORPD
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : XORPD
CPL       : 3
CATEGORY  : LOGICAL_FP
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : SQRTSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:sd MEM0:r:sd
PATTERN   : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:sd REG1=XMM_B():r:sd
}
{
ICLASS    : PUNPCKLBW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8

PATTERN   : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8
}
{
ICLASS    : PUNPCKLWD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16
PATTERN   : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16
}
{
ICLASS    : PUNPCKLDQ
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32
PATTERN   : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32
}
{
ICLASS    : PACKSSWB
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
}
{
ICLASS    : PACKSSWB
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PCMPGTB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
}
{
ICLASS    : PCMPGTB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
}
{
ICLASS    : PCMPGTW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
}
{
ICLASS    : PCMPGTW
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PCMPGTD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
}
{
ICLASS    : PCMPGTD
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
}
{
ICLASS    : PACKUSWB
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
}
{
ICLASS    : PACKUSWB
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PUNPCKLBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PUNPCKLWD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PUNPCKLDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PACKSSWB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT  HALF_WIDE_OUTPUT
PATTERN   : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PCMPGTB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
PATTERN   : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
}
{
ICLASS    : PCMPGTW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PCMPGTD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
PATTERN   : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
}
{
ICLASS    : PACKUSWB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
PATTERN   : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PSHUFW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
OPERANDS  : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b
PATTERN   : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b
}
{
ICLASS    : PCMPEQB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
PATTERN   : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
}
{
ICLASS    : PCMPEQW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
PATTERN   : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PCMPEQD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
PATTERN   : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
}
{
ICLASS    : EMMS
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : x87_mmx_state_w NOTSX
PATTERN   : 0x0F 0x77 no_refining_prefix
OPERANDS  :
}
{
ICLASS    : PSHUFD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b
PATTERN   : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b
}
{
ICLASS    : PCMPEQB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
PATTERN   : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
}
{
ICLASS    : PCMPEQW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PCMPEQD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
PATTERN   : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
}
{
ICLASS    : PSHUFLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b
PATTERN   : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b
}
{
ICLASS    : PSHUFHW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b
PATTERN   : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b
}
{
ICLASS    : JO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP 
}
{
ICLASS    : JO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}


{
ICLASS    : JNO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNO
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JNB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP

}
{
ICLASS    : JNB
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JNZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP

}
{
ICLASS    : JNZ
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JNBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNBE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}




{
ICLASS    : SETO
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ of-tst ]
PATTERN   : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNO
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ of-tst ]
PATTERN   : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETB
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ cf-tst ]
PATTERN   : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNB
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ cf-tst ]
PATTERN   : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETZ
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNZ
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ zf-tst ]
PATTERN   : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETBE
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ cf-tst zf-tst ]
PATTERN   : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNBE
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ cf-tst zf-tst ]
PATTERN   : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x0F 0xA0 DF64()
OPERANDS  : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xA1 DF64()
OPERANDS  : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
}
{
ICLASS    : CPUID
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : I486REAL
PATTERN   : 0x0F 0xA2
OPERANDS  : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP
}
{
ICLASS    : BT
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u  af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:r:v REG0=GPRv_R():r
PATTERN   : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():r REG1=GPRv_R():r
}

{
ICLASS    : CMPXCHG_LOCK
DISASM    :  cmpxchg
CPL       : 3
CATEGORY  : SEMAPHORE
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
EXTENSION : BASE
ISA_SET   : I486REAL
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP 
}
{
ICLASS    : CMPXCHG
CPL       : 3
CATEGORY  : SEMAPHORE
ATTRIBUTES : BYTEOP LOCKABLE
EXTENSION : BASE
ISA_SET   : I486REAL
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP 
}
{
ICLASS    : CMPXCHG
CPL       : 3
CATEGORY  : SEMAPHORE
ATTRIBUTES : BYTEOP
EXTENSION : BASE
ISA_SET   : I486REAL
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP
}



{
ICLASS    : CMPXCHG_LOCK
DISASM    :  cmpxchg
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP 
}
{
ICLASS    : CMPXCHG
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP 
}
{
ICLASS    : CMPXCHG
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP
}



{
ICLASS    : LSS
CPL       : 3
CATEGORY  : SEGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP
}
{
ICLASS    : BTR_LOCK
DISASM    :  btr
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
}

{
ICLASS    : LFS
CPL       : 3
CATEGORY  : SEGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP
}
{
ICLASS    : LGS
CPL       : 3
CATEGORY  : SEGOP
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP
}
{
ICLASS    : MOVZX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:b
PATTERN   : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w REG1=GPR8_B():r
PATTERN   : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:w
PATTERN   : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w REG1=GPR16_B():r
}
{
ICLASS    : XADD_LOCK
DISASM    :  xadd
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():rw 
}
{
ICLASS    : XADD
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : BYTEOP LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:b REG0=GPR8_R():rw 
}
{
ICLASS    : XADD
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : BYTEOP
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():rw REG1=GPR8_R():rw
}



{
ICLASS    : XADD_LOCK
DISASM    :  xadd
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():rw 
}
{
ICLASS    : XADD
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():rw 
}
{
ICLASS    : XADD
CPL       : 3
CATEGORY  : SEMAPHORE
EXTENSION : BASE
ISA_SET   : I486REAL
FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]

PATTERN   : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():rw
}


{
ICLASS    : CMPPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b
PATTERN   : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b
}
{
ICLASS    : MOVNTI
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL
PATTERN   : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  EOSZ!=3 MODRM()
OPERANDS  : MEM0:w:d REG0=GPR32_R():r
PATTERN   : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  EOSZ=3 MODRM()
OPERANDS  : MEM0:w:q REG0=GPR64_R():r
}
{
ICLASS    : PINSRW
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES :  NOTSX
PATTERN   : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
OPERANDS  : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b
PATTERN   : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b
}
{
ICLASS    : PEXTRW
EXCEPTIONS: mmx-nomem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b
}
{
ICLASS    : SHUFPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b
PATTERN   : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b
}
{
ICLASS    : CMPSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b
PATTERN   : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b
}
{
ICLASS    : CMPPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b
PATTERN   : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b
}
{
ICLASS    : PINSRW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b
PATTERN   : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b
}
{
ICLASS    : PEXTRW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
PATTERN   : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b
}
{
ICLASS    : SHUFPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b
PATTERN   : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b
}
{
ICLASS    : CMPSD_XMM
DISASM    : cmpsd 
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b
PATTERN   : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b
}
{
ICLASS    : PSRLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u16 MEM0:r:q
}
{
ICLASS    : PSRLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
}
{
ICLASS    : PSRLD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u32 MEM0:r:q
}
{
ICLASS    : PSRLD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q
}
{
ICLASS    : PSRLQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u64 MEM0:r:q
}
{
ICLASS    : PSRLQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q
}
{
ICLASS    : PADDQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSE2
PATTERN   : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64
PATTERN   : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64
}
{
ICLASS    : PMULLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
PATTERN   : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PMOVMSKB
EXCEPTIONS: mmx-nomem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : SSE
COMMENT   : KNI on PentiumIII. MMX instructions intro'd w/SSE
PATTERN   : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():w REG1=MMX_B():r:q:i8
}
{
ICLASS    : ADDSUBPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : PSRLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
}
{
ICLASS    : PSRLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}



{
ICLASS    : PSRLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
}
{
ICLASS    : PSRLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}




{
ICLASS    : PSRLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
}
{
ICLASS    : PSRLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS:  SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}




{
ICLASS    : PADDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMULLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMOVMSKB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
PATTERN   : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8
}
{
ICLASS    : MOVQ2DQ
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
ATTRIBUTES : MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64
}
{
ICLASS    : ADDSUBPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MOVDQ2Q
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
ATTRIBUTES : MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64
}
{
ICLASS    : PAVGB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PAVGB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
}
{
ICLASS    : PSRAW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q
}
{
ICLASS    : PSRAW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q
}
{
ICLASS    : PSRAD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i32 MEM0:r:q
}
{
ICLASS    : PSRAD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q
}
{
ICLASS    : PAVGW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
}
{
ICLASS    : PAVGW
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PMULHUW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16
}
{
ICLASS    : PMULHUW
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16
}
{
ICLASS    : PMULHW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
}
{
ICLASS    : PMULHW
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : MOVNTQ
EXCEPTIONS: mmx-nofp2
ATTRIBUTES: NOTSX NONTEMPORAL
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:q REG0=MMX_R():r:q
}
{
ICLASS    : PAVGB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8
PATTERN   : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8
}


{
ICLASS    : PSRAW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64
}
{
ICLASS    : PSRAW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64
}




{
ICLASS    : PSRAD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64
}
{
ICLASS    : PSRAD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64
}




{
ICLASS    : PAVGW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16
PATTERN   : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16
}
{
ICLASS    : PMULHUW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16
PATTERN   : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16
}
{
ICLASS    : PMULHW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : CVTTPD2DQ
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64
PATTERN   : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64
}
{
ICLASS    : MOVNTDQ
ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_1
PATTERN   : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:dq REG0=XMM_R():r:dq
}
{
ICLASS    : CVTDQ2PD
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES :  MXCSR
PATTERN   : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32
PATTERN   : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32
}
{
ICLASS    : CVTPD2DQ
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64
PATTERN   : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64
}
{
ICLASS    : PSLLW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u16 MEM0:r:q
PATTERN   : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
}
{
ICLASS    : PSLLD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u32 MEM0:r:q
PATTERN   : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q
}
{
ICLASS    : PSLLQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u64 MEM0:r:q
PATTERN   : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q
}
{
ICLASS    : PMULUDQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSE2
PATTERN   : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32
PATTERN   : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32
}
{
ICLASS    : PMADDWD
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
PATTERN   : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
}
{
ICLASS    : PSADBW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : MASKMOVQ
EXCEPTIONS: mmx-nofp2
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
PATTERN   : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  OVERRIDE_SEG0()
OPERANDS  : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
}


{
ICLASS    : PSLLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:u16 MEM0:r:dq
}
{
ICLASS    : PSLLW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq
}



{
ICLASS    : PSLLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
}
{
ICLASS    : PSLLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}





{
ICLASS    : PSLLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64
}
{
ICLASS    : PSLLQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_7
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64
}



{
ICLASS    : PMULUDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMADDWD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES:  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PSADBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : MASKMOVDQU
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
PATTERN   : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() OVERRIDE_SEG0()
OPERANDS  : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
}
{
ICLASS    : LDDQU
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : 
PATTERN   : 0x0F 0xF0  MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix
OPERANDS  : REG0=XMM_R():w:pd MEM0:r:dq
}
{
ICLASS    : INVD
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x08
OPERANDS  :
}
{
ICLASS    : WBINVD
CPL       : 0
CATEGORY  : SYSTEM
EXTENSION : BASE
ISA_SET   : I486REAL
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x09
OPERANDS  :
}
{
ICLASS    : UD0
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : PPRO
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xFF
OPERANDS  :
}
{
ICLASS    : UD1
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : PPRO
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=GPR32_R():r MEM0:r:d
PATTERN   : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():r REG1=GPR32_B():r 
}
{
ICLASS    : UD2
CPL       : 3
CATEGORY  : MISC
EXTENSION : BASE
ISA_SET   : PPRO
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0x0B
OPERANDS  :
}
{
ICLASS    : MOVAPS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_1
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps MEM0:r:ps

PATTERN   : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
IFORM     : MOVAPS_XMMps_XMMps_0F28

PATTERN   : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:ps REG0=XMM_R():r:ps

PATTERN   : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_B():w:ps REG1=XMM_R():r:ps
IFORM     : MOVAPS_XMMps_XMMps_0F29
}

{
ICLASS    : CVTPI2PS
EXCEPTIONS: mmx-fp
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:q:f32 MEM0:r:q:i32
PATTERN   : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:q:f32 REG1=MMX_B():r:q:i32
}
{
ICLASS    : MOVNTPS
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_1
PATTERN   : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:dq REG0=XMM_R():r:ps
}
{
ICLASS    : CVTTPS2PI
EXCEPTIONS: mmx-fp
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q:i32 MEM0:r:q:f32
PATTERN   : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32
}
{
ICLASS    : CVTPS2PI
EXCEPTIONS: mmx-fp
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q:f32 MEM0:r:q:i32
PATTERN   : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q:f32 REG1=XMM_B():r:q:i32
}
{
ICLASS    : UCOMISS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
FLAGS     : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
PATTERN   : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():r:ss MEM0:r:ss
PATTERN   : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():r:ss REG1=XMM_B():r:ss
}
{
ICLASS    : COMISS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
FLAGS     : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
PATTERN   : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():r:ss MEM0:r:ss
PATTERN   : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():r:ss REG1=XMM_B():r:ss
}
{
ICLASS    : CVTSI2SS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:ss:f32 MEM0:r:d:i32
PATTERN   : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=XMM_R():w:ss:f32 REG1=GPR32_B():r:d:i32
PATTERN   : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:ss:f32 MEM0:r:q:i32
PATTERN   : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=XMM_R():w:ss:f32 REG1=GPR64_B():r:q:i32
}
{
ICLASS    : CVTTSS2SI
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32
PATTERN   : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32
PATTERN   : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32
PATTERN   : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32
}
{
ICLASS    : CVTSS2SI
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32
PATTERN   : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32
PATTERN   : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32
PATTERN   : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32
}
{
ICLASS    : MOVAPD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_1
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:pd MEM0:r:pd

PATTERN   : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
IFORM     : MOVAPD_XMMpd_XMMpd_0F28

PATTERN   : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:pd REG0=XMM_R():r:pd

PATTERN   : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_B():w:pd REG1=XMM_R():r:pd
IFORM     : MOVAPD_XMMpd_XMMpd_0F29
}
{
ICLASS    : CVTPI2PD
EXCEPTIONS: mmx-nofp
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32
PATTERN   : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32
}
{
ICLASS    : MOVNTPD
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_1
PATTERN   : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:dq REG0=XMM_R():r:pd
}
{
ICLASS    : CVTTPD2PI
EXCEPTIONS: mmx-fp-16align
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64
PATTERN   : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64
}
{
ICLASS    : CVTPD2PI
EXCEPTIONS: mmx-fp-16align
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX
PATTERN   : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64
PATTERN   : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64
}
{
ICLASS    : UCOMISD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
FLAGS     : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
PATTERN   : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():r:sd MEM0:r:sd
PATTERN   : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():r:sd REG1=XMM_B():r:sd
}
{
ICLASS    : COMISD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
FLAGS     : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
PATTERN   : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():r:sd MEM0:r:sd
PATTERN   : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():r:sd REG1=XMM_B():r:sd
}
{
ICLASS    : CVTSI2SD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:sd:f64 MEM0:r:d:i32
PATTERN   : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=XMM_R():w:sd:f64 REG1=GPR32_B():r:d:i32
PATTERN   : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:sd:f64 MEM0:r:q:i64
PATTERN   : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=XMM_R():w:sd:f64 REG1=GPR64_B():r:q:i64
}
{
ICLASS    : CVTTSD2SI
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64
PATTERN   : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64
PATTERN   : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64
PATTERN   : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64
}
{
ICLASS    : CVTSD2SI
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix MODRM()
OPERANDS  : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64
PATTERN   : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() norexw_prefix
OPERANDS  : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64
PATTERN   : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix MODRM()
OPERANDS  : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64
PATTERN   : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66() rexw_prefix
OPERANDS  : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64
}
{
ICLASS    : CMOVS
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVS
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNS
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVNS
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVP
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVP
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNP
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVNP
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVL
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVL
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNL
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVNL
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVLE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVLE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : CMOVNLE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v
}
{
ICLASS    : CMOVNLE
CPL       : 3
CATEGORY  : CMOV
EXTENSION : BASE
ISA_SET   : CMOV
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : ADDPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MULPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : CVTPS2PD
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
ATTRIBUTES: MXCSR 
PATTERN   : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32
PATTERN   : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32
}
{
ICLASS    : CVTDQ2PS
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32
PATTERN   : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32
}
{
ICLASS    : SUBPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MINPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : DIVPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : MAXPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : ADDSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : MULSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : CVTSS2SD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:sd:f64 MEM0:r:ss:f32
PATTERN   : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:sd:f64 REG1=XMM_B():r:ss:f32
}
{
ICLASS    : CVTTPS2DQ
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32
PATTERN   : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32
}
{
ICLASS    : SUBSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : MINSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : DIVSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : MAXSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ss MEM0:r:ss
PATTERN   : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
}
{
ICLASS    : ADDPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : MULPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : CVTPD2PS
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64
PATTERN   : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64
}
{
ICLASS    : CVTPS2DQ
CPL       : 3
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32
PATTERN   : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32
}
{
ICLASS    : SUBPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : MINPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : DIVPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : MAXPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR MXCSR
PATTERN   : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : ADDSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : MULSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : CVTSD2SS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : CONVERT
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:ss:f32 MEM0:r:sd:f64
PATTERN   : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:ss:f32 REG1=XMM_B():r:sd:f64
}
{
ICLASS    : SUBSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : MINSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : DIVSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : MAXSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:sd MEM0:r:sd
PATTERN   : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
}
{
ICLASS    : PUNPCKHBW
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : SKIPLOW32 NOTSX
PATTERN   : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:d
}
{
ICLASS    : PUNPCKHWD
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : SKIPLOW32 NOTSX
PATTERN   : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:d
}
{
ICLASS    : PUNPCKHDQ
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : SKIPLOW32 NOTSX
PATTERN   : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:d
}
{
ICLASS    : PACKSSDW
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
}
{
ICLASS    : PACKSSDW
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
}
{
ICLASS    : MOVD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 norexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:d
PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() mode64 norexw_prefix
OPERANDS  : REG0=XMM_R():w:dq REG1=GPR32_B():r
PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64 MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:d
PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() not64
OPERANDS  : REG0=XMM_R():w:dq REG1=GPR32_B():r


PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 norexw_prefix  MODRM()
OPERANDS  : MEM0:w:d REG0=XMM_R():r:d
PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() mode64 norexw_prefix
OPERANDS  : REG0=GPR32_B():w REG1=XMM_R():r:d
PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64 MODRM()
OPERANDS  : MEM0:w:d REG0=XMM_R():r:d
PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() not64
OPERANDS  : REG0=GPR32_B():w REG1=XMM_R():r:d
}
{
ICLASS    : MOVD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
ATTRIBUTES :  NOTSX
PATTERN   : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  mode64 norexw_prefix MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:d

PATTERN   : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  mode64 norexw_prefix
OPERANDS  : REG0=MMX_R():w:q REG1=GPR32_B():r

PATTERN   : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  not64  MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:d

PATTERN   : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  not64
OPERANDS  : REG0=MMX_R():w:q REG1=GPR32_B():r


PATTERN   : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  mode64 norexw_prefix MODRM()
OPERANDS  : MEM0:w:d REG0=MMX_R():r:d

PATTERN   : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  mode64 norexw_prefix
OPERANDS  : REG0=GPR32_B():w REG1=MMX_R():r:d

PATTERN   : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  not64 MODRM()
OPERANDS  : MEM0:w:d REG0=MMX_R():r:d

PATTERN   : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  not64
OPERANDS  : REG0=GPR32_B():w REG1=MMX_R():r:d
}


{
ICLASS    : MOVQ
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 rexw_prefix MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:q
IFORM     : MOVQ_XMMdq_MEMq_0F6E

PATTERN   : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() mode64 rexw_prefix
OPERANDS  : REG0=XMM_R():w:dq REG1=GPR64_B():r

PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 rexw_prefix MODRM()
OPERANDS  : MEM0:w:q REG0=XMM_R():r:q
IFORM     : MOVQ_MEMq_XMMq_0F7E

PATTERN   : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() mode64 rexw_prefix
OPERANDS  : REG0=GPR64_B():w REG1=XMM_R():r:q

PATTERN   : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:q REG0=XMM_R():r:q
IFORM     : MOVQ_MEMq_XMMq_0FD6

PATTERN   : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_B():w:dq REG1=XMM_R():r:q
IFORM     : MOVQ_XMMdq_XMMq_0FD6

PATTERN   : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:q
IFORM     : MOVQ_XMMdq_MEMq_0F7E

PATTERN   : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:q
IFORM     : MOVQ_XMMdq_XMMq_0F7E
}


{
ICLASS    : MOVQ
EXCEPTIONS: mmx-nofp2 # FIXME guessing here...
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : MMX
ISA_SET   : PENTIUMMMX

PATTERN   : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  mode64 rexw_prefix MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
IFORM     : MOVQ_MMXq_MEMq_0F6E

PATTERN   : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  mode64 rexw_prefix
OPERANDS  : REG0=MMX_R():w:q REG1=GPR64_B():r

PATTERN   : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  mode64 rexw_prefix MODRM()
OPERANDS  : MEM0:w:q REG0=MMX_R():r:q
IFORM     : MOVQ_MEMq_MMXq_0F7E

PATTERN   : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  mode64 rexw_prefix
OPERANDS  : REG0=GPR64_B():w REG1=MMX_R():r:q

PATTERN   : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
IFORM     : MOVQ_MMXq_MEMq_0F6F

PATTERN   : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q REG1=MMX_B():r:q
IFORM     : MOVQ_MMXq_MMXq_0F6F

PATTERN   : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:q REG0=MMX_R():r:q
IFORM     : MOVQ_MEMq_MMXq_0F7F

PATTERN   : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_B():w:q REG1=MMX_R():r:q
IFORM     : MOVQ_MMXq_MMXq_0F7F
}

{
ICLASS    : PUNPCKHBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64   REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PUNPCKHWD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64   REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PUNPCKHDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64   REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PACKSSDW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT  HALF_WIDE_OUTPUT
PATTERN   : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
PATTERN   : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
}
{
ICLASS    : PUNPCKLQDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
COMMENT   : mem form only uses q portion of the dq load. See SDM.
PATTERN   : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : PUNPCKHQDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES : SKIPLOW64   REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
}
{
ICLASS    : MOVDQU
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4M
ATTRIBUTES : 
PATTERN   : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq

PATTERN   : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
IFORM     : MOVDQU_XMMdq_XMMdq_0F6F

PATTERN   : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : MEM0:w:dq REG0=XMM_R():r:dq

PATTERN   : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
IFORM     : MOVDQU_XMMdq_XMMdq_0F7F
}
{
ICLASS    : VMREAD
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]

PATTERN   : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64   MODRM() CR_WIDTH()
OPERANDS  : MEM0:rw:q REG0=GPR64_R():r

PATTERN   : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()
OPERANDS  : REG0=GPR64_B():rw REG1=GPR64_R():r

PATTERN   : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64  MODRM() CR_WIDTH()
OPERANDS  : MEM0:rw:d REG0=GPR32_R():r

PATTERN   : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()
OPERANDS  : REG0=GPR32_B():rw REG1=GPR32_R():r
}
{
ICLASS    : VMWRITE
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]

PATTERN   : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64  MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR64_R():r MEM0:r:q

PATTERN   : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()
OPERANDS  : REG0=GPR64_R():r REG1=GPR64_B():r

PATTERN   : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64  MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR32_R():r MEM0:r:d

PATTERN   : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64  CR_WIDTH()
OPERANDS  : REG0=GPR32_R():r REG1=GPR32_B():r
}
{
ICLASS    : HADDPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : HSUBPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:pd MEM0:r:pd
PATTERN   : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
}
{
ICLASS    : MOVDQA
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_1
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : MEM0:w:dq REG0=XMM_R():r:dq

PATTERN   : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
IFORM     : MOVDQA_XMMdq_XMMdq_0F7F

PATTERN   : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq

PATTERN   : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
IFORM     : MOVDQA_XMMdq_XMMdq_0F6F
}
{
ICLASS    : HADDPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : HSUBPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE3
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  IGNORE66() MODRM()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:ps
PATTERN   : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  IGNORE66()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
}
{
ICLASS    : JS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JNS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNS
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JNP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNP
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : JL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JNL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNL
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}



{
ICLASS    : JNLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN   : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS    : JNLE
CPL       : 3
CATEGORY  : COND_BR
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE

PATTERN   : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}


{
ICLASS    : SETS
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNS
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst ]
PATTERN   : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETP
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNP
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ pf-tst ]
PATTERN   : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETL
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNL
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst of-tst ]
PATTERN   : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETLE
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : SETNLE
CPL       : 3
CATEGORY  : SETCC
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : BYTEOP
FLAGS     : READONLY [ sf-tst of-tst zf-tst ]
PATTERN   : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:w:b
PATTERN   : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR8_B():w
}
{
ICLASS    : PUSH
CPL       : 3
CATEGORY  : PUSH
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0x0F 0xA8 DF64()
OPERANDS  : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
}
{
ICLASS    : POP
CPL       : 3
CATEGORY  : POP
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: NOTSX
PATTERN   : 0x0F 0xA9 DF64()
OPERANDS  : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
}
{
ICLASS    : RSM
CPL       : 3
CATEGORY  : SYSRET
EXTENSION : BASE
ISA_SET   : I486
ATTRIBUTES: NOTSX
FLAGS     : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN   : 0x0F 0xAA
OPERANDS  : REG0=rIP():w:SUPP
}

{
ICLASS    : BTS_LOCK
DISASM    :  bts
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTS
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTS
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
}



{
ICLASS    : SHRD
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b

PATTERN   : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b
}
{
ICLASS    : SHRD
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL

PATTERN   : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL
}

{
ICLASS    : SHLD
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b

PATTERN   : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b
}

{
ICLASS    : SHLD
CPL       : 3
CATEGORY  : SHIFT
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
PATTERN   : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL

PATTERN   : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL
}

{
ICLASS    : IMUL
CPL       : 3
CATEGORY  : BINARY
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
PATTERN   : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():rw MEM0:r:v

PATTERN   : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():rw REG1=GPRv_B():r
}

{
ICLASS    : BTC_LOCK
DISASM    :  btc
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]

PATTERN   : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTC
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
ATTRIBUTES : LOCKABLE
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]

PATTERN   : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
OPERANDS  : MEM0:rw:v REG0=GPRv_R():r 
}
{
ICLASS    : BTC
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u af-u pf-u cf-mod ]

PATTERN   : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_B():rw REG1=GPRv_R():r
}


{
ICLASS    : BSF
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
COMMENT   : replaced in the HSW builds
PATTERN   : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v

PATTERN   : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : BSR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
COMMENT   : replaced in the HSW builds
PATTERN   : 0x0F 0xBD  MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v

PATTERN   : 0x0F 0xBD  MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}
{
ICLASS    : MOVSX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:b
}
{
ICLASS    : MOVSX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w REG1=GPR8_B():r
}
{
ICLASS    : MOVSX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:w
}
{
ICLASS    : MOVSX
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I386
PATTERN   : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w REG1=GPR16_B():r
}
{
ICLASS    : BSWAP
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : BASE
ISA_SET   : I486REAL
PATTERN   : 0x0F 0b1100_1 SRM[rrr]
OPERANDS  : REG0=GPRv_SB():rw
}
{
ICLASS    : PSUBUSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PSUBUSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBUSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PSUBUSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PMINUB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PMINUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PAND
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PAND
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDUSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PADDUSB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDUSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PADDUSW
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PMAXUB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PMAXUB
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PANDN
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
}
{
ICLASS    : PANDN
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBUSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS : SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBUSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS : SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMINUB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PAND
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDUSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDUSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMAXUB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PANDN
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PMINSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : POR
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PMAXSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PXOR
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMINSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : POR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMAXSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PXOR
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBQ
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSE2
PATTERN   : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PADDD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : MMX
ISA_SET   : PENTIUMMMX
PATTERN   : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSUBB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSUBQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PADDW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
PATTERN   : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
}
{
ICLASS    : PADDD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE2
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHADDW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHADDW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHADDD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHADDD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHADDSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHADDSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHSUBW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHSUBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHSUBD
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHSUBD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PHSUBSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PHSUBSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PMADDUBSW
EXCEPTIONS: mmx-mem
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX
PATTERN   : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
PATTERN   : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
}
{
ICLASS    : PMADDUBSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT
PATTERN   : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
PATTERN   : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
}
{
ICLASS    : PMULHRSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PMULHRSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSHUFB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSHUFB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSIGNB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSIGNB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSIGNW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSIGNW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PSIGND
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
EXCEPTIONS: mmx-mem
PATTERN   : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q
}
{
ICLASS    : PSIGND
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PALIGNR
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM() UIMM8()
OPERANDS  : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b
PATTERN   : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b
}
{
ICLASS    : PALIGNR
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b
PATTERN   : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b
}
{
ICLASS    : PABSB
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q REG1=MMX_B():r:q
}
{
ICLASS    : PABSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PABSW
EXCEPTIONS: mmx-mem
ATTRIBUTES: NOTSX
CPL       : 3
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
PATTERN   : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q REG1=MMX_B():r:q
}
{
ICLASS    : PABSW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
PATTERN   : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
}
{
ICLASS    : PABSD
EXCEPTIONS: mmx-mem
CPL       : 3
ATTRIBUTES : simd_scalar NOTSX
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=MMX_R():w:q MEM0:r:q
}
{
ICLASS    : PABSD
CPL       : 3
ATTRIBUTES : simd_scalar NOTSX
CATEGORY  : MMX
EXTENSION : SSSE3
PATTERN   : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MMX_R():w:q REG1=MMX_B():r:q
}
{
ICLASS    : PABSD
CPL       : 3
ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
PATTERN   : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
}
{
ICLASS    : PABSD
CPL       : 3
ATTRIBUTES : simd_scalar
CATEGORY  : SSE
EXTENSION : SSSE3
EXCEPTIONS: SSE_TYPE_4
PATTERN   : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
}

####################################################################################
{
ICLASS    : POPCNT
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : POPCNT
ATTRIBUTES:   IGNORES_OSFXSR
# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix
#   to get to the 16b form 32b and 64b modes.
FLAGS     : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ]
PATTERN   : 0x0F 0xB8  f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]   MODRM()
OPERANDS  : REG0=GPRv_R():w:v     MEM0:r:v
PATTERN   : 0x0F 0xB8  f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w:v     REG1=GPRv_B():r:v
}
####################################################################################
{
ICLASS    : PCMPGTQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x37  osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq     MEM0:r:dq
PATTERN   : 0x0F 0x38 0x37  osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq     REG1=XMM_B():r:dq
}
####################################################################################
{
ICLASS    : CRC32
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
ATTRIBUTES :   IGNORES_OSFXSR
# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix
#   to get to the 16b form 32b and 64b modes.

COMMENT: The dest min size is 32b, even for EOSZ 16b. 

# The byte-readers 

PATTERN   : 0x0F 0x38 0xF0  f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]    MODRM()
OPERANDS  : REG0=GPRy_R():rw:y     MEM0:r:b
PATTERN   : 0x0F 0x38 0xF0  f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  
OPERANDS  : REG0=GPRy_R():rw:y     REG1=GPR8_B():r:b


# The scalable readers

PATTERN   : 0x0F 0x38 0xF1  f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]   MODRM()
OPERANDS  : REG0=GPRy_R():rw:y     MEM0:r:v
PATTERN   : 0x0F 0x38 0xF1  f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  
OPERANDS  : REG0=GPRy_R():rw:y     REG1=GPRv_B():r:v

}



{
ICLASS    : BLENDPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b

PATTERN   : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b
}
{
ICLASS    : BLENDPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b

PATTERN   : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b
}
#######################################################################33
{
ICLASS    : BLENDVPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64

PATTERN   : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64
}

{
ICLASS    : BLENDVPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32

PATTERN   : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32
}
####################################################################################
{
ICLASS    : PCMPEQQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq

PATTERN   : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
}
####################################################################################
{
ICLASS    : DPPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_2D
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64  IMM0:r:b

PATTERN   : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64  IMM0:r:b
}
{
ICLASS    : DPPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_2D
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32  IMM0:r:b

PATTERN   : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32  IMM0:r:b
}
####################################################################################
{
ICLASS    : MOVNTDQA
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_1
ATTRIBUTES :  REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
PATTERN   : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq MEM0:r:dq
}
####################################################################################
{
ICLASS    : EXTRACTPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:d REG0=XMM_R():r:ps  IMM0:r:b

PATTERN   : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=GPR32_B():w:d REG1=XMM_R():r:dq  IMM0:r:b
}
####################################################################################
{
ICLASS    : INSERTPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b

PATTERN   : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps  IMM0:r:b
}
############################################################################
{
ICLASS    : MPSADBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT
PATTERN   : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b

PATTERN   : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b
}
############################################################################
{
ICLASS    : PACKUSDW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
PATTERN   : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32

PATTERN   : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
}
############################################################################
{
ICLASS    : PBLENDW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b

PATTERN   : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b
}
############################################################################
{
ICLASS    : PBLENDVB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP

PATTERN   : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP
}
############################################################################
{
ICLASS    : PEXTRB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:b           REG0=XMM_R():r:dq IMM0:r:b
# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b???
PATTERN   : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b
}
############################################################################
{
ICLASS    : PEXTRW_SSE4
DISASM_INTEL: pextrw
DISASM_ATTSV: pextrw
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
# this one aliases with the SSE2 version so we made a new name

PATTERN   : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:w           REG0=XMM_R():r:dq IMM0:r:b
IFORM     : PEXTRW_SSE4_MEMw_XMMdq_IMMb

# this one aliases with the SSE2 version so we made a new name
PATTERN   : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b
IFORM     : PEXTRW_SSE4_GPR32_XMMdq_IMMb
}

############################################################################
{
ICLASS    : PEXTRQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:q           REG0=XMM_R():r:dq IMM0:r:b
PATTERN   : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b
}
############################################################################
{
ICLASS    : PEXTRD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : MEM0:w:d           REG0=XMM_R():r:dq IMM0:r:b
# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b???
PATTERN   : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b
}
############################################################################
{
ICLASS    : PINSRB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:b            IMM0:r:b

PATTERN   : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d  IMM0:r:b
}
############################################################################
{
ICLASS    : PINSRD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:d            IMM0:r:b

PATTERN   : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d  IMM0:r:b
}
############################################################################
{
ICLASS    : PINSRQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq MEM0:r:q            IMM0:r:b

PATTERN   : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q  IMM0:r:b
}
############################################################################
{
ICLASS    : ROUNDPD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:pd   MEM0:r:pd           IMM0:r:b
PATTERN   : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():w:pd   REG1=XMM_B():r:pd   IMM0:r:b
}
############################################################################
{
ICLASS    : ROUNDPS
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_2
ATTRIBUTES :  REQUIRES_ALIGNMENT MXCSR
PATTERN   : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:ps   MEM0:r:ps           IMM0:r:b
PATTERN   : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():w:ps   REG1=XMM_B():r:ps   IMM0:r:b
}
############################################################################
{
ICLASS    : ROUNDSD
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:q   MEM0:r:q           IMM0:r:b
PATTERN   : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():w:q   REG1=XMM_B():r:q   IMM0:r:b
}
############################################################################
{
ICLASS    : ROUNDSS
CPL       : 3
ATTRIBUTES : simd_scalar  MXCSR
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_3
PATTERN   : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:d   MEM0:r:d           IMM0:r:b
PATTERN   : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():w:d   REG1=XMM_B():r:d   IMM0:r:b
}
############################################################################
{
ICLASS    : PTEST
CPL       : 3
CATEGORY  : LOGICAL
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
FLAGS     : MUST [ cf-mod zf-mod  of-0 af-0 pf-0 sf-0 ]
PATTERN   : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():r:dq   MEM0:r:dq
PATTERN   : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():r:dq   REG1=XMM_B():r:dq
}
############################################################################
{
ICLASS    : PHMINPOSUW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq   MEM0:r:dq
PATTERN   : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq   REG1=XMM_B():r:dq
}


{
ICLASS    : PMAXSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMAXSD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMAXUD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMAXUW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}

{
ICLASS    : PMINSB
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMINSD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMINUD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMINUW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}

{
ICLASS    : PMULLD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}
{
ICLASS    : PMULDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():rw:dq    MEM0:r:dq
PATTERN   : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():rw:dq    REG1=XMM_B():r:dq
}





{
ICLASS    : PMOVSXBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i16    MEM0:r:q:i8
PATTERN   : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i16    REG1=XMM_B():r:q:i8
}
{
ICLASS    : PMOVSXBD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32    MEM0:r:d:i8
PATTERN   : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i32    REG1=XMM_B():r:d:i8
}
{
ICLASS    : PMOVSXBQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i64    MEM0:r:w:i8
PATTERN   : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i64    REG1=XMM_B():r:w:i8
}

{
ICLASS    : PMOVSXWD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i32    MEM0:r:q:i16
PATTERN   : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i32    REG1=XMM_B():r:q:i16
}
{
ICLASS    : PMOVSXWQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i64    MEM0:r:d:i16
PATTERN   : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i64    REG1=XMM_B():r:d:i16
}
{
ICLASS    : PMOVSXDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:i64    MEM0:r:q:i32
PATTERN   : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:i64    REG1=XMM_B():r:q:i32
}

{
ICLASS    : PMOVZXBW
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u16    MEM0:r:q:u8
PATTERN   : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u16    REG1=XMM_B():r:q:u8
}
{
ICLASS    : PMOVZXBD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u32    MEM0:r:d:u8
PATTERN   : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u32    REG1=XMM_B():r:d:u8
}
{
ICLASS    : PMOVZXBQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u64    MEM0:r:w:u8
PATTERN   : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u64    REG1=XMM_B():r:w:u8
}

{
ICLASS    : PMOVZXWD
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u32    MEM0:r:q:u16
PATTERN   : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u32    REG1=XMM_B():r:q:u16
}
{
ICLASS    : PMOVZXWQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u64    MEM0:r:d:u16
PATTERN   : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u64    REG1=XMM_B():r:d:u16
}
{
ICLASS    : PMOVZXDQ
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
EXCEPTIONS: SSE_TYPE_5
ATTRIBUTES : 
PATTERN   : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=XMM_R():w:dq:u64    MEM0:r:q:u32
PATTERN   : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=XMM_R():w:dq:u64    REG1=XMM_B():r:q:u32
}







{
ICLASS    : PCMPESTRI
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: 
FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]

PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP

PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP

PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP

PATTERN   : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP
}
{
ICLASS    : PCMPISTRI
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: 
FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]

PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_ECX:w:SUPP

PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP

PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RCX:w:SUPP

PATTERN   : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP
}

{
ICLASS    : PCMPESTRM
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: 
FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]

PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP

PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP

PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP

PATTERN   : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP

}
{
ICLASS    : PCMPISTRM
CPL       : 3
CATEGORY  : SSE
EXTENSION : SSE4
ISA_SET   : SSE42
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES: 
FLAGS     : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
PATTERN   : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     MEM0:r:dq         IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP

PATTERN   : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS  : REG0=XMM_R():r:dq     REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP
}
####################################################################################
{
ICLASS    : XGETBV
CPL       : 3
CATEGORY  : XSAVE
EXTENSION : XSAVE
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix
OPERANDS  : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP  REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP
}

{
ICLASS    : XSETBV
CPL       : 0
CATEGORY  : XSAVE
EXTENSION : XSAVE
ATTRIBUTES : RING0 NOTSX
PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix
OPERANDS  : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP  REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP
}


{
ICLASS    : XSAVE
CPL       : 3
CATEGORY  : XSAVE
EXTENSION : XSAVE
COMMENT   : variable length store
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
}
{
ICLASS    : XRSTOR
CPL       : 3
CATEGORY  : XSAVE
EXTENSION : XSAVE
COMMENT   : variable length load and conditianal reg write
ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
}


{
ICLASS    : XSAVE64
CPL       : 3
CATEGORY  : XSAVE
EXTENSION : XSAVE
COMMENT   : variable length store
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
OPERANDS  : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
}

{
ICLASS    : XRSTOR64
CPL       : 3
CATEGORY  : XSAVE
EXTENSION : XSAVE
COMMENT   : variable length load and conditianal reg write
ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
PATTERN   : 0x0F 0xAE MOD[mm]  MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
OPERANDS  : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
}





####################################################################################

{
ICLASS    : MOVBE
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : MOVBE
COMMENT   : Intro on Atom Silverthorne. Intercepted by Haswell.
#
#  must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes.
#
PATTERN   : 0x0F 0x38 0xF0   not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : REG0=GPRv_R():w MEM0:r:v
PATTERN   : 0x0F 0x38 0xF1   not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()
OPERANDS  : MEM0:w:v  REG0=GPRv_R():r
}


{
ICLASS    : GETSEC
CPL       : 3
CATEGORY  : SYSTEM
ATTRIBUTES: PROTECTED_MODE NOTSX
EXTENSION : SMX
PATTERN   : 0x0F 0x37
OPERANDS  : REG0=XED_REG_EAX:rcw:SUPP  REG1=XED_REG_EBX:r:SUPP
}


####################################################################################
{
ICLASS    : AESKEYGENASSIST
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()  UIMM8()
OPERANDS  : REG0=XMM_R():w:dq  REG1=XMM_B():r:dq IMM0:r:b
PATTERN   : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():w:dq  MEM0:r:dq IMM0:r:b
}
{
ICLASS    : AESENC
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq  REG1=XMM_B():r:dq
PATTERN   : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq  MEM0:r:dq
}
{
ICLASS    : AESENCLAST
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq  REG1=XMM_B():r:dq
PATTERN   : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq  MEM0:r:dq
}
{
ICLASS    : AESDEC
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq  REG1=XMM_B():r:dq
PATTERN   : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq  MEM0:r:dq
}
{
ICLASS    : AESDECLAST
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():rw:dq  REG1=XMM_B():r:dq
PATTERN   : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():rw:dq  MEM0:r:dq
}
{
ICLASS    : AESIMC
CPL       : 3
CATEGORY  : AES
EXTENSION : AES
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()
OPERANDS  : REG0=XMM_R():w:dq  REG1=XMM_B():r:dq
PATTERN   : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM()
OPERANDS  : REG0=XMM_R():w:dq  MEM0:r:dq
}
####################################################################################
{
ICLASS    : PCLMULQDQ
CPL       : 3
CATEGORY  : PCLMULQDQ
EXTENSION : PCLMULQDQ
EXCEPTIONS: SSE_TYPE_4
ATTRIBUTES :  REQUIRES_ALIGNMENT
PATTERN   : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3  REG[rrr] RM[nnn]  REFINING66()  UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq  REG1=XMM_B():r:dq IMM0:r:b
PATTERN   : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() MODRM() UIMM8()
OPERANDS  : REG0=XMM_R():rw:dq  MEM0:r:dq IMM0:r:b
}


#######################################################################
{
ICLASS    : INVEPT
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES : RING0 NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
PATTERN   : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
PATTERN   : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64  MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
COMMENT   : SDM rev 27
}
{
ICLASS    : INVVPID
CPL       : 0
CATEGORY  : VTX
EXTENSION : VTX
ATTRIBUTES : RING0 NOTSX
FLAGS     : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
PATTERN   : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() mode64 MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR64_R():r MEM0:r:dq
PATTERN   : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn]  REFINING66() not64  MODRM() CR_WIDTH()
OPERANDS  : REG0=GPR32_R():r MEM0:r:dq
COMMENT   : SDM rev 27
}




