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#
#Copyright (c) 2017 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
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XOP_INSTRUCTIONS()::
{
ICLASS: VPMACSSWW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x85 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16

PATTERN: XOPV 0x85 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16
}

{
ICLASS: VPMACSSWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x86 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0x86 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPMACSSDQL
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x87 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64

PATTERN: XOPV 0x87 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
}

{
ICLASS: VPMACSWW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x95 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16

PATTERN: XOPV 0x95 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16
}

{
ICLASS: VPMACSWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x96 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0x96 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPMACSDQL
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x97 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64

PATTERN: XOPV 0x97 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
}

{
ICLASS: VPCMOV
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xA2 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1

PATTERN: XOPV 0xA2 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1

PATTERN: XOPV 0xA2 VNP W1 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1

PATTERN: XOPV 0xA2 VNP W1 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1

PATTERN: XOPV 0xA2 VNP W0 VL256  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1

PATTERN: XOPV 0xA2 VNP W0 VL256  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1

PATTERN: XOPV 0xA2 VNP W1 VL256  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1

PATTERN: XOPV 0xA2 VNP W1 VL256  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1
}

{
ICLASS: VPPERM
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xA3 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16

PATTERN: XOPV 0xA3 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16

PATTERN: XOPV 0xA3 VNP W1 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16

PATTERN: XOPV 0xA3 VNP W1 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16
}

{
ICLASS: VPMADCSSWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xA6 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0xA6 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPMADCSWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xB6 VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0xB6 VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPROTB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8

PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8
}

{
ICLASS: VPROTW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16

PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u16
}

{
ICLASS: VPROTD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32

PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u32
}

{
ICLASS: VPROTQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64

PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u64
}

{
ICLASS: VPMACSSDD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x8E VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0x8E VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPMACSSDQH
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x8F VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64

PATTERN: XOPV 0x8F VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
}

{
ICLASS: VPMACSDD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x9E VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32

PATTERN: XOPV 0x9E VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32
}

{
ICLASS: VPMACSDQH
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x9F VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64

PATTERN: XOPV 0x9F VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
}

{
ICLASS: VPCOMB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xCC VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:i8

PATTERN: XOPV 0xCC VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:i8
}

{
ICLASS: VPCOMW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xCD VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:i16

PATTERN: XOPV 0xCD VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:i16
}

{
ICLASS: VPCOMD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xCE VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:i32

PATTERN: XOPV 0xCE VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:i32
}

{
ICLASS: VPCOMQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xCF VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:i64

PATTERN: XOPV 0xCF VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:i64
}

{
ICLASS: VPCOMUB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xEC VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8

PATTERN: XOPV 0xEC VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8
}

{
ICLASS: VPCOMUW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xED VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16

PATTERN: XOPV 0xED VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u16
}

{
ICLASS: VPCOMUD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xEE VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32

PATTERN: XOPV 0xEE VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u32
}

{
ICLASS: VPCOMUQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xEF VNP W0 VL128  XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64

PATTERN: XOPV 0xEF VNP W0 VL128  XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u64
}

{
ICLASS: VFRCZPS
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP
ATTRIBUTES:  MXCSR

PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32

PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32

PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32

PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
}

{
ICLASS: VFRCZPD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP
ATTRIBUTES:  MXCSR

PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64

PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64

PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64

PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
}

{
ICLASS: VFRCZSS
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP
ATTRIBUTES: SIMD_SCALAR  MXCSR

PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32

PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32
}

{
ICLASS: VFRCZSD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP
ATTRIBUTES: SIMD_SCALAR  MXCSR

PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64

PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64
}

{
ICLASS: VPROTB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x90 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8

PATTERN: XOPV 0x90 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8

PATTERN: XOPV 0x90 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8

PATTERN: XOPV 0x90 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
}

{
ICLASS: VPROTW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x91 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16

PATTERN: XOPV 0x91 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16

PATTERN: XOPV 0x91 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16

PATTERN: XOPV 0x91 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
}

{
ICLASS: VPROTD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x92 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32

PATTERN: XOPV 0x92 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32

PATTERN: XOPV 0x92 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32

PATTERN: XOPV 0x92 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
}

{
ICLASS: VPROTQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x93 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64

PATTERN: XOPV 0x93 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64

PATTERN: XOPV 0x93 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64

PATTERN: XOPV 0x93 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
}

{
ICLASS: VPSHLB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x94 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8

PATTERN: XOPV 0x94 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8

PATTERN: XOPV 0x94 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8

PATTERN: XOPV 0x94 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
}

{
ICLASS: VPSHLW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x95 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16

PATTERN: XOPV 0x95 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16

PATTERN: XOPV 0x95 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16

PATTERN: XOPV 0x95 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
}

{
ICLASS: VPSHLD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x96 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32

PATTERN: XOPV 0x96 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32

PATTERN: XOPV 0x96 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32

PATTERN: XOPV 0x96 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
}

{
ICLASS: VPSHLQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x97 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64

PATTERN: XOPV 0x97 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64

PATTERN: XOPV 0x97 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64

PATTERN: XOPV 0x97 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
}

{
ICLASS: VPHADDBW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8

PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8
}

{
ICLASS: VPHADDBD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8

PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8
}

{
ICLASS: VPHADDBQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8

PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8
}

{
ICLASS: VPHADDWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16

PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16
}

{
ICLASS: VPHADDWQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16

PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16
}

{
ICLASS: VPHADDUBW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8

PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8
}

{
ICLASS: VPHADDUBD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8

PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8
}

{
ICLASS: VPHADDUBQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8

PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8
}

{
ICLASS: VPHADDUWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16

PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16
}

{
ICLASS: VPHADDUWQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16

PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16
}

{
ICLASS: VPHSUBBW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8

PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8
}

{
ICLASS: VPHSUBWD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16

PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16
}

{
ICLASS: VPHSUBDQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32

PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32
}

{
ICLASS: VPSHAB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x98 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8

PATTERN: XOPV 0x98 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8

PATTERN: XOPV 0x98 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8

PATTERN: XOPV 0x98 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
}

{
ICLASS: VPSHAW
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x99 VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16

PATTERN: XOPV 0x99 VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16

PATTERN: XOPV 0x99 VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16

PATTERN: XOPV 0x99 VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
}

{
ICLASS: VPSHAD
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x9A VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32

PATTERN: XOPV 0x9A VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32

PATTERN: XOPV 0x9A VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32

PATTERN: XOPV 0x9A VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
}

{
ICLASS: VPSHAQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x9B VNP W0 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64

PATTERN: XOPV 0x9B VNP W0 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64

PATTERN: XOPV 0x9B VNP W1 VL128  XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64

PATTERN: XOPV 0x9B VNP W1 VL128  XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64
}

{
ICLASS: VPHADDDQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32

PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32
}

{
ICLASS: VPHADDUDQ
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32

PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32
}

{
ICLASS: BEXTR_XOP
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]

PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64  VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d

PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d
}

{
ICLASS: BLCFILL
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLSFILL
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLCS
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: TZMSK
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLCIC
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLSIC
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: T1MSKC
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLCMSK
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: BLCI
CPL: 3
CATEGORY: TBM
ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]

PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x02 VNP not64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128  XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}

{
ICLASS: LLWPCB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS: REG0=GPRy_B():w:y
}

{
ICLASS: SLWPCB
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=GPRy_B():w:y
}

{
ICLASS: LWPINS
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP
FLAGS: MUST [ cf-mod ]

PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d

PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d
}

{
ICLASS: LWPVAL
CPL: 3
CATEGORY: XOP
ISA_SET: XOP
EXTENSION: XOP

PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d

PATTERN: XOPV 0x12 VNP W0 VL128  XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d
}
