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#Copyright (c) 2016 Intel Corporation
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UISA_VMODRM_ZMM()::
 MOD=0b00  UISA_VSIB_ZMM()             | 
 MOD=0b01  UISA_VSIB_ZMM() MEMDISP8()  | 
 MOD=0b10  UISA_VSIB_ZMM() MEMDISP32() | 

UISA_VMODRM_YMM()::
 MOD=0b00  UISA_VSIB_YMM()             | 
 MOD=0b01  UISA_VSIB_YMM() MEMDISP8()  | 
 MOD=0b10  UISA_VSIB_YMM() MEMDISP32() | 

UISA_VMODRM_XMM()::
 MOD=0b00  UISA_VSIB_XMM()             | 
 MOD=0b01  UISA_VSIB_XMM() MEMDISP8()  | 
 MOD=0b10  UISA_VSIB_XMM() MEMDISP32() | 


UISA_VSIB_ZMM()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_ZMM()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_ZMM()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_ZMM()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_ZMM()  SCALE=8  
UISA_VSIB_YMM()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_YMM()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_YMM()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_YMM()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_YMM()  SCALE=8  
UISA_VSIB_XMM()::
SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_XMM()  SCALE=1  
SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_XMM()  SCALE=2  
SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_XMM()  SCALE=4  
SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE()  | INDEX=UISA_VSIB_INDEX_XMM()  SCALE=8  


xed_reg_enum_t UISA_VSIB_INDEX_ZMM()::
VEXDEST4=0 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_ZMM0
VEXDEST4=0 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_ZMM1
VEXDEST4=0 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_ZMM2
VEXDEST4=0 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_ZMM3
VEXDEST4=0 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_ZMM4
VEXDEST4=0 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_ZMM5
VEXDEST4=0 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_ZMM6
VEXDEST4=0 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_ZMM7
VEXDEST4=0 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_ZMM8
VEXDEST4=0 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_ZMM9
VEXDEST4=0 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_ZMM10
VEXDEST4=0 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_ZMM11
VEXDEST4=0 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_ZMM12
VEXDEST4=0 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_ZMM13
VEXDEST4=0 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_ZMM14
VEXDEST4=0 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_ZMM15
VEXDEST4=1 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_ZMM16
VEXDEST4=1 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_ZMM17
VEXDEST4=1 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_ZMM18
VEXDEST4=1 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_ZMM19
VEXDEST4=1 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_ZMM20
VEXDEST4=1 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_ZMM21
VEXDEST4=1 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_ZMM22
VEXDEST4=1 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_ZMM23
VEXDEST4=1 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_ZMM24
VEXDEST4=1 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_ZMM25
VEXDEST4=1 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_ZMM26
VEXDEST4=1 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_ZMM27
VEXDEST4=1 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_ZMM28
VEXDEST4=1 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_ZMM29
VEXDEST4=1 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_ZMM30
VEXDEST4=1 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_ZMM31



xed_reg_enum_t UISA_VSIB_INDEX_YMM()::
VEXDEST4=0 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_YMM0
VEXDEST4=0 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_YMM1
VEXDEST4=0 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_YMM2
VEXDEST4=0 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_YMM3
VEXDEST4=0 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_YMM4
VEXDEST4=0 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_YMM5
VEXDEST4=0 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_YMM6
VEXDEST4=0 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_YMM7
VEXDEST4=0 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_YMM8
VEXDEST4=0 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_YMM9
VEXDEST4=0 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_YMM10
VEXDEST4=0 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_YMM11
VEXDEST4=0 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_YMM12
VEXDEST4=0 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_YMM13
VEXDEST4=0 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_YMM14
VEXDEST4=0 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_YMM15
VEXDEST4=1 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_YMM16
VEXDEST4=1 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_YMM17
VEXDEST4=1 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_YMM18
VEXDEST4=1 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_YMM19
VEXDEST4=1 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_YMM20
VEXDEST4=1 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_YMM21
VEXDEST4=1 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_YMM22
VEXDEST4=1 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_YMM23
VEXDEST4=1 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_YMM24
VEXDEST4=1 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_YMM25
VEXDEST4=1 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_YMM26
VEXDEST4=1 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_YMM27
VEXDEST4=1 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_YMM28
VEXDEST4=1 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_YMM29
VEXDEST4=1 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_YMM30
VEXDEST4=1 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_YMM31


xed_reg_enum_t UISA_VSIB_INDEX_XMM()::
VEXDEST4=0 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_XMM0
VEXDEST4=0 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_XMM1
VEXDEST4=0 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_XMM2
VEXDEST4=0 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_XMM3
VEXDEST4=0 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_XMM4
VEXDEST4=0 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_XMM5
VEXDEST4=0 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_XMM6
VEXDEST4=0 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_XMM7
VEXDEST4=0 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_XMM8
VEXDEST4=0 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_XMM9
VEXDEST4=0 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_XMM10
VEXDEST4=0 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_XMM11
VEXDEST4=0 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_XMM12
VEXDEST4=0 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_XMM13
VEXDEST4=0 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_XMM14
VEXDEST4=0 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_XMM15
VEXDEST4=1 REXX=0   SIBINDEX=0 | OUTREG=XED_REG_XMM16
VEXDEST4=1 REXX=0   SIBINDEX=1 | OUTREG=XED_REG_XMM17
VEXDEST4=1 REXX=0   SIBINDEX=2 | OUTREG=XED_REG_XMM18
VEXDEST4=1 REXX=0   SIBINDEX=3 | OUTREG=XED_REG_XMM19
VEXDEST4=1 REXX=0   SIBINDEX=4 | OUTREG=XED_REG_XMM20
VEXDEST4=1 REXX=0   SIBINDEX=5 | OUTREG=XED_REG_XMM21
VEXDEST4=1 REXX=0   SIBINDEX=6 | OUTREG=XED_REG_XMM22
VEXDEST4=1 REXX=0   SIBINDEX=7 | OUTREG=XED_REG_XMM23
VEXDEST4=1 REXX=1   SIBINDEX=0 | OUTREG=XED_REG_XMM24
VEXDEST4=1 REXX=1   SIBINDEX=1 | OUTREG=XED_REG_XMM25
VEXDEST4=1 REXX=1   SIBINDEX=2 | OUTREG=XED_REG_XMM26
VEXDEST4=1 REXX=1   SIBINDEX=3 | OUTREG=XED_REG_XMM27
VEXDEST4=1 REXX=1   SIBINDEX=4 | OUTREG=XED_REG_XMM28
VEXDEST4=1 REXX=1   SIBINDEX=5 | OUTREG=XED_REG_XMM29
VEXDEST4=1 REXX=1   SIBINDEX=6 | OUTREG=XED_REG_XMM30
VEXDEST4=1 REXX=1   SIBINDEX=7 | OUTREG=XED_REG_XMM31


UISA_VSIB_BASE()::
REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()

# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8  and DISP32 
REXB=0 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()

REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()
REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()

# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8  and DISP32 
REXB=1 SIBBASE=5 MOD=0  MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()
REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()

REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()
REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()



  
  



