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#
#Copyright (c) 2016 Intel Corporation
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#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
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#      http://www.apache.org/licenses/LICENSE-2.0
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#  distributed under the License is distributed on an "AS IS" BASIS,
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xed_reg_enum_t XMM_R3()::
mode16 | OUTREG=XMM_R3_32()
mode32 | OUTREG=XMM_R3_32()
mode64 | OUTREG=XMM_R3_64()

xed_reg_enum_t XMM_R3_32()::
REG=0 | OUTREG=XED_REG_XMM0
REG=1 | OUTREG=XED_REG_XMM1
REG=2 | OUTREG=XED_REG_XMM2
REG=3 | OUTREG=XED_REG_XMM3
REG=4 | OUTREG=XED_REG_XMM4
REG=5 | OUTREG=XED_REG_XMM5
REG=6 | OUTREG=XED_REG_XMM6
REG=7 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7

REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31


xed_reg_enum_t YMM_R3()::
mode16 | OUTREG=YMM_R3_32()
mode32 | OUTREG=YMM_R3_32()
mode64 | OUTREG=YMM_R3_64()

xed_reg_enum_t YMM_R3_32()::
REG=0 | OUTREG=XED_REG_YMM0
REG=1 | OUTREG=XED_REG_YMM1
REG=2 | OUTREG=XED_REG_YMM2
REG=3 | OUTREG=XED_REG_YMM3
REG=4 | OUTREG=XED_REG_YMM4
REG=5 | OUTREG=XED_REG_YMM5
REG=6 | OUTREG=XED_REG_YMM6
REG=7 | OUTREG=XED_REG_YMM7
xed_reg_enum_t YMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7
REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31



xed_reg_enum_t ZMM_R3()::
mode16 | OUTREG=ZMM_R3_32()
mode32 | OUTREG=ZMM_R3_32()
mode64 | OUTREG=ZMM_R3_64()

xed_reg_enum_t ZMM_R3_32()::
REG=0 | OUTREG=XED_REG_ZMM0
REG=1 | OUTREG=XED_REG_ZMM1
REG=2 | OUTREG=XED_REG_ZMM2
REG=3 | OUTREG=XED_REG_ZMM3
REG=4 | OUTREG=XED_REG_ZMM4
REG=5 | OUTREG=XED_REG_ZMM5
REG=6 | OUTREG=XED_REG_ZMM6
REG=7 | OUTREG=XED_REG_ZMM7

xed_reg_enum_t ZMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7
REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31


