#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
#
#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING VEXP2PD (VEXP2PD-512-1)
{
ICLASS:      VEXP2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VEXP2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VEXP2PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
}


# EMITTING VEXP2PS (VEXP2PS-512-1)
{
ICLASS:      VEXP2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VEXP2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VEXP2PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
}


# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1)
{
ICLASS:      VGATHERPF0DPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1)
{
ICLASS:      VGATHERPF0DPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1)
{
ICLASS:      VGATHERPF0QPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1)
{
ICLASS:      VGATHERPF0QPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1)
{
ICLASS:      VGATHERPF1DPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1)
{
ICLASS:      VGATHERPF1DPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1)
{
ICLASS:      VGATHERPF1QPD
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1)
{
ICLASS:      VGATHERPF1QPS
CPL:         3
CATEGORY:    GATHER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VRCP28PD (VRCP28PD-512-1)
{
ICLASS:      VRCP28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VRCP28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VRCP28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
}


# EMITTING VRCP28PS (VRCP28PS-512-1)
{
ICLASS:      VRCP28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VRCP28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VRCP28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
}


# EMITTING VRCP28SD (VRCP28SD-128-1)
{
ICLASS:      VRCP28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
}

{
ICLASS:      VRCP28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
}

{
ICLASS:      VRCP28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
}


# EMITTING VRCP28SS (VRCP28SS-128-1)
{
ICLASS:      VRCP28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
}

{
ICLASS:      VRCP28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
}

{
ICLASS:      VRCP28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
}


# EMITTING VRSQRT28PD (VRSQRT28PD-512-1)
{
ICLASS:      VRSQRT28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VRSQRT28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
}

{
ICLASS:      VRSQRT28PD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
}


# EMITTING VRSQRT28PS (VRSQRT28PS-512-1)
{
ICLASS:      VRSQRT28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VRSQRT28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MASKOP_EVEX 
PATTERN:    EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
}

{
ICLASS:      VRSQRT28PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
}


# EMITTING VRSQRT28SD (VRSQRT28SD-128-1)
{
ICLASS:      VRSQRT28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
}

{
ICLASS:      VRSQRT28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
}

{
ICLASS:      VRSQRT28SD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W1    ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
}


# EMITTING VRSQRT28SS (VRSQRT28SS-128-1)
{
ICLASS:      VRSQRT28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
}

{
ICLASS:      VRSQRT28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MASKOP_EVEX 
PATTERN:    EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
}

{
ICLASS:      VRSQRT28SS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512ER_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 
PATTERN:    EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  W0    ESIZE_32_BITS() NELEM_SCALAR()
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
IFORM:       VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
}


# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1)
{
ICLASS:      VSCATTERPF0DPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1)
{
ICLASS:      VSCATTERPF0DPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1)
{
ICLASS:      VSCATTERPF0QPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1)
{
ICLASS:      VSCATTERPF0QPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1)
{
ICLASS:      VSCATTERPF1DPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_YMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1)
{
ICLASS:      VSCATTERPF1DPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1)
{
ICLASS:      VSCATTERPF1QPD
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0   VL512  W1 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_64_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
}


# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1)
{
ICLASS:      VSCATTERPF1QPS
CPL:         3
CATEGORY:    SCATTER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512PF_512
EXCEPTIONS:     AVX512-E12NP
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 
PATTERN:    EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0   VL512  W0 RM=4 UISA_VMODRM_ZMM() eanot16  NOVSR  ZEROING=0  ESIZE_32_BITS() NELEM_GSCAT()
OPERANDS:    MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw
IFORM:       VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
}


INSTRUCTIONS()::
# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1)
{
ICLASS:      PREFETCHWT1
CPL:         3
CATEGORY:    PREFETCHWT1
EXTENSION:   PREFETCHWT1
ISA_SET:     PREFETCHWT1
REAL_OPCODE: Y
ATTRIBUTES:  PREFETCH 
PATTERN:     0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn]  MODRM()       
OPERANDS:    MEM0:r:b:u8
IFORM:       PREFETCHWT1_MEMu8
}


