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#Copyright (c) 2016 Intel Corporation
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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
EVEX_INSTRUCTIONS()::
# EMITTING VPERMB (VPERMB-128-1)
{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
IFORM:       VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
}

{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
IFORM:       VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
}


# EMITTING VPERMB (VPERMB-256-1)
{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
IFORM:       VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
}

{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
IFORM:       VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
}


# EMITTING VPERMB (VPERMB-512-1)
{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
IFORM:       VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
}

{
ICLASS:      VPERMB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
IFORM:       VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
}


# EMITTING VPERMI2B (VPERMI2B-128-1)
{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
IFORM:       VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
}

{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
IFORM:       VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
}


# EMITTING VPERMI2B (VPERMI2B-256-1)
{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
IFORM:       VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
}

{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
IFORM:       VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
}


# EMITTING VPERMI2B (VPERMI2B-512-1)
{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
IFORM:       VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
}

{
ICLASS:      VPERMI2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
IFORM:       VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
}


# EMITTING VPERMT2B (VPERMT2B-128-1)
{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
IFORM:       VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
}

{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
IFORM:       VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
}


# EMITTING VPERMT2B (VPERMT2B-256-1)
{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
IFORM:       VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
}

{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
IFORM:       VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
}


# EMITTING VPERMT2B (VPERMT2B-512-1)
{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
IFORM:       VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
}

{
ICLASS:      VPERMT2B
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0    ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
IFORM:       VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
}


# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1)
{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64
IFORM:       VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512
}

{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_128
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512
}


# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1)
{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64
IFORM:       VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512
}

{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_256
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512
}


# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1)
{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64
IFORM:       VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512
}

{
ICLASS:      VPMULTISHIFTQB
CPL:         3
CATEGORY:    AVX512_VBMI
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512
}


