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#
#Copyright (c) 2016 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
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#END_LEGAL
AVX_INSTRUCTIONS()::


{
ICLASS    : KAND
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x41  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KANDN
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x42  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KANDNR
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x43  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KNOT
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x44  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KOR
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x45  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KXNOR
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x46  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KXOR
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x47  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KMERGE2L1H
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x48  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}
{
ICLASS    : KMERGE2L1L
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
PATTERN   : VV1 0x49  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw
}


{
ICLASS    : KORTESTD
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
FLAGS     : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ]
PATTERN   : VV1 0x98  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():r:mskw    REG1=MASK_B():r:mskw
COMMENT   : flags operand is added implicitly by XED generator
}
##MACRO_USE: vex_mask_logical_flags(KORTESTQ,0x98,REXW=1)




# was KMOVD
{
ICLASS    : KMOV
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV

# load forms, mask dest/ mask src
PATTERN   : VV1 0x90  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=MASK_R():w:mskw    REG1=MASK_B():r:mskw

# load forms, mask dest / gpr src
PATTERN   : VV1 0x92  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64
OPERANDS  : REG0=MASK_R():w:mskw    REG1=GPR32_B():r:mskw


# store forms, gpr dest/ mask src
PATTERN   : VV1 0x93  VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64
OPERANDS  : REG0=GPR32_R():w:mskw   REG1=MASK_B():r:mskw
}



{
ICLASS    : KCONCATH
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
#
# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX.
#  I could change the NT to one that uses the VEXR instead. That would work better if REX comes back.
#
PATTERN   : VV1 0x95  VL128 VNP V0F REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():w:q    REG1=MASK_N():r:mskw    REG2=MASK_B():r:mskw
}
{
ICLASS    : KCONCATL
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
#
# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX.
#  I could change the NT to one that uses the VEXR instead. That would work better if REX comes back.
#
PATTERN   : VV1 0x97  VL128 VNP V0F REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():w:q    REG1=MASK_N():r:mskw    REG2=MASK_B():r:mskw
}







{
ICLASS    : KEXTRACT
CPL       : 3
CATEGORY  : KNCMASK
EXTENSION : KNC
ISA_SET:    KNCV
#
# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX.
#  I could change the NT to one that uses the VEXR instead. That would work better if REX comes back.
#
PATTERN   : VV1 0x3E  VL128 V66 V0F3A REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]  UIMM8()
OPERANDS  : REG0=MASK_R():w:mskw REG1=GPR64_B():r:q IMM0:r:b
}



######################################################
# Scalar instructions
######################################################

{
ICLASS    : LZCNT_VEX
DISASM    : lzcnt
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV
FLAGS     : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ]

PATTERN   : VV1 0xBD  VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():w:d    REG1=GPR32_B():r:d

PATTERN   : VV1 0xBD  VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():w:q    REG1=GPR64_B():r:q
}






{
ICLASS    : CLEVICT0
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0xAE  VL128 VF2 V0F  NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch  #FIXME: rw or r???
}
{
ICLASS    : CLEVICT1
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0xAE  VL128 VF3 V0F  NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch  #FIXME: rw or r???
}



{
ICLASS    : DELAY
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV

PATTERN   : VV1 0xAE  VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn]  W0
OPERANDS  : REG0=GPR32_B():r:d

PATTERN   : VV1 0xAE  VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn]  W1
OPERANDS  : REG0=GPR64_B():r:q
}
{
ICLASS    : SPFLT
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV

PATTERN   : VV1 0xAE  VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn]  W0
OPERANDS  : REG0=GPR32_B():r:d

PATTERN   : VV1 0xAE  VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn]  W1
OPERANDS  : REG0=GPR64_B():r:q
}

# DRW is the dest read/write flag

# I made up my own names for the VEX'ed POPCNT and TZCNT to
# differetiate them from the nonVEX versions of the same instructions.
# The XED encoder requires this as VEXVALID is not an encoder input
# and we do not want it to be one for most instructions. I could add
# something new but have not.

{
ICLASS    : POPCNT_VEX
DISASM    : popcnt
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV
FLAGS     : MUST [ zf-mod cf-0 of-0 sf-0 af-0 pf-0 ]
PATTERN   : VV1 0xB8  VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():w:d   REG1=GPR32_B():r:d

PATTERN   : VV1 0xB8  VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():w:q  REG1=GPR64_B():r:q
}
{
ICLASS    : TZCNT_VEX
DISASM    : tzcnt
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV
FLAGS     : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ]
PATTERN   : VV1 0xBC  VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():w:d   REG1=GPR32_B():r:d

PATTERN   : VV1 0xBC  VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():w:q  REG1=GPR64_B():r:q
}
{
ICLASS    : TZCNTI
DISASM    : tzcnti
CPL       : 3
CATEGORY  : KNCSCALAR
EXTENSION : KNC
ISA_SET:    KNCV
FLAGS     : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ]
PATTERN   : VV1 0xBC  VL128 VF2 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR32_R():rw:d   REG1=GPR32_B():r:d

PATTERN   : VV1 0xBC  VL128 VF2 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPR64_R():rw:q  REG1=GPR64_B():r:q
}




{
ICLASS    : VPREFETCH0
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b001] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCH1
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCH2
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCHE0
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b101] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCHE1
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b110] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCHE2
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCHENTA
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b100] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}
{
ICLASS    : VPREFETCHNTA
CPL       : 3
CATEGORY  : PREFETCH
EXTENSION : KNC
ISA_SET:    KNCV
ATTRIBUTES : PREFETCH
PATTERN   : VV1 0x18  VL128 VNP V0F  NOVSR MOD[mm] MOD!=3 REG[0b000] RM[nnn]  MODRM()
OPERANDS  : MEM0:r:mprefetch
}



