From d6af629055fc2f977c33385296f77b37ed5daec4 Mon Sep 17 00:00:00 2001 From: Mark Charney Date: Sat, 21 Jan 2017 10:59:52 -0500 Subject: [PATCH] add CET to base layer Change-Id: I7f8930399dbaba3742edcbbc95b23a934b8b2807 (cherry picked from commit 4deac32dc633ee4eafaed78fb5e08a7638ef171f) --- datafiles/cet/cet-fields.txt | 21 ++ datafiles/cet/cet-isa.xed.txt | 275 +++++++++++++++++++++++++++ datafiles/cet/cet-nop-remove.xed.txt | 111 +++++++++++ datafiles/cet/cet-regs.txt | 20 ++ datafiles/cet/cpuid.xed.txt | 18 ++ datafiles/cet/files.cfg | 27 +++ datafiles/files.cfg | 1 + datafiles/{pt => }/future-chips.txt | 2 +- datafiles/pt/files.cfg | 1 - xed_mbuild.py | 9 + 10 files changed, 483 insertions(+), 2 deletions(-) create mode 100644 datafiles/cet/cet-fields.txt create mode 100644 datafiles/cet/cet-isa.xed.txt create mode 100644 datafiles/cet/cet-nop-remove.xed.txt create mode 100644 datafiles/cet/cet-regs.txt create mode 100644 datafiles/cet/cpuid.xed.txt create mode 100644 datafiles/cet/files.cfg rename datafiles/{pt => }/future-chips.txt (95%) diff --git a/datafiles/cet/cet-fields.txt b/datafiles/cet/cet-fields.txt new file mode 100644 index 0000000..45da9e3 --- /dev/null +++ b/datafiles/cet/cet-fields.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +CET SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + + diff --git a/datafiles/cet/cet-isa.xed.txt b/datafiles/cet/cet-isa.xed.txt new file mode 100644 index 0000000..b8fd52f --- /dev/null +++ b/datafiles/cet/cet-isa.xed.txt @@ -0,0 +1,275 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLRSSBSY (CLRSSBSY-N/A-1) +{ +ICLASS: CLRSSBSY +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() +OPERANDS: MEM0:w:q:u64 +IFORM: CLRSSBSY_MEMu64 +} + + +# EMITTING ENDBR32 (ENDBR32-N/A-1) +{ +ICLASS: ENDBR32 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR32 +} + +# EMITTING ENDBR64 (ENDBR64-N/A-1) +{ +ICLASS: ENDBR64 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR64 +} + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + + +# EMITTING INCSSPD (INCSSPD-N/A-1) +{ +ICLASS: INCSSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W0 +OPERANDS: +IFORM: INCSSPD +} + + +# EMITTING INCSSPQ (INCSSPQ-N/A-1) +{ +ICLASS: INCSSPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W1 mode64 +OPERANDS: +IFORM: INCSSPQ +} + + +# EMITTING RDSSPD (RDSSPD-N/A-1) +{ +ICLASS: RDSSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 +OPERANDS: REG0=GPR32_B():w:d:u32 +IFORM: RDSSPD_GPR32u32 +} + + +# EMITTING RDSSPQ (RDSSPQ-N/A-1) +{ +ICLASS: RDSSPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 +OPERANDS: REG0=GPR64_B():w:q:u64 +IFORM: RDSSPQ_GPR64u64 +} + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + + + +# EMITTING RSTORSSPD (RSTORSSPD-N/A-1) +{ +ICLASS: RSTORSSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix W0 +OPERANDS: MEM0:rw:d:u32 +IFORM: RSTORSSPD_MEMu32 +} + + +# EMITTING RSTORSSPQ (RSTORSSPQ-N/A-1) +{ +ICLASS: RSTORSSPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix W1 mode64 +OPERANDS: MEM0:rw:q:u64 +IFORM: RSTORSSPQ_MEMu64 +} + + +# EMITTING SAVESSP (SAVESSP-N/A-1) +{ +ICLASS: SAVESSP +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix +OPERANDS: +IFORM: SAVESSP +} + + +# EMITTING SETSSBSY (SETSSBSY-N/A-1) +{ +ICLASS: SETSSBSY +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] f3_refining_prefix MODRM() +OPERANDS: MEM0:w:q:u64 +IFORM: SETSSBSY_MEMu64 +} + + +# EMITTING WRSSD (WRSSD-N/A-1) +{ +ICLASS: WRSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRSSQ (WRSSQ-N/A-1) +{ +ICLASS: WRSSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRSSQ_MEMu64_GPR64u64 +} + + +# EMITTING WRUSSD (WRUSSD-N/A-1) +{ +ICLASS: WRUSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRUSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRUSSQ (WRUSSQ-N/A-1) +{ +ICLASS: WRUSSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: N +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRUSSQ_MEMu64_GPR64u64 +} + + diff --git a/datafiles/cet/cet-nop-remove.xed.txt b/datafiles/cet/cet-nop-remove.xed.txt new file mode 100644 index 0000000..b74dc06 --- /dev/null +++ b/datafiles/cet/cet-nop-remove.xed.txt @@ -0,0 +1,111 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +UDELETE: NOP0F1E + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q} + +# mem forms + +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + + +# reg forms + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + + + + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b001 is for CET for all values of RM. +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +} + diff --git a/datafiles/cet/cet-regs.txt b/datafiles/cet/cet-regs.txt new file mode 100644 index 0000000..4e3bf44 --- /dev/null +++ b/datafiles/cet/cet-regs.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SSP MSR NA +IA32_U_CET MSR NA diff --git a/datafiles/cet/cpuid.xed.txt b/datafiles/cet/cpuid.xed.txt new file mode 100644 index 0000000..55b42fa --- /dev/null +++ b/datafiles/cet/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_CET: cet.7.0.ecx.7 diff --git a/datafiles/cet/files.cfg b/datafiles/cet/files.cfg new file mode 100644 index 0000000..a51b0e5 --- /dev/null +++ b/datafiles/cet/files.cfg @@ -0,0 +1,27 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: cet-nop-remove.xed.txt + dec-instructions: cet-isa.xed.txt + + enc-instructions: cet-nop-remove.xed.txt + enc-instructions: cet-isa.xed.txt + + cpuid: cpuid.xed.txt + + registers: cet-regs.txt + fields: cet-fields.txt diff --git a/datafiles/files.cfg b/datafiles/files.cfg index 553ec93..7df86e5 100644 --- a/datafiles/files.cfg +++ b/datafiles/files.cfg @@ -30,6 +30,7 @@ dec-patterns : xed-immediates.txt dec-patterns : xed-addressing-modes-new.txt chip-models : xed-chips.txt +chip-models : future-chips.txt conversion-table : xed-convert.txt # decode patterns used for encode diff --git a/datafiles/pt/future-chips.txt b/datafiles/future-chips.txt similarity index 95% rename from datafiles/pt/future-chips.txt rename to datafiles/future-chips.txt index bc97a9c..04b23fc 100644 --- a/datafiles/pt/future-chips.txt +++ b/datafiles/future-chips.txt @@ -21,4 +21,4 @@ # time and I had to put the new instructions on some chip so I made # somethign up. -FUTURE: ALL_OF(SKYLAKE_SERVER) PT +FUTURE: ALL_OF(SKYLAKE_SERVER) PT CET diff --git a/datafiles/pt/files.cfg b/datafiles/pt/files.cfg index 1e67e4b..495d6c7 100644 --- a/datafiles/pt/files.cfg +++ b/datafiles/pt/files.cfg @@ -17,5 +17,4 @@ #END_LEGAL dec-instructions: intelpt-isa.xed.txt enc-instructions: intelpt-isa.xed.txt - chip-models: future-chips.txt diff --git a/xed_mbuild.py b/xed_mbuild.py index a93b7d1..3262462 100755 --- a/xed_mbuild.py +++ b/xed_mbuild.py @@ -542,6 +542,7 @@ def mkenv(): ivbint=True, avxhsw=True, mpx=True, + cet=True, glm=True, skl=True, skx=True, @@ -705,6 +706,10 @@ def xed_args(env): action="store_false", dest="mpx", help="Do not include MPX.") + env.parser.add_option("--no-cet", + action="store_false", + dest="cet", + help="Do not include CET.") env.parser.add_option("--no-sha", action="store_false", dest="sha", @@ -1073,6 +1078,8 @@ def build_libxed(env,work_queue): env.add_define('XED_SUPPORTS_KNC') if env['mpx']: env.add_define('XED_MPX') + if env['cet']: + env.add_define('XED_CET') if env['sha']: env.add_define('XED_SUPPORTS_SHA') @@ -1123,6 +1130,8 @@ def build_libxed(env,work_queue): _add_normal_ext(env,'xsaveopt') if env['mpx']: _add_normal_ext(env,'mpx') + if env['cet']: + _add_normal_ext(env,'cet') if env['sha']: _add_normal_ext(env,'sha') if env['ivbint']: