commit ffd94e705cc102c3e9c29a730eac1195f68b5109 Author: Mark Charney Date: Fri Dec 16 16:09:38 2016 -0500 initial commit Change-Id: I32a6db1a17988d9df8ff69aa1672dbf08b108e8a diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..af6d16e --- /dev/null +++ b/.gitignore @@ -0,0 +1,17 @@ +.o +*.obj +*.exe +*.pyc +*~ +*# +obj* +.buildid +xed2-install* +xed-install* +.#* +TAGS +/VS10/xed.vcxproj.user +/VS10/xed.sdf +kits/* +logs/* +.developer diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..7b1fcae --- /dev/null +++ b/LICENSE @@ -0,0 +1,178 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. 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a/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt b/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt new file mode 100644 index 0000000..0e5ea4a --- /dev/null +++ b/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt @@ -0,0 +1,91 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING V4FMADDPS (V4FMADDPS-512-1) +{ +ICLASS: V4FMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FMADDSS (V4FMADDSS-128-1) +{ +ICLASS: V4FMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) +{ +ICLASS: V4FNMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +{ +ICLASS: V4FNMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + diff --git a/datafiles/4fmaps-512/cpuid.xed.txt b/datafiles/4fmaps-512/cpuid.xed.txt new file mode 100644 index 0000000..d35d005 --- /dev/null +++ b/datafiles/4fmaps-512/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_4FMAPS_512: avx512_4fmaps.7.0.edx.3 +XED_ISA_SET_AVX512_4FMAPS_SCALAR: avx512_4fmaps.7.0.edx.3 diff --git a/datafiles/4fmaps-512/files.cfg b/datafiles/4fmaps-512/files.cfg new file mode 100644 index 0000000..0a4578c --- /dev/null +++ b/datafiles/4fmaps-512/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + dec-instructions: 4fmaps-512-isa.xed.txt + enc-instructions: 4fmaps-512-isa.xed.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt b/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt new file mode 100644 index 0000000..83002e6 --- /dev/null +++ b/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt @@ -0,0 +1,59 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) +{ +ICLASS: VP4DPWSSD +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) +{ +ICLASS: VP4DPWSSDS +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + diff --git a/datafiles/4vnniw-512/cpuid.xed.txt b/datafiles/4vnniw-512/cpuid.xed.txt new file mode 100644 index 0000000..44e74be --- /dev/null +++ b/datafiles/4vnniw-512/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_4VNNIW_512: avx512_4vnniw.7.0.edx.2 diff --git a/datafiles/4vnniw-512/files.cfg b/datafiles/4vnniw-512/files.cfg new file mode 100644 index 0000000..6a872cc --- /dev/null +++ b/datafiles/4vnniw-512/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + dec-instructions: 4vnniw-512-isa.xed.txt + enc-instructions: 4vnniw-512-isa.xed.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/amdxop/amd-fma4-isa.txt b/datafiles/amdxop/amd-fma4-isa.txt new file mode 100644 index 0000000..2a32dca --- /dev/null +++ b/datafiles/amdxop/amd-fma4-isa.txt @@ -0,0 +1,582 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: +{ +ICLASS: VFMADDSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 +} diff --git a/datafiles/amdxop/amd-vpermil2-isa.txt b/datafiles/amdxop/amd-vpermil2-isa.txt new file mode 100644 index 0000000..575e3c5 --- /dev/null +++ b/datafiles/amdxop/amd-vpermil2-isa.txt @@ -0,0 +1,97 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPERMIL2PS +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP + +# 128b W0 +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b + +} + + + +{ +ICLASS : VPERMIL2PD +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP + +# 128b W0 +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b + +} + diff --git a/datafiles/amdxop/amd-xop-dec.txt b/datafiles/amdxop/amd-xop-dec.txt new file mode 100644 index 0000000..994dbe3 --- /dev/null +++ b/datafiles/amdxop/amd-xop-dec.txt @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_SPLITTER():: +VEXVALID=3 XOP_INSTRUCTIONS() | + +EVEX_SPLITTER():: +VEXVALID=3 XOP_INSTRUCTIONS() | + diff --git a/datafiles/amdxop/amd-xop-enc.txt b/datafiles/amdxop/amd-xop-enc.txt new file mode 100644 index 0000000..09cf7ec --- /dev/null +++ b/datafiles/amdxop/amd-xop-enc.txt @@ -0,0 +1,62 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +######## XOP ################################# +SEQUENCE XOP_ENC_BIND + XOP_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + XOP_REXXB_ENC_BIND + XOP_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE XOP_ENC_EMIT + XOP_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + XOP_REXXB_ENC_EMIT + XOP_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + +############################################## + +VEXED_REX():: +VEXVALID=3 -> XOP_ENC() + +XOP_TYPE_ENC():: +XMAP8 -> 0x8F +XMAP9 -> 0x8F +XMAPA -> 0x8F +otherwise -> error + +XOP_MAP_ENC():: +XMAP8 REXW[w] -> 0b0_1000 w +XMAP9 REXW[w] -> 0b0_1001 w +XMAPA REXW[w] -> 0b0_1010 w +otherwise -> error + +XOP_REXXB_ENC():: +mode64 REXX=0 REXB=0 -> 0b11 +mode64 REXX=1 REXB=0 -> 0b01 +mode64 REXX=0 REXB=1 -> 0b10 +mode64 REXX=1 REXB=1 -> 0b00 +not64 REXX=0 REXB=0 -> 0b11 +not64 REXX=1 REXB=0 -> error +not64 REXX=0 REXB=1 -> error +not64 REXX=1 REXB=1 -> error +otherwise -> nothing diff --git a/datafiles/amdxop/amd-xop-isa.txt b/datafiles/amdxop/amd-xop-isa.txt new file mode 100644 index 0000000..3caad31 --- /dev/null +++ b/datafiles/amdxop/amd-xop-isa.txt @@ -0,0 +1,1129 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XOP_INSTRUCTIONS():: +{ +ICLASS: VPMACSSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCMOV +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1 +} + +{ +ICLASS: VPPERM +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPMADCSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMADCSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u16 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u32 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u64 +} + +{ +ICLASS: VPMACSSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCOMB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:i8 + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:i8 +} + +{ +ICLASS: VPCOMW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:i16 + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:i16 +} + +{ +ICLASS: VPCOMD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:i32 + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:i32 +} + +{ +ICLASS: VPCOMQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:i64 + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:i64 +} + +{ +ICLASS: VPCOMUB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u16 +} + +{ +ICLASS: VPCOMUD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u32 +} + +{ +ICLASS: VPCOMUQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u64 +} + +{ +ICLASS: VFRCZPS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFRCZPD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFRCZSS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS: VFRCZSD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPSHLB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPSHLW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPSHLD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPSHLQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPHADDBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDUBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHADDUWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHSUBBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8 + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHSUBWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHSUBDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPSHAW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPSHAD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS: VPHADDDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPHADDUDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32 + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32 +} + +{ +ICLASS: BEXTR_XOP +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ] + +PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d + +PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d +} + +{ +ICLASS: BLCFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLSFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLCS +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: TZMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLCIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLSIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: T1MSKC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLCMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: BLCI +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y +} + +{ +ICLASS: LLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS: REG0=GPRy_B():w:y +} + +{ +ICLASS: SLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=GPRy_B():w:y +} + +{ +ICLASS: LWPINS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +FLAGS: MUST [ cf-mod ] + +PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d +} + +{ +ICLASS: LWPVAL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP + +PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() +OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d +} diff --git a/datafiles/amdxop/cpuid.xed.txt b/datafiles/amdxop/cpuid.xed.txt new file mode 100644 index 0000000..fa7e36c --- /dev/null +++ b/datafiles/amdxop/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XOP: n/a + XED_ISA_SET_TBM: n/a + XED_ISA_SET_FMA4: n/a diff --git a/datafiles/amdxop/files.cfg b/datafiles/amdxop/files.cfg new file mode 100644 index 0000000..96ebc2b --- /dev/null +++ b/datafiles/amdxop/files.cfg @@ -0,0 +1,30 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +state:xop-state-bits.txt + + +dec-patterns:amd-xop-dec.txt +dec-instructions:amd-xop-isa.txt +enc-instructions:amd-xop-isa.txt +dec-instructions:amd-fma4-isa.txt +enc-instructions:amd-fma4-isa.txt +dec-instructions:amd-vpermil2-isa.txt +enc-instructions:amd-vpermil2-isa.txt +enc-patterns:amd-xop-enc.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/amdxop/xop-state-bits.txt b/datafiles/amdxop/xop-state-bits.txt new file mode 100644 index 0000000..842683a --- /dev/null +++ b/datafiles/amdxop/xop-state-bits.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XMAP8 MAP=8 +XMAP9 MAP=9 +XMAPA MAP=10 + +XOPV VEXVALID=3 diff --git a/datafiles/avx/avx-aes-isa.txt b/datafiles/avx/avx-aes-isa.txt new file mode 100644 index 0000000..b3d2574 --- /dev/null +++ b/datafiles/avx/avx-aes-isa.txt @@ -0,0 +1,86 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +{ +ICLASS : VAESKEYGENASSIST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : VAESENC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESENCLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDEC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDECLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESIMC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + diff --git a/datafiles/avx/avx-chips.txt b/datafiles/avx/avx-chips.txt new file mode 100644 index 0000000..cf89ce7 --- /dev/null +++ b/datafiles/avx/avx-chips.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SANDYBRIDGE: ALL_OF(WESTMERE) AVX AVXAES XSAVE XSAVEOPT diff --git a/datafiles/avx/avx-fields.txt b/datafiles/avx/avx-fields.txt new file mode 100644 index 0000000..1097585 --- /dev/null +++ b/datafiles/avx/avx-fields.txt @@ -0,0 +1,28 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# ==== ==== ========= ========== ============== +# default +# name type bit-width visibility behavior +# ==== ==== ========= ========== ============== +VEXDEST3 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +VEXDEST210 SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +VL SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +VEX_PREFIX SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO # VEX.PP +VEX_C4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO # ENCONLY +BCAST SCALAR xed_bits_t 5 SUPPRESSED NOPRINT INTERNAL DO EO + diff --git a/datafiles/avx/avx-fma-isa.txt b/datafiles/avx/avx-fma-isa.txt new file mode 100644 index 0000000..048877b --- /dev/null +++ b/datafiles/avx/avx-fma-isa.txt @@ -0,0 +1,1257 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. +# Encoder must enforce equality between two parameters. Never had to do this before. +# Extra check? +# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) +############################################################################################# +# Operand orders: +# A = B * C + D +#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 +#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 +#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 + +# dst is in MODRM.REG +# regsrc is in VEX.vvvv +# memop is in MODRM.RM +############################################################################################ + + + + + + + + + + + + +########################################################## + + + + + + + + + + + + +################################################################## + + + + + + + + + + + + + +################################################################## +{ +ICLASS : VFMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + + +################################################### +{ +ICLASS : VFMADDSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMADDSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +################################################### + +{ +ICLASS : VFMSUBADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMSUBADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} + + +################################################### + +{ +ICLASS : VFMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + + + diff --git a/datafiles/avx/avx-imm-enc.txt b/datafiles/avx/avx-imm-enc.txt new file mode 100644 index 0000000..52dd9fa --- /dev/null +++ b/datafiles/avx/avx-imm-enc.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SE_IMM8():: +true ESRC[ssss] UIMM0[dddd] -> ssss_dddd diff --git a/datafiles/avx/avx-imm.txt b/datafiles/avx/avx-imm.txt new file mode 100644 index 0000000..550af6a --- /dev/null +++ b/datafiles/avx/avx-imm.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SE_IMM8():: +UIMM0[ssss_uuuu] | IMM_WIDTH=8 ESRC=ssss diff --git a/datafiles/avx/avx-isa-supp-enc.txt b/datafiles/avx/avx-isa-supp-enc.txt new file mode 100644 index 0000000..5787b20 --- /dev/null +++ b/datafiles/avx/avx-isa-supp-enc.txt @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#AVX_SPLITTER():: +#VEXVALID=0 -> INSTRUCTIONS() +#VEXVALID=1 -> AVX_INSTRUCTIONS() + + + + diff --git a/datafiles/avx/avx-isa-supp.txt b/datafiles/avx/avx-isa-supp.txt new file mode 100644 index 0000000..d8c3711 --- /dev/null +++ b/datafiles/avx/avx-isa-supp.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_SPLITTER():: +VEXVALID=0 INSTRUCTIONS() | +VEXVALID=1 AVX_INSTRUCTIONS() | diff --git a/datafiles/avx/avx-isa.txt b/datafiles/avx/avx-isa.txt new file mode 100644 index 0000000..aba8248 --- /dev/null +++ b/datafiles/avx/avx-isa.txt @@ -0,0 +1,4402 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# The neat thing is we can just end a nonterminal by starting a new one. + +AVX_INSTRUCTIONS():: +{ +ICLASS : VADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VADDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VADDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VADDSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VADDSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VANDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +{ +ICLASS : VANDNPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDNPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + + +{ +ICLASS : VBLENDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VBLENDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + + + + +{ +ICLASS : VCMPPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + +{ +ICLASS : VCMPSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + + +{ +ICLASS : VCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 +} + + +{ +ICLASS : VCVTDQ2PD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 + +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VCVTDQ2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 + +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 +} + +{ +ICLASS : VCVTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTPD2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64 + +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VCVTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTPS2PD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32 + +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32 +} + + + + +{ +ICLASS : VCVTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCVTTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + + + + +{ +ICLASS : VCVTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS : VCVTTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + + + + +{ +ICLASS : VCVTSD2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64 + +PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64 + +} + + +{ +ICLASS : VCVTSI2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSI2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSS2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32 + +PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VDIVPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VDIVPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VDIVSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VDIVSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VEXTRACTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b +} + + + +{ +ICLASS : VDPPD +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b +} + +{ +ICLASS : VDPPS +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VEXTRACTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b +} + + +{ +ICLASS : VZEROALL +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w + +PATTERN : VV1 0x77 VNP V0F VL256 NOVSR +OPERANDS: + +} + +# FIXME: how to denote partial upper clobber! +{ +ICLASS : VZEROUPPER +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w? + +PATTERN : VV1 0x77 VNP V0F VL128 NOVSR +OPERANDS: +} + + +{ +ICLASS : VHADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VHSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPERMILPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 + +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VPERMILPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32 + +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VPERM2F128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VBROADCASTSS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +} +{ +ICLASS : VBROADCASTSD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +} + +{ +ICLASS : VBROADCASTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +COMMENT : There is no F128 type. I just set these to f64 for lack of anything better. +PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +} + + +{ +ICLASS : VINSERTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 +} + +{ +ICLASS : VINSERTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b +} + + + + + +{ +ICLASS : VLDDQU +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + + + + +{ +ICLASS : VMASKMOVPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop +# load forms +PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 + +PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32 + +# store forms +PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32 + +PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32 +} + +{ +ICLASS : VMASKMOVPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop +# load forms +PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64 + +PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64 + +# store forms +PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64 + +PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64 +} + +{ +ICLASS : VPTEST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq + +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq +} + +{ +ICLASS : VTESTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VTESTPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VMAXPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMAXPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMAXSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMAXSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMINPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMINPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMINSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMINSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VMOVAPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_28 + +# 128b store + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVAPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_28 +# 128b store + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + +} + +{ +ICLASS : VMOVQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 64b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_6E + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q + +# 64b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_7E + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q + + +# 2nd page of MOVQ forms +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_7E + +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : VMOVQ_XMMdq_XMMq_7E + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_D6 + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : VMOVQ_XMMdq_XMMq_D6 + +} + + + + +{ +ICLASS : VMOVDDUP +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + + + +{ +ICLASS : VMOVDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_7F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_6F + + +# STORE YMM + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_7F +} + + +{ +ICLASS : VMOVDQU +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_6F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_7F + +# STORE YMM + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_7F +} + +################################################# +## skipping to the end +################################################# + +################################################# +## MACROS +################################################# +{ +ICLASS : VMOVSHDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VMOVSLDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPAND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPANDN +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPXOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} + + +{ +ICLASS : VPABSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : VPABSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16 + +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : VPABSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32 + +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPHMINPOSUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 +} + + + + + + + + + + +{ +ICLASS : VPSHUFD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} + + + + + + + + + + + + + +{ +ICLASS : VPACKSSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKSSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPACKUSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKUSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPADDB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPADDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPADDSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPADDUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPADDUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPAVGB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPAVGW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPCMPEQB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPCMPEQW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPCMPEQD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPCMPEQQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPCMPGTB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPCMPGTW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPCMPGTD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPCMPGTQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPHADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPMULHUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMULHRSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMULUDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPMULDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSHUFB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS : VPSIGNB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSIGNW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSIGND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSUBSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPSUBUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSUBUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPSUBB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPSUBQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPUNPCKHBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKHWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKHDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPUNPCKLBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKLWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKLDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : VPSRLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} + + + + + + + + + + + + + + + + + + + + +{ +ICLASS : VMOVLHPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32 +} +{ +ICLASS : VMOVHLPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +} + + + + + + + +{ +ICLASS : VPALIGNR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b +} + + + + + + + + + + + + +############################################################ +{ +ICLASS : VROUNDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VROUNDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} +{ +ICLASS : VROUNDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} +{ +ICLASS : VROUNDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + +{ +ICLASS : VSHUFPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VSHUFPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + +{ +ICLASS : VRCPPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRCPSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VRSQRTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRSQRTSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VSQRTPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} +{ +ICLASS : VSQRTPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VSQRTSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSQRTSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VUNPCKHPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VUNPCKHPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VSUBSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR SIMD_SCALAR +PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSUBSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMULPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VMULPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VMULSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VMULSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} +{ +ICLASS : VORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMAXSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMAXSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMAXSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMAXUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMAXUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMAXUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS : VPMINSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMINSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMINSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMINUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMINUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMINUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + + +{ +ICLASS : VPMADDWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMADDUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8 +} + + +{ +ICLASS : VMPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} + + +############################################################ +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + + +{ +ICLASS : VUCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VUCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32 +} + +############################################### + + +{ +ICLASS : VUNPCKLPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VUNPCKLPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + + +{ +ICLASS : VXORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VXORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +############################################################################ + +{ +ICLASS : VMOVSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10 + +PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32 + +PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11 +} +############################################################################ +{ +ICLASS : VMOVSD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10 + +PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 + +PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11 +} +############################################################################ +{ +ICLASS : VMOVUPD +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_11 +} + +############################################################################ +{ +ICLASS : VMOVUPS +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_11 +} + + +############################################################################ +{ +ICLASS : VMOVLPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 +} + +{ +ICLASS : VMOVLPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 +} + +{ +ICLASS : VMOVHPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64 +} + +{ +ICLASS : VMOVHPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32 +} +############################################################################ + +{ +ICLASS : VMOVMSKPD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64 + +# 256b versions + +PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMOVMSKPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32 + +# 256b versions + +PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32 +} + +############################################################################ +{ +ICLASS : VPMOVMSKB +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8 +} + +############################################################################ + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +} + + + +############################################################################ +############################################################################ +{ +ICLASS : VPEXTRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15 + +# special C5 reg-only versions from SSE2: + +PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5 +} +############################################################################ +{ +ICLASS : VPEXTRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b +} +############################################################################ + + + + + + +{ +ICLASS : VPINSRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +} + +{ +ICLASS : VPINSRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : WIG +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b + +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +} + +{ +ICLASS : VPINSRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +} +{ +ICLASS : VPINSRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +} + +############################################################################ + + + + + +{ +ICLASS : VPCMPESTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : VPCMPISTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : VPCMPESTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPISTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### + + + +#################################################################################### +{ +ICLASS : VMASKMOVDQU +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop fixed_base0 NOTSX +PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + +#################################################################################### +{ +ICLASS : VLDMXCSR +EXCEPTIONS: avx-type-5L +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : VSTMXCSR +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR_RD +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +####################################################################################### + +{ +ICLASS : VPBLENDVB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8 + +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8 +} + +{ +ICLASS : VBLENDVPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64 + +} + +{ +ICLASS : VBLENDVPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32 + + +} + +####################################################################################### + + + +{ +ICLASS : VMOVNTDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX + +PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + + + + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +} + diff --git a/datafiles/avx/avx-movnt-store.txt b/datafiles/avx/avx-movnt-store.txt new file mode 100644 index 0000000..b3febc4 --- /dev/null +++ b/datafiles/avx/avx-movnt-store.txt @@ -0,0 +1,54 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +} + diff --git a/datafiles/avx/avx-operand-width.txt b/datafiles/avx/avx-operand-width.txt new file mode 100644 index 0000000..faa84ba --- /dev/null +++ b/datafiles/avx/avx-operand-width.txt @@ -0,0 +1,36 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# +qq i32 32 +yub u8 32 +yuw u16 32 +yud u32 32 +yuq u64 32 +y128 u128 32 + +yb i8 32 +yw i16 32 +yd i32 32 +yq i64 32 + +yps f32 32 +ypd f64 32 + + diff --git a/datafiles/avx/avx-pclmul-isa.txt b/datafiles/avx/avx-pclmul-isa.txt new file mode 100644 index 0000000..7414b85 --- /dev/null +++ b/datafiles/avx/avx-pclmul-isa.txt @@ -0,0 +1,29 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VPCLMULQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +} diff --git a/datafiles/avx/avx-pointer-width.txt b/datafiles/avx/avx-pointer-width.txt new file mode 100644 index 0000000..a079610 --- /dev/null +++ b/datafiles/avx/avx-pointer-width.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +32 ymmword y diff --git a/datafiles/avx/avx-reg-table.txt b/datafiles/avx/avx-reg-table.txt new file mode 100644 index 0000000..c1a4941 --- /dev/null +++ b/datafiles/avx/avx-reg-table.txt @@ -0,0 +1,235 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t XMM_SE():: +mode16 | OUTREG=XMM_SE32() +mode32 | OUTREG=XMM_SE32() +mode64 | OUTREG=XMM_SE64() + +xed_reg_enum_t XMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_XMM0 +ESRC=0x1 | OUTREG=XED_REG_XMM1 +ESRC=0x2 | OUTREG=XED_REG_XMM2 +ESRC=0x3 | OUTREG=XED_REG_XMM3 +ESRC=0x4 | OUTREG=XED_REG_XMM4 +ESRC=0x5 | OUTREG=XED_REG_XMM5 +ESRC=0x6 | OUTREG=XED_REG_XMM6 +ESRC=0x7 | OUTREG=XED_REG_XMM7 +ESRC=0x8 | OUTREG=XED_REG_XMM8 +ESRC=0x9 | OUTREG=XED_REG_XMM9 +ESRC=0xA | OUTREG=XED_REG_XMM10 +ESRC=0xB | OUTREG=XED_REG_XMM11 +ESRC=0xC | OUTREG=XED_REG_XMM12 +ESRC=0xD | OUTREG=XED_REG_XMM13 +ESRC=0xE | OUTREG=XED_REG_XMM14 +ESRC=0xF | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t XMM_SE32():: +ESRC=0 | OUTREG=XED_REG_XMM0 enc +ESRC=1 | OUTREG=XED_REG_XMM1 enc +ESRC=2 | OUTREG=XED_REG_XMM2 enc +ESRC=3 | OUTREG=XED_REG_XMM3 enc +ESRC=4 | OUTREG=XED_REG_XMM4 enc +ESRC=5 | OUTREG=XED_REG_XMM5 enc +ESRC=6 | OUTREG=XED_REG_XMM6 enc +ESRC=7 | OUTREG=XED_REG_XMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_XMM0 +ESRC=0x9 | OUTREG=XED_REG_XMM1 +ESRC=0xA | OUTREG=XED_REG_XMM2 +ESRC=0xB | OUTREG=XED_REG_XMM3 +ESRC=0xC | OUTREG=XED_REG_XMM4 +ESRC=0xD | OUTREG=XED_REG_XMM5 +ESRC=0xE | OUTREG=XED_REG_XMM6 +ESRC=0xF | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t YMM_SE():: +mode16 | OUTREG=YMM_SE32() +mode32 | OUTREG=YMM_SE32() +mode64 | OUTREG=YMM_SE64() + +xed_reg_enum_t YMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_YMM0 +ESRC=0x1 | OUTREG=XED_REG_YMM1 +ESRC=0x2 | OUTREG=XED_REG_YMM2 +ESRC=0x3 | OUTREG=XED_REG_YMM3 +ESRC=0x4 | OUTREG=XED_REG_YMM4 +ESRC=0x5 | OUTREG=XED_REG_YMM5 +ESRC=0x6 | OUTREG=XED_REG_YMM6 +ESRC=0x7 | OUTREG=XED_REG_YMM7 +ESRC=0x8 | OUTREG=XED_REG_YMM8 +ESRC=0x9 | OUTREG=XED_REG_YMM9 +ESRC=0xA | OUTREG=XED_REG_YMM10 +ESRC=0xB | OUTREG=XED_REG_YMM11 +ESRC=0xC | OUTREG=XED_REG_YMM12 +ESRC=0xD | OUTREG=XED_REG_YMM13 +ESRC=0xE | OUTREG=XED_REG_YMM14 +ESRC=0xF | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_SE32():: +ESRC=0 | OUTREG=XED_REG_YMM0 enc +ESRC=1 | OUTREG=XED_REG_YMM1 enc +ESRC=2 | OUTREG=XED_REG_YMM2 enc +ESRC=3 | OUTREG=XED_REG_YMM3 enc +ESRC=4 | OUTREG=XED_REG_YMM4 enc +ESRC=5 | OUTREG=XED_REG_YMM5 enc +ESRC=6 | OUTREG=XED_REG_YMM6 enc +ESRC=7 | OUTREG=XED_REG_YMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_YMM0 +ESRC=0x9 | OUTREG=XED_REG_YMM1 +ESRC=0xA | OUTREG=XED_REG_YMM2 +ESRC=0xB | OUTREG=XED_REG_YMM3 +ESRC=0xC | OUTREG=XED_REG_YMM4 +ESRC=0xD | OUTREG=XED_REG_YMM5 +ESRC=0xE | OUTREG=XED_REG_YMM6 +ESRC=0xF | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t XMM_N():: +mode16 | OUTREG=XMM_N_32(): +mode32 | OUTREG=XMM_N_32(): +mode64 | OUTREG=XMM_N_64(): + +xed_reg_enum_t XMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t YMM_N():: +mode16 | OUTREG=YMM_N_32(): +mode32 | OUTREG=YMM_N_32(): +mode64 | OUTREG=YMM_N_64(): + +xed_reg_enum_t YMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_R():: +mode16 | OUTREG=YMM_R_32(): +mode32 | OUTREG=YMM_R_32(): +mode64 | OUTREG=YMM_R_64(): + + +xed_reg_enum_t YMM_R_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + + +xed_reg_enum_t YMM_B():: +mode16 | OUTREG=YMM_B_32(): +mode32 | OUTREG=YMM_B_32(): +mode64 | OUTREG=YMM_B_64(): + + +xed_reg_enum_t YMM_B_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXB=1 RM=7 | OUTREG=XED_REG_YMM15 diff --git a/datafiles/avx/avx-regs.txt b/datafiles/avx/avx-regs.txt new file mode 100644 index 0000000..022dab7 --- /dev/null +++ b/datafiles/avx/avx-regs.txt @@ -0,0 +1,59 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XMM0 xmm 128 YMM0 0 +XMM1 xmm 128 YMM1 1 +XMM2 xmm 128 YMM2 2 +XMM3 xmm 128 YMM3 3 + +XMM4 xmm 128 YMM4 4 +XMM5 xmm 128 YMM5 5 +XMM6 xmm 128 YMM6 6 +XMM7 xmm 128 YMM7 7 + +XMM8 xmm 128 YMM8 8 +XMM9 xmm 128 YMM9 9 +XMM10 xmm 128 YMM10 10 +XMM11 xmm 128 YMM11 11 + +XMM12 xmm 128 YMM12 12 +XMM13 xmm 128 YMM13 13 +XMM14 xmm 128 YMM14 14 +XMM15 xmm 128 YMM15 15 + +YMM0 ymm 256 YMM0 0 +YMM1 ymm 256 YMM1 1 +YMM2 ymm 256 YMM2 2 +YMM3 ymm 256 YMM3 3 +YMM4 ymm 256 YMM4 4 +YMM5 ymm 256 YMM5 5 +YMM6 ymm 256 YMM6 6 +YMM7 ymm 256 YMM7 7 +YMM8 ymm 256 YMM8 8 +YMM9 ymm 256 YMM9 9 +YMM10 ymm 256 YMM10 10 +YMM11 ymm 256 YMM11 11 +YMM12 ymm 256 YMM12 12 +YMM13 ymm 256 YMM13 13 +YMM14 ymm 256 YMM14 14 +YMM15 ymm 256 YMM15 15 + + + + + diff --git a/datafiles/avx/avx-spine.txt b/datafiles/avx/avx-spine.txt new file mode 100644 index 0000000..acbb478 --- /dev/null +++ b/datafiles/avx/avx-spine.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ISA():: +PREFIXES() OSZ_NONTERM() ASZ_NONTERM() AVX_SPLITTER() | + + diff --git a/datafiles/avx/avx-state-bits.txt b/datafiles/avx/avx-state-bits.txt new file mode 100644 index 0000000..7dbd134 --- /dev/null +++ b/datafiles/avx/avx-state-bits.txt @@ -0,0 +1,41 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +VL128 VL=0 +VL256 VL=1 + +VV1 VEXVALID=1 +VV0 VEXVALID=0 + +VMAP0 MAP=0 +V0F MAP=1 +V0F38 MAP=2 +V0F3A MAP=3 + +VNP VEX_PREFIX=0 +V66 VEX_PREFIX=1 +VF2 VEX_PREFIX=2 +VF3 VEX_PREFIX=3 + +# No VEX-SPECIFIED-REGISTER +NOVSR VEXDEST3=0b1 VEXDEST210=0b111 + +EMX_BROADCAST_1TO4_32 BCAST=10 # 128 +EMX_BROADCAST_1TO4_64 BCAST=13 # 256 +EMX_BROADCAST_1TO8_32 BCAST=3 # 256 +EMX_BROADCAST_2TO4_64 BCAST=20 # 256 + diff --git a/datafiles/avx/avx-vex-enc.txt b/datafiles/avx/avx-vex-enc.txt new file mode 100755 index 0000000..fbc9d52 --- /dev/null +++ b/datafiles/avx/avx-vex-enc.txt @@ -0,0 +1,117 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! AVX instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() + +VEXED_REX():: +VEXVALID=0 -> REX_PREFIX_ENC() +VEXVALID=1 -> NEWVEX_ENC() + + +################################################# +SEQUENCE NEWVEX_ENC_BIND + VEX_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + VEX_REXXB_ENC_BIND + VEX_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE NEWVEX_ENC_EMIT + VEX_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + VEX_REXXB_ENC_EMIT + VEX_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + +############################################## +VEX_TYPE_ENC():: +REXX=1 -> 0xC4 VEX_C4=1 +REXB=1 -> 0xC4 VEX_C4=1 +MAP=0 -> 0xC4 VEX_C4=1 +MAP=2 -> 0xC4 VEX_C4=1 +MAP=3 -> 0xC4 VEX_C4=1 +REXW=1 -> 0xC4 VEX_C4=1 +otherwise -> 0xC5 VEX_C4=0 + +VEX_REXR_ENC():: +mode64 REXR=1 -> 0b0 +mode64 REXR=0 -> 0b1 +not64 REXR=1 -> error +not64 REXR=0 -> 0b1 + +VEX_REXXB_ENC():: +mode64 VEX_C4=1 REXX=0 REXB=0 -> 0b11 +mode64 VEX_C4=1 REXX=1 REXB=0 -> 0b01 +mode64 VEX_C4=1 REXX=0 REXB=1 -> 0b10 +mode64 VEX_C4=1 REXX=1 REXB=1 -> 0b00 +not64 VEX_C4=1 REXX=0 REXB=0 -> 0b11 +not64 VEX_C4=1 REXX=1 REXB=0 -> error +not64 VEX_C4=1 REXX=0 REXB=1 -> error +not64 VEX_C4=1 REXX=1 REXB=1 -> error +otherwise -> nothing + +# also emits W + +VEX_MAP_ENC():: +VEX_C4=1 MAP=0 REXW[w] -> 0b0_0000 w +VEX_C4=1 MAP=1 REXW[w] -> 0b0_0001 w +VEX_C4=1 MAP=2 REXW[w] -> 0b0_0010 w +VEX_C4=1 MAP=3 REXW[w] -> 0b0_0011 w +otherwise -> nothing + +# for VEX C5, VEXDEST3 MUST be 1 in 32b mode +VEX_REG_ENC():: +mode64 VEXDEST3[u] VEXDEST210[ddd] -> u_ddd +not64 VEXDEST3[u] VEXDEST210[ddd] -> 1_ddd + + +# FOR VEX'ed instructions, I need to turn off the normal REX prefix +# encoder. Ideally, I could use fields names other than REX{WRXB}, +# but the register lookup functions need those names. I can get away +# with using different names for the f2/f3/66 refining legacy prefixes +# since they are only referenced by the AVX instructions. + +VEX_ESCVL_ENC():: +VL128 VNP -> 0b000 +VL128 V66 -> 0b001 +VL128 VF3 -> 0b010 +VL128 VF2 -> 0b011 +VL256 VNP -> 0b100 +VL256 V66 -> 0b101 +VL256 VF3 -> 0b110 +VL256 VF2 -> 0b111 + + +############################################################################## + diff --git a/datafiles/avx/avx-vex.txt b/datafiles/avx/avx-vex.txt new file mode 100644 index 0000000..f3e09cc --- /dev/null +++ b/datafiles/avx/avx-vex.txt @@ -0,0 +1,28 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# FOR VEX'ed instructions, I need to turn off the normal REX prefix +# encoder. Ideally, I could use fields names other than REX{WRXB}, +# but the register lookup functions need those names. I can get away +# with using different names for the f2/f3/66 refining legacy prefixes +# since they are only referenced by the AVX instructions. + + + + + + diff --git a/datafiles/avx/cpuid.xed.txt b/datafiles/avx/cpuid.xed.txt new file mode 100644 index 0000000..40d795d --- /dev/null +++ b/datafiles/avx/cpuid.xed.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX: avx.1.0.ecx.28 + XED_ISA_SET_AVXAES: aes.1.0.ecx.25 avx.1.0.ecx.28 + XED_ISA_SET_FMA: fma.1.0.ecx.12 avx.1.0.ecx.28 diff --git a/datafiles/avx/files-fma.cfg b/datafiles/avx/files-fma.cfg new file mode 100644 index 0000000..d0c3f1b --- /dev/null +++ b/datafiles/avx/files-fma.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions:avx-fma-isa.txt + enc-instructions:avx-fma-isa.txt + + diff --git a/datafiles/avx/files.cfg b/datafiles/avx/files.cfg new file mode 100644 index 0000000..3956478 --- /dev/null +++ b/datafiles/avx/files.cfg @@ -0,0 +1,49 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + add:dec-spine:avx-spine.txt:2 + dec-instructions:avx-isa.txt + enc-instructions:avx-isa.txt + + dec-instructions:avx-movnt-store.txt + enc-instructions:avx-movnt-store.txt + dec-instructions:avx-aes-isa.txt + enc-instructions:avx-aes-isa.txt + + dec-instructions:avx-pclmul-isa.txt + enc-instructions:avx-pclmul-isa.txt + + state:avx-state-bits.txt + widths:avx-operand-width.txt + pointer-names:avx-pointer-width.txt + registers:avx-regs.txt + dec-patterns:avx-reg-table.txt + enc-dec-patterns:avx-reg-table.txt + fields:avx-fields.txt +# + dec-patterns:avx-isa-supp.txt + enc-patterns:avx-isa-supp-enc.txt +# + dec-patterns:avx-vex.txt + dec-patterns:avx-imm.txt +# + enc-patterns:avx-vex-enc.txt + enc-patterns:avx-imm-enc.txt + +chip-models:avx-chips.txt +cpuid : cpuid.xed.txt + diff --git a/datafiles/avx512-future/avx512-future-chips.txt b/datafiles/avx512-future/avx512-future-chips.txt new file mode 100644 index 0000000..62ea7db --- /dev/null +++ b/datafiles/avx512-future/avx512-future-chips.txt @@ -0,0 +1,28 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX512_FUTURE: ALL_OF(SKYLAKE_SERVER) SHA \ + AVX512IFMA_128 \ + AVX512IFMA_256 \ + AVX512IFMA_512 \ + AVX512VBMI_128 \ + AVX512VBMI_256 \ + AVX512VBMI_512 + + + diff --git a/datafiles/avx512-future/files.cfg b/datafiles/avx512-future/files.cfg new file mode 100644 index 0000000..5a2aeb9 --- /dev/null +++ b/datafiles/avx512-future/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + chip-models:avx512-future-chips.txt diff --git a/datafiles/avx512-skx/cpuid.xed.txt b/datafiles/avx512-skx/cpuid.xed.txt new file mode 100644 index 0000000..eaf26ca --- /dev/null +++ b/datafiles/avx512-skx/cpuid.xed.txt @@ -0,0 +1,29 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512BW_128: avx512bw.7.0.ebx.30 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512BW_128N: avx512bw.7.0.ebx.30 + XED_ISA_SET_AVX512BW_256: avx512bw.7.0.ebx.30 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512BW_512: avx512bw.7.0.ebx.30 + XED_ISA_SET_AVX512BW_KOP: avx512bw.7.0.ebx.30 + + XED_ISA_SET_AVX512DQ_128: avx512dq.7.0.ebx.17 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512DQ_128N: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_256: avx512dq.7.0.ebx.17 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512DQ_512: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_KOP: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_SCALAR: avx512dq.7.0.ebx.17 diff --git a/datafiles/avx512-skx/files.cfg b/datafiles/avx512-skx/files.cfg new file mode 100644 index 0000000..b1ace2f --- /dev/null +++ b/datafiles/avx512-skx/files.cfg @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + state:skx-state-bits.txt + + dec-instructions: skx-isa.xed.txt + enc-instructions: skx-isa.xed.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/avx512-skx/skx-isa.xed.txt b/datafiles/avx512-skx/skx-isa.xed.txt new file mode 100644 index 0000000..491c004 --- /dev/null +++ b/datafiles/avx512-skx/skx-isa.xed.txt @@ -0,0 +1,28055 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-128-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPD (VADDPD-256-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-128-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDPS (VADDPS-256-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-128-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGND (VALIGND-256-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-128-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-256-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-128-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-256-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-512-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-128-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-256-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-512-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VANDPD (VANDPD-128-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-256-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-512-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VANDPS (VANDPS-128-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-256-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-512-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-128-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-256-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-128-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-256-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) +{ +ICLASS: VBROADCASTF32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) +{ +ICLASS: VBROADCASTI32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-128-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-256-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-128-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-256-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-128-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-256-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-128-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-256-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-128-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-256-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-128-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-256-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-512-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-128-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-256-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-128-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-256-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-128-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-256-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-128-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-256-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-128-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-256-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-128-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-256-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-128-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-256-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-128-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-256-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-128-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-256-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-128-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-256-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-128-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-256-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-128-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-256-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-128-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-256-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-128-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-256-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-128-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-256-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-128-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-256-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-128-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-256-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-128-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-256-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-128-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-256-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-128-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-256-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-128-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-256-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-512-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-128-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-256-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-512-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFPCLASSSD (VFPCLASSSD-128-1) +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSSS (VFPCLASSSS-128-1) +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-128-1) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 +IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-256-1) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 +IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-128-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 +IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-256-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 +IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-128-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 +IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-256-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 +IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-128-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:q:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-256-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-128-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-256-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-128-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-256-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-128-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-256-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-128-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-256-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-128-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-256-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-128-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-256-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-128-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPD (VMINPD-256-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-128-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPS (VMINPS-256-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-128-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-256-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-128-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-256-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 +IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-128-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 +IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-256-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 +IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-128-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-256-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 +IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-128-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-256-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 +IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-128-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-256-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-128-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-256-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-128-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPD (VMULPD-256-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-128-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULPS (VMULPS-256-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VORPD (VORPD-128-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VORPD (VORPD-256-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VORPD (VORPD-512-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VORPS (VORPS-128-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VORPS (VORPS-256-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VORPS (VORPS-512-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPABSB (VPABSB-128-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-256-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-512-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 +IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 +IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSD (VPABSD-128-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-256-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-128-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 +IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-256-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 +IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSW (VPABSW-128-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-256-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-512-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 +IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-128-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-256-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-512-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-128-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-256-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-512-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-128-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-256-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-512-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-128-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-256-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-512-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDB (VPADDB-128-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-256-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-512-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDD (VPADDD-128-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDD (VPADDD-256-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-128-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-256-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-128-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-256-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-512-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-128-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-256-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-512-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-128-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-256-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-512-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-128-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-256-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-512-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-128-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-256-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-512-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-128-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-256-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-512-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPANDD (VPANDD-128-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDD (VPANDD-256-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-128-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-256-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-128-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-256-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-128-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-256-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-128-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-256-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-512-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-128-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-256-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-512-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-128-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-256-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-512-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-128-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-256-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-128-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-256-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-128-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-256-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-512-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 +IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 +IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 +IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-128-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-256-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-512-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-128-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-256-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-128-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-256-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-512-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-128-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-256-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-128-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-256-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-128-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-256-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-512-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-128-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-256-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-512-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-128-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-256-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-128-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-256-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-128-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-256-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-512-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-128-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-256-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-128-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-256-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-512-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-128-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-256-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-128-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-256-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-128-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-256-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-512-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-128-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-256-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-512-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-128-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-256-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-256-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-128-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-256-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-128-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-256-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-128-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-256-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-128-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-256-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-128-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-256-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-512-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-256-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-128-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-256-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-128-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-256-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-128-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-256-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-128-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-256-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-128-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-256-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-512-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-128-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-256-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-512-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPEXTRB (VPEXTRB-128-1) +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE +PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +} + + +# EMITTING VPEXTRD (VPEXTRD-128-1) +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +} + + +# EMITTING VPEXTRQ (VPEXTRQ-128-1) +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-1) +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD +PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-2) +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-128-1) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 +IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-256-1) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 +IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-128-1) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 +IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-256-1) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 +IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-128-1) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:q:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-256-1) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-128-1) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 +IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-256-1) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 +IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPINSRB (VPINSRB-128-1) +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +} + +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_BYTE +PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPINSRD (VPINSRD-128-1) +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +} + +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPINSRQ (VPINSRQ-128-1) +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +} + +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPINSRW (VPINSRW-128-1) +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +} + +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_WORD +PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-128-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-256-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-128-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-256-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-128-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-256-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-512-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-128-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-256-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-512-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-128-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-256-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-512-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-128-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-256-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-128-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-256-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-128-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-256-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-512-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-128-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-256-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-512-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-128-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-256-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-128-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-256-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-128-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-256-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-512-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-128-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-256-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-512-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-128-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-256-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-128-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-256-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-128-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-256-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-512-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-128-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-256-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-512-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-128-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-256-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-128-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-256-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-128-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-256-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-512-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-128-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 +IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-256-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 +IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-512-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 +IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-128-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 +IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-256-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 +IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-512-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 +IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-128-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-256-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-512-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-128-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-256-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-512-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-128-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-256-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-512-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-128-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-256-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-512-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-128-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 +IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-256-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 +IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-512-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 +IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-128-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-256-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-128-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-256-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-512-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-128-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-256-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-128-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 +IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-256-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 +IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-512-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 +IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-128-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-256-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-128-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-256-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-512-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-128-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-256-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-128-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-256-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-128-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-256-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-512-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-128-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-256-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-512-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-128-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-256-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-512-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-128-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-256-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-128-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-256-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-512-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-128-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-256-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-512-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-128-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-256-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-128-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-256-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-128-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPORQ (VPORQ-256-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-128-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLD (VPROLD-256-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-128-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-256-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-128-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-256-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-128-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-256-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-128-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORD (VPRORD-256-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-128-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-256-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-128-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-256-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-128-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-256-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-128-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-256-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-512-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 +IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-128-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-256-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-128-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-256-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSHUFB (VPSHUFB-128-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-256-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-512-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-128-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-256-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-128-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-256-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-512-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-128-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-256-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-512-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-128-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-256-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-512-1) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-128-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-256-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-128-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-256-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-128-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-256-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-512-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-2) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-128-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-256-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-128-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-256-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-128-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-256-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-512-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-128-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-256-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-512-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-128-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-256-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-128-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-256-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-128-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-256-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-512-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-128-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-256-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-512-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-128-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-256-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-128-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-256-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-128-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-256-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-512-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-128-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-256-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-512-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-128-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-256-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-512-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-128-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-256-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-512-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-128-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-256-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-512-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-128-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-256-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-128-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-256-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-512-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-128-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-256-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-128-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-256-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-128-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-256-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-512-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-128-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-256-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-512-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-128-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-256-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-128-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-256-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-128-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-256-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-512-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPXORD (VPXORD-128-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORD (VPXORD-256-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-128-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-256-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-128-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-256-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-512-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-128-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-256-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-512-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGESD (VRANGESD-128-1) +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGESS (VRANGESS-128-1) +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-128-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-256-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-128-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-256-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-128-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-256-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-512-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-128-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-256-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-512-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCESD (VREDUCESD-128-1) +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCESS (VREDUCESS-128-1) +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-128-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-256-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-128-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-256-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-128-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-256-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-128-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-256-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-128-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-256-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-128-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-256-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-128-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-256-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-128-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-256-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-128-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-256-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-128-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-256-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-128-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-256-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-128-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-256-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-128-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-256-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-128-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-256-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-128-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-256-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-128-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-256-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-128-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-256-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-128-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-256-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VXORPD (VXORPD-128-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-256-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-512-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VXORPS (VXORPS-128-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-256-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-512-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KADDB (KADDB-256-1) +{ +ICLASS: KADDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDD (KADDD-256-1) +{ +ICLASS: KADDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDQ (KADDQ-256-1) +{ +ICLASS: KADDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDW (KADDW-256-1) +{ +ICLASS: KADDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDB (KANDB-256-1) +{ +ICLASS: KANDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDD (KANDD-256-1) +{ +ICLASS: KANDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNB (KANDNB-256-1) +{ +ICLASS: KANDNB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDND (KANDND-256-1) +{ +ICLASS: KANDND +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNQ (KANDNQ-256-1) +{ +ICLASS: KANDNQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDQ (KANDQ-256-1) +{ +ICLASS: KANDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-1) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 +IFORM: KMOVB_MASKmskw_MASKu8_AVX512 +} + +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 +IFORM: KMOVB_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-2) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw +IFORM: KMOVB_MEMu8_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-3) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-4) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-1) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 +IFORM: KMOVD_MASKmskw_MASKu32_AVX512 +} + +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 +IFORM: KMOVD_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-2) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw +IFORM: KMOVD_MEMu32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-3) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-4) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-1) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 +IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 +} + +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 +IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-2) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR +OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw +IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-3) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 +IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-4) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw +IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 +} + + +# EMITTING KNOTB (KNOTB-128-1) +{ +ICLASS: KNOTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTD (KNOTD-128-1) +{ +ICLASS: KNOTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTQ (KNOTQ-128-1) +{ +ICLASS: KNOTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORB (KORB-256-1) +{ +ICLASS: KORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORD (KORD-256-1) +{ +ICLASS: KORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORQ (KORQ-256-1) +{ +ICLASS: KORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTB (KORTESTB-128-1) +{ +ICLASS: KORTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTD (KORTESTD-128-1) +{ +ICLASS: KORTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTQ (KORTESTQ-128-1) +{ +ICLASS: KORTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLB (KSHIFTLB-128-1) +{ +ICLASS: KSHIFTLB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLD (KSHIFTLD-128-1) +{ +ICLASS: KSHIFTLD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLQ (KSHIFTLQ-128-1) +{ +ICLASS: KSHIFTLQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRB (KSHIFTRB-128-1) +{ +ICLASS: KSHIFTRB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRD (KSHIFTRD-128-1) +{ +ICLASS: KSHIFTRD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRQ (KSHIFTRQ-128-1) +{ +ICLASS: KSHIFTRQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KTESTB (KTESTB-128-1) +{ +ICLASS: KTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTD (KTESTD-128-1) +{ +ICLASS: KTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTQ (KTESTQ-128-1) +{ +ICLASS: KTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTW (KTESTW-128-1) +{ +ICLASS: KTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKDQ (KUNPCKDQ-256-1) +{ +ICLASS: KUNPCKDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKWD (KUNPCKWD-256-1) +{ +ICLASS: KUNPCKWD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORB (KXNORB-256-1) +{ +ICLASS: KXNORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORD (KXNORD-256-1) +{ +ICLASS: KXNORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORQ (KXNORQ-256-1) +{ +ICLASS: KXNORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORB (KXORB-256-1) +{ +ICLASS: KXORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORD (KXORD-256-1) +{ +ICLASS: KXORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORQ (KXORQ-256-1) +{ +ICLASS: KXORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + diff --git a/datafiles/avx512-skx/skx-state-bits.txt b/datafiles/avx512-skx/skx-state-bits.txt new file mode 100644 index 0000000..ca6aedc --- /dev/null +++ b/datafiles/avx512-skx/skx-state-bits.txt @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +EMX_BROADCAST_1TO2_8 BCAST=23 +EMX_BROADCAST_1TO4_8 BCAST=24 +EMX_BROADCAST_1TO8_8 BCAST=25 + +EMX_BROADCAST_1TO2_16 BCAST=26 +EMX_BROADCAST_1TO4_16 BCAST=27 diff --git a/datafiles/avx512cd/cpuid.xed.txt b/datafiles/avx512cd/cpuid.xed.txt new file mode 100644 index 0000000..2cbf211 --- /dev/null +++ b/datafiles/avx512cd/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512CD_128: avx512cd.7.0.ebx.28 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512CD_256: avx512cd.7.0.ebx.28 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512CD_512: avx512cd.7.0.ebx.28 diff --git a/datafiles/avx512cd/files.cfg b/datafiles/avx512cd/files.cfg new file mode 100644 index 0000000..f4e1f01 --- /dev/null +++ b/datafiles/avx512cd/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: vconflict-isa.xed.txt + enc-instructions: vconflict-isa.xed.txt + + + + cpuid : cpuid.xed.txt + diff --git a/datafiles/avx512cd/vconflict-isa.xed.txt b/datafiles/avx512cd/vconflict-isa.xed.txt new file mode 100644 index 0000000..a1fba37 --- /dev/null +++ b/datafiles/avx512cd/vconflict-isa.xed.txt @@ -0,0 +1,177 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 +IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-512-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + +# EMITTING VPLZCNTD (VPLZCNTD-512-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-512-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + diff --git a/datafiles/avx512f/avx-pointer-width.txt b/datafiles/avx512f/avx-pointer-width.txt new file mode 100644 index 0000000..a079610 --- /dev/null +++ b/datafiles/avx512f/avx-pointer-width.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +32 ymmword y diff --git a/datafiles/avx512f/avx512-addressing-dec.txt b/datafiles/avx512f/avx512-addressing-dec.txt new file mode 100644 index 0000000..0b12d15 --- /dev/null +++ b/datafiles/avx512f/avx512-addressing-dec.txt @@ -0,0 +1,189 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +UISA_VMODRM_ZMM():: + MOD=0b00 UISA_VSIB_ZMM() | + MOD=0b01 UISA_VSIB_ZMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_ZMM() MEMDISP32() | + +UISA_VMODRM_YMM():: + MOD=0b00 UISA_VSIB_YMM() | + MOD=0b01 UISA_VSIB_YMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_YMM() MEMDISP32() | + +UISA_VMODRM_XMM():: + MOD=0b00 UISA_VSIB_XMM() | + MOD=0b01 UISA_VSIB_XMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_XMM() MEMDISP32() | + + +UISA_VSIB_ZMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=8 +UISA_VSIB_YMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=8 +UISA_VSIB_XMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=8 + + +xed_reg_enum_t UISA_VSIB_INDEX_ZMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM31 + + + +xed_reg_enum_t UISA_VSIB_INDEX_YMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM31 + + +xed_reg_enum_t UISA_VSIB_INDEX_XMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM31 + + +UISA_VSIB_BASE():: +REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG() + + + + + + + + diff --git a/datafiles/avx512f/avx512-addressing-enc.txt b/datafiles/avx512f/avx512-addressing-enc.txt new file mode 100644 index 0000000..e2c9c29 --- /dev/null +++ b/datafiles/avx512f/avx512-addressing-enc.txt @@ -0,0 +1,167 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SEQUENCE UISA_VMODRM_ZMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_ZMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA +SEQUENCE UISA_VMODRM_YMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_YMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA +SEQUENCE UISA_VMODRM_XMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_XMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA + +# For now, ignoring the difference in x/y/zmm for the index register. Could +# split these. +SEQUENCE UISA_VMODRM_ZMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() +SEQUENCE UISA_VMODRM_YMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() +SEQUENCE UISA_VMODRM_XMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +###################################### + + + +UISA_ENC_INDEX_ZMM():: +INDEX=XED_REG_ZMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_ZMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_ZMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_ZMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_ZMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_ZMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_ZMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_ZMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_ZMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_ZMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_ZMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_ZMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_ZMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_ZMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_ZMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_ZMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_ZMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_ZMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_ZMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_ZMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_ZMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_ZMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_ZMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_ZMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_ZMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_ZMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_ZMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_ZMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_ZMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_ZMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_ZMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_ZMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 +UISA_ENC_INDEX_YMM():: +INDEX=XED_REG_YMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_YMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 +UISA_ENC_INDEX_XMM():: +INDEX=XED_REG_XMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_XMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 + + + + + + + diff --git a/datafiles/avx512f/avx512-disp8-enc.txt b/datafiles/avx512f/avx512-disp8-enc.txt new file mode 100644 index 0000000..88bccff --- /dev/null +++ b/datafiles/avx512f/avx512-disp8-enc.txt @@ -0,0 +1,119 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ESIZE_128_BITS():: +otherwise -> nothing +ESIZE_64_BITS():: +otherwise -> nothing +ESIZE_32_BITS():: +otherwise -> nothing +ESIZE_16_BITS():: +otherwise -> nothing +ESIZE_8_BITS():: +otherwise -> nothing +ESIZE_4_BITS():: +otherwise -> nothing +ESIZE_2_BITS():: +otherwise -> nothing +ESIZE_1_BITS():: +otherwise -> nothing + +NELEM_MOVDDUP():: +otherwise -> nothing +NELEM_FULLMEM():: +otherwise -> nothing + +NELEM_HALFMEM():: +otherwise -> nothing + +NELEM_QUARTERMEM():: +otherwise -> nothing + +NELEM_EIGHTHMEM():: +otherwise -> nothing + +NELEM_GPR_READER_BYTE():: +otherwise -> nothing +NELEM_GPR_READER_WORD():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP_D():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP_Q():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_BYTE():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_WORD():: +otherwise -> nothing +NELEM_TUPLE1_BYTE():: +otherwise -> nothing +NELEM_TUPLE1_WORD():: +otherwise -> nothing + +NELEM_SCALAR():: +otherwise -> nothing +NELEM_TUPLE1_SUBDWORD():: +otherwise -> nothing +NELEM_GPR_READER():: +otherwise -> nothing +NELEM_GPR_READER_SUBDWORD():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_SUBDWORD():: +otherwise -> nothing + +NELEM_MEM128():: +BCAST!=0 -> error +otherwise -> BCRC=0 + +# TUPLE1,2,4,8, FULL and HALF + +NELEM_TUPLE1():: +otherwise -> nothing + +NELEM_GSCAT():: +otherwise -> nothing + +NELEM_TUPLE2():: +otherwise -> nothing + +NELEM_TUPLE4():: +otherwise -> nothing + +NELEM_TUPLE8():: +otherwise -> nothing + +# these have broadcasting + +NELEM_FULL():: +BCAST!=0 -> BCRC=1 +otherwise -> BCRC=0 + +NELEM_HALF():: +BCAST!=0 -> BCRC=1 +otherwise -> BCRC=0 + +FIX_ROUND_LEN512():: +otherwise -> nothing +FIX_ROUND_LEN128():: +otherwise -> nothing + + + + diff --git a/datafiles/avx512f/avx512-disp8.txt b/datafiles/avx512f/avx512-disp8.txt new file mode 100644 index 0000000..5fb1345 --- /dev/null +++ b/datafiles/avx512f/avx512-disp8.txt @@ -0,0 +1,331 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#The "MEM" suffix on tuples means NO BROADCAST ALLOWED + +# SET THE ELEMENT SIZE DURING DECODE -- using spreadsheet InputSize field +# FIXME: fix and use 'otherwise' instead of REX=0! +ESIZE_128_BITS():: +REX=0 | ELEMENT_SIZE=128 +ESIZE_64_BITS():: +REX=0 | ELEMENT_SIZE=64 +ESIZE_32_BITS():: +REX=0 | ELEMENT_SIZE=32 +ESIZE_16_BITS():: +REX=0 | ELEMENT_SIZE=16 +ESIZE_8_BITS():: +REX=0 | ELEMENT_SIZE=8 +ESIZE_4_BITS():: +REX=0 | ELEMENT_SIZE=4 +ESIZE_2_BITS():: +REX=0 | ELEMENT_SIZE=2 +ESIZE_1_BITS():: +REX=0 | ELEMENT_SIZE=1 + +# eightmem is a 8B reference +# quartermem is a 16B reference +# halfmem is a 32B reference +# fullmem is a 64B reference + +# legacy movddup references 64b when doing a 128b VL +# but acts like fullmem for 256/512. +NELEM_MOVDDUP():: +ELEMENT_SIZE=64 VL128 | NELEM=1 +ELEMENT_SIZE=64 VL256 | NELEM=4 +ELEMENT_SIZE=64 VL512 | NELEM=8 + +# element size is in bits... +NELEM_FULLMEM():: # updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=512 +ELEMENT_SIZE=2 VL512 | NELEM=256 +ELEMENT_SIZE=4 VL512 | NELEM=128 +ELEMENT_SIZE=8 VL512 | NELEM=64 +ELEMENT_SIZE=16 VL512 | NELEM=32 +ELEMENT_SIZE=32 VL512 | NELEM=16 +ELEMENT_SIZE=64 VL512 | NELEM=8 +ELEMENT_SIZE=128 VL512 | NELEM=4 +ELEMENT_SIZE=256 VL512 | NELEM=2 +ELEMENT_SIZE=512 VL512 | NELEM=1 + +ELEMENT_SIZE=1 VL256 | NELEM=256 +ELEMENT_SIZE=2 VL256 | NELEM=128 +ELEMENT_SIZE=4 VL256 | NELEM=64 +ELEMENT_SIZE=8 VL256 | NELEM=32 +ELEMENT_SIZE=16 VL256 | NELEM=16 +ELEMENT_SIZE=32 VL256 | NELEM=8 +ELEMENT_SIZE=64 VL256 | NELEM=4 +ELEMENT_SIZE=128 VL256 | NELEM=2 +ELEMENT_SIZE=256 VL256 | NELEM=1 +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=128 +ELEMENT_SIZE=2 VL128 | NELEM=64 +ELEMENT_SIZE=4 VL128 | NELEM=32 +ELEMENT_SIZE=8 VL128 | NELEM=16 +ELEMENT_SIZE=16 VL128 | NELEM=8 +ELEMENT_SIZE=32 VL128 | NELEM=4 +ELEMENT_SIZE=64 VL128 | NELEM=2 +ELEMENT_SIZE=128 VL128 | NELEM=1 +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + +NELEM_HALFMEM():: # 32B/256b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=256 +ELEMENT_SIZE=2 VL512 | NELEM=128 +ELEMENT_SIZE=4 VL512 | NELEM=64 +ELEMENT_SIZE=8 VL512 | NELEM=32 +ELEMENT_SIZE=16 VL512 | NELEM=16 +ELEMENT_SIZE=32 VL512 | NELEM=8 +ELEMENT_SIZE=64 VL512 | NELEM=4 +ELEMENT_SIZE=128 VL512 | NELEM=2 +ELEMENT_SIZE=256 VL512 | NELEM=1 +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=128 +ELEMENT_SIZE=2 VL256 | NELEM=64 +ELEMENT_SIZE=4 VL256 | NELEM=32 +ELEMENT_SIZE=8 VL256 | NELEM=16 +ELEMENT_SIZE=16 VL256 | NELEM=8 +ELEMENT_SIZE=32 VL256 | NELEM=4 +ELEMENT_SIZE=64 VL256 | NELEM=2 +ELEMENT_SIZE=128 VL256 | NELEM=1 +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=64 +ELEMENT_SIZE=2 VL128 | NELEM=32 +ELEMENT_SIZE=4 VL128 | NELEM=16 +ELEMENT_SIZE=8 VL128 | NELEM=8 +ELEMENT_SIZE=16 VL128 | NELEM=4 +ELEMENT_SIZE=32 VL128 | NELEM=2 +ELEMENT_SIZE=64 VL128 | NELEM=1 +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + + +NELEM_QUARTERMEM():: # 16B/128b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=128 +ELEMENT_SIZE=2 VL512 | NELEM=64 +ELEMENT_SIZE=4 VL512 | NELEM=32 +ELEMENT_SIZE=8 VL512 | NELEM=16 +ELEMENT_SIZE=16 VL512 | NELEM=8 +ELEMENT_SIZE=32 VL512 | NELEM=4 +ELEMENT_SIZE=64 VL512 | NELEM=2 +ELEMENT_SIZE=128 VL512 | NELEM=1 +ELEMENT_SIZE=256 VL512 | error +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=64 +ELEMENT_SIZE=2 VL256 | NELEM=32 +ELEMENT_SIZE=4 VL256 | NELEM=16 +ELEMENT_SIZE=8 VL256 | NELEM=8 +ELEMENT_SIZE=16 VL256 | NELEM=4 +ELEMENT_SIZE=32 VL256 | NELEM=2 +ELEMENT_SIZE=64 VL256 | NELEM=1 +ELEMENT_SIZE=128 VL256 | error +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=32 +ELEMENT_SIZE=2 VL128 | NELEM=16 +ELEMENT_SIZE=4 VL128 | NELEM=8 +ELEMENT_SIZE=8 VL128 | NELEM=4 +ELEMENT_SIZE=16 VL128 | NELEM=2 +ELEMENT_SIZE=32 VL128 | NELEM=1 +ELEMENT_SIZE=64 VL128 | error +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + + +NELEM_EIGHTHMEM():: # 8B/64b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=64 +ELEMENT_SIZE=2 VL512 | NELEM=32 +ELEMENT_SIZE=4 VL512 | NELEM=16 +ELEMENT_SIZE=8 VL512 | NELEM=8 +ELEMENT_SIZE=16 VL512 | NELEM=4 +ELEMENT_SIZE=32 VL512 | NELEM=2 +ELEMENT_SIZE=64 VL512 | NELEM=1 +ELEMENT_SIZE=128 VL512 | error +ELEMENT_SIZE=256 VL512 | error +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=32 +ELEMENT_SIZE=2 VL256 | NELEM=16 +ELEMENT_SIZE=4 VL256 | NELEM=8 +ELEMENT_SIZE=8 VL256 | NELEM=4 +ELEMENT_SIZE=16 VL256 | NELEM=2 +ELEMENT_SIZE=32 VL256 | NELEM=1 +ELEMENT_SIZE=64 VL256 | error +ELEMENT_SIZE=128 VL256 | error +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=16 +ELEMENT_SIZE=2 VL128 | NELEM=8 +ELEMENT_SIZE=4 VL128 | NELEM=4 +ELEMENT_SIZE=8 VL128 | NELEM=2 +ELEMENT_SIZE=16 VL128 | NELEM=1 +ELEMENT_SIZE=32 VL128 | error +ELEMENT_SIZE=64 VL128 | error +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + +NELEM_GPR_READER_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP_D():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP_Q():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + +NELEM_SCALAR():: # same as tuple1 updated 2011-02-18 +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + + +# TUPLE1,2,4,8, FULL and HALF + +NELEM_TUPLE1():: #updated 2011-02-18 +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GSCAT():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + + +NELEM_TUPLE2():: #updated 2011-02-18 +VL128 | NELEM=2 +VL256 | NELEM=2 +VL512 | NELEM=2 + +NELEM_TUPLE4():: #updated 2011-02-18 +VL128 | NELEM=4 +VL256 | NELEM=4 +VL512 | NELEM=4 + +NELEM_TUPLE8():: # updated 2011-02-18 +VL128 | NELEM=8 +VL256 | NELEM=8 +VL512 | NELEM=8 + +NELEM_MEM128():: # element_size=64 always!! SPECIAL updated 2011-02-18 +BCRC=0b0 | ELEMENT_SIZE=64 NELEM=2 +BCRC=0b1 | error + + +NELEM_FULL():: +BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=32 +BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO32_16 +BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=16 +BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO16_32 +BCRC=0b0 ELEMENT_SIZE=64 VL512 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=64 VL512 | NELEM=1 EMX_BROADCAST_1TO8_64 + +BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=16 +BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO16_16 +BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO8_32 +BCRC=0b0 ELEMENT_SIZE=64 VL256 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=64 VL256 | NELEM=1 EMX_BROADCAST_1TO4_64 + +BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO8_16 +BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO4_32 +BCRC=0b0 ELEMENT_SIZE=64 VL128 | NELEM=2 +BCRC=0b1 ELEMENT_SIZE=64 VL128 | NELEM=1 EMX_BROADCAST_1TO2_64 + + +# 512b=64B=16DW=8QW -> Half = 256b=32B=8DWORDS=4QWORDS +# 256b=32B=8DW=4QW -> Half = 128b=16B=4DW=2QW +# 128b=16B=4DW=2QW -> Half = 64b=8B=2DW=1QW +NELEM_HALF():: # updated 2011-02-18 +BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO8_32 + +BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO4_32 + +BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=2 +BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO2_32 + + +# For reg/reg ops with rounding control, we have to avoid having the +# RC bits mes up the length. So we fix them here. +FIX_ROUND_LEN512():: +mode16 | VL512 +mode32 | VL512 +mode64 | VL512 +FIX_ROUND_LEN128():: +mode16 | VL128 +mode32 | VL128 +mode64 | VL128 diff --git a/datafiles/avx512f/avx512-evex-dec.txt b/datafiles/avx512f/avx512-evex-dec.txt new file mode 100644 index 0000000..c4ad71b --- /dev/null +++ b/datafiles/avx512f/avx512-evex-dec.txt @@ -0,0 +1,46 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX512_ROUND():: +LLRC=0b00 | ROUNDC=1 SAE=1 +LLRC=0b01 | ROUNDC=2 SAE=1 +LLRC=0b10 | ROUNDC=3 SAE=1 +LLRC=0b11 | ROUNDC=4 SAE=1 + +SAE():: +BCRC=1 | SAE=1 +BCRC=0 | error + +# NEWKEY: VEXPFX_OP == 0x62 +# NEWKEY: MBITS --> REXR, REXX (complemented MBITS) +# NEWKEY: BRR -> REXB, REXRR (complemented BRR bits) +# NEWKEY: EVMAP -> V0F, V0F38, V0F3A or error +# NEWKEY: REXW +# NEWKEY: VEXDEST3 +# NEWKEY: VEXDEST210 +# NEWKEY: UBIT +# NEWKEY: VEXPP_OP -> VNP/V66/VF3/VF2 recoding +# NEWKEY: confirm no refining prefix or rex prefix +# NEWKEY: set VEXVALID=2 +# NEWKEY: ZEROING[z] +# NEWKEY: LLRCDECODE()-> LLRC -> VL128,256,512 or error +# NEWKEY: BCRC[b] +# NEWKEY: VEXDEST4P[p] +# NEWKEY: VEXDEST4_INVERT() <<<< invert VEXDEST4 +# NEWKEY: MASK[aaa] + diff --git a/datafiles/avx512f/avx512-evex-enc.txt b/datafiles/avx512f/avx512-evex-enc.txt new file mode 100644 index 0000000..78cc604 --- /dev/null +++ b/datafiles/avx512f/avx512-evex-enc.txt @@ -0,0 +1,162 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! GSSE instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() + +VEXED_REX():: +VEXVALID=2 -> EVEX_ENC() + + +################################################# +SEQUENCE EVEX_ENC_BIND + # R,X,B R map(mmm) (byte 1) + # W, vvvv, U, pp (byte 2) + # z, LL/RC, b V', aaa ( byte 3) + EVEX_62_REXR_ENC_BIND + EVEX_REXX_ENC_BIND + EVEX_REXB_ENC_BIND + EVEX_REXRR_ENC_BIND + EVEX_MAP_ENC_BIND + EVEX_REXW_VVVV_ENC_BIND + EVEX_UPP_ENC_BIND + EVEX_LL_ENC_BIND + AVX512_EVEX_BYTE3_ENC_BIND + + +SEQUENCE EVEX_ENC_EMIT + EVEX_62_REXR_ENC_EMIT + EVEX_REXX_ENC_EMIT + EVEX_REXB_ENC_EMIT + EVEX_REXRR_ENC_EMIT + EVEX_MAP_ENC_EMIT + EVEX_REXW_VVVV_ENC_EMIT + EVEX_UPP_ENC_EMIT + EVEX_LL_ENC_EMIT + AVX512_EVEX_BYTE3_ENC_EMIT + + +EVEX_62_REXR_ENC():: +mode64 REXR=1 -> 0x62 0b0 +mode64 REXR=0 -> 0x62 0b1 +mode32 REXR=1 -> error +mode32 REXR=0 -> 0x62 0b1 + +EVEX_REXX_ENC():: +mode64 REXX=1 -> 0b0 +mode64 REXX=0 -> 0b1 +mode32 REXX=1 -> error +mode32 REXX=0 -> 0b1 + +EVEX_REXB_ENC():: +mode64 REXB=1 -> 0b0 +mode64 REXB=0 -> 0b1 +mode32 REXB=1 -> error +mode32 REXB=0 -> 0b1 + +EVEX_REXRR_ENC():: +mode64 REXRR=1 -> 0b0 +mode64 REXRR=0 -> 0b1 +mode32 REXRR=1 -> error +mode32 REXRR=0 -> 0b1 + +EVEX_MAP_ENC():: +MAP=0 -> 0b0000 +MAP=1 -> 0b0001 +MAP=2 -> 0b0010 +MAP=3 -> 0b0011 + +EVEX_REXW_VVVV_ENC():: +true REXW[w] VEXDEST3[u] VEXDEST210[ddd] -> w u_ddd + +# emit the EVEX.U=1 with the EVEX.pp field +EVEX_UPP_ENC():: +VNP -> 0b100 +V66 -> 0b101 +VF3 -> 0b110 +VF2 -> 0b111 + +EVEX_LL_ENC():: +ROUNDC=0 SAE=0 VL128 -> LLRC=0 +ROUNDC=0 SAE=0 VL256 -> LLRC=1 +ROUNDC=0 SAE=0 VL512 -> LLRC=2 + +# scalars (XED has scalars as VL128) +ROUNDC=0 SAE=1 VL128 -> LLRC=0 BCRC=1 # sae only, no rounding +ROUNDC=1 SAE=1 VL128 -> LLRC=0 BCRC=1 # rounding only supported with sae +ROUNDC=2 SAE=1 VL128 -> LLRC=1 BCRC=1 # rounding only supported with sae +ROUNDC=3 SAE=1 VL128 -> LLRC=2 BCRC=1 # rounding only supported with sae +ROUNDC=4 SAE=1 VL128 -> LLRC=3 BCRC=1 # rounding only supported with sae + +# everything else (must be VL512) +ROUNDC=0 SAE=1 VL512 -> LLRC=0 BCRC=1 # sae only, no rounding +ROUNDC=1 SAE=1 VL512 -> LLRC=0 BCRC=1 # rounding only supported with sae +ROUNDC=2 SAE=1 VL512 -> LLRC=1 BCRC=1 # rounding only supported with sae +ROUNDC=3 SAE=1 VL512 -> LLRC=2 BCRC=1 # rounding only supported with sae +ROUNDC=4 SAE=1 VL512 -> LLRC=3 BCRC=1 # rounding only supported with sae + + +AVX512_EVEX_BYTE3_ENC():: +ZEROING[z] LLRC[nn] BCRC[b] VEXDEST4=0 MASK[aaa] -> z_nn_b 0b1 aaa +ZEROING[z] LLRC[nn] BCRC[b] VEXDEST4=1 MASK[aaa] -> z_nn_b 0b0 aaa + + + +################################################# +SEQUENCE NEWVEX3_ENC_BIND + VEX_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + VEX_REXXB_ENC_BIND + VEX_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE NEWVEX3_ENC_EMIT + VEX_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + VEX_REXXB_ENC_EMIT + VEX_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + + + +############################################################################## + +AVX512_ROUND():: +ROUNDC=1 -> LLRC=0 BCRC=1 +ROUNDC=2 -> LLRC=1 BCRC=1 +ROUNDC=3 -> LLRC=2 BCRC=1 +ROUNDC=4 -> LLRC=3 BCRC=1 + +SAE():: +SAE=1 -> BCRC=1 +SAE=0 -> BCRC=0 diff --git a/datafiles/avx512f/avx512-fields.txt b/datafiles/avx512f/avx512-fields.txt new file mode 100644 index 0000000..492b6d1 --- /dev/null +++ b/datafiles/avx512f/avx512-fields.txt @@ -0,0 +1,38 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +ZEROING SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +LLRC SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +BCRC SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +REXRR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +VEXDEST4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +MASK SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +ROUNDC SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EI +SAE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + +# this is required for KNC's disp8 C-code override file +# (for their unaligned memop support). +NO_SCALE_DISP8 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +EVEXRR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +UBIT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + + diff --git a/datafiles/avx512f/avx512-foundation-isa.xed.txt b/datafiles/avx512f/avx512-foundation-isa.xed.txt new file mode 100644 index 0000000..a5d1692 --- /dev/null +++ b/datafiles/avx512f/avx512-foundation-isa.xed.txt @@ -0,0 +1,13469 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-512-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-512-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDSD (VADDSD-128-1) +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDSS (VADDSS-128-1) +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-512-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-512-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-512-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-512-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) +{ +ICLASS: VBROADCASTF64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) +{ +ICLASS: VBROADCASTI64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-512-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-512-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPSD (VCMPSD-128-1) +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPSS (VCMPSS-128-1) +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMISD (VCOMISD-128-1) +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCOMISS (VCOMISS-128-1) +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-512-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-512-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-512-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-1) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-2) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SS (VCVTSD2SS-128-1) +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-1) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-2) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-1) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-2) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-1) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-2) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 +} + + +# EMITTING VCVTSS2SD (VCVTSS2SD-128-1) +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-1) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-2) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-1) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-2) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-512-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-512-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVSD (VDIVSD-128-1) +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVSS (VDIVSS-128-1) +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTPS (VEXTRACTPS-128-1) +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-512-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-512-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132SD (VFMADD132SD-128-1) +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132SS (VFMADD132SS-128-1) +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-512-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-512-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213SD (VFMADD213SD-128-1) +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213SS (VFMADD213SS-128-1) +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-512-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-512-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231SD (VFMADD231SD-128-1) +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231SS (VFMADD231SS-128-1) +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-512-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-512-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132SD (VFMSUB132SD-128-1) +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132SS (VFMSUB132SS-128-1) +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-512-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-512-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213SD (VFMSUB213SD-128-1) +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213SS (VFMSUB213SS-128-1) +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-512-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-512-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231SD (VFMSUB231SD-128-1) +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231SS (VFMSUB231SS-128-1) +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-512-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-512-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132SD (VFNMADD132SD-128-1) +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132SS (VFNMADD132SS-128-1) +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-512-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-512-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213SD (VFNMADD213SD-128-1) +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213SS (VFNMADD213SS-128-1) +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-512-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-512-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231SD (VFNMADD231SD-128-1) +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231SS (VFNMADD231SS-128-1) +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-512-1) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 +IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-512-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f32 +IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-512-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 +IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-512-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 +IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-512-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-512-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPSD (VGETEXPSD-128-1) +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VGETEXPSS (VGETEXPSS-128-1) +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-512-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-512-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTSD (VGETMANTSD-128-1) +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTSS (VGETMANTSS-128-1) +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTPS (VINSERTPS-128-1) +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1 +PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-512-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-512-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXSD (VMAXSD-128-1) +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXSS (VMAXSS-128-1) +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-512-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-512-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINSD (VMINSD-128-1) +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINSS (VMINSS-128-1) +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-1) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-2) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-512-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVHLPS (VMOVHLPS-128-1) +{ +ICLASS: VMOVHLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 +IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-1) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 +IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-2) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-1) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 +IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-2) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLHPS (VMOVLHPS-128-1) +{ +ICLASS: VMOVLHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 +IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-1) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-2) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 +IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-1) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 +IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-2) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 +IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-512-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 +IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-512-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 +IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-512-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 +IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-512-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 +IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-1) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 +IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-2) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-3) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-4) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-1) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-2) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-3) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-4) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-512-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-512-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-1) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-2) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-3) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-4) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-512-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-512-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULSD (VMULSD-128-1) +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULSS (VMULSS-128-1) +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-512-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-512-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 +IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPADDD (VPADDD-512-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-512-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDD (VPANDD-512-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-512-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-512-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-512-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-512-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-512-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 mode64 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-512-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-512-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-512-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-512-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-512-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-512-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-512-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-512-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-512-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-512-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-512-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-512-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-512-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-512-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-512-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-512-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-512-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-512-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-512-1) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u32 +IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-512-1) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 +IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-512-1) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 +IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-512-1) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 +IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPMAXSD (VPMAXSD-512-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-512-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-512-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-512-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-512-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-512-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-512-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-512-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-512-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-512-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-512-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-512-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-512-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-512-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-512-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-512-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-512-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-512-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-512-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-512-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-512-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-512-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-512-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-512-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-512-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-512-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-512-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSHUFD (VPSHUFD-512-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-2) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-2) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-512-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-512-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-2) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-512-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-512-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-512-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-512-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-512-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-512-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-512-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-512-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-512-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-512-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-512-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORD (VPXORD-512-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-512-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-512-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-512-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14SD (VRCP14SD-128-1) +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRCP14SS (VRCP14SS-128-1) +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESD (VRNDSCALESD-128-1) +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESS (VRNDSCALESS-128-1) +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-512-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-512-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14SD (VRSQRT14SD-128-1) +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14SS (VRSQRT14SS-128-1) +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-512-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-512-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFSD (VSCALEFSD-128-1) +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFSS (VSCALEFSS-128-1) +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-512-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-512-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-512-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-512-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-512-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-512-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-512-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-512-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTSD (VSQRTSD-128-1) +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSQRTSS (VSQRTSS-128-1) +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-512-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-512-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBSD (VSUBSD-128-1) +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBSS (VSUBSS-128-1) +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUCOMISD (VUCOMISD-128-1) +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUCOMISS (VUCOMISS-128-1) +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-512-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-512-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-512-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-512-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KANDNW (KANDNW-256-1) +{ +ICLASS: KANDNW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDW (KANDW-256-1) +{ +ICLASS: KANDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-1) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 +IFORM: KMOVW_MASKmskw_MASKu16_AVX512 +} + +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 +IFORM: KMOVW_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-2) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR +OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw +IFORM: KMOVW_MEMu16_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-3) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-4) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KNOTW (KNOTW-128-1) +{ +ICLASS: KNOTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTW (KORTESTW-128-1) +{ +ICLASS: KORTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORW (KORW-256-1) +{ +ICLASS: KORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLW (KSHIFTLW-128-1) +{ +ICLASS: KSHIFTLW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRW (KSHIFTRW-128-1) +{ +ICLASS: KSHIFTRW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KUNPCKBW (KUNPCKBW-256-1) +{ +ICLASS: KUNPCKBW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORW (KXNORW-256-1) +{ +ICLASS: KXNORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORW (KXORW-256-1) +{ +ICLASS: KXORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + diff --git a/datafiles/avx512f/avx512-ild-getters.txt b/datafiles/avx512f/avx512-ild-getters.txt new file mode 100644 index 0000000..ecc67f6 --- /dev/null +++ b/datafiles/avx512f/avx512-ild-getters.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +#Filename #priority, largest wins +#cur_dir is current file's directory #(e.g. 4 wins over 0) +%(cur_dir)s/ild/include/avx512-ild-getters.h 4 diff --git a/datafiles/avx512f/avx512-kregs.txt b/datafiles/avx512f/avx512-kregs.txt new file mode 100644 index 0000000..0c83139 --- /dev/null +++ b/datafiles/avx512f/avx512-kregs.txt @@ -0,0 +1,25 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +K0 mask 64 K0 0 +K1 mask 64 K1 1 +K2 mask 64 K2 2 +K3 mask 64 K3 3 +K4 mask 64 K4 4 +K5 mask 64 K5 5 +K6 mask 64 K6 6 +K7 mask 64 K7 7 diff --git a/datafiles/avx512f/avx512-operand-widths.txt b/datafiles/avx512f/avx512-operand-widths.txt new file mode 100644 index 0000000..c2e0f22 --- /dev/null +++ b/datafiles/avx512f/avx512-operand-widths.txt @@ -0,0 +1,54 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# +vv var 0 # relies on nelem * elem_size +zv var 0 # relies on nelem * elem_size + +wrd u16 16bits +mskw i1 64bits # FIXME: bad name + +zmskw i1 512bits + +zf32 f32 512bits +zf64 f64 512bits + +zb i8 512bits +zw i16 512bits +zd i32 512bits +zq i64 512bits + +zub u8 512bits +zuw u16 512bits +zud u32 512bits +zuq u64 512bits + +# alternative names... +zi8 i8 512bits +zi16 i16 512bits +zi32 i32 512bits +zi64 i64 512bits + +zu8 u8 512bits +zu16 u16 512bits +zu32 u32 512bits +zu64 u64 512bits +zu128 u128 512bits + + diff --git a/datafiles/avx512f/avx512-pointer-width.txt b/datafiles/avx512f/avx512-pointer-width.txt new file mode 100644 index 0000000..576195c --- /dev/null +++ b/datafiles/avx512f/avx512-pointer-width.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +64 zmmword z + diff --git a/datafiles/avx512f/avx512-reg-table-gpr.txt b/datafiles/avx512f/avx512-reg-table-gpr.txt new file mode 100644 index 0000000..11f5c97 --- /dev/null +++ b/datafiles/avx512f/avx512-reg-table-gpr.txt @@ -0,0 +1,26 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t GPRm_B():: +mode64 | OUTREG=GPR64_B() +mode32 | OUTREG=GPR32_B() +mode16 | OUTREG=GPR32_B() + +xed_reg_enum_t GPRm_R():: +mode64 | OUTREG=GPR64_R() +mode32 | OUTREG=GPR32_R() +mode16 | OUTREG=GPR32_R() diff --git a/datafiles/avx512f/avx512-reg-table-mask.txt b/datafiles/avx512f/avx512-reg-table-mask.txt new file mode 100644 index 0000000..3a8e2a8 --- /dev/null +++ b/datafiles/avx512f/avx512-reg-table-mask.txt @@ -0,0 +1,75 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# FIXME: the rest of this file is common w/KNC. Split it out to avoid +# duplication + +xed_reg_enum_t MASK1():: +MASK=0x0 | OUTREG=XED_REG_K0 +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +xed_reg_enum_t MASKNOT0():: +MASK=0x0 | OUTREG=XED_REG_ERROR +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +# used for compares in EVEX +xed_reg_enum_t MASK_R():: +REXRR=0 REXR=0 REG=0x0 | OUTREG=XED_REG_K0 +REXRR=0 REXR=0 REG=0x1 | OUTREG=XED_REG_K1 +REXRR=0 REXR=0 REG=0x2 | OUTREG=XED_REG_K2 +REXRR=0 REXR=0 REG=0x3 | OUTREG=XED_REG_K3 +REXRR=0 REXR=0 REG=0x4 | OUTREG=XED_REG_K4 +REXRR=0 REXR=0 REG=0x5 | OUTREG=XED_REG_K5 +REXRR=0 REXR=0 REG=0x6 | OUTREG=XED_REG_K6 +REXRR=0 REXR=0 REG=0x7 | OUTREG=XED_REG_K7 + +# only used in VEX space for K-mask ops +xed_reg_enum_t MASK_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_K0 +REXB=0 RM=0x1 | OUTREG=XED_REG_K1 +REXB=0 RM=0x2 | OUTREG=XED_REG_K2 +REXB=0 RM=0x3 | OUTREG=XED_REG_K3 +REXB=0 RM=0x4 | OUTREG=XED_REG_K4 +REXB=0 RM=0x5 | OUTREG=XED_REG_K5 +REXB=0 RM=0x6 | OUTREG=XED_REG_K6 +REXB=0 RM=0x7 | OUTREG=XED_REG_K7 + +# only used in VEX space for K-mask ops +# stored inverted +xed_reg_enum_t MASK_N():: +VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0 + diff --git a/datafiles/avx512f/avx512-reg-tables-b3.txt b/datafiles/avx512f/avx512-reg-tables-b3.txt new file mode 100644 index 0000000..b2e27dc --- /dev/null +++ b/datafiles/avx512f/avx512-reg-tables-b3.txt @@ -0,0 +1,172 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_B3():: +mode16 | OUTREG=XMM_B3_32() +mode32 | OUTREG=XMM_B3_32() +mode64 | OUTREG=XMM_B3_64() + +xed_reg_enum_t XMM_B3_32():: +RM=0 | OUTREG=XED_REG_XMM0 +RM=1 | OUTREG=XED_REG_XMM1 +RM=2 | OUTREG=XED_REG_XMM2 +RM=3 | OUTREG=XED_REG_XMM3 +RM=4 | OUTREG=XED_REG_XMM4 +RM=5 | OUTREG=XED_REG_XMM5 +RM=6 | OUTREG=XED_REG_XMM6 +RM=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7 + +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31 + + + +xed_reg_enum_t YMM_B3():: +mode16 | OUTREG=YMM_B3_32() +mode32 | OUTREG=YMM_B3_32() +mode64 | OUTREG=YMM_B3_64() + +xed_reg_enum_t YMM_B3_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_B3():: +mode16 | OUTREG=ZMM_B3_32() +mode32 | OUTREG=ZMM_B3_32() +mode64 | OUTREG=ZMM_B3_64() + +xed_reg_enum_t ZMM_B3_32():: +RM=0 | OUTREG=XED_REG_ZMM0 +RM=1 | OUTREG=XED_REG_ZMM1 +RM=2 | OUTREG=XED_REG_ZMM2 +RM=3 | OUTREG=XED_REG_ZMM3 +RM=4 | OUTREG=XED_REG_ZMM4 +RM=5 | OUTREG=XED_REG_ZMM5 +RM=6 | OUTREG=XED_REG_ZMM6 +RM=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15 +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31 + diff --git a/datafiles/avx512f/avx512-reg-tables-n3.txt b/datafiles/avx512f/avx512-reg-tables-n3.txt new file mode 100644 index 0000000..99f91a7 --- /dev/null +++ b/datafiles/avx512f/avx512-reg-tables-n3.txt @@ -0,0 +1,174 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_N3():: +mode16 | OUTREG=XMM_N3_32() +mode32 | OUTREG=XMM_N3_32() +mode64 | OUTREG=XMM_N3_64() + +xed_reg_enum_t XMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_N3():: +mode16 | OUTREG=YMM_N3_32() +mode32 | OUTREG=YMM_N3_32() +mode64 | OUTREG=YMM_N3_64() + +xed_reg_enum_t YMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t YMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31 + + +xed_reg_enum_t ZMM_N3():: +mode16 | OUTREG=ZMM_N3_32() +mode32 | OUTREG=ZMM_N3_32() +mode64 | OUTREG=ZMM_N3_64() + + +xed_reg_enum_t ZMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST210=0 | OUTREG=XED_REG_ZMM7 + + +xed_reg_enum_t ZMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31 + diff --git a/datafiles/avx512f/avx512-reg-tables-r3.txt b/datafiles/avx512f/avx512-reg-tables-r3.txt new file mode 100644 index 0000000..21c7387 --- /dev/null +++ b/datafiles/avx512f/avx512-reg-tables-r3.txt @@ -0,0 +1,172 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R3():: +mode16 | OUTREG=XMM_R3_32() +mode32 | OUTREG=XMM_R3_32() +mode64 | OUTREG=XMM_R3_64() + +xed_reg_enum_t XMM_R3_32():: +REG=0 | OUTREG=XED_REG_XMM0 +REG=1 | OUTREG=XED_REG_XMM1 +REG=2 | OUTREG=XED_REG_XMM2 +REG=3 | OUTREG=XED_REG_XMM3 +REG=4 | OUTREG=XED_REG_XMM4 +REG=5 | OUTREG=XED_REG_XMM5 +REG=6 | OUTREG=XED_REG_XMM6 +REG=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7 + +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_R3():: +mode16 | OUTREG=YMM_R3_32() +mode32 | OUTREG=YMM_R3_32() +mode64 | OUTREG=YMM_R3_64() + +xed_reg_enum_t YMM_R3_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_R3():: +mode16 | OUTREG=ZMM_R3_32() +mode32 | OUTREG=ZMM_R3_32() +mode64 | OUTREG=ZMM_R3_64() + +xed_reg_enum_t ZMM_R3_32():: +REG=0 | OUTREG=XED_REG_ZMM0 +REG=1 | OUTREG=XED_REG_ZMM1 +REG=2 | OUTREG=XED_REG_ZMM2 +REG=3 | OUTREG=XED_REG_ZMM3 +REG=4 | OUTREG=XED_REG_ZMM4 +REG=5 | OUTREG=XED_REG_ZMM5 +REG=6 | OUTREG=XED_REG_ZMM6 +REG=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31 + + diff --git a/datafiles/avx512f/avx512-regs.txt b/datafiles/avx512f/avx512-regs.txt new file mode 100644 index 0000000..a6763f6 --- /dev/null +++ b/datafiles/avx512f/avx512-regs.txt @@ -0,0 +1,102 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XMM0 xmm 128 ZMM0 0 +XMM1 xmm 128 ZMM1 1 +XMM2 xmm 128 ZMM2 2 +XMM3 xmm 128 ZMM3 3 +XMM4 xmm 128 ZMM4 4 +XMM5 xmm 128 ZMM5 5 +XMM6 xmm 128 ZMM6 6 +XMM7 xmm 128 ZMM7 7 + +XMM8 xmm 128 ZMM8 8 +XMM9 xmm 128 ZMM9 9 +XMM10 xmm 128 ZMM10 10 +XMM11 xmm 128 ZMM11 11 +XMM12 xmm 128 ZMM12 12 +XMM13 xmm 128 ZMM13 13 +XMM14 xmm 128 ZMM14 14 +XMM15 xmm 128 ZMM15 15 + +XMM16 xmm 128 ZMM16 16 +XMM17 xmm 128 ZMM17 17 +XMM18 xmm 128 ZMM18 18 +XMM19 xmm 128 ZMM19 19 +XMM20 xmm 128 ZMM20 20 +XMM21 xmm 128 ZMM21 21 +XMM22 xmm 128 ZMM22 22 +XMM23 xmm 128 ZMM23 23 +XMM24 xmm 128 ZMM24 24 +XMM25 xmm 128 ZMM25 25 +XMM26 xmm 128 ZMM26 26 +XMM27 xmm 128 ZMM27 27 +XMM28 xmm 128 ZMM28 28 +XMM29 xmm 128 ZMM29 29 +XMM30 xmm 128 ZMM30 30 +XMM31 xmm 128 ZMM31 31 + +YMM0 ymm 256 ZMM0 0 +YMM1 ymm 256 ZMM1 1 +YMM2 ymm 256 ZMM2 2 +YMM3 ymm 256 ZMM3 3 +YMM4 ymm 256 ZMM4 4 +YMM5 ymm 256 ZMM5 5 +YMM6 ymm 256 ZMM6 6 +YMM7 ymm 256 ZMM7 7 +YMM8 ymm 256 ZMM8 8 +YMM9 ymm 256 ZMM9 9 +YMM10 ymm 256 ZMM10 10 +YMM11 ymm 256 ZMM11 11 +YMM12 ymm 256 ZMM12 12 +YMM13 ymm 256 ZMM13 13 +YMM14 ymm 256 ZMM14 14 +YMM15 ymm 256 ZMM15 15 + +YMM16 ymm 256 ZMM16 16 +YMM17 ymm 256 ZMM17 17 +YMM18 ymm 256 ZMM18 18 +YMM19 ymm 256 ZMM19 19 +YMM20 ymm 256 ZMM20 20 +YMM21 ymm 256 ZMM21 21 +YMM22 ymm 256 ZMM22 22 +YMM23 ymm 256 ZMM23 23 +YMM24 ymm 256 ZMM24 24 +YMM25 ymm 256 ZMM25 25 +YMM26 ymm 256 ZMM26 26 +YMM27 ymm 256 ZMM27 27 +YMM28 ymm 256 ZMM28 28 +YMM29 ymm 256 ZMM29 29 +YMM30 ymm 256 ZMM30 30 +YMM31 ymm 256 ZMM31 31 + + + + + + + + + + + + + + + + + diff --git a/datafiles/avx512f/avx512-state-bits.txt b/datafiles/avx512f/avx512-state-bits.txt new file mode 100644 index 0000000..25a6869 --- /dev/null +++ b/datafiles/avx512f/avx512-state-bits.txt @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +EVV VEXVALID=2 + +EMX_BROADCAST_1TO16_32 BCAST=1 # 512 +EMX_BROADCAST_4TO16_32 BCAST=2 # 512 +EMX_BROADCAST_1TO8_64 BCAST=5 # 512 +EMX_BROADCAST_4TO8_64 BCAST=6 # 512 +EMX_BROADCAST_2TO16_32 BCAST=7 # 512 +EMX_BROADCAST_2TO8_64 BCAST=8 # 512 +EMX_BROADCAST_8TO16_32 BCAST=9 # 512 +EMX_BROADCAST_1TO32_16 BCAST=16 # 512 +EMX_BROADCAST_1TO64_8 BCAST=19 # 512 +# these do not show up on earlier processors +EMX_BROADCAST_4TO8_32 BCAST=4 # 256 +EMX_BROADCAST_2TO4_32 BCAST=12 # 128 +EMX_BROADCAST_2TO8_32 BCAST=21 # 256 +EMX_BROADCAST_1TO2_32 BCAST=22 # 128 diff --git a/datafiles/avx512f/avx512-strings.txt b/datafiles/avx512f/avx512-strings.txt new file mode 100644 index 0000000..9c45b90 --- /dev/null +++ b/datafiles/avx512f/avx512-strings.txt @@ -0,0 +1,63 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ZEROSTR(XED_OPERAND_ZEROING):: +0 -> '' +1 -> '{z}' + +SAESTR(XED_OPERAND_SAE):: +0 -> '' +1 -> '{sae}' + +# AVX512 only has rounding with implied SAE +ROUNDC(XED_OPERAND_ROUNDC):: +0 -> '' +1 -> '{rne-sae}' +2 -> '{rd-sae}' +3 -> '{ru-sae}' +4 -> '{rz-sae}' + + +BCASTSTR(XED_OPERAND_BCAST):: +0 -> '' +1 -> '{1to16}' +2 -> '{4to16}' +3 -> '{1to8}' +4 -> '{4to8}' +5 -> '{1to8}' +6 -> '{4to8}' +7 -> '{2to16}' +8 -> '{2to8}' +9 -> '{8to16}' +10 -> '{1to4}' +11 -> '{1to2}' +12 -> '{2to4}' +13 -> '{1to4}' +14 -> '{1to8}' +15 -> '{1to16}' +16 -> '{1to32}' +17 -> '{1to16}' +18 -> '{1to32}' +19 -> '{1to64}' +20 -> '{2to4}' +21 -> '{2to8}' +22 -> '{1to2}' +23 -> '{1to2}' +24 -> '{1to4}' +25 -> '{1to8}' +26 -> '{1to2}' +27 -> '{1to4}' diff --git a/datafiles/avx512f/cpuid.xed.txt b/datafiles/avx512f/cpuid.xed.txt new file mode 100644 index 0000000..1f506c4 --- /dev/null +++ b/datafiles/avx512f/cpuid.xed.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512F_128: avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512F_128N: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_256: avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512F_512: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_KOP: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_SCALAR: avx512f.7.0.ebx.16 diff --git a/datafiles/avx512f/files.cfg b/datafiles/avx512f/files.cfg new file mode 100644 index 0000000..102e337 --- /dev/null +++ b/datafiles/avx512f/files.cfg @@ -0,0 +1,58 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + state:avx512-state-bits.txt + registers:avx512-regs.txt + registers:avx512-kregs.txt + + dec-patterns:avx512-evex-dec.txt # vex and evex prefixes + enc-patterns:avx512-evex-enc.txt # vex and evex prefixes + + dec-patterns:avx512-disp8.txt + enc-patterns:avx512-disp8-enc.txt + + dec-patterns:avx512-addressing-dec.txt + enc-patterns:avx512-addressing-enc.txt + + dec-patterns:avx512-reg-table-mask.txt + enc-dec-patterns:avx512-reg-table-mask.txt + dec-patterns:avx512-reg-table-gpr.txt + enc-dec-patterns:avx512-reg-table-gpr.txt + + + dec-patterns:avx512-reg-tables-r3.txt + enc-dec-patterns:avx512-reg-tables-r3.txt + dec-patterns:avx512-reg-tables-b3.txt + enc-dec-patterns:avx512-reg-tables-b3.txt + dec-patterns:avx512-reg-tables-n3.txt + enc-dec-patterns:avx512-reg-tables-n3.txt + + widths:avx512-operand-widths.txt + pointer-names:avx512-pointer-width.txt + fields:avx512-fields.txt + + dec-instructions: avx512-foundation-isa.xed.txt + enc-instructions: avx512-foundation-isa.xed.txt + + conversion-table:avx512-strings.txt + + ild-getters: avx512-ild-getters.txt + + + + +cpuid : cpuid.xed.txt diff --git a/datafiles/avx512f/ild/include/avx512-ild-getters.h b/datafiles/avx512f/ild/include/avx512-ild-getters.h new file mode 100644 index 0000000..b418ede --- /dev/null +++ b/datafiles/avx512f/ild/include/avx512-ild-getters.h @@ -0,0 +1,44 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// AVX512 ILD getters + +#if !defined(_XED_ILD_AVX512_GETTERS_H) +#define _XED_ILD_AVX512_GETTERS_H +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-types.h" +#include "xed-ild.h" + + +/* ild getters */ + +static XED_INLINE +xed_uint32_t xed3_operand_get_mask_not0(const xed_decoded_inst_t *d) { + /* aaa != 0 */ + return xed3_operand_get_mask(d) != 0; +} +static XED_INLINE +xed_uint32_t xed3_operand_get_mask_zero(const xed_decoded_inst_t *d) { + /* aaa == 0 */ + return xed3_operand_get_mask(d) == 0; +} + + +#endif diff --git a/datafiles/avx512f/shared-files.cfg b/datafiles/avx512f/shared-files.cfg new file mode 100644 index 0000000..a3cc643 --- /dev/null +++ b/datafiles/avx512f/shared-files.cfg @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# common stuff for AVX512 + + add:dec-spine:%(xed_dir)s/datafiles/knc/uisa-spine.txt:4 + + state:%(xed_dir)s/datafiles/knc/uisa-state-bits.txt + + dec-patterns:%(xed_dir)s/datafiles/knc/uisa-splitter.txt + + +# These do not have the XMM/YMM regs (and our kregs are wider) + registers:%(xed_dir)s/datafiles/knc/lrb2-regs.txt + +# we change two functions for LRB/UISA for the N*disp8 scaling + remove-source:source:xed-operand-values-interface-repl.c + add-source:source:%(xed_dir)s/datafiles/knc/xed-operand-values-interface-uisa.c + diff --git a/datafiles/avx512f/tests/bulk-tests.txt b/datafiles/avx512f/tests/bulk-tests.txt new file mode 100644 index 0000000..2208070 --- /dev/null +++ b/datafiles/avx512f/tests/bulk-tests.txt @@ -0,0 +1,10 @@ +BUILDDIR/xed -64 -e vaddps zmm3 k1 zmm1 zmm2 +BUILDDIR/xed -64 -d 62F1744958DA +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1 +BUILDDIR/xed -64 -d 62F2FD4F920408 +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1 +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1,11 +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1,11223344 +BUILDDIR/xed -64 -d 62727D4F924CC500 +BUILDDIR/xed -64 -e VGATHERDPS ZMM9 K7 MEM64:RBP,ZMM0,8,0 + diff --git a/datafiles/avx512f/tests/make.tests b/datafiles/avx512f/tests/make.tests new file mode 100755 index 0000000..dbb1709 --- /dev/null +++ b/datafiles/avx512f/tests/make.tests @@ -0,0 +1 @@ +../../../tests/run-cmd.py --bulk-make-tests bulk-tests.txt --build-dir ../../../obj diff --git a/datafiles/avx512f/tests/run.tests b/datafiles/avx512f/tests/run.tests new file mode 100755 index 0000000..fcd72d7 --- /dev/null +++ b/datafiles/avx512f/tests/run.tests @@ -0,0 +1 @@ +../../../tests/run-cmd.py --build-dir ../../../obj diff --git a/datafiles/avx512f/tests/test-00000/cmd b/datafiles/avx512f/tests/test-00000/cmd new file mode 100644 index 0000000..9b14498 --- /dev/null +++ b/datafiles/avx512f/tests/test-00000/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e vaddps zmm3 k1 zmm1 zmm2 diff --git a/datafiles/avx512f/tests/test-00000/retcode.reference b/datafiles/avx512f/tests/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00000/stderr.reference b/datafiles/avx512f/tests/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00000/stdout.reference b/datafiles/avx512f/tests/test-00000/stdout.reference new file mode 100644 index 0000000..dfc2afa --- /dev/null +++ b/datafiles/avx512f/tests/test-00000/stdout.reference @@ -0,0 +1,4 @@ +Request: VADDPS MODE:2, REG0:ZMM3, REG1:K1, REG2:ZMM1, REG3:ZMM2, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 REG3 +Encodable! 62F1744958DA +.byte 0x62,0xf1,0x74,0x49,0x58,0xda diff --git a/datafiles/avx512f/tests/test-00001/cmd b/datafiles/avx512f/tests/test-00001/cmd new file mode 100644 index 0000000..660f133 --- /dev/null +++ b/datafiles/avx512f/tests/test-00001/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -d 62F1744958DA diff --git a/datafiles/avx512f/tests/test-00001/retcode.reference b/datafiles/avx512f/tests/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00001/stderr.reference b/datafiles/avx512f/tests/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00001/stdout.reference b/datafiles/avx512f/tests/test-00001/stdout.reference new file mode 100644 index 0000000..73a9e35 --- /dev/null +++ b/datafiles/avx512f/tests/test-00001/stdout.reference @@ -0,0 +1,3 @@ +62F1744958DA +ICLASS: VADDPS CATEGORY: AVX512 EXTENSION: AVX512EVEX IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 ISA_SET: AVX512F_512 +SHORT: vaddps zmm3, k1, zmm1, zmm2 diff --git a/datafiles/avx512f/tests/test-00002/cmd b/datafiles/avx512f/tests/test-00002/cmd new file mode 100644 index 0000000..40e41eb --- /dev/null +++ b/datafiles/avx512f/tests/test-00002/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1 diff --git a/datafiles/avx512f/tests/test-00002/retcode.reference b/datafiles/avx512f/tests/test-00002/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00002/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00002/stderr.reference b/datafiles/avx512f/tests/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00002/stdout.reference b/datafiles/avx512f/tests/test-00002/stdout.reference new file mode 100644 index 0000000..44fae15 --- /dev/null +++ b/datafiles/avx512f/tests/test-00002/stdout.reference @@ -0,0 +1,4 @@ +Request: VGATHERDPD MEM_WIDTH:64, MEM0:zmmword ptr [RAX+YMM1*1], MODE:2, REG0:ZMM0, REG1:K7, SMODE:2 +OPERAND ORDER: REG0 REG1 MEM0 +Encodable! 62F2FD4F920408 +.byte 0x62,0xf2,0xfd,0x4f,0x92,0x04,0x08 diff --git a/datafiles/avx512f/tests/test-00003/cmd b/datafiles/avx512f/tests/test-00003/cmd new file mode 100644 index 0000000..a30686a --- /dev/null +++ b/datafiles/avx512f/tests/test-00003/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -d 62F2FD4F920408 diff --git a/datafiles/avx512f/tests/test-00003/retcode.reference b/datafiles/avx512f/tests/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00003/stderr.reference b/datafiles/avx512f/tests/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00003/stdout.reference b/datafiles/avx512f/tests/test-00003/stdout.reference new file mode 100644 index 0000000..74c1e65 --- /dev/null +++ b/datafiles/avx512f/tests/test-00003/stdout.reference @@ -0,0 +1,3 @@ +62F2FD4F920408 +ICLASS: VGATHERDPD CATEGORY: GATHER EXTENSION: AVX512EVEX IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512 ISA_SET: AVX512F_512 +SHORT: vgatherdpd zmm0, k7, zmmword ptr [rax+ymm1*1] diff --git a/datafiles/avx512f/tests/test-00004/cmd b/datafiles/avx512f/tests/test-00004/cmd new file mode 100644 index 0000000..40e41eb --- /dev/null +++ b/datafiles/avx512f/tests/test-00004/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1 diff --git a/datafiles/avx512f/tests/test-00004/retcode.reference b/datafiles/avx512f/tests/test-00004/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00004/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00004/stderr.reference b/datafiles/avx512f/tests/test-00004/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00004/stdout.reference b/datafiles/avx512f/tests/test-00004/stdout.reference new file mode 100644 index 0000000..44fae15 --- /dev/null +++ b/datafiles/avx512f/tests/test-00004/stdout.reference @@ -0,0 +1,4 @@ +Request: VGATHERDPD MEM_WIDTH:64, MEM0:zmmword ptr [RAX+YMM1*1], MODE:2, REG0:ZMM0, REG1:K7, SMODE:2 +OPERAND ORDER: REG0 REG1 MEM0 +Encodable! 62F2FD4F920408 +.byte 0x62,0xf2,0xfd,0x4f,0x92,0x04,0x08 diff --git a/datafiles/avx512f/tests/test-00005/cmd b/datafiles/avx512f/tests/test-00005/cmd new file mode 100644 index 0000000..f792ab8 --- /dev/null +++ b/datafiles/avx512f/tests/test-00005/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1,11 diff --git a/datafiles/avx512f/tests/test-00005/retcode.reference b/datafiles/avx512f/tests/test-00005/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00005/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00005/stderr.reference b/datafiles/avx512f/tests/test-00005/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00005/stdout.reference b/datafiles/avx512f/tests/test-00005/stdout.reference new file mode 100644 index 0000000..e25af49 --- /dev/null +++ b/datafiles/avx512f/tests/test-00005/stdout.reference @@ -0,0 +1,4 @@ +Request: VGATHERDPD DISP_WIDTH:8, MEM_WIDTH:64, MEM0:zmmword ptr [RAX+YMM1*1+0x11], MODE:2, REG0:ZMM0, REG1:K7, SMODE:2 +OPERAND ORDER: REG0 REG1 MEM0 +Encodable! 62F2FD4F92440811 +.byte 0x62,0xf2,0xfd,0x4f,0x92,0x44,0x08,0x11 diff --git a/datafiles/avx512f/tests/test-00006/cmd b/datafiles/avx512f/tests/test-00006/cmd new file mode 100644 index 0000000..6cc483d --- /dev/null +++ b/datafiles/avx512f/tests/test-00006/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e VGATHERDPD zmm0 k7 MEM64:rax,ymm1,1,11223344 diff --git a/datafiles/avx512f/tests/test-00006/retcode.reference b/datafiles/avx512f/tests/test-00006/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00006/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00006/stderr.reference b/datafiles/avx512f/tests/test-00006/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00006/stdout.reference b/datafiles/avx512f/tests/test-00006/stdout.reference new file mode 100644 index 0000000..250931e --- /dev/null +++ b/datafiles/avx512f/tests/test-00006/stdout.reference @@ -0,0 +1,4 @@ +Request: VGATHERDPD DISP_WIDTH:32, MEM_WIDTH:64, MEM0:zmmword ptr [RAX+YMM1*1+0x11223344], MODE:2, REG0:ZMM0, REG1:K7, SMODE:2 +OPERAND ORDER: REG0 REG1 MEM0 +Encodable! 62F2FD4F92840844332211 +.byte 0x62,0xf2,0xfd,0x4f,0x92,0x84,0x08,0x44,0x33,0x22,0x11 diff --git a/datafiles/avx512f/tests/test-00007/cmd b/datafiles/avx512f/tests/test-00007/cmd new file mode 100644 index 0000000..8d82422 --- /dev/null +++ b/datafiles/avx512f/tests/test-00007/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -d 62727D4F924CC500 diff --git a/datafiles/avx512f/tests/test-00007/retcode.reference b/datafiles/avx512f/tests/test-00007/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00007/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00007/stderr.reference b/datafiles/avx512f/tests/test-00007/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00007/stdout.reference b/datafiles/avx512f/tests/test-00007/stdout.reference new file mode 100644 index 0000000..70e519c --- /dev/null +++ b/datafiles/avx512f/tests/test-00007/stdout.reference @@ -0,0 +1,3 @@ +62727D4F924CC500 +ICLASS: VGATHERDPS CATEGORY: GATHER EXTENSION: AVX512EVEX IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512 ISA_SET: AVX512F_512 +SHORT: vgatherdps zmm9, k7, zmmword ptr [rbp+zmm0*8] diff --git a/datafiles/avx512f/tests/test-00008/cmd b/datafiles/avx512f/tests/test-00008/cmd new file mode 100644 index 0000000..d923962 --- /dev/null +++ b/datafiles/avx512f/tests/test-00008/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -e VGATHERDPS ZMM9 K7 MEM64:RBP,ZMM0,8,0 diff --git a/datafiles/avx512f/tests/test-00008/retcode.reference b/datafiles/avx512f/tests/test-00008/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/avx512f/tests/test-00008/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/avx512f/tests/test-00008/stderr.reference b/datafiles/avx512f/tests/test-00008/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/avx512f/tests/test-00008/stdout.reference b/datafiles/avx512f/tests/test-00008/stdout.reference new file mode 100644 index 0000000..d39d709 --- /dev/null +++ b/datafiles/avx512f/tests/test-00008/stdout.reference @@ -0,0 +1,4 @@ +Request: VGATHERDPS DISP_WIDTH:8, MEM_WIDTH:64, MEM0:zmmword ptr [RBP+ZMM0*8], MODE:2, REG0:ZMM9, REG1:K7, SMODE:2 +OPERAND ORDER: REG0 REG1 MEM0 +Encodable! 62727D4F924CC500 +.byte 0x62,0x72,0x7d,0x4f,0x92,0x4c,0xc5,0x00 diff --git a/datafiles/avx512ifma/cpuid.xed.txt b/datafiles/avx512ifma/cpuid.xed.txt new file mode 100644 index 0000000..7abdec0 --- /dev/null +++ b/datafiles/avx512ifma/cpuid.xed.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512IFMA_128: avx512ifma.7.0.ebx.21 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512IFMA_256: avx512ifma.7.0.ebx.21 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512IFMA_512: avx512ifma.7.0.ebx.21 + diff --git a/datafiles/avx512ifma/files.cfg b/datafiles/avx512ifma/files.cfg new file mode 100644 index 0000000..ec9de95 --- /dev/null +++ b/datafiles/avx512ifma/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions: ifma-isa.xed.txt + enc-instructions: ifma-isa.xed.txt + +cpuid : cpuid.xed.txt diff --git a/datafiles/avx512ifma/ifma-isa.xed.txt b/datafiles/avx512ifma/ifma-isa.xed.txt new file mode 100644 index 0000000..88e6960 --- /dev/null +++ b/datafiles/avx512ifma/ifma-isa.xed.txt @@ -0,0 +1,207 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + diff --git a/datafiles/avx512vbmi/cpuid.xed.txt b/datafiles/avx512vbmi/cpuid.xed.txt new file mode 100644 index 0000000..f63d2d6 --- /dev/null +++ b/datafiles/avx512vbmi/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512VBMI_128: avx512vbmi.7.0.ecx.1 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512VBMI_256: avx512vbmi.7.0.ecx.1 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512VBMI_512: avx512vbmi.7.0.ecx.1 diff --git a/datafiles/avx512vbmi/files.cfg b/datafiles/avx512vbmi/files.cfg new file mode 100644 index 0000000..c29493b --- /dev/null +++ b/datafiles/avx512vbmi/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions: vbmi-isa.xed.txt + enc-instructions: vbmi-isa.xed.txt + +cpuid : cpuid.xed.txt diff --git a/datafiles/avx512vbmi/vbmi-isa.xed.txt b/datafiles/avx512vbmi/vbmi-isa.xed.txt new file mode 100644 index 0000000..d7d12d5 --- /dev/null +++ b/datafiles/avx512vbmi/vbmi-isa.xed.txt @@ -0,0 +1,387 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPERMB (VPERMB-128-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-256-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-512-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-128-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-256-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-512-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-128-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-256-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-512-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +} + + diff --git a/datafiles/avxhsw/cpuid.xed.txt b/datafiles/avxhsw/cpuid.xed.txt new file mode 100644 index 0000000..97f1b0f --- /dev/null +++ b/datafiles/avxhsw/cpuid.xed.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX2: avx2.7.0.ebx.5 + XED_ISA_SET_AVX2GATHER: avx2.7.0.ebx.5 + XED_ISA_SET_RTM: rtm.7.0.ebx.11 + XED_ISA_SET_BMI1: bmi1.7.0.ebx.3 + XED_ISA_SET_BMI2: bmi2.7.0.ebx.8 + XED_ISA_SET_INVPCID: invpcid.7.0.ebx.10 diff --git a/datafiles/avxhsw/files.cfg b/datafiles/avxhsw/files.cfg new file mode 100644 index 0000000..58f472d --- /dev/null +++ b/datafiles/avxhsw/files.cfg @@ -0,0 +1,48 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +chip-models:hsw-ext-chips.txt + +dec-instructions:gather-isa.txt +dec-instructions:hsw-int256-isa.txt +dec-instructions:hsw-isa.txt +dec-instructions:hsw-lzcnt.txt +dec-instructions:hsw-vex-gpr-isa.txt +dec-instructions:hsw-vshift-isa.txt +dec-instructions:movnt-load-isa.txt +dec-instructions:vmfunc-isa.txt +dec-instructions:rtm.xed + + +enc-instructions:gather-isa.txt +enc-instructions:hsw-int256-isa.txt +enc-instructions:hsw-isa.txt +enc-instructions:hsw-lzcnt.txt +enc-instructions:hsw-vex-gpr-isa.txt +enc-instructions:hsw-vshift-isa.txt +enc-instructions:movnt-load-isa.txt +enc-instructions:vmfunc-isa.txt +enc-instructions:rtm.xed + + dec-patterns:hsw-reg-table.txt +enc-dec-patterns:hsw-reg-table.txt + +dec-patterns:vsib-addressing-dec.txt +enc-patterns:vsib-addressing-enc.txt + +state:hsw-state-bits.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/avxhsw/gather-isa.txt b/datafiles/avxhsw/gather-isa.txt new file mode 100644 index 0000000..7be3eec --- /dev/null +++ b/datafiles/avxhsw/gather-isa.txt @@ -0,0 +1,199 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +# DEST in MODRM.REG +# BASE in SIB.base +# INDEX in SIB.index +# MASK in VEX.VVVV -- NOTE mask is a signed integer!!! + +# VL = 128 VL = 256 +# dest/mask index memsz dest/mask index memsz +# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b +# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b +# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b +# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b + + + +{ +ICLASS : VGATHERDPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERDPD_YMMf64_MEMqq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERDPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:qq:f32 REG1=YMM_N():rw:qq:i32 +IFORM: VGATHERDPS_YMMf32_MEMqq_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERDPS_XMMf32_MEMdq_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERQPD_YMMf64_MEMqq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERQPD_XMMf64_MEMdq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:q:f32 REG1=XMM_N():rw:q:i32 +IFORM: VGATHERQPS_XMMf32_MEMq_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + +{ +ICLASS : VPGATHERDQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERDQ_YMMu64_MEMqq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERDQ_XMMu64_MEMdq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERDD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:qq:u32 REG1=YMM_N():rw:qq:i32 +IFORM: VPGATHERDD_YMMu32_MEMqq_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERDD_XMMu32_MEMdq_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERQQ_YMMu64_MEMqq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERQQ_XMMu64_MEMdq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:q:u32 REG1=XMM_N():rw:q:i32 +IFORM: VPGATHERQD_XMMu32_MEMq_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + diff --git a/datafiles/avxhsw/hsw-ext-chips.txt b/datafiles/avxhsw/hsw-ext-chips.txt new file mode 100644 index 0000000..6156862 --- /dev/null +++ b/datafiles/avxhsw/hsw-ext-chips.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +HASWELL: ALL_OF(IVYBRIDGE) FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER INVPCID MOVBE VMFUNC RTM + + + diff --git a/datafiles/avxhsw/hsw-int256-isa.txt b/datafiles/avxhsw/hsw-int256-isa.txt new file mode 100644 index 0000000..0fccd1e --- /dev/null +++ b/datafiles/avxhsw/hsw-int256-isa.txt @@ -0,0 +1,1818 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPABSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 +} +{ +ICLASS : VPABSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 + +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 +} +{ +ICLASS : VPABSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 + +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHMINPOSUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 +} + + + + + + + + + + +{ +ICLASS : VPACKSSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKSSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPACKUSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKUSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 +} + + +{ +ICLASS : VPADDB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPADDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPADDSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPADDUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPADDUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPAVGB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPAVGW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + + +{ +ICLASS : VPCMPEQB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPCMPEQW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPCMPEQD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPCMPEQQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPCMPGTB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPCMPGTW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPCMPGTD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPCMPGTQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + + +{ +ICLASS : VPHADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMADDWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMADDUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 +} + +{ +ICLASS : VPMAXSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMAXSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMAXSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMAXUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMAXUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMAXUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMINSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMINSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMINSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMINUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMINUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMINUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMULHUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMULHRSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMULHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMULUDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPMULDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSHUFB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} + +{ +ICLASS : VPSIGNB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSIGNW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSIGND +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + + +{ +ICLASS : VPSUBSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPSUBUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSUBUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPSUBB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPSUBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPUNPCKHBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKHWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKHDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPUNPCKLBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKLWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VPALIGNR +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VMPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} + + + +{ +ICLASS : VPOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} + + + +{ +ICLASS : VPBLENDVB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 + +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 +} + + + + +{ +ICLASS : VPMOVMSKB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 +} + + + +{ +ICLASS : VPSHUFD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b +} +{ +ICLASS : VPSHUFHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VPSHUFLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} + + + +{ +ICLASS : VPSRLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} + +############################################## + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 + +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + + + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 +} + + +################################## +# newer stuff 2009-08-14 + + +{ +ICLASS : VINSERTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b + +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b +} + + + + + +{ +ICLASS : VEXTRACTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b +} + + +########################################################################### + +### # VPMASKMOVD masked load and store +### # VPMASKMOVQ masked load and store + + + + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +} + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 +} +########################################################################### + + +### # VPERM2I128 256b only + +{ +ICLASS : VPERM2I128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b +} + + +{ +ICLASS : VPERMQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b +} + +{ +ICLASS : VPERMPD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + + + + + + + +{ +ICLASS : VPERMD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + + +PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPERMPS +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +########################################################################### + + +### # VPBLENDD imm 128/256 + + + +{ +ICLASS : VPBLENDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b + + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b +} + + + +########################################################################### + +{ +ICLASS : VPBROADCASTB +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 + +} + + + + +{ +ICLASS : VPBROADCASTW +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 +} + + + + +### # VPBROADCASTD gpr/mem + + +{ +ICLASS : VPBROADCASTD +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 + + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 +} + + + +### # VPBROADCASTQ gpr/mem + +{ +ICLASS : VPBROADCASTQ +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 +} + + + + + + +{ +ICLASS : VBROADCASTSS +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : xmm,xmm and ymm,xmm +PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 +} + + +{ +ICLASS : VBROADCASTSD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : ymm,xmm only +PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 +} + + + +{ +ICLASS : VBROADCASTI128 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? +PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 +} diff --git a/datafiles/avxhsw/hsw-isa.txt b/datafiles/avxhsw/hsw-isa.txt new file mode 100644 index 0000000..c288c1b --- /dev/null +++ b/datafiles/avxhsw/hsw-isa.txt @@ -0,0 +1,68 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : TZCNT +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +} + +{ +ICLASS : BSF +VERSION : 1 +COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + +{ +ICLASS : INVPCID +CPL : 0 +CATEGORY : MISC +EXTENSION : INVPCID +ISA_SET : INVPCID +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : +} diff --git a/datafiles/avxhsw/hsw-lzcnt.txt b/datafiles/avxhsw/hsw-lzcnt.txt new file mode 100644 index 0000000..45cc6b2 --- /dev/null +++ b/datafiles/avxhsw/hsw-lzcnt.txt @@ -0,0 +1,60 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +# This replace the AMD version in LZCNT builds +VERSION : 2 +CPL : 3 +CATEGORY : LZCNT +EXTENSION : LZCNT +COMMENT: : These next one WAS introduced first by AMD circa SSE4a. +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 2 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} diff --git a/datafiles/avxhsw/hsw-reg-table.txt b/datafiles/avxhsw/hsw-reg-table.txt new file mode 100644 index 0000000..1bd7619 --- /dev/null +++ b/datafiles/avxhsw/hsw-reg-table.txt @@ -0,0 +1,197 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t GPRy_N():: +EASZ=3 | OUTREG=VGPR64_N() +EASZ=2 | OUTREG=VGPR32_N() +EASZ=1 | OUTREG=VGPR32_N() + + +xed_reg_enum_t VGPRv_N():: +EOSZ=1 | OUTREG=VGPR32_N() +EOSZ=2 | OUTREG=VGPR32_N() +EOSZ=3 | OUTREG=VGPR64_N() + + +xed_reg_enum_t VGPR32_N():: +mode16 | OUTREG=VGPR32_N_32() +mode32 | OUTREG=VGPR32_N_32() +mode64 | OUTREG=VGPR32_N_64() + +xed_reg_enum_t VGPR32_B():: +mode16 | OUTREG=VGPR32_B_32() +mode32 | OUTREG=VGPR32_B_32() +mode64 | OUTREG=VGPR32_B_64() + +xed_reg_enum_t VGPR32_R():: +mode16 | OUTREG=VGPR32_R_32() +mode32 | OUTREG=VGPR32_R_32() +mode64 | OUTREG=VGPR32_R_64() + + + + + + +xed_reg_enum_t VGPR32_N_32():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST210=0 | OUTREG=XED_REG_EDI + +xed_reg_enum_t VGPR32_N_64():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_EDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8D +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9D +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10D +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11D +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12D +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13D +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14D +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15D + + +xed_reg_enum_t VGPR64_N():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_RAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_RCX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_RDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_RBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_RSP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_RBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_RSI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_RDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15 + + +########### + +xed_reg_enum_t VGPR32_R_32():: # IGNORES (REXR) IN 32b mode +REG=0 | OUTREG=XED_REG_EAX +REG=1 | OUTREG=XED_REG_ECX +REG=2 | OUTREG=XED_REG_EDX +REG=3 | OUTREG=XED_REG_EBX +REG=4 | OUTREG=XED_REG_ESP +REG=5 | OUTREG=XED_REG_EBP +REG=6 | OUTREG=XED_REG_ESI +REG=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_EAX +REXR=0 REG=1 | OUTREG=XED_REG_ECX +REXR=0 REG=2 | OUTREG=XED_REG_EDX +REXR=0 REG=3 | OUTREG=XED_REG_EBX +REXR=0 REG=4 | OUTREG=XED_REG_ESP +REXR=0 REG=5 | OUTREG=XED_REG_EBP +REXR=0 REG=6 | OUTREG=XED_REG_ESI +REXR=0 REG=7 | OUTREG=XED_REG_EDI +REXR=1 REG=0 | OUTREG=XED_REG_R8D +REXR=1 REG=1 | OUTREG=XED_REG_R9D +REXR=1 REG=2 | OUTREG=XED_REG_R10D +REXR=1 REG=3 | OUTREG=XED_REG_R11D +REXR=1 REG=4 | OUTREG=XED_REG_R12D +REXR=1 REG=5 | OUTREG=XED_REG_R13D +REXR=1 REG=6 | OUTREG=XED_REG_R14D +REXR=1 REG=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_R():: +REXR=0 REG=0 | OUTREG=XED_REG_RAX +REXR=0 REG=1 | OUTREG=XED_REG_RCX +REXR=0 REG=2 | OUTREG=XED_REG_RDX +REXR=0 REG=3 | OUTREG=XED_REG_RBX +REXR=0 REG=4 | OUTREG=XED_REG_RSP +REXR=0 REG=5 | OUTREG=XED_REG_RBP +REXR=0 REG=6 | OUTREG=XED_REG_RSI +REXR=0 REG=7 | OUTREG=XED_REG_RDI +REXR=1 REG=0 | OUTREG=XED_REG_R8 +REXR=1 REG=1 | OUTREG=XED_REG_R9 +REXR=1 REG=2 | OUTREG=XED_REG_R10 +REXR=1 REG=3 | OUTREG=XED_REG_R11 +REXR=1 REG=4 | OUTREG=XED_REG_R12 +REXR=1 REG=5 | OUTREG=XED_REG_R13 +REXR=1 REG=6 | OUTREG=XED_REG_R14 +REXR=1 REG=7 | OUTREG=XED_REG_R15 + + +################### + +xed_reg_enum_t VGPR32_B_32():: # IGNORES (REXB) IN 32b mode +RM=0 | OUTREG=XED_REG_EAX +RM=1 | OUTREG=XED_REG_ECX +RM=2 | OUTREG=XED_REG_EDX +RM=3 | OUTREG=XED_REG_EBX +RM=4 | OUTREG=XED_REG_ESP +RM=5 | OUTREG=XED_REG_EBP +RM=6 | OUTREG=XED_REG_ESI +RM=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_EAX +REXB=0 RM=1 | OUTREG=XED_REG_ECX +REXB=0 RM=2 | OUTREG=XED_REG_EDX +REXB=0 RM=3 | OUTREG=XED_REG_EBX +REXB=0 RM=4 | OUTREG=XED_REG_ESP +REXB=0 RM=5 | OUTREG=XED_REG_EBP +REXB=0 RM=6 | OUTREG=XED_REG_ESI +REXB=0 RM=7 | OUTREG=XED_REG_EDI +REXB=1 RM=0 | OUTREG=XED_REG_R8D +REXB=1 RM=1 | OUTREG=XED_REG_R9D +REXB=1 RM=2 | OUTREG=XED_REG_R10D +REXB=1 RM=3 | OUTREG=XED_REG_R11D +REXB=1 RM=4 | OUTREG=XED_REG_R12D +REXB=1 RM=5 | OUTREG=XED_REG_R13D +REXB=1 RM=6 | OUTREG=XED_REG_R14D +REXB=1 RM=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_B():: +REXB=0 RM=0 | OUTREG=XED_REG_RAX +REXB=0 RM=1 | OUTREG=XED_REG_RCX +REXB=0 RM=2 | OUTREG=XED_REG_RDX +REXB=0 RM=3 | OUTREG=XED_REG_RBX +REXB=0 RM=4 | OUTREG=XED_REG_RSP +REXB=0 RM=5 | OUTREG=XED_REG_RBP +REXB=0 RM=6 | OUTREG=XED_REG_RSI +REXB=0 RM=7 | OUTREG=XED_REG_RDI +REXB=1 RM=0 | OUTREG=XED_REG_R8 +REXB=1 RM=1 | OUTREG=XED_REG_R9 +REXB=1 RM=2 | OUTREG=XED_REG_R10 +REXB=1 RM=3 | OUTREG=XED_REG_R11 +REXB=1 RM=4 | OUTREG=XED_REG_R12 +REXB=1 RM=5 | OUTREG=XED_REG_R13 +REXB=1 RM=6 | OUTREG=XED_REG_R14 +REXB=1 RM=7 | OUTREG=XED_REG_R15 + + diff --git a/datafiles/avxhsw/hsw-state-bits.txt b/datafiles/avxhsw/hsw-state-bits.txt new file mode 100644 index 0000000..9892886 --- /dev/null +++ b/datafiles/avxhsw/hsw-state-bits.txt @@ -0,0 +1,26 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +EMX_BROADCAST_1TO2_64 BCAST=11 # 128 +EMX_BROADCAST_1TO8_16 BCAST=14 # 128 +EMX_BROADCAST_1TO16_16 BCAST=15 # 256 +EMX_BROADCAST_1TO16_8 BCAST=17 # 128 +EMX_BROADCAST_1TO32_8 BCAST=18 # 256 + + diff --git a/datafiles/avxhsw/hsw-vex-gpr-isa.txt b/datafiles/avxhsw/hsw-vex-gpr-isa.txt new file mode 100644 index 0000000..b9c9505 --- /dev/null +++ b/datafiles/avxhsw/hsw-vex-gpr-isa.txt @@ -0,0 +1,382 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + +{ +ICLASS : PDEP +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] + +#32b +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : PEXT +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] + + +#32b +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + + +{ +ICLASS : ANDN +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +# 32b +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : BLSR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q + +} + +{ +ICLASS : BLSMSK +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] + +#32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +#64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BLSI +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BZHI +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-mod ] + +# 32b +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + +{ +ICLASS : BEXTR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +# 32b +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : SHLX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SARX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SHRX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : MULX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg:w vvvv:w rm:r rdx:r +# 32b +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +# 64b +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP +} + +{ +ICLASS : RORX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change + +# 32b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +# 64b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b +} diff --git a/datafiles/avxhsw/hsw-vshift-isa.txt b/datafiles/avxhsw/hsw-vshift-isa.txt new file mode 100644 index 0000000..0521ea5 --- /dev/null +++ b/datafiles/avxhsw/hsw-vshift-isa.txt @@ -0,0 +1,121 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + + + +{ +ICLASS : VPSLLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSLLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSRLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRAVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + + diff --git a/datafiles/avxhsw/movnt-load-isa.txt b/datafiles/avxhsw/movnt-load-isa.txt new file mode 100644 index 0000000..8963979 --- /dev/null +++ b/datafiles/avxhsw/movnt-load-isa.txt @@ -0,0 +1,34 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX2 +EXCEPTIONS: avx-type-1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX + +PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + diff --git a/datafiles/avxhsw/rtm.xed b/datafiles/avxhsw/rtm.xed new file mode 100644 index 0000000..291d3dd --- /dev/null +++ b/datafiles/avxhsw/rtm.xed @@ -0,0 +1,61 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XBEGIN +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Not always a branch. If aborts, then branches & eax is written + +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP +} + +{ +ICLASS : XEND +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Transaction end. may branch +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : XABORT +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : RTM +COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b +} + + +{ +ICLASS : XTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : RTM +COMMENT : test if in RTM transaction mode +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix +OPERANDS : +} diff --git a/datafiles/avxhsw/vmfunc-isa.txt b/datafiles/avxhsw/vmfunc-isa.txt new file mode 100644 index 0000000..bf2d5d5 --- /dev/null +++ b/datafiles/avxhsw/vmfunc-isa.txt @@ -0,0 +1,29 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : VMFUNC +CPL : 3 +CATEGORY : VTX +EXTENSION : VMFUNC +ISA_SET : VMFUNC +ATTRIBUTES : +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix +OPERANDS : +} diff --git a/datafiles/avxhsw/vsib-addressing-dec.txt b/datafiles/avxhsw/vsib-addressing-dec.txt new file mode 100644 index 0000000..9d51f65 --- /dev/null +++ b/datafiles/avxhsw/vsib-addressing-dec.txt @@ -0,0 +1,112 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# SPARSE OPERATIONS REQUIRE A SPECIAL MODRM BYTE and a mandatory VSIB BYTE + +VMODRM_YMM():: + MOD=0b00 VSIB_YMM() | + MOD=0b01 VSIB_YMM() MEMDISP8() | + MOD=0b10 VSIB_YMM() MEMDISP32() | + + +VMODRM_XMM():: + MOD=0b00 VSIB_XMM() | + MOD=0b01 VSIB_XMM() MEMDISP8() | + MOD=0b10 VSIB_XMM() MEMDISP32() | + +VSIB_YMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=8 + +VSIB_XMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=8 + +xed_reg_enum_t VSIB_INDEX_YMM():: +REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0 +REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1 +REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2 +REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3 +REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4 +REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5 +REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6 +REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7 +REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8 +REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9 +REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10 +REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11 +REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12 +REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13 +REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14 +REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15 + + +xed_reg_enum_t VSIB_INDEX_XMM():: +REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0 +REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1 +REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2 +REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3 +REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4 +REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5 +REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6 +REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7 +REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8 +REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9 +REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10 +REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11 +REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12 +REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13 +REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14 +REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15 + + +VSIB_BASE():: +REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG() + + + + + + + + diff --git a/datafiles/avxhsw/vsib-addressing-enc.txt b/datafiles/avxhsw/vsib-addressing-enc.txt new file mode 100644 index 0000000..bea1d8d --- /dev/null +++ b/datafiles/avxhsw/vsib-addressing-enc.txt @@ -0,0 +1,205 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SEQUENCE VMODRM_XMM_BIND + VMODRM_MOD_ENCODE_BIND() + VSIB_ENC_BASE_BIND() + VSIB_ENC_INDEX_XMM_BIND() + VSIB_ENC_SCALE_BIND() + VSIB_ENC_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + DISP_NT_BIND() + +SEQUENCE VMODRM_YMM_BIND + VMODRM_MOD_ENCODE_BIND() + VSIB_ENC_BASE_BIND() + VSIB_ENC_INDEX_YMM_BIND() + VSIB_ENC_SCALE_BIND() + VSIB_ENC_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + DISP_NT_BIND() + +# MODRM.MOD is emitted as part of the instruction +SEQUENCE VMODRM_XMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +SEQUENCE VMODRM_YMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +###################################### +VMODRM_MOD_ENCODE():: + +# (1) no base with rBP/r13 +# Add a fake 1B displacement to rBP and r13 if they do not have one already +eamode32 DISP_WIDTH=0 BASE0=ArBP() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +eamode32 DISP_WIDTH=0 BASE0=Ar13() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +eamode64 DISP_WIDTH=0 BASE0=ArBP() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +eamode64 DISP_WIDTH=0 BASE0=Ar13() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +# (2) no disp with most base regs +# All these 32b and 64b can handle no displacement +eamode32 DISP_WIDTH=0 BASE0=ArAX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArBX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArCX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArDX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArSI() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArDI() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArSP() -> MOD=0 + +eamode32 DISP_WIDTH=0 BASE0=Ar8() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar9() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar10() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar11() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar12() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar14() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar15() mode64 -> MOD=0 + +# rBP and r13 are handled above +eamode64 DISP_WIDTH=0 BASE0=ArAX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArBX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArCX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArDX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArSI() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArDI() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArSP() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar8() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar9() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar10() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar11() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar12() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar14() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar15() -> MOD=0 + +# (3) 8b displacement +eamode32 DISP_WIDTH=8 -> MOD=1 +eamode64 DISP_WIDTH=8 BASE0=GPR64e() -> MOD=1 + + +# (4) 32b displacement with no base or some base +eamode32 DISP_WIDTH=32 BASE0=@ -> MOD=0 #no base +eamode32 DISP_WIDTH=32 BASE0=GPR32e() -> MOD=2 #some base, not RIP +eamode64 DISP_WIDTH=32 BASE0=@ -> MOD=0 #no base + +eamode64 DISP_WIDTH=32 BASE0=ArAX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArBX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArCX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArDX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArSI() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArDI() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArSP() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArBP() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar8() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar9() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar10() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar11() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar12() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar13() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar14() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar15() -> MOD=2 + +otherwise -> error + +VSIB_ENC_BASE():: + BASE0=ArAX() -> REXB=0 SIBBASE=0 + BASE0=ArCX() -> REXB=0 SIBBASE=1 + BASE0=ArDX() -> REXB=0 SIBBASE=2 + BASE0=ArBX() -> REXB=0 SIBBASE=3 + BASE0=ArSP() -> REXB=0 SIBBASE=4 + + BASE0=@ -> DISP_WIDTH_32() REXB=0 SIBBASE=5 + + # RBP/EBP or r13/r13d must have a displacement + BASE0=ArBP() -> DISP_WIDTH_8_32() REXB=0 SIBBASE=5 + + BASE0=Ar13() -> DISP_WIDTH_8_32() REXB=1 SIBBASE=5 + + + BASE0=ArSI() -> REXB=0 SIBBASE=6 + BASE0=ArDI() -> REXB=0 SIBBASE=7 + BASE0=Ar8() -> REXB=1 SIBBASE=0 + BASE0=Ar9() -> REXB=1 SIBBASE=1 + BASE0=Ar10() -> REXB=1 SIBBASE=2 + BASE0=Ar11() -> REXB=1 SIBBASE=3 + BASE0=Ar12() -> REXB=1 SIBBASE=4 + + BASE0=Ar14() -> REXB=1 SIBBASE=6 + BASE0=Ar15() -> REXB=1 SIBBASE=7 + otherwise -> error + + + + +VSIB_ENC_SCALE():: + SCALE=0 -> SIBSCALE=0 + SCALE=1 -> SIBSCALE=0 + SCALE=2 -> SIBSCALE=1 + SCALE=4 -> SIBSCALE=2 + SCALE=8 -> SIBSCALE=3 + otherwise -> error + +VSIB_ENC():: + true SIBBASE[bbb] SIBINDEX[iii] SIBSCALE[ss] -> ss_iii_bbb + + +VSIB_ENC_INDEX_XMM():: +INDEX=XED_REG_XMM0 -> REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM1 -> REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM2 -> REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM3 -> REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM4 -> REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM5 -> REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM6 -> REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM7 -> REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM8 -> REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM9 -> REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM10 -> REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM11 -> REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM12 -> REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM13 -> REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM14 -> REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM15 -> REXX=1 SIBINDEX=7 + + +VSIB_ENC_INDEX_YMM():: +INDEX=XED_REG_YMM0 -> REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM1 -> REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM2 -> REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM3 -> REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM4 -> REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM5 -> REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM6 -> REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM7 -> REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM8 -> REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM9 -> REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM10 -> REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM11 -> REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM12 -> REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM13 -> REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM14 -> REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM15 -> REXX=1 SIBINDEX=7 + + +DISP_WIDTH_8_32():: +DISP_WIDTH=8 -> nothing +DISP_WIDTH=32 -> nothing + diff --git a/datafiles/bdw/bdw-chips.txt b/datafiles/bdw/bdw-chips.txt new file mode 100644 index 0000000..f71f3f9 --- /dev/null +++ b/datafiles/bdw/bdw-chips.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# PREFETCHW semantics added to PREFETCHW opcode but not subject +# to chip-check because of prior implemntation as NOP +BROADWELL: ALL_OF(HASWELL) BDW RDSEED SMAP + diff --git a/datafiles/bdw/cpuid.xed.txt b/datafiles/bdw/cpuid.xed.txt new file mode 100644 index 0000000..451cae5 --- /dev/null +++ b/datafiles/bdw/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_BDW: adoxadcx.7.0.ebx.19 + XED_ISA_SET_RDSEED: rdseed.7.0.ebx.18 + XED_ISA_SET_SMAP: smap.7.0.ebx.20 diff --git a/datafiles/bdw/files.cfg b/datafiles/bdw/files.cfg new file mode 100644 index 0000000..acd07c6 --- /dev/null +++ b/datafiles/bdw/files.cfg @@ -0,0 +1,28 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions:lin2.xed.txt + enc-instructions:lin2.xed.txt + + dec-instructions:rdseed.xed.txt + enc-instructions:rdseed.xed.txt + + dec-instructions:smap.xed.txt + enc-instructions:smap.xed.txt + +chip-models:bdw-chips.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/bdw/lin2.xed.txt b/datafiles/bdw/lin2.xed.txt new file mode 100644 index 0000000..4fa7bdc --- /dev/null +++ b/datafiles/bdw/lin2.xed.txt @@ -0,0 +1,61 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : ADCX +CPL : 3 +CATEGORY : BDW +EXTENSION : BDW +FLAGS : MUST [ cf-tst cf-mod ] +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + + + +{ +ICLASS : ADOX +CPL : 3 +CATEGORY : BDW +EXTENSION : BDW +FLAGS : MUST [ of-tst of-mod ] +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + diff --git a/datafiles/bdw/rdseed.xed.txt b/datafiles/bdw/rdseed.xed.txt new file mode 100644 index 0000000..b2bbcc1 --- /dev/null +++ b/datafiles/bdw/rdseed.xed.txt @@ -0,0 +1,30 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDSEED +CPL : 3 +CATEGORY : RDSEED +EXTENSION : RDSEED +ISA_SET : RDSEED +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + diff --git a/datafiles/bdw/smap.xed.txt b/datafiles/bdw/smap.xed.txt new file mode 100644 index 0000000..6462b33 --- /dev/null +++ b/datafiles/bdw/smap.xed.txt @@ -0,0 +1,42 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS : CLAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-0 ] +# 0F 01 CA = 1100_1010 = 11_001_010 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : STAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-1 ] +# 0F 01 CB = 1100_1011 = 11_001_011 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix +OPERANDS : +} + diff --git a/datafiles/cpuid.xed.txt b/datafiles/cpuid.xed.txt new file mode 100644 index 0000000..3722f77 --- /dev/null +++ b/datafiles/cpuid.xed.txt @@ -0,0 +1,77 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_XSAVE: xsave.1.0.ecx.26 osxsave.1.0.ecx.27 +XED_ISA_SET_AES: aes.1.0.ecx.25 + +XED_ISA_SET_CLFSH: clflush.1.0.edx.19 + +XED_ISA_SET_CMPXCHG16B: cmpxchg16b.1.0.ecx.13 + +XED_ISA_SET_FXSAVE: fxsave.1.0.edx.24 +XED_ISA_SET_FXSAVE64: fxsave.1.0.edx.24 intel64.80000001.0.edx.29 +XED_ISA_SET_I186: n/a +XED_ISA_SET_I286PROTECTED: n/a +XED_ISA_SET_I286REAL: n/a +XED_ISA_SET_I386: n/a +XED_ISA_SET_I486: n/a +XED_ISA_SET_I486REAL: n/a +XED_ISA_SET_I86: n/a + +XED_ISA_SET_LAHF: lahf.80000001.0.ecx.0 +XED_ISA_SET_LONGMODE: intel64.80000001.0.edx.29 +XED_ISA_SET_LZCNT: lzcnt.80000001.0.ecx.5 + +XED_ISA_SET_MOVBE: movebe.1.0.ecx.22 +XED_ISA_SET_PAUSE: n/a +XED_ISA_SET_PCLMULQDQ: pclmulqdq.1.0.ecx.1 +XED_ISA_SET_PENTIUMMMX: n/a +XED_ISA_SET_PENTIUMREAL: n/a + +XED_ISA_SET_POPCNT: popcnt.1.0.ecx.23 +XED_ISA_SET_PPRO: n/a +XED_ISA_SET_PREFETCHW: prefetchw.80000001.0.ecx.8 + +XED_ISA_SET_PREFETCH_NOP: n/a +XED_ISA_SET_PT: intelpt.7.0.ebx.25 +XED_ISA_SET_RDPMC: n/a +XED_ISA_SET_RDTSCP: rdtscp.80000001.0.edx.27 + +XED_ISA_SET_SMX: smx.1.0.ecx.6 +XED_ISA_SET_SSE: sse.1.0.edx.25 +XED_ISA_SET_SSE2: sse2.1.0.edx.26 +XED_ISA_SET_SSE3: sse3.1.0.ecx.0 +XED_ISA_SET_SSE4: sse4.1.0.ecx.19 +XED_ISA_SET_SSE42: sse42.1.0.ecx.20 + +XED_ISA_SET_SSEMXCSR: sse.1.0.edx.25 +XED_ISA_SET_SSSE3: ssse3.1.0.ecx.9 + +XED_ISA_SET_VMFUNC: n/a + +XED_ISA_SET_VTX: vmx.1.0.ecx.5 +XED_ISA_SET_X87: n/a + + + +XED_ISA_SET_AMD: n/a +XED_ISA_SET_3DNOW: n/a +XED_ISA_SET_SSE4A: n/a +XED_ISA_SET_SVM: n/a + + + diff --git a/datafiles/files-amd.cfg b/datafiles/files-amd.cfg new file mode 100644 index 0000000..4f1adf4 --- /dev/null +++ b/datafiles/files-amd.cfg @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# AMD extensions + +dec-instructions : xed-amd-3dnow.txt +enc-instructions : xed-amd-3dnow.txt + +dec-instructions : xed-amd-base.txt +enc-instructions : xed-amd-base.txt + +dec-instructions : xed-amd-svm.txt +enc-instructions : xed-amd-svm.txt + +enc-instructions : xed-amd-sse4a.txt +dec-instructions : xed-amd-sse4a.txt + +enc-instructions : xed-amd-clzero.txt +dec-instructions : xed-amd-clzero.txt diff --git a/datafiles/files-xmm.cfg b/datafiles/files-xmm.cfg new file mode 100644 index 0000000..edd4a66 --- /dev/null +++ b/datafiles/files-xmm.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + registers : xed-regs-xmm.txt diff --git a/datafiles/files-xregs.cfg b/datafiles/files-xregs.cfg new file mode 100644 index 0000000..bde43bb --- /dev/null +++ b/datafiles/files-xregs.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-patterns : xed-reg-tables-xmm.txt +# decode files used for encode: +enc-dec-patterns : xed-reg-tables-xmm.txt diff --git a/datafiles/files.cfg b/datafiles/files.cfg new file mode 100644 index 0000000..553ec93 --- /dev/null +++ b/datafiles/files.cfg @@ -0,0 +1,67 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# public "base" isa configuration files + +dec-spine : xed-spine.txt + +#decoder patterns +dec-patterns : xed-prefixes.txt +dec-patterns : xed-reg-tables.txt +dec-patterns : xed-gpr8-dec-reg-table.txt + +dec-patterns : xed-eOSZ.txt +dec-patterns : xed-eASZ.txt +dec-patterns : xed-immediates.txt +dec-patterns : xed-addressing-modes-new.txt + +chip-models : xed-chips.txt +conversion-table : xed-convert.txt + +# decode patterns used for encode +enc-dec-patterns : xed-reg-tables.txt +enc-dec-patterns : xed-eASZ.txt +enc-dec-patterns : xed-immediates.txt + +# encoder patterns +enc-patterns : xed-gpr8-enc-reg-table.txt +enc-patterns : xed-modrm-encode.txt +enc-patterns : xed-prefixes-encode.txt +enc-patterns : xed-regs-enc.txt + +dec-instructions : xed-isa.txt +enc-instructions : xed-isa.txt + +dec-instructions : xed-amd-prefetch.txt +enc-instructions : xed-amd-prefetch.txt + +enc-instructions : xed-nops.txt +fields : xed-fields.txt +state : xed-state-bits.txt +registers : xed-regs.txt +registers : knc-kregs.txt + +element-types : xed-operand-types.txt +element-type-base : xed-operand-element-type-enum-base.txt +widths : xed-operand-width.txt +# extra widths for NTs and REGs that do not have them +extra-widths: oc2-extras.txt + +pointer-names : xed-pointer-width.txt + +ild-scanners: xed-ild-scanners.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/glm/files.cfg b/datafiles/glm/files.cfg new file mode 100644 index 0000000..63c020c --- /dev/null +++ b/datafiles/glm/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + chip-models:glm-chips.txt + diff --git a/datafiles/glm/glm-chips.txt b/datafiles/glm/glm-chips.txt new file mode 100644 index 0000000..825e8bc --- /dev/null +++ b/datafiles/glm/glm-chips.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# Requires IVB for RDWRFSGS, BDW for RDSEED, SMAP +GOLDMONT: ALL_OF(SILVERMONT) MPX SHA RDSEED RDWRFSGS \ + XSAVE XSAVEOPT XSAVEC XSAVES SMAP diff --git a/datafiles/ild/include/xed-ild-scanners-base.h b/datafiles/ild/include/xed-ild-scanners-base.h new file mode 100755 index 0000000..31dce2c --- /dev/null +++ b/datafiles/ild/include/xed-ild-scanners-base.h @@ -0,0 +1,62 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-ild-scanners.h +/// instruction length decoder scanners + +#if !defined(_XED_ILD_SCANNERS_BASE_H_) +# define _XED_ILD_SCANNERS_BASE_H_ +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-types.h" + +void xed_ild_scanners_init(void) { + xed_ild_operator_init(&prefix_op,"prefix", prefix_scanner); + +#if defined(XED_AVX) + xed_ild_operator_init(&vex_op,"vex", vex_scanner); + + xed_ild_operator_init(&vex_opcode_op, "vex_opcode", vex_opcode_scanner); +# if defined(XED_AMD_ENABLED) + xed_ild_operator_init(&xop_op, "xop_opcode", xop_scanner); +# endif + xed_ild_operator_init(&vex_c4_op, "vex_c4_opcode", vex_c4_scanner); + xed_ild_operator_init(&vex_c5_op, "vex_c5_opcode", vex_c5_scanner); +#endif + + xed_ild_operator_init(&opcode_op,"opcode", opcode_scanner); + xed_ild_operator_init(&modrm_op,"modrm", modrm_scanner); + xed_ild_operator_init(&sib_op,"sib", sib_scanner); + xed_ild_operator_init(&disp_op,"disp", disp_scanner); + xed_ild_operator_init(&imm_op,"imm", imm_scanner); + + xed_add_ild_operator(&prefix_op); +#if defined(XED_AVX) + xed_add_ild_operator(&vex_op); +#endif + xed_add_ild_operator(&opcode_op); + xed_add_ild_operator(&modrm_op); + xed_add_ild_operator(&sib_op); + xed_add_ild_operator(&disp_op); + xed_add_ild_operator(&imm_op); +} + + +#endif + diff --git a/datafiles/ivbavx/cpuid.xed.txt b/datafiles/ivbavx/cpuid.xed.txt new file mode 100644 index 0000000..ca0a277 --- /dev/null +++ b/datafiles/ivbavx/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_F16C: f16c.1.0.ecx.29 diff --git a/datafiles/ivbavx/files.cfg b/datafiles/ivbavx/files.cfg new file mode 100644 index 0000000..50f4eec --- /dev/null +++ b/datafiles/ivbavx/files.cfg @@ -0,0 +1,26 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + chip-models:ivb-chips.txt + dec-instructions:fp16-isa.txt + enc-instructions:fp16-isa.txt + + element-types:fp16-operand-types.txt +element-type-base:fp16-element-type-enum.txt + + +cpuid : cpuid.xed.txt diff --git a/datafiles/ivbavx/fp16-element-type-enum.txt b/datafiles/ivbavx/fp16-element-type-enum.txt new file mode 100644 index 0000000..0e009b5 --- /dev/null +++ b/datafiles/ivbavx/fp16-element-type-enum.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +FLOAT16 ///< 16b floating point + diff --git a/datafiles/ivbavx/fp16-isa.txt b/datafiles/ivbavx/fp16-isa.txt new file mode 100644 index 0000000..df8c407 --- /dev/null +++ b/datafiles/ivbavx/fp16-isa.txt @@ -0,0 +1,71 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VCVTPH2PS +COMMENT : UPCONVERT -- NO IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b form + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 + + +# 256b form + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16 +} + + +{ +ICLASS : VCVTPS2PH +COMMENT : DOWNCONVERT -- HAS IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b imm8 form + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b + +# 256b imm8 form + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b + +} + diff --git a/datafiles/ivbavx/fp16-operand-types.txt b/datafiles/ivbavx/fp16-operand-types.txt new file mode 100644 index 0000000..1bc22f1 --- /dev/null +++ b/datafiles/ivbavx/fp16-operand-types.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +f16 FLOAT16 16 + diff --git a/datafiles/ivbavx/ivb-chips.txt b/datafiles/ivbavx/ivb-chips.txt new file mode 100644 index 0000000..fe94dad --- /dev/null +++ b/datafiles/ivbavx/ivb-chips.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +IVYBRIDGE: ALL_OF(SANDYBRIDGE) RDRAND F16C RDWRFSGS diff --git a/datafiles/ivbint/cpuid.xed.txt b/datafiles/ivbint/cpuid.xed.txt new file mode 100644 index 0000000..84ab53a --- /dev/null +++ b/datafiles/ivbint/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_RDWRFSGS: rdwrfsgs.7.0.ebx.0 +XED_ISA_SET_RDRAND: rdrand.1.0.ecx.30 diff --git a/datafiles/ivbint/files.cfg b/datafiles/ivbint/files.cfg new file mode 100644 index 0000000..8aee599 --- /dev/null +++ b/datafiles/ivbint/files.cfg @@ -0,0 +1,26 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions:ivb-int-isa.txt + enc-instructions:ivb-int-isa.txt + dec-instructions:fsgsbase-isa.txt + enc-instructions:fsgsbase-isa.txt + registers:ivb-regs.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/ivbint/fsgsbase-isa.txt b/datafiles/ivbint/fsgsbase-isa.txt new file mode 100644 index 0000000..c756660 --- /dev/null +++ b/datafiles/ivbint/fsgsbase-isa.txt @@ -0,0 +1,65 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + + +{ +ICLASS : RDFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y + +} +{ +ICLASS : RDGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y + +} + + + +{ +ICLASS : WRFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y + +} +{ +ICLASS : WRGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y + +} diff --git a/datafiles/ivbint/ivb-int-isa.txt b/datafiles/ivbint/ivb-int-isa.txt new file mode 100644 index 0000000..a1032e6 --- /dev/null +++ b/datafiles/ivbint/ivb-int-isa.txt @@ -0,0 +1,30 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDRAND +CPL : 3 +CATEGORY : RDRAND +EXTENSION : RDRAND +ISA_SET : RDRAND +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + diff --git a/datafiles/ivbint/ivb-regs.txt b/datafiles/ivbint/ivb-regs.txt new file mode 100644 index 0000000..453f705 --- /dev/null +++ b/datafiles/ivbint/ivb-regs.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +FSBASE pseudo NA +GSBASE pseudo NA diff --git a/datafiles/knc-kregs.txt b/datafiles/knc-kregs.txt new file mode 100644 index 0000000..8b9d4e6 --- /dev/null +++ b/datafiles/knc-kregs.txt @@ -0,0 +1,25 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +K0 mask 16 K0 0 +K1 mask 16 K1 1 +K2 mask 16 K2 2 +K3 mask 16 K3 3 +K4 mask 16 K4 4 +K5 mask 16 K5 5 +K6 mask 16 K6 6 +K7 mask 16 K7 7 diff --git a/datafiles/knc/files-no-avx512f.cfg b/datafiles/knc/files-no-avx512f.cfg new file mode 100644 index 0000000..1efa722 --- /dev/null +++ b/datafiles/knc/files-no-avx512f.cfg @@ -0,0 +1,60 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# LRB2.7/KNC standalone + + add:dec-spine:uisa-spine.txt:3 + state:uisa-state-bits.txt + fields:knc-fields-no-avx512f.txt + fields:knc-fields-with-avx512f.txt + + dec-patterns:knc-evex-dec.txt # knc splitter augmentation + enc-patterns:knc-evex-enc-top.txt # vex and evex prefixes + enc-patterns:knc-evex-enc.txt # knc evex prefixes + + dec-patterns:lrb2-converts.txt + enc-dec-patterns:lrb2-converts.txt + conversion-table:lrb2-strings.txt + chip-models:lrb2-chips.txt + + widths:uisa-operand-widths.txt + + dec-patterns:lrb2-addressing-dec.txt + enc-patterns:lrb2-addressing-enc.txt + + dec-patterns:uisa-splitter.txt + +# These do not have the XMM/YMM regs + registers:lrb2-regs.txt + dec-patterns:lrb2-evex-reg-tables.txt + enc-dec-patterns:lrb2-evex-reg-tables.txt + +# instructions + dec-instructions:lrb2-scalar-mask-isa.txt + enc-instructions:lrb2-scalar-mask-isa.txt + dec-instructions:jkbr-isa.txt + enc-instructions:jkbr-isa.txt + dec-instructions:lrb2-evex-isa.txt + enc-instructions:lrb2-evex-isa.txt + dec-instructions:knc-streaming-isa.txt + enc-instructions:knc-streaming-isa.txt + dec-instructions:knc-nop-isa.txt + enc-instructions:knc-nop-isa.txt + +# we change two functions for LRB/UISA for the N*disp8 scaling + remove-source:source:xed-operand-values-interface-repl.c + add-source:source:xed-operand-values-interface-uisa.c diff --git a/datafiles/knc/files-with-avx512f.cfg b/datafiles/knc/files-with-avx512f.cfg new file mode 100644 index 0000000..6f73623 --- /dev/null +++ b/datafiles/knc/files-with-avx512f.cfg @@ -0,0 +1,48 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# LRB2.7/KNC standalone + + state:uisa-state-bits.txt + fields:knc-fields-with-avx512f.txt + chip-models:lrb2-chips.txt + + dec-patterns:lrb2-converts.txt + enc-dec-patterns:lrb2-converts.txt + conversion-table:lrb2-strings.txt + + widths:uisa-operand-widths.txt + + dec-patterns:lrb2-addressing-dec.txt + enc-patterns:lrb2-addressing-enc.txt + + dec-patterns:knc-evex-dec.txt # knc splitter augmentation + enc-patterns:knc-evex-enc.txt # knc evex encoding + + dec-instructions:lrb2-scalar-mask-isa.txt + enc-instructions:lrb2-scalar-mask-isa.txt + dec-instructions:jkbr-isa.txt + enc-instructions:jkbr-isa.txt + dec-instructions:lrb2-evex-isa.txt + enc-instructions:lrb2-evex-isa.txt + dec-instructions:knc-streaming-isa.txt + enc-instructions:knc-streaming-isa.txt + # omitting the knc-standard dropping of most fat nops because KNC + # drops many nops which other chips implement. + + + diff --git a/datafiles/knc/jkbr-isa.txt b/datafiles/knc/jkbr-isa.txt new file mode 100644 index 0000000..398edd4 --- /dev/null +++ b/datafiles/knc/jkbr-isa.txt @@ -0,0 +1,79 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + +{ +ICLASS: JKNZD +CPL: 3 +CATEGORY: COND_BR +EXTENSION: KNCV +ISA_SET: KNCJKBR +PATTERN: VV1 0x75 VNP VMAP0 W0 BRDISP8() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:b +IFORM: JKNZD_MASKmskw_RELBRb_KNC + +} + +{ +ICLASS: JKNZD +CPL: 3 +CATEGORY: COND_BR +EXTENSION: KNCV +ISA_SET: KNCJKBR + +PATTERN: VV1 0x85 VNP not64 V0F W0 BRDISPz() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:z + +PATTERN: VV1 0x85 VNP mode64 V0F W0 BRDISP32() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:z + +IFORM: JKNZD_MASKmskw_RELBRz_KNC + +} + +{ +ICLASS: JKZD +CPL: 3 +CATEGORY: COND_BR +EXTENSION: KNCV +ISA_SET: KNCJKBR +PATTERN: VV1 0x74 VNP VMAP0 W0 BRDISP8() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:b +IFORM: JKZD_MASKmskw_RELBRb_KNC + +} + + +{ +ICLASS: JKZD +CPL: 3 +CATEGORY: COND_BR +EXTENSION: KNCV +ISA_SET: KNCJKBR + +PATTERN: VV1 0x84 not64 VNP V0F W0 BRDISPz() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:z + +PATTERN: VV1 0x84 mode64 VNP V0F W0 BRDISP32() +OPERANDS: REG0=MASK_N():w:mskw RELBR:r:z + +IFORM: JKZD_MASKmskw_RELBRz_KNC + +} + diff --git a/datafiles/knc/knc-evex-dec.txt b/datafiles/knc/knc-evex-dec.txt new file mode 100644 index 0000000..32848bb --- /dev/null +++ b/datafiles/knc/knc-evex-dec.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +EVEX_SPLITTER():: +VEXVALID=4 KNC_EVEX_INSTRUCTIONS() | + + diff --git a/datafiles/knc/knc-evex-enc-top.txt b/datafiles/knc/knc-evex-enc-top.txt new file mode 100644 index 0000000..eace8a2 --- /dev/null +++ b/datafiles/knc/knc-evex-enc-top.txt @@ -0,0 +1,32 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! GSSE instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() diff --git a/datafiles/knc/knc-evex-enc.txt b/datafiles/knc/knc-evex-enc.txt new file mode 100644 index 0000000..7c19d07 --- /dev/null +++ b/datafiles/knc/knc-evex-enc.txt @@ -0,0 +1,110 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! GSSE instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() + +VEXED_REX():: +VEXVALID=4 -> KNC_EVEX_ENC() + + +################################################# +SEQUENCE KNC_EVEX_ENC_BIND + # R,X,B R map (byte 1) + # W, vvvv, L, pp (byte 2) + # NR, sss, V', kkk ( byte 3) + EVEX_62_REXR_ENC_BIND + EVEX_REXX_ENC_BIND + EVEX_REXB_ENC_BIND + EVEX_REXRR_ENC_BIND + EVEX_MAP_ENC_BIND + EVEX_REXW_VVVV_ENC_BIND + EVEX_ESCVL_ENC_BIND + EVEX_BYTE3_ENC_BIND + + +SEQUENCE KNC_EVEX_ENC_EMIT + EVEX_62_REXR_ENC_EMIT + EVEX_REXX_ENC_EMIT + EVEX_REXB_ENC_EMIT + EVEX_REXRR_ENC_EMIT + EVEX_MAP_ENC_EMIT + EVEX_REXW_VVVV_ENC_EMIT + EVEX_ESCVL_ENC_EMIT + EVEX_BYTE3_ENC_EMIT + + +EVEX_62_REXR_ENC():: +mode64 REXR=1 -> 0x62 0b0 +mode64 REXR=0 -> 0x62 0b1 +mode32 REXR=1 -> error +mode32 REXR=0 -> 0x62 0b1 + +EVEX_REXX_ENC():: +mode64 REXX=1 -> 0b0 +mode64 REXX=0 -> 0b1 +mode32 REXX=1 -> error +mode32 REXX=0 -> 0b1 + +EVEX_REXB_ENC():: +mode64 REXB=1 -> 0b0 +mode64 REXB=0 -> 0b1 +mode32 REXB=1 -> error +mode32 REXB=0 -> 0b1 + +EVEX_REXRR_ENC():: +mode64 REXRR=1 -> 0b0 +mode64 REXRR=0 -> 0b1 +mode32 REXRR=1 -> error +mode32 REXRR=0 -> 0b1 + +EVEX_MAP_ENC():: +MAP=0 -> 0b0000 +MAP=1 -> 0b0001 +MAP=2 -> 0b0010 +MAP=3 -> 0b0011 + +EVEX_REXW_VVVV_ENC():: +mode64 REXW[w] VEXDEST3[u] VEXDEST210[ddd] -> w u_ddd +mode32 REXW[w] VEXDEST3[u]=1 VEXDEST210[ddd] -> w u_ddd +mode32 REXW[w] VEXDEST3[u]=0 VEXDEST210[ddd] -> error + +#include the required zero bit before the pp bits +EVEX_ESCVL_ENC():: + VNP -> 0b000 + V66 -> 0b001 + VF3 -> 0b010 + VF2 -> 0b011 + +EVEX_BYTE3_ENC():: +NR[n] SWIZ[sss] VEXDEST4=0 MASK[kkk] -> n_sss 1_ kkk +NR[n] SWIZ[sss] VEXDEST4=1 MASK[kkk] -> n_sss 0_ kkk + diff --git a/datafiles/knc/knc-fields-no-avx512f.txt b/datafiles/knc/knc-fields-no-avx512f.txt new file mode 100644 index 0000000..b81e083 --- /dev/null +++ b/datafiles/knc/knc-fields-no-avx512f.txt @@ -0,0 +1,37 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# ==== ==== ========= ========== ============== +# default +# name type bit-width visibility behavior +# ==== ==== ========= ========== ============== +REXRR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +VEXDEST4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# bit3 of the immediate field used as high bit of register source +ESRC3 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +MASK SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +ROUNDC SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +SAE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +UBIT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# for the loadunpack and pack store instructions where +# we do not scale displacement by the number of elements.. +NO_SCALE_DISP8 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + diff --git a/datafiles/knc/knc-fields-with-avx512f.txt b/datafiles/knc/knc-fields-with-avx512f.txt new file mode 100644 index 0000000..5a19f68 --- /dev/null +++ b/datafiles/knc/knc-fields-with-avx512f.txt @@ -0,0 +1,30 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# ==== ==== ========= ========== ============== +# default +# name type bit-width visibility behavior +# ==== ==== ========= ========== ============== +SWIZ SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EI +NR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +NT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + +SWIZZLE_SIZE SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +CONVERT SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +REGSWIZ SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +# we get BCAST from the AVX grammar now. diff --git a/datafiles/knc/knc-nop-isa.txt b/datafiles/knc/knc-nop-isa.txt new file mode 100644 index 0000000..e0cce93 --- /dev/null +++ b/datafiles/knc/knc-nop-isa.txt @@ -0,0 +1,51 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +UDELETE : NOP0F18 +UDELETE : NOP0F19 +UDELETE : NOP0F1A +UDELETE : NOP0F1B +UDELETE : NOP0F1C +UDELETE : NOP0F1D +UDELETE : NOP0F1E +UDELETE : NOP0F1F +# only have to detete the NOP version to avoid using this as a fat nop +# when encoding. +UDELETE : NOP0F0D_reg + + +{ +ICLASS : NOP +UNAME : NOP0F1FKNC +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : KNC_MISC + +PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_GPRv_0F1F + +PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_GPRv_0F1F +} + + diff --git a/datafiles/knc/knc-streaming-isa.txt b/datafiles/knc/knc-streaming-isa.txt new file mode 100644 index 0000000..1c2a0d4 --- /dev/null +++ b/datafiles/knc/knc-streaming-isa.txt @@ -0,0 +1,73 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +KNC_EVEX_INSTRUCTIONS():: + +# VMOVNRA{PS,PD} PD = F3 0F W1 EH0 29 +# PS = F2 0F W0 EH0 29 + +# VMOVNRNGOA{PS,PD} PD = F3 0F W1 EH1 29 +# PS = F2 0F W0 EH1 29 + +{ +ICLASS : VMOVNRAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCSTREAM +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV REQUIRES_ALIGNMENT +# store to memory +PATTERN : KVV 0x29 V0F VF2 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] NR=0 MODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:rw:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +} +{ +ICLASS : VMOVNRNGOAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCSTREAM +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV REQUIRES_ALIGNMENT +# store to memory +PATTERN : KVV 0x29 V0F VF2 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] NR=1 MODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:rw:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +} + +{ +ICLASS : VMOVNRAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCSTREAM +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV KNC_F64 REQUIRES_ALIGNMENT +# store to memory, no legal down convert. +PATTERN : KVV 0x29 V0F VF3 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] NR=0 MODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:rw:zf64:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +} +{ +ICLASS : VMOVNRNGOAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCSTREAM +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV KNC_F64 REQUIRES_ALIGNMENT +# store to memory, no legal down convert. +PATTERN : KVV 0x29 V0F VF3 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] NR=1 MODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:rw:zf64:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +} + diff --git a/datafiles/knc/lrb2-addressing-dec.txt b/datafiles/knc/lrb2-addressing-dec.txt new file mode 100644 index 0000000..44116ca --- /dev/null +++ b/datafiles/knc/lrb2-addressing-dec.txt @@ -0,0 +1,98 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +KNC_VMODRM():: + MOD=0b00 KNC_VSIB() | + MOD=0b01 KNC_VSIB() MEMDISP8() | + MOD=0b10 KNC_VSIB() MEMDISP32() | + + +KNC_VSIB():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE() | INDEX=KNC_VSIB_INDEX() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE() | INDEX=KNC_VSIB_INDEX() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE() | INDEX=KNC_VSIB_INDEX() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] KNC_VSIB_BASE() | INDEX=KNC_VSIB_INDEX() SCALE=8 + + +xed_reg_enum_t KNC_VSIB_INDEX():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM31 + + +KNC_VSIB_BASE():: +REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG() + + + + + + + + diff --git a/datafiles/knc/lrb2-addressing-enc.txt b/datafiles/knc/lrb2-addressing-enc.txt new file mode 100644 index 0000000..ad7bcf6 --- /dev/null +++ b/datafiles/knc/lrb2-addressing-enc.txt @@ -0,0 +1,67 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SEQUENCE KNC_VMODRM_BIND + VMODRM_MOD_ENCODE_BIND() + VSIB_ENC_BASE_BIND() + KNC_ENC_INDEX_BIND() + VSIB_ENC_SCALE_BIND() + VSIB_ENC_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + DISP_NT_BIND() + +SEQUENCE KNC_VMODRM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + + +KNC_ENC_INDEX():: + INDEX=XED_REG_ZMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 + INDEX=XED_REG_ZMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 + INDEX=XED_REG_ZMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 + INDEX=XED_REG_ZMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 + INDEX=XED_REG_ZMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 + INDEX=XED_REG_ZMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 + INDEX=XED_REG_ZMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 + INDEX=XED_REG_ZMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 + INDEX=XED_REG_ZMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 + INDEX=XED_REG_ZMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 + INDEX=XED_REG_ZMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 + INDEX=XED_REG_ZMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 + INDEX=XED_REG_ZMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 + INDEX=XED_REG_ZMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 + INDEX=XED_REG_ZMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 + INDEX=XED_REG_ZMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 + INDEX=XED_REG_ZMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 + INDEX=XED_REG_ZMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 + INDEX=XED_REG_ZMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 + INDEX=XED_REG_ZMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 + INDEX=XED_REG_ZMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 + INDEX=XED_REG_ZMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 + INDEX=XED_REG_ZMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 + INDEX=XED_REG_ZMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 + INDEX=XED_REG_ZMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 + INDEX=XED_REG_ZMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 + INDEX=XED_REG_ZMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 + INDEX=XED_REG_ZMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 + INDEX=XED_REG_ZMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 + INDEX=XED_REG_ZMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 + INDEX=XED_REG_ZMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 + INDEX=XED_REG_ZMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 + + diff --git a/datafiles/knc/lrb2-chips.txt b/datafiles/knc/lrb2-chips.txt new file mode 100644 index 0000000..7c8a587 --- /dev/null +++ b/datafiles/knc/lrb2-chips.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# does not include cmpxchg16B + +KNC: ALL_OF(PENTIUM) KNCE KNCV KNCJKBR SSEMXCSR LONGMODE KNCSTREAM KNC_PF_HINT KNC_MISC FXSAVE FXSAVE64 diff --git a/datafiles/knc/lrb2-converts.txt b/datafiles/knc/lrb2-converts.txt new file mode 100644 index 0000000..c105318 --- /dev/null +++ b/datafiles/knc/lrb2-converts.txt @@ -0,0 +1,304 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +NOSWIZD():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +NOSWIZF32():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +NOSWIZQ():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +UPCONVERT_FLT64():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_DOUBLE +SWIZ=0b001 | CONVERT=1 ELEMENT_SIZE=64 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_DOUBLE +SWIZ=0b010 | CONVERT=2 ELEMENT_SIZE=64 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_DOUBLE +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +UPCONVERT_FLT64_LOAD():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_DOUBLE +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +### + + + + +UPCONVERT_FLT32():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | CONVERT=9 ELEMENT_SIZE=32 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b011 | CONVERT=3 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_FLOAT16 +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b101 | CONVERT=5 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + + +UPCONVERT_FLT32_LIMITED():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | error +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +# VCVTPS2PD has special upconvert semantics +UPCONVERT_FLT32_HALF():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | CONVERT=9 ELEMENT_SIZE=32 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + + +UPCONVERT_FLT32_LOAD():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | CONVERT=3 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_FLOAT16 +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +# +# SPECIAL CASE: f32 loads use int8 for case 5 +# +SWIZ=0b101 | CONVERT=8 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +# +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + +### + + +UPCONVERT_INT64():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | CONVERT=1 ELEMENT_SIZE=64 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b010 | CONVERT=2 ELEMENT_SIZE=64 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +UPCONVERT_INT64_LOAD():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +### + +UPCONVERT_INT32():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | CONVERT=9 ELEMENT_SIZE=32 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b011 | error +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b101 | CONVERT=5 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + + +UPCONVERT_INT32_LIMITED():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | error +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + + + +# VCVTDQ2PD and VCVTUDQ2PD have special upconvert restrictions +UPCONVERT_INT32_HALF():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | CONVERT=9 ELEMENT_SIZE=32 NELEM=1 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b010 | CONVERT=10 ELEMENT_SIZE=32 NELEM=4 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +UPCONVERT_INT32_LOAD():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b101 | CONVERT=5 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + + +### + +DNCONVERT_FLT32():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_SINGLE +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | CONVERT=3 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_FLOAT16 +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b101 | CONVERT=5 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + + + + + +### + +DNCONVERT_INT32():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=32 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | CONVERT=4 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b101 | CONVERT=5 ELEMENT_SIZE=8 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b110 | CONVERT=6 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_UINT +SWIZ=0b111 | CONVERT=7 ELEMENT_SIZE=16 NELEM=16 TYPE=XED_OPERAND_ELEMENT_TYPE_INT + +DNCONVERT_INT64():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_INT +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +DNCONVERT_FLT64():: +SWIZ=0b000 | CONVERT=0 ELEMENT_SIZE=64 NELEM=8 TYPE=XED_OPERAND_ELEMENT_TYPE_DOUBLE +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + + +############################# + +REG_SWIZZLE64():: +SWIZ=0b000 | REGSWIZ=0 SWIZZLE_SIZE=8 NELEM=4 +SWIZ=0b001 | REGSWIZ=1 SWIZZLE_SIZE=8 NELEM=4 +SWIZ=0b010 | REGSWIZ=2 SWIZZLE_SIZE=8 NELEM=4 +SWIZ=0b011 | REGSWIZ=3 SWIZZLE_SIZE=8 NELEM=4 +SWIZ=0b100 | REGSWIZ=4 SWIZZLE_SIZE=8 NELEM=1 +SWIZ=0b101 | REGSWIZ=5 SWIZZLE_SIZE=8 NELEM=1 +SWIZ=0b110 | REGSWIZ=6 SWIZZLE_SIZE=8 NELEM=1 +SWIZ=0b111 | REGSWIZ=7 SWIZZLE_SIZE=8 NELEM=1 + +REG_SWIZZLE32():: +SWIZ=0b000 | REGSWIZ=0 SWIZZLE_SIZE=7 NELEM=4 +SWIZ=0b001 | REGSWIZ=1 SWIZZLE_SIZE=7 NELEM=4 +SWIZ=0b010 | REGSWIZ=2 SWIZZLE_SIZE=7 NELEM=4 +SWIZ=0b011 | REGSWIZ=3 SWIZZLE_SIZE=7 NELEM=4 +SWIZ=0b100 | REGSWIZ=4 SWIZZLE_SIZE=7 NELEM=1 +SWIZ=0b101 | REGSWIZ=5 SWIZZLE_SIZE=7 NELEM=1 +SWIZ=0b110 | REGSWIZ=6 SWIZZLE_SIZE=7 NELEM=1 +SWIZ=0b111 | REGSWIZ=7 SWIZZLE_SIZE=7 NELEM=1 + + +### + +KNC_SAE():: +SWIZ=0b000 | SAE=0 +SWIZ=0b001 | SAE=0 +SWIZ=0b010 | SAE=0 +SWIZ=0b011 | SAE=0 +SWIZ=0b100 | SAE=1 +SWIZ=0b101 | SAE=1 +SWIZ=0b110 | SAE=1 +SWIZ=0b111 | SAE=1 + +NOSAE():: +SWIZ=0b000 | +SWIZ=0b001 | +SWIZ=0b010 | +SWIZ=0b011 | +SWIZ=0b100 | error +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + +ROUND():: +SWIZ=0b000 | ROUNDC=1 +SWIZ=0b001 | ROUNDC=2 +SWIZ=0b010 | ROUNDC=3 +SWIZ=0b011 | ROUNDC=4 +SWIZ=0b100 | ROUNDC=1 +SWIZ=0b101 | ROUNDC=2 +SWIZ=0b110 | ROUNDC=3 +SWIZ=0b111 | ROUNDC=4 + +NOROUND():: +SWIZ=0b000 | +SWIZ=0b001 | error +SWIZ=0b010 | error +SWIZ=0b011 | error +SWIZ=0b100 | +SWIZ=0b101 | error +SWIZ=0b110 | error +SWIZ=0b111 | error + diff --git a/datafiles/knc/lrb2-evex-isa.txt b/datafiles/knc/lrb2-evex-isa.txt new file mode 100644 index 0000000..8ed34f7 --- /dev/null +++ b/datafiles/knc/lrb2-evex-isa.txt @@ -0,0 +1,2735 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +KNC_EVEX_INSTRUCTIONS():: + + +{ +ICLASS : VADDPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x58 V0F VNP REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x58 V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x58 V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VADDPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x58 V0F V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x58 V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x58 V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VGMAXPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x53 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x53 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x53 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VGMAXPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x53 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x53 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x53 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=SAEC +} +{ +ICLASS : VGMINPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x52 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x52 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x52 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VGMINPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x52 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x52 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x52 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=SAEC +} +{ +ICLASS : VBLENDMPS +CPL : 3 +CATEGORY : BLEND +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX MASK_AS_CONTROL +PATTERN : KVV 0x65 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x65 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x65 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VBLENDMPD +CPL : 3 +CATEGORY : BLEND +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x65 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x65 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x65 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + + +{ +ICLASS : VADDNPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x50 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x50 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x50 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VADDNPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x50 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x50 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x50 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + + +{ +ICLASS : VSUBPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x5C V0F VNP REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x5C V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x5C V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VSUBPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x5C V0F V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x5C V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x5C V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VSUBRPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x6D V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x6D V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x6D V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VSUBRPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x6D V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x6D V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x6D V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VMULPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x59 V0F VNP REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x59 V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x59 V0F VNP REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VMULPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x59 V0F V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x59 V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x59 V0F V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VGMAXABSPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x51 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x51 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x51 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=SAEC +} + +{ +ICLASS : VFMADD233PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xA4 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LIMITED() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xA4 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xA4 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMADD132PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x98 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x98 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x98 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMADD132PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x98 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x98 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x98 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFMADD213PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xA8 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xA8 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xA8 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMADD213PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xA8 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xA8 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xA8 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFMADD231PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xB8 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xB8 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xB8 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMADD231PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xB8 V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xB8 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xB8 V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMADD132PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9C V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x9C V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x9C V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMADD132PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9C V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x9C V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x9C V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFNMADD213PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAC V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xAC V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xAC V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMADD213PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAC V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xAC V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xAC V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFNMADD231PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBC V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xBC V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xBC V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMADD231PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBC V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xBC V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xBC V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMSUB132PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9A V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x9A V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x9A V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMSUB132PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9A V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x9A V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x9A V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFMSUB213PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAA V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xAA V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xAA V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMSUB213PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAA V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xAA V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xAA V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFMSUB231PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBA V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xBA V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xBA V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFMSUB231PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBA V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xBA V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xBA V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMSUB132PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9E V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x9E V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x9E V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMSUB132PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x9E V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x9E V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x9E V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFNMSUB213PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAE V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xAE V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xAE V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMSUB213PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xAE V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xAE V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xAE V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VFNMSUB231PS +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBE V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xBE V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xBE V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} + +{ +ICLASS : VFNMSUB231PD +CPL : 3 +CATEGORY : UFMA +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xBE V0F38 V66 REXW=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xBE V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xBE V0F38 V66 REXW=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + + + +{ +ICLASS : VMOVAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV REQUIRES_ALIGNMENT MASKOP_EVEX +# load from memory +PATTERN : KVV 0x28 V0F VNP REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register +PATTERN : KVV 0x28 V0F VNP REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ + +# load from register +PATTERN : KVV 0x28 V0F VNP REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 +} +{ +ICLASS : VMOVAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +# load from memory +PATTERN : KVV 0x28 V0F V66 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register +PATTERN : KVV 0x28 V0F V66 REXW=1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ + +# load from register +PATTERN : KVV 0x28 V0F V66 REXW=1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 +} +{ +ICLASS : VMOVAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV REQUIRES_ALIGNMENT MASKOP_EVEX +# store to memory +PATTERN : KVV 0x29 V0F VNP REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +} +{ +ICLASS : VMOVAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_VMOV KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +# store to memory, no legal down convert. +PATTERN : KVV 0x29 V0F V66 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:w:zf64:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +} + + + +## + + + + + + +## + + + + + +{ +ICLASS : VMOVDQA32 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_VMOV REQUIRES_ALIGNMENT MASKOP_EVEX +# load from memory +PATTERN : KVV 0x6F V0F V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register +PATTERN : KVV 0x6F V0F V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=REGSWIZ + +# load from register +PATTERN : KVV 0x6F V0F V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd +} +{ +ICLASS : VMOVDQA64 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_VMOV KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX +# load from memory +PATTERN : KVV 0x6F V0F V66 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register +PATTERN : KVV 0x6F V0F V66 REXW=1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():r:mskw REG2=ZMM_B3():r:zq:TXT=REGSWIZ + +# load from register +PATTERN : KVV 0x6F V0F V66 REXW=1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():r:mskw REG2=ZMM_B3():r:zq +} +{ +ICLASS : VMOVDQA32 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_VMOV REQUIRES_ALIGNMENT MASKOP_EVEX +# store to memory +PATTERN : KVV 0x7F V0F V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT32() +OPERANDS : MEM0:w:zv:TXT=NT:TXT=CONVERT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zd +} +{ +ICLASS : VMOVDQA64 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_VMOV KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX +# store to memory, no legal down convert. +PATTERN : KVV 0x7F V0F V66 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT64() +OPERANDS : MEM0:w:zq:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zq +} + + + + + + + + + + + + + + + + + + + + + + + +# this one writes the mask +{ +ICLASS : VPADDSETSD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCD V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xCD V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xCD V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +{ +ICLASS : VFIXUPNANPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x55 V0F38 REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x55 V0F38 REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x55 V0F38 REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=SAEC +} +{ +ICLASS : VFIXUPNANPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x55 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x55 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x55 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=SAEC +} +{ +ICLASS : VSCALEPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x84 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x84 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x84 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMADD231D +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xB5 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xB5 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xB5 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMADD233D +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xB4 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LIMITED() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xB4 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xB4 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMAXSD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x3D V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x3D V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x3D V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMAXUD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x3F V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x3F V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x3F V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMINSD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x39 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x39 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x39 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPMINUD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x3B V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x3B V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x3B V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +{ +ICLASS : VPBLENDMD +CPL : 3 +CATEGORY : BLEND +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX MASK_AS_CONTROL + +PATTERN : KVV 0x64 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x64 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x64 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPBLENDMQ +CPL : 3 +CATEGORY : BLEND +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX MASK_AS_CONTROL + +PATTERN : KVV 0x64 V0F38 REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x64 V0F38 REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x64 V0F38 REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +} +{ +ICLASS : VPANDD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xDB V0F REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xDB V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xDB V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPANDQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xDB V0F REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xDB V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xDB V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +} +{ +ICLASS : VPANDND +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xDF V0F REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xDF V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xDF V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPANDNQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xDF V0F REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xDF V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xDF V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +} +{ +ICLASS : VPORD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xEB V0F REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xEB V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xEB V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPORQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xEB V0F REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xEB V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xEB V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +} +{ +ICLASS : VPXORD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xEF V0F REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xEF V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xEF V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPXORQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xEF V0F REXW=1 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xEF V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0xEF V0F REXW=1 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +} + + +{ +ICLASS : VPADDD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xFE V0F REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xFE V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xFE V0F REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPSUBD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xFA V0F V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0xFA V0F V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0xFA V0F V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} +{ +ICLASS : VPSUBRD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x6C V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x6C V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x6C V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + + +{ +ICLASS : VPMULLD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x40 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x40 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x40 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +{ +ICLASS : VPMULHD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x87 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x87 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x87 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +{ +ICLASS : VPMULHUD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_INT REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x86 V0F38 REXW=0 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT + + +PATTERN : KVV 0x86 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ +PATTERN : KVV 0x86 V0F38 REXW=0 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +## + + + + + + + + +### + + + + +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b + +PATTERN : KVV 0x72 V0F V66 REXW=0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_N3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +} + + + + + + + +{ +ICLASS : VPSLLVD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x47 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x47 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd + +PATTERN : KVV 0x47 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +} + + +{ +ICLASS : VPSRAVD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x46 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x46 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd + +PATTERN : KVV 0x46 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +} + + +{ +ICLASS : VPSRLVD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x45 V0F38 V66 REXW=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x45 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd + +PATTERN : KVV 0x45 V0F38 V66 REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +} + + +### + + + + +{ +ICLASS : VPSHUFD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x70 V0F V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() NOSWIZD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x70 V0F V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd IMM0:r:b + +PATTERN : KVV 0x70 V0F V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd IMM0:r:b +} +{ +ICLASS : VPERMF32X4 +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x07 V0F3A V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() NOSWIZD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x07 V0F3A V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd IMM0:r:b + +PATTERN : KVV 0x07 V0F3A V66 REXW=0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd IMM0:r:b +} + +######### + + + + + +{ +ICLASS : VCVTPS2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x5A V0F REXW=0 VNP NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_HALF() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x5A V0F REXW=0 VNP NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ + +PATTERN : KVV 0x5A V0F REXW=0 VNP NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC +} + + +{ +ICLASS : VGETEXPPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x42 V0F38 V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x42 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ + +PATTERN : KVV 0x42 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC +} + + + +{ +ICLASS : VGETEXPPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x42 V0F38 V66 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x42 V0F38 V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ + +PATTERN : KVV 0x42 V0F38 V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=SAEC +} + + + + +{ +ICLASS : VCVTDQ2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xE6 V0F W0 VF3 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_HALF() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0xE6 V0F W0 VF3 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ + +PATTERN : KVV 0xE6 V0F W0 VF3 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 +} +{ +ICLASS : VCVTUDQ2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x7A V0F W0 VF3 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_HALF() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x7A V0F W0 VF3 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ + +PATTERN : KVV 0x7A V0F W0 VF3 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 +} + + + + + +########################### + + + +{ +ICLASS : VBROADCASTF32X4 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x1A V0F38 V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=4:SUPP EMX_BROADCAST_4TO16_32 +} +{ +ICLASS : VBROADCASTSS +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x18 V0F38 V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=1:SUPP EMX_BROADCAST_1TO16_32 +} + + +{ +ICLASS : VBROADCASTSD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x19 V0F38 V66 REXW=1 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=1:SUPP EMX_BROADCAST_1TO8_64 +} +{ +ICLASS : VBROADCASTF64x4 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x1B V0F38 V66 REXW=1 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=4:SUPP EMX_BROADCAST_4TO8_64 +} + + + + +##### + + + +{ +ICLASS : VBROADCASTI32X4 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x5A V0F38 V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd:i32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=4:SUPP EMX_BROADCAST_4TO16_32 +} +{ +ICLASS : VPBROADCASTD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x58 V0F38 V66 REXW=0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd:i32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=1:SUPP EMX_BROADCAST_1TO16_32 +} + + +{ +ICLASS : VPBROADCASTQ +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x59 V0F38 V66 REXW=1 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq:i64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=1:SUPP EMX_BROADCAST_1TO8_64 +} +{ +ICLASS : VBROADCASTI64x4 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_I64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x5B V0F38 V66 REXW=1 REXW=1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq:i64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NELEM=4:SUPP EMX_BROADCAST_4TO8_64 +} + + + +### + + + + + +{ +ICLASS : VADDSETSPS +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKOP_EVEX +COMMENT : +PATTERN : KVV 0xCC V0F38 V66 W0 MOD[0b11] MOD=3 REG[uuu] RM[www] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ + +PATTERN : KVV 0xCC V0F38 V66 W0 MOD[0b11] MOD=3 REG[uuu] RM[www] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=ROUNDC:TXT=SAEC +} +{ +ICLASS : VADDSETSPS +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX +COMMENT : +PATTERN : KVV 0xCC V0F38 V66 W0 MOD[mm] MOD!=3 REG[uuu] RM[rrr] MODRM() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT +} + + + + + + +{ +ICLASS : VLOADUNPACKHD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY MASKADDR NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD4 V0F38 VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} +{ +ICLASS : VLOADUNPACKLD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY MASKADDR NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD0 V0F38 VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} + + + +{ +ICLASS : VLOADUNPACKHPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR MASKADDR KNC_F64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD5 V0F38 VNP W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=NT NO_SCALE_DISP8=1 +} +{ +ICLASS : VLOADUNPACKLPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR MASKADDR KNC_F64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD1 V0F38 VNP W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=NT NO_SCALE_DISP8=1 +} + + + +{ +ICLASS : VLOADUNPACKHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR MASKADDR NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD5 V0F38 VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} +{ +ICLASS : VLOADUNPACKLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY KNC_FP MXCSR MASKADDR NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD1 V0F38 VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} + + + +{ +ICLASS : VLOADUNPACKHQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY MASKADDR KNC_I64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD4 V0F38 VNP W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} +{ +ICLASS : VLOADUNPACKLQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ATTRIBUTES : MEMONLY MASKADDR KNC_I64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xD0 V0F38 VNP W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT NO_SCALE_DISP8=1 +} + + + + +################ +# v2 template --- some have imm8 +# + + + +{ +ICLASS : VCMPPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xC2 V66 V0F W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0xC2 V66 V0F W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0xC2 V66 V0F W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64:TXT=SAEC IMM0:r:b +} + + + + +{ +ICLASS : VCMPPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xC2 VNP V0F W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0xC2 VNP V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0xC2 VNP V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32:TXT=SAEC IMM0:r:b +} + + + + +{ +ICLASS : VPCMPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x1F V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0x1F V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0x1F V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd IMM0:r:b +} + + + +{ +ICLASS : VPCMPUD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x1E V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zud MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0x1E V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zud REG3=ZMM_B3():r:zud:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0x1E V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zud REG3=ZMM_B3():r:zud IMM0:r:b +} + + + + +{ +ICLASS : VPCMPEQD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x76 V66 V0F W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x76 V66 V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +PATTERN : KVV 0x76 V66 V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPCMPGTD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x66 V66 V0F W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x66 V66 V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +PATTERN : KVV 0x66 V66 V0F W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPCMPLTD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x74 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x74 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +PATTERN : KVV 0x74 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPTESTMD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +COMMENT : NO ROUNDING FORM +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x27 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x27 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd:TXT=REGSWIZ +PATTERN : KVV 0x27 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zd REG3=ZMM_B3():r:zd +} + + + + + + +{ +ICLASS : VPACKSTOREHD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_I32 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD4 V66 V0F38 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT32() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zd NO_SCALE_DISP8=1 +} +{ +ICLASS : VPACKSTORELD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_I32 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD0 V66 V0F38 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT32() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zd NO_SCALE_DISP8=1 +} + +{ +ICLASS : VPACKSTOREHPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_F64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD5 V66 V0F38 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 NO_SCALE_DISP8=1 +} +{ +ICLASS : VPACKSTORELPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_F64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD1 V66 V0F38 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 NO_SCALE_DISP8=1 +} + +{ +ICLASS : VPACKSTOREHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_F32 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD5 V66 V0F38 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 NO_SCALE_DISP8=1 +} +{ +ICLASS : VPACKSTORELPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_F32 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD1 V66 V0F38 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 NO_SCALE_DISP8=1 +} + +{ +ICLASS : VPACKSTOREHQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_I64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD4 V66 V0F38 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT64() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zq NO_SCALE_DISP8=1 +} +{ +ICLASS : VPACKSTORELQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_FP MXCSR MASKADDR KNC_I64 NO_SCALE_DISP8 AGEN_PACK SPECIAL_AGEN_REQUIRED MASKOP_EVEX # FIXME: MEMONLY??? + +# store to memory +PATTERN : KVV 0xD0 V66 V0F38 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() DNCONVERT_INT64() +OPERANDS : MEM0:w:zv:TXT=CONVERT:TXT=NT REG0=MASK1():r:mskw REG1=ZMM_R3():r:zq NO_SCALE_DISP8=1 +} + + + +################ +# v4 template +# + + + + +{ +ICLASS : VEXP223PS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xC8 V0F38 V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() NOSWIZF32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT + +PATTERN : KVV 0xC8 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=SAEC + +PATTERN : KVV 0xC8 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd +} +{ +ICLASS : VLOG2PS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xC9 V0F38 V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() NOSWIZF32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT + +PATTERN : KVV 0xC9 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=SAEC + +PATTERN : KVV 0xC9 V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd +} +{ +ICLASS : VRCP23PS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCA V0F38 V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() NOSWIZF32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT + +PATTERN : KVV 0xCA V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=SAEC + +PATTERN : KVV 0xCA V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd +} +{ +ICLASS : VRSQRT23PS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCB V0F38 V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() NOSWIZF32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zd:TXT=NT + +PATTERN : KVV 0xCB V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=SAEC + +PATTERN : KVV 0xCB V0F38 V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd +} + + + + +################# +# v5 template - some have imm8 +# + + +# two opnd, int32 src, no round, noevsr, + +# two opnd, int32 src, no round, noevsr, imm8 + + +{ +ICLASS : VCVTFXPNTDQ2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xCB V0F3A VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + + +PATTERN : KVV 0xCB V0F3A VNP W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0xCB V0F3A VNP W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zd:TXT=SAEC IMM0:r:b +} + +# two opnd, flt32 src, round, noevsr, + + +# two opnd, flt64 src, round, noevsr + + + +{ +ICLASS : VCVTPD2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x5A V0F V66 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +PATTERN : KVV 0x5A V0F V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ +PATTERN : KVV 0x5A V0F V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 ROUND() KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=ROUNDC:TXT=SAEC +} + + + + + +{ +ICLASS : VCVTFXPNTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0xE6 V0F3A VF2 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0xE6 V0F3A VF2 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=REGSWIZ IMM0:r:b +PATTERN : KVV 0xE6 V0F3A VF2 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=SAEC IMM0:r:b +} + + + + + + + +{ +ICLASS : VCVTFXPNTUDQ2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +COMMENT : FIXME: ROUNDING MODE comes from SSS[1:0] but not used for direct input rounding. FIXME: Not disallowing SWIZ=1xx + +PATTERN : KVV 0xCA V0F3A VNP W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +PATTERN : KVV 0xCA V0F3A VNP W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zud:TXT=REGSWIZ IMM0:r:b + +PATTERN : KVV 0xCA V0F3A VNP W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zud:TXT=SAEC IMM0:r:b +} + + + + + + + +{ +ICLASS : VGETMANTPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES: KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x26 V0F3A V66 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x26 V0F3A V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0x26 V0F3A V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +} +{ +ICLASS : VCVTFXPNTPD2UDQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCA V0F3A VF2 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0xCA V0F3A VF2 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0xCA V0F3A VF2 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +} +{ +ICLASS : VRNDFXPNTPD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ATTRIBUTES: KNC_FP MXCSR KNC_F64 REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x52 V0F3A V66 W1 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x52 V0F3A V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0x52 V0F3A V66 W1 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE64() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +} + + +{ +ICLASS : VGETMANTPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES: KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x26 V0F3A V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x26 V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0x26 V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b +} +{ +ICLASS : VCVTFXPNTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES: KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCB V0F3A V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0xCB V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0xCB V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b +} +{ +ICLASS : VCVTFXPNTPS2UDQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES: KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0xCA V0F3A V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0xCA V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0xCA V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zud REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b +} +{ +ICLASS : VRNDFXPNTPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES: KNC_FP MXCSR REQUIRES_ALIGNMENT MASKOP_EVEX + +PATTERN : KVV 0x52 V0F3A V66 W0 NOEVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() UPCONVERT_FLT32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT IMM0:r:b + +# It does not ROUND +PATTERN : KVV 0x52 V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=1 KNC_SAE() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=SAEC IMM0:r:b + +PATTERN : KVV 0x52 V0F3A V66 W0 NOEVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32:TXT=REGSWIZ IMM0:r:b +} + + +################# +# v6 template -- srd/dst swappage +# + +{ +ICLASS : VGATHERDPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_GATHER KNC_F64 gather REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0x92 V66 V0F38 W1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() UPCONVERT_FLT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf64 REG1=MASK1():rw:mskw MEM0:r:zv:TXT=NT:TXT=CONVERT NELEM=1:SUPP +} +{ +ICLASS : VGATHERDPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_GATHER KNC_F32 gather REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0x92 V66 V0F38 W0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():rw:mskw MEM0:r:zv:TXT=NT:TXT=CONVERT NELEM=1:SUPP +} +{ +ICLASS : VPGATHERDD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_GATHER KNC_I32 gather REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0x90 V66 V0F38 W0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() UPCONVERT_INT32_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():rw:mskw MEM0:r:zv:TXT=NT:TXT=CONVERT NELEM=1:SUPP +} +{ +ICLASS : VPGATHERDQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_GATHER KNC_I64 gather REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0x90 V66 V0F38 W1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() UPCONVERT_INT64_LOAD() +OPERANDS : REG0=ZMM_R3():rw:zq REG1=MASK1():rw:mskw MEM0:r:zv:TXT=NT:TXT=CONVERT NELEM=1:SUPP +} + + + +{ +ICLASS : VPSCATTERDD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_SCATTER KNC_I32 scatter REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xA0 V66 V0F38 W0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() DNCONVERT_INT32() +OPERANDS : MEM0:w:zv:TXT=NT:TXT=CONVERT REG1=MASK1():rw:mskw REG0=ZMM_R3():r:zd NELEM=1:SUPP +} +{ +ICLASS : VPSCATTERDQ +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_SCATTER KNC_I64 scatter REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xA0 V66 V0F38 W1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() DNCONVERT_INT64() +OPERANDS : MEM0:w:zv:TXT=NT:TXT=CONVERT REG1=MASK1():rw:mskw REG0=ZMM_R3():r:zq NELEM=1:SUPP +} +{ +ICLASS : VSCATTERDPD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_SCATTER KNC_F64 scatter REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xA2 V66 V0F38 W1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() DNCONVERT_FLT64() +OPERANDS : MEM0:w:zv:TXT=NT:TXT=CONVERT REG1=MASK1():rw:mskw REG0=ZMM_R3():r:zf64 NELEM=1:SUPP +} +{ +ICLASS : VSCATTERDPS +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ISA_SET : KNCE +ATTRIBUTES : KNC_SCATTER KNC_F32 scatter REQUIRES_ALIGNMENT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xA2 V66 V0F38 W0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[rrr] RM[0b100] KNC_VMODRM() DNCONVERT_FLT32() +OPERANDS : MEM0:w:zv:TXT=NT:TXT=CONVERT REG1=MASK1():rw:mskw REG0=ZMM_R3():r:zf32 NELEM=1:SUPP +} + + + +################# +# v7 template +# + + + + + +{ +ICLASS : VPADCD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX + +# load from memory +PATTERN : KVV 0x5C V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x5C V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x5C V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} + +{ +ICLASS : VPSBBD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX + +# load from memory +PATTERN : KVV 0x5E V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x5E V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x5E V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPSBBRD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX + +# load from memory +PATTERN : KVV 0x6E V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x6E V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x6E V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPSUBRSETBD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX + +# load from memory +PATTERN : KVV 0x6F V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x6F V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x6F V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} +{ +ICLASS : VPSUBSETBD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX + +# load from memory +PATTERN : KVV 0x5F V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x5F V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x5F V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} + +# writes the mask... +{ +ICLASS : VPADDSETCD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : REQUIRES_ALIGNMENT MASKOP_EVEX +COMMENT : strange: writes a 2nd mask and reads the dest as a real source. +# load from memory +PATTERN : KVV 0x5D V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UPCONVERT_INT32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw MEM0:r:zv:TXT=CONVERT:TXT=NT + +# load from register swizzle +PATTERN : KVV 0x5D V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 REG_SWIZZLE32() +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd:TXT=REGSWIZ + +# no round on reg/reg version +PATTERN : KVV 0x5D V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=1 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zd REG1=MASK1():r:mskw REG2=MASK_N():w:mskw REG3=ZMM_B3():r:zd +} + +################# +# v8 template +# + + + + +{ +ICLASS : VALIGND +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x03 V0F3A V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() NOSWIZD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zd:TXT=NT IMM0:r:b + +PATTERN : KVV 0x03 V0F3A V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 UIMM8() SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +} +{ +ICLASS : VPERMD +CPL : 3 +CATEGORY : KNC +EXTENSION : KNCE +ATTRIBUTES : NOSWIZ REQUIRES_ALIGNMENT MASKOP_EVEX +PATTERN : KVV 0x36 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() NOSWIZD() +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:zd:TXT=NT + +PATTERN : KVV 0x36 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] NR=0 SWIZ=0 +OPERANDS : REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +} + +################# +# v9 template + + +{ +ICLASS : VGATHERPF0DPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ATTRIBUTES : KNC_GATHER PREFETCH SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b001] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:r:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + +{ +ICLASS : VGATHERPF1DPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ATTRIBUTES : KNC_GATHER PREFETCH SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b010] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:r:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + + +{ +ICLASS : VGATHERPF0HINTDPD +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET : KNC_PF_HINT +ATTRIBUTES : KNC_GATHER PREFETCH SPARSEHINT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b000] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:r:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + +{ +ICLASS : VGATHERPF0HINTDPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET : KNC_PF_HINT +ATTRIBUTES : KNC_GATHER PREFETCH SPARSEHINT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b000] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:r:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + + +{ +ICLASS : VSCATTERPF0DPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ATTRIBUTES : KNC_SCATTER PREFETCH SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b101] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:w:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + +{ +ICLASS : VSCATTERPF1DPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ATTRIBUTES : KNC_SCATTER PREFETCH SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b110] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:w:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + + + +{ +ICLASS : VSCATTERPF0HINTDPD +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET : KNC_PF_HINT +ATTRIBUTES : KNC_SCATTER PREFETCH SPARSEHINT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=1 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b100] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:w:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + + +{ +ICLASS : VSCATTERPF0HINTDPS +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET : KNC_PF_HINT +ATTRIBUTES : KNC_SCATTER PREFETCH SPARSEHINT SPECIAL_AGEN_REQUIRED MASKOP_EVEX +PATTERN : KVV 0xC6 V0F38 V66 REXW=0 NO_SPARSE_EVSR MOD[mm] MOD!=3 REG[0b100] RM[0b100] KNC_VMODRM() UPCONVERT_FLT32_LOAD() +OPERANDS : MEM0:w:zv:TXT=NT REG0=MASK1():rw:mskw +COMMENT : the upconvert is only to set the element size for disp8*N in the base address +} + + +###################################################################### +## EVEX versions of the CLEVECT* and VPREFETCH* NI +###################################################################### + + +{ +ICLASS : CLEVICT0_EVEX +DISASM : clevict0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0xAE VL512 VF2 V0F NOEVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : CLEVICT0_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : CLEVICT1_EVEX +DISASM : clevict1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0xAE VL512 VF3 V0F NOEVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : CLEVICT1_EVEX_MEMmprefetch_EVEX +} + + + +{ +ICLASS : VPREFETCH0_EVEX +DISASM : vprefetch0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCH0_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCH1_EVEX +DISASM : vprefetch1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCH1_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCH2_EVEX +DISASM : vprefetch2 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCH2_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCHE0_EVEX +DISASM : vprefetche0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCHE0_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCHE1_EVEX +DISASM : vprefetche1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCHE1_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCHE2_EVEX +DISASM : vprefetche2 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCHE2_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCHENTA_EVEX +DISASM : vprefetchenta +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCHENTA_EVEX_MEMmprefetch_EVEX +} +{ +ICLASS : VPREFETCHNTA_EVEX +DISASM : vprefetchnta +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNCE +ISA_SET: KNCE +ATTRIBUTES : PREFETCH MASKOP_EVEX +PATTERN : KVV 0x18 VL512 VNP V0F NOEVSR MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() NOSWIZD() +OPERANDS : MEM0:r:mprefetch +IFORM : VPREFETCHNTA_EVEX_MEMmprefetch_EVEX +} + diff --git a/datafiles/knc/lrb2-evex-reg-tables.txt b/datafiles/knc/lrb2-evex-reg-tables.txt new file mode 100644 index 0000000..53e60ea --- /dev/null +++ b/datafiles/knc/lrb2-evex-reg-tables.txt @@ -0,0 +1,166 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t ZMM_N3():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31 + + + +xed_reg_enum_t ZMM_R3():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15 +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31 + + + +xed_reg_enum_t ZMM_B3():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15 +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31 + + +xed_reg_enum_t MASK1():: +MASK=0x0 | OUTREG=XED_REG_K0 +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +xed_reg_enum_t MASK_R():: +REG=0x0 | OUTREG=XED_REG_K0 +REG=0x1 | OUTREG=XED_REG_K1 +REG=0x2 | OUTREG=XED_REG_K2 +REG=0x3 | OUTREG=XED_REG_K3 +REG=0x4 | OUTREG=XED_REG_K4 +REG=0x5 | OUTREG=XED_REG_K5 +REG=0x6 | OUTREG=XED_REG_K6 +REG=0x7 | OUTREG=XED_REG_K7 + +xed_reg_enum_t MASK_B():: +RM=0x0 | OUTREG=XED_REG_K0 +RM=0x1 | OUTREG=XED_REG_K1 +RM=0x2 | OUTREG=XED_REG_K2 +RM=0x3 | OUTREG=XED_REG_K3 +RM=0x4 | OUTREG=XED_REG_K4 +RM=0x5 | OUTREG=XED_REG_K5 +RM=0x6 | OUTREG=XED_REG_K6 +RM=0x7 | OUTREG=XED_REG_K7 + + +# stored inverted +xed_reg_enum_t MASK_N():: +VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0 diff --git a/datafiles/knc/lrb2-regs.txt b/datafiles/knc/lrb2-regs.txt new file mode 100644 index 0000000..7acbd89 --- /dev/null +++ b/datafiles/knc/lrb2-regs.txt @@ -0,0 +1,49 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ZMM0 zmm 512 ZMM0 0 +ZMM1 zmm 512 ZMM1 1 +ZMM2 zmm 512 ZMM2 2 +ZMM3 zmm 512 ZMM3 3 +ZMM4 zmm 512 ZMM4 4 +ZMM5 zmm 512 ZMM5 5 +ZMM6 zmm 512 ZMM6 6 +ZMM7 zmm 512 ZMM7 7 +ZMM8 zmm 512 ZMM8 8 +ZMM9 zmm 512 ZMM9 9 +ZMM10 zmm 512 ZMM10 10 +ZMM11 zmm 512 ZMM11 11 +ZMM12 zmm 512 ZMM12 12 +ZMM13 zmm 512 ZMM13 13 +ZMM14 zmm 512 ZMM14 14 +ZMM15 zmm 512 ZMM15 15 +ZMM16 zmm 512 ZMM16 16 +ZMM17 zmm 512 ZMM17 17 +ZMM18 zmm 512 ZMM18 18 +ZMM19 zmm 512 ZMM19 19 +ZMM20 zmm 512 ZMM20 20 +ZMM21 zmm 512 ZMM21 21 +ZMM22 zmm 512 ZMM22 22 +ZMM23 zmm 512 ZMM23 23 +ZMM24 zmm 512 ZMM24 24 +ZMM25 zmm 512 ZMM25 25 +ZMM26 zmm 512 ZMM26 26 +ZMM27 zmm 512 ZMM27 27 +ZMM28 zmm 512 ZMM28 28 +ZMM29 zmm 512 ZMM29 29 +ZMM30 zmm 512 ZMM30 30 +ZMM31 zmm 512 ZMM31 31 diff --git a/datafiles/knc/lrb2-scalar-mask-isa.txt b/datafiles/knc/lrb2-scalar-mask-isa.txt new file mode 100644 index 0000000..cd09071 --- /dev/null +++ b/datafiles/knc/lrb2-scalar-mask-isa.txt @@ -0,0 +1,404 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : KAND +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x41 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KANDN +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x42 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KANDNR +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x43 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KNOT +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x44 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KOR +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x45 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KXNOR +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x46 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KXOR +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x47 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KMERGE2L1H +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x48 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} +{ +ICLASS : KMERGE2L1L +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +PATTERN : VV1 0x49 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +} + + +{ +ICLASS : KORTESTD +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +FLAGS : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ] +PATTERN : VV1 0x98 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +COMMENT : flags operand is added implicitly by XED generator +} +##MACRO_USE: vex_mask_logical_flags(KORTESTQ,0x98,REXW=1) + + + + +# was KMOVD +{ +ICLASS : KMOV +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV + +# load forms, mask dest/ mask src +PATTERN : VV1 0x90 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw + +# load forms, mask dest / gpr src +PATTERN : VV1 0x92 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +OPERANDS : REG0=MASK_R():w:mskw REG1=GPR32_B():r:mskw + + +# store forms, gpr dest/ mask src +PATTERN : VV1 0x93 VL128 VNP V0F REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +OPERANDS : REG0=GPR32_R():w:mskw REG1=MASK_B():r:mskw +} + + + +{ +ICLASS : KCONCATH +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +# +# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX. +# I could change the NT to one that uses the VEXR instead. That would work better if REX comes back. +# +PATTERN : VV1 0x95 VL128 VNP V0F REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +} +{ +ICLASS : KCONCATL +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +# +# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX. +# I could change the NT to one that uses the VEXR instead. That would work better if REX comes back. +# +PATTERN : VV1 0x97 VL128 VNP V0F REXW=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +} + + + + + + + +{ +ICLASS : KEXTRACT +CPL : 3 +CATEGORY : KNCMASK +EXTENSION : KNC +ISA_SET: KNCV +# +# This uses GPR64_R -- that is only possible because we define REXR in the C5 VEX. +# I could change the NT to one that uses the VEXR instead. That would work better if REX comes back. +# +PATTERN : VV1 0x3E VL128 V66 V0F3A REXW=0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MASK_R():w:mskw REG1=GPR64_B():r:q IMM0:r:b +} + + + +###################################################### +# Scalar instructions +###################################################### + +{ +ICLASS : LZCNT_VEX +DISASM : lzcnt +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV +FLAGS : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ] + +PATTERN : VV1 0xBD VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=GPR32_B():r:d + +PATTERN : VV1 0xBD VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q REG1=GPR64_B():r:q +} + + + + + + +{ +ICLASS : CLEVICT0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0xAE VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch #FIXME: rw or r??? +} +{ +ICLASS : CLEVICT1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0xAE VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch #FIXME: rw or r??? +} + + + +{ +ICLASS : DELAY +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV + +PATTERN : VV1 0xAE VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn] W0 +OPERANDS : REG0=GPR32_B():r:d + +PATTERN : VV1 0xAE VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn] W1 +OPERANDS : REG0=GPR64_B():r:q +} +{ +ICLASS : SPFLT +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV + +PATTERN : VV1 0xAE VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn] W0 +OPERANDS : REG0=GPR32_B():r:d + +PATTERN : VV1 0xAE VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[0b110] RM[nnn] W1 +OPERANDS : REG0=GPR64_B():r:q +} + +# DRW is the dest read/write flag + +# I made up my own names for the VEX'ed POPCNT and TZCNT to +# differetiate them from the nonVEX versions of the same instructions. +# The XED encoder requires this as VEXVALID is not an encoder input +# and we do not want it to be one for most instructions. I could add +# something new but have not. + +{ +ICLASS : POPCNT_VEX +DISASM : popcnt +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV +FLAGS : MUST [ zf-mod cf-0 of-0 sf-0 af-0 pf-0 ] +PATTERN : VV1 0xB8 VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=GPR32_B():r:d + +PATTERN : VV1 0xB8 VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q REG1=GPR64_B():r:q +} +{ +ICLASS : TZCNT_VEX +DISASM : tzcnt +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV +FLAGS : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ] +PATTERN : VV1 0xBC VL128 VF3 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=GPR32_B():r:d + +PATTERN : VV1 0xBC VL128 VF3 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q REG1=GPR64_B():r:q +} +{ +ICLASS : TZCNTI +DISASM : tzcnti +CPL : 3 +CATEGORY : KNCSCALAR +EXTENSION : KNC +ISA_SET: KNCV +FLAGS : MUST [ zf-mod cf-mod of-0 sf-0 af-0 pf-0 ] +PATTERN : VV1 0xBC VL128 VF2 V0F W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d + +PATTERN : VV1 0xBC VL128 VF2 V0F W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +} + + + + +{ +ICLASS : VPREFETCH0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCH1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCH2 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCHE0 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCHE1 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCHE2 +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCHENTA +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : VPREFETCHNTA +CPL : 3 +CATEGORY : PREFETCH +EXTENSION : KNC +ISA_SET: KNCV +ATTRIBUTES : PREFETCH +PATTERN : VV1 0x18 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + diff --git a/datafiles/knc/lrb2-strings.txt b/datafiles/knc/lrb2-strings.txt new file mode 100644 index 0000000..f4a41a1 --- /dev/null +++ b/datafiles/knc/lrb2-strings.txt @@ -0,0 +1,142 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +CONVERT(XED_OPERAND_CONVERT):: +0 -> '' +1 -> '{1to8}' +2 -> '{4to8}' +3 -> '{float16}' +4 -> '{uint8}' +5 -> '{sint8}' +6 -> '{uint16}' +7 -> '{int16}' +8 -> '{int8}' +9 -> '{1to16}' +10 -> '{4to16}' + + + +REGSWIZ(XED_OPERAND_REGSWIZ):: +0 -> '' +1 -> '{cdab}' +2 -> '{badc}' +3 -> '{dacb}' +4 -> '{aaaa}' +5 -> '{bbbb}' +6 -> '{cccc}' +7 -> '{dddd}' + +ROUNDC(XED_OPERAND_ROUNDC):: +0 -> '' +1 -> '{rne}' +2 -> '{rd}' +3 -> '{ru}' +4 -> '{rz}' + +SAEC(XED_OPERAND_SAE):: +0 -> '' +1 -> '{sae}' + + +NT(XED_OPERAND_NR):: +0 -> '' +1 -> '{eh}' # {nt} + + +UPCONVERT_FLOAT32(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> '{1to16}' +0b010 -> '{4to16}' +0b011 -> '{float16}' +0b100 -> '{uint8}' +0b101 -> error +0b110 -> '{uint16}' +0b111 -> '{int16}' + + +UPCONVERT_INT32(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> '{1to16}' +0b010 -> '{4to16}' +0b011 -> error +0b100 -> '{uint8}' +0b101 -> '{int8}' +0b110 -> '{uint16}' +0b111 -> '{int16}' + +UPCONVERT_FLOAT64(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> '{1to8}' +0b010 -> '{4to8}' +0b011 -> error +0b100 -> error +0b101 -> error +0b110 -> error +0b111 -> error + +UPCONVERT_INT64(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> '{1to8}' +0b010 -> '{4to8}' +0b011 -> error +0b100 -> error +0b101 -> error +0b110 -> error +0b111 -> error + + +DOWNCONVERT_FLOAT32(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> error +0b010 -> error +0b011 -> '{float16}' +0b100 -> '{uint8}' +0b101 -> error +0b110 -> '{uint16}' +0b111 -> '{int16}' + +DOWNCONVERT_INT32(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> error +0b010 -> error +0b011 -> error +0b100 -> '{uint8}' +0b101 -> '{int8}' +0b110 -> '{uint16}' +0b111 -> '{int16}' + +DOWNCONVERT_FLOAT64(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> error +0b010 -> error +0b011 -> error +0b100 -> error +0b101 -> error +0b110 -> error +0b111 -> error + +DOWNCONVERT_INT64(XED_OPERAND_SWIZ):: +0b000 -> '' +0b001 -> error +0b010 -> error +0b011 -> error +0b100 -> error +0b101 -> error +0b110 -> error +0b111 -> error + + diff --git a/datafiles/knc/uisa-operand-widths.txt b/datafiles/knc/uisa-operand-widths.txt new file mode 100644 index 0000000..cf4efa1 --- /dev/null +++ b/datafiles/knc/uisa-operand-widths.txt @@ -0,0 +1,50 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# +zv var 0 # relies on nelem * elem_size + +zf32 f32 512bits +zf64 f64 512bits + +zb i8 512bits +zw i16 512bits +zd i32 512bits +zq i64 512bits + +zub u8 512bits +zuw u16 512bits +zud u32 512bits +zuq u64 512bits +z128 u128 512bits + +# alternative names... +zi8 i8 512bits +zi16 i16 512bits +zi32 i32 512bits +zi64 i64 512bits + +zu8 u8 512bits +zu16 u16 512bits +zu32 u32 512bits +zu64 u64 512bits +z128 u128 512bits + +wrd u16 16bits +mskw i1 16bits diff --git a/datafiles/knc/uisa-spine.txt b/datafiles/knc/uisa-spine.txt new file mode 100644 index 0000000..19996f9 --- /dev/null +++ b/datafiles/knc/uisa-spine.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ISA():: +PREFIXES() OSZ_NONTERM() ASZ_NONTERM() EVEX_SPLITTER() | + + diff --git a/datafiles/knc/uisa-splitter.txt b/datafiles/knc/uisa-splitter.txt new file mode 100644 index 0000000..9289316 --- /dev/null +++ b/datafiles/knc/uisa-splitter.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +EVEX_SPLITTER():: +VEXVALID=0 INSTRUCTIONS() | +VEXVALID=1 AVX_INSTRUCTIONS() | +VEXVALID=2 EVEX_INSTRUCTIONS() | + diff --git a/datafiles/knc/uisa-state-bits.txt b/datafiles/knc/uisa-state-bits.txt new file mode 100644 index 0000000..17fbfb2 --- /dev/null +++ b/datafiles/knc/uisa-state-bits.txt @@ -0,0 +1,39 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +VL512 VL=2 +VLBAD VL=3 # unused VL setting to cause things not to decode. + +# KNC EVEX is KVV +# +KVV VEXVALID=4 + +# No VEX-SPECIFIED-REGISTER +NOEVSR VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +# No VEX-SPECIFIED-REGISTER for GATHERS/SCATTERS -- index reg 5th bit is VEXTDEST4 +NO_SPARSE_EVSR VEXDEST3=0b1 VEXDEST210=0b111 + +# These conflict w/another chip ... so if you ever build a combo +# model you'll have to remove these somehow. +# +EMX_BROADCAST_1TO16_32 BCAST=1 # 512 +EMX_BROADCAST_4TO16_32 BCAST=2 # 512 +EMX_BROADCAST_1TO8_64 BCAST=5 # 512 +EMX_BROADCAST_4TO8_64 BCAST=6 # 512 + diff --git a/datafiles/knc/xed-operand-values-interface-uisa.c b/datafiles/knc/xed-operand-values-interface-uisa.c new file mode 100644 index 0000000..5c2b068 --- /dev/null +++ b/datafiles/knc/xed-operand-values-interface-uisa.c @@ -0,0 +1,135 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-values-interface-uisa.c + + +/* The code in this file is used to override the corresponding XED library + * functions in a different file in the main XED sources. This code is for + * the unusual disp8*N handling that is present in UISA and nothing + * else. When UISA is public, I can roll this verison of the function in to + * the baseline of XED. The files.cfg file controls the file replacement. + */ + +#include "xed-internal-header.h" +#include "xed-operand-values-interface.h" +#include "xed-util.h" +#include "xed-init-pointer-names.h" +#include "xed-operand-ctype-enum.h" +#include "xed-operand-ctype-map.h" +#include "xed-reg-class.h" +#include //memset + + + +xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits_raw( + const xed_operand_values_t* p) +{ + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + return xed3_operand_get_disp_width(p); +} + +xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits( + const xed_operand_values_t* p) +{ + xed_uint32_t raw_width; + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + raw_width = xed3_operand_get_disp_width(p); + if (raw_width == 8) { + xed_int64_t nelem = xed3_operand_get_nelem(p); + if (nelem) { + xed_int64_t element_size = xed3_operand_get_element_size(p); + if (element_size * nelem > 1) //FIXME bad test + // just double the apparent width because the most UISA + // will do is multiply by 64. + return 16; + } + } + return raw_width; +} + + +xed_int64_t xed_operand_values_get_memory_displacement_int64( + const xed_operand_values_t* p) +{ + unsigned int len; + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + + len = xed3_operand_get_disp_width(p); + switch(len) { + case 8: { + xed_int64_t odisp; + xed_int64_t disp = xed3_operand_get_disp(p); + xed_int64_t nelem = xed3_operand_get_nelem(p); + + // converted to bytes + xed_int64_t element_size = xed3_operand_get_element_size(p)>>3; + + + // the loadunpack & packstore instructions ignore the number of + // elements + if (xed3_operand_get_no_scale_disp8(p)) + nelem = 1; + + odisp = disp * nelem * element_size; + /* printf("DISP: " XED_FMT_LX16 " NELEM + " XED_FMT_LD " SIZE " XED_FMT_LD + " ODISP: " XED_FMT_LX16 "\n", + disp ,nelem, element_size , odisp); */ + if (nelem) + return odisp; + else + return disp; + } + case 16: + case 32: + case 64: return xed3_operand_get_disp(p); + default: + return 0; + } +} + +#include "xed-ild.h" + +xed_int64_t +xed_operand_values_get_memory_displacement_int64_raw( + const xed_operand_values_t* p) +{ + unsigned int len; + + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + + len = xed3_operand_get_disp_width(p); //bits + switch(len) { + case 8: + case 16: + case 32: + case 64: + return xed3_operand_get_disp(p); + default: + return 0; + } +} + + + diff --git a/datafiles/knl/cpuid.xed.txt b/datafiles/knl/cpuid.xed.txt new file mode 100644 index 0000000..4dcced5 --- /dev/null +++ b/datafiles/knl/cpuid.xed.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512ER_512: avx512er.7.0.ebx.27 + XED_ISA_SET_AVX512ER_SCALAR: avx512er.7.0.ebx.27 + XED_ISA_SET_AVX512PF_512: avx512pf.7.0.ebx.26 + XED_ISA_SET_PREFETCHWT1: prefetchwt1.7.0.ecx.0 diff --git a/datafiles/knl/files.cfg b/datafiles/knl/files.cfg new file mode 100644 index 0000000..f3266eb --- /dev/null +++ b/datafiles/knl/files.cfg @@ -0,0 +1,27 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: knl-chips.txt + + dec-instructions: knl-fixup.txt + enc-instructions: knl-fixup.txt + dec-instructions: knl-isa.xed.txt + enc-instructions: knl-isa.xed.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/knl/knl-chips.txt b/datafiles/knl/knl-chips.txt new file mode 100644 index 0000000..6be12f8 --- /dev/null +++ b/datafiles/knl/knl-chips.txt @@ -0,0 +1,31 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# No HSW INVPCID, RTM, VMFUNC +# No BDW SMAP +KNL: ALL_OF(IVYBRIDGE) \ + AVX512F_SCALAR \ + AVX512F_KOP \ + AVX512F_512 \ + AVX512F_128N \ + AVX512CD_512 \ + AVX512ER_512 \ + AVX512ER_SCALAR \ + AVX512PF_512 \ + PREFETCHWT1 \ + BDW RDSEED FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER MOVBE diff --git a/datafiles/knl/knl-fixup.txt b/datafiles/knl/knl-fixup.txt new file mode 100644 index 0000000..08f2f46 --- /dev/null +++ b/datafiles/knl/knl-fixup.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +UDELETE : PREFETCH_RESERVED_0F0Dr2 diff --git a/datafiles/knl/knl-isa.xed.txt b/datafiles/knl/knl-isa.xed.txt new file mode 100644 index 0000000..d73c0f4 --- /dev/null +++ b/datafiles/knl/knl-isa.xed.txt @@ -0,0 +1,739 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VEXP2PD (VEXP2PD-512-1) +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VEXP2PS (VEXP2PS-512-1) +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) +{ +ICLASS: VGATHERPF0DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) +{ +ICLASS: VGATHERPF0DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) +{ +ICLASS: VGATHERPF0QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) +{ +ICLASS: VGATHERPF0QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) +{ +ICLASS: VGATHERPF1DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) +{ +ICLASS: VGATHERPF1DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) +{ +ICLASS: VGATHERPF1QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) +{ +ICLASS: VGATHERPF1QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VRCP28PD (VRCP28PD-512-1) +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRCP28PS (VRCP28PS-512-1) +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRCP28SD (VRCP28SD-128-1) +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRCP28SS (VRCP28SS-128-1) +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28PD (VRSQRT28PD-512-1) +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28PS (VRSQRT28PS-512-1) +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28SD (VRSQRT28SD-128-1) +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28SS (VRSQRT28SS-128-1) +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) +{ +ICLASS: VSCATTERPF0DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) +{ +ICLASS: VSCATTERPF0DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) +{ +ICLASS: VSCATTERPF0QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) +{ +ICLASS: VSCATTERPF0QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) +{ +ICLASS: VSCATTERPF1DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) +{ +ICLASS: VSCATTERPF1DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) +{ +ICLASS: VSCATTERPF1QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) +{ +ICLASS: VSCATTERPF1QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +INSTRUCTIONS():: +# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) +{ +ICLASS: PREFETCHWT1 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: PREFETCHWT1 +ISA_SET: PREFETCHWT1 +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHWT1_MEMu8 +} + + diff --git a/datafiles/knm/cpuid.xed.txt b/datafiles/knm/cpuid.xed.txt new file mode 100644 index 0000000..9875649 --- /dev/null +++ b/datafiles/knm/cpuid.xed.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_4VNNIW_512: avx512_4vnniw.7.0.edx.2 +XED_ISA_SET_AVX512_4FMAPS_512: avx512_4fmaps.7.0.edx.3 +XED_ISA_SET_AVX512_4FMAPS_SCALAR: avx512_4fmaps.7.0.edx.3 + diff --git a/datafiles/knm/files.cfg b/datafiles/knm/files.cfg new file mode 100644 index 0000000..3f95c13 --- /dev/null +++ b/datafiles/knm/files.cfg @@ -0,0 +1,27 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: knm-chips.txt +# cpuid: cpuid.xed.txt + +# dec-instructions: knm-isa.xed.txt +# enc-instructions: knm-isa.xed.txt + +# FIXME: move this to the right place (4VNNIW or 4FMAPS) + dec-patterns: knm-disp8.txt + enc-patterns: knm-disp8-enc.txt diff --git a/datafiles/knm/knm-chips.txt b/datafiles/knm/knm-chips.txt new file mode 100644 index 0000000..cdff653 --- /dev/null +++ b/datafiles/knm/knm-chips.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +KNM: ALL_OF(KNL) \ + AVX512_4VNNIW_512 \ + AVX512_4FMAPS_512 \ + AVX512_4FMAPS_SCALAR \ + AVX512_VPOPCNTDQ_512 diff --git a/datafiles/knm/knm-disp8-enc.txt b/datafiles/knm/knm-disp8-enc.txt new file mode 100644 index 0000000..9123660 --- /dev/null +++ b/datafiles/knm/knm-disp8-enc.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +NELEM_TUPLE1_4X():: +otherwise -> nothing diff --git a/datafiles/knm/knm-disp8.txt b/datafiles/knm/knm-disp8.txt new file mode 100644 index 0000000..d7677b6 --- /dev/null +++ b/datafiles/knm/knm-disp8.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +NELEM_TUPLE1_4X():: +VL128 | NELEM=4 +VL256 | NELEM=4 +VL512 | NELEM=4 + diff --git a/datafiles/knm/knm-isa.xed.txt b/datafiles/knm/knm-isa.xed.txt new file mode 100644 index 0000000..8df47f9 --- /dev/null +++ b/datafiles/knm/knm-isa.xed.txt @@ -0,0 +1,123 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING V4FMADDPS (V4FMADDPS-512-1) +{ +ICLASS: V4FMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: N +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FMADDSS (V4FMADDSS-128-1) +{ +ICLASS: V4FMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: N +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) +{ +ICLASS: V4FNMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: N +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +{ +ICLASS: V4FNMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: N +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) +{ +ICLASS: VP4DPWSSD +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: N +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:i16 +IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) +{ +ICLASS: VP4DPWSSDS +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: N +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:i16 +IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + diff --git a/datafiles/memory/clflushopt.xed.txt b/datafiles/memory/clflushopt.xed.txt new file mode 100644 index 0000000..0bf24d2 --- /dev/null +++ b/datafiles/memory/clflushopt.xed.txt @@ -0,0 +1,32 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLFLUSHOPT +CPL: 3 +CATEGORY: CLFLUSHOPT +EXTENSION: CLFLUSHOPT +ISA_SET: CLFLUSHOPT +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + diff --git a/datafiles/memory/clwb.xed.txt b/datafiles/memory/clwb.xed.txt new file mode 100644 index 0000000..8dd59c6 --- /dev/null +++ b/datafiles/memory/clwb.xed.txt @@ -0,0 +1,32 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLWB +CPL: 3 +CATEGORY: CLWB +EXTENSION: CLWB +ISA_SET: CLWB +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + diff --git a/datafiles/memory/cpuid.xed.txt b/datafiles/memory/cpuid.xed.txt new file mode 100644 index 0000000..d55bc56 --- /dev/null +++ b/datafiles/memory/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_CLFLUSHOPT: clflushopt.7.0.ebx.23 + XED_ISA_SET_CLWB: clwb.7.0.ebx.24 diff --git a/datafiles/memory/files.cfg b/datafiles/memory/files.cfg new file mode 100644 index 0000000..47ae539 --- /dev/null +++ b/datafiles/memory/files.cfg @@ -0,0 +1,29 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models:memory-chips.txt + + + dec-instructions: clwb.xed.txt + enc-instructions: clwb.xed.txt + + dec-instructions: clflushopt.xed.txt + enc-instructions: clflushopt.xed.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/memory/memory-chips.txt b/datafiles/memory/memory-chips.txt new file mode 100644 index 0000000..6905de6 --- /dev/null +++ b/datafiles/memory/memory-chips.txt @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# This is intentionally *completely* inaccurate but Intel is not +# saying which chips will have these instructions publicly at this +# time and I had to put the new instructions on some chip so I made +# somethign up. + +MEMORY_FUTURE: ALL_OF(SKYLAKE_SERVER) CLFLUSHOPT CLWB diff --git a/datafiles/mpx/cpuid.xed.txt b/datafiles/mpx/cpuid.xed.txt new file mode 100644 index 0000000..735ee92 --- /dev/null +++ b/datafiles/mpx/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_MPX: mpx.7.0.ebx.14 diff --git a/datafiles/mpx/files.cfg b/datafiles/mpx/files.cfg new file mode 100644 index 0000000..aaaeb10 --- /dev/null +++ b/datafiles/mpx/files.cfg @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +dec-instructions:mpx-isa.txt +enc-instructions:mpx-isa.txt + + dec-patterns:mpx-reg-check.txt + enc-patterns:mpx-reg-check-enc.txt + + dec-patterns:mpx-reg-tables.txt +enc-dec-patterns:mpx-reg-tables.txt + + registers:mpx-regs.txt + fields:mpx-fields.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/mpx/mpx-fields.txt b/datafiles/mpx/mpx-fields.txt new file mode 100644 index 0000000..6d24a78 --- /dev/null +++ b/datafiles/mpx/mpx-fields.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +MPXMODE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI diff --git a/datafiles/mpx/mpx-isa.txt b/datafiles/mpx/mpx-isa.txt new file mode 100644 index 0000000..b09ad37 --- /dev/null +++ b/datafiles/mpx/mpx-isa.txt @@ -0,0 +1,225 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + + +UDELETE: NOP0F1A +UDELETE: NOP0F1B + + + +{ +ICLASS: BNDMK +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: NO_RIP_REL +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():w AGEN:r +} + + + + +{ +ICLASS: BNDCL +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCU +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCN +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r + +} + +{ +ICLASS: BNDMOV +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: load form + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_R():w REG1=BND_B():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 + + + +} + +{ +ICLASS: BNDMOV +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: store form + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_B():w REG1=BND_R():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r +} + + +{ +ICLASS: BNDLDX +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:bnd32 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +} + +{ +ICLASS: BNDSTX +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: MEM0:w:bnd32 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +} + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. + +PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} + + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : For MPXMODE=0 operation + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEMv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEM_0F1B +} + + diff --git a/datafiles/mpx/mpx-reg-check-enc.txt b/datafiles/mpx/mpx-reg-check-enc.txt new file mode 100644 index 0000000..06e1a2e --- /dev/null +++ b/datafiles/mpx/mpx-reg-check-enc.txt @@ -0,0 +1,52 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND_R_CHECK():: +REXR=0 REG=0x0 -> nothing +REXR=0 REG=0x1 -> nothing +REXR=0 REG=0x2 -> nothing +REXR=0 REG=0x3 -> nothing +REXR=0 REG=0x4 -> error +REXR=0 REG=0x5 -> error +REXR=0 REG=0x6 -> error +REXR=0 REG=0x7 -> error +REXR=1 REG=0x0 -> error +REXR=1 REG=0x1 -> error +REXR=1 REG=0x2 -> error +REXR=1 REG=0x3 -> error +REXR=1 REG=0x4 -> error +REXR=1 REG=0x5 -> error +REXR=1 REG=0x6 -> error +REXR=1 REG=0x7 -> error + +BND_B_CHECK():: +REXB=0 RM=0x0 -> nothing +REXB=0 RM=0x1 -> nothing +REXB=0 RM=0x2 -> nothing +REXB=0 RM=0x3 -> nothing +REXB=0 RM=0x4 -> error +REXB=0 RM=0x5 -> error +REXB=0 RM=0x6 -> error +REXB=0 RM=0x7 -> error +REXB=1 RM=0x0 -> error +REXB=1 RM=0x1 -> error +REXB=1 RM=0x2 -> error +REXB=1 RM=0x3 -> error +REXB=1 RM=0x4 -> error +REXB=1 RM=0x5 -> error +REXB=1 RM=0x6 -> error +REXB=1 RM=0x7 -> error diff --git a/datafiles/mpx/mpx-reg-check.txt b/datafiles/mpx/mpx-reg-check.txt new file mode 100644 index 0000000..99437f9 --- /dev/null +++ b/datafiles/mpx/mpx-reg-check.txt @@ -0,0 +1,52 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND_R_CHECK():: +REXR=0 REG=0x0 | +REXR=0 REG=0x1 | +REXR=0 REG=0x2 | +REXR=0 REG=0x3 | +REXR=0 REG=0x4 | error +REXR=0 REG=0x5 | error +REXR=0 REG=0x6 | error +REXR=0 REG=0x7 | error +REXR=1 REG=0x0 | error +REXR=1 REG=0x1 | error +REXR=1 REG=0x2 | error +REXR=1 REG=0x3 | error +REXR=1 REG=0x4 | error +REXR=1 REG=0x5 | error +REXR=1 REG=0x6 | error +REXR=1 REG=0x7 | error + +BND_B_CHECK():: +REXB=0 RM=0x0 | +REXB=0 RM=0x1 | +REXB=0 RM=0x2 | +REXB=0 RM=0x3 | +REXB=0 RM=0x4 | error +REXB=0 RM=0x5 | error +REXB=0 RM=0x6 | error +REXB=0 RM=0x7 | error +REXB=1 RM=0x0 | error +REXB=1 RM=0x1 | error +REXB=1 RM=0x2 | error +REXB=1 RM=0x3 | error +REXB=1 RM=0x4 | error +REXB=1 RM=0x5 | error +REXB=1 RM=0x6 | error +REXB=1 RM=0x7 | error diff --git a/datafiles/mpx/mpx-reg-tables.txt b/datafiles/mpx/mpx-reg-tables.txt new file mode 100644 index 0000000..c1a2a75 --- /dev/null +++ b/datafiles/mpx/mpx-reg-tables.txt @@ -0,0 +1,52 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t BND_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_BND0 +REXR=0 REG=0x1 | OUTREG=XED_REG_BND1 +REXR=0 REG=0x2 | OUTREG=XED_REG_BND2 +REXR=0 REG=0x3 | OUTREG=XED_REG_BND3 +REXR=0 REG=0x4 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +xed_reg_enum_t BND_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_BND0 +REXB=0 RM=0x1 | OUTREG=XED_REG_BND1 +REXB=0 RM=0x2 | OUTREG=XED_REG_BND2 +REXB=0 RM=0x3 | OUTREG=XED_REG_BND3 +REXB=0 RM=0x4 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR diff --git a/datafiles/mpx/mpx-regs.txt b/datafiles/mpx/mpx-regs.txt new file mode 100644 index 0000000..6e42f86 --- /dev/null +++ b/datafiles/mpx/mpx-regs.txt @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND0 bound 128 BND0 0 +BND1 bound 128 BND1 1 +BND2 bound 128 BND2 2 +BND3 bound 128 BND3 3 +BNDCFGU bndcfg 64 BNDCFGU 0 +BNDSTATUS bndstat 64 BNDSTATUS 0 diff --git a/datafiles/mpx/tests/bulk-tests.txt b/datafiles/mpx/tests/bulk-tests.txt new file mode 100644 index 0000000..3e59254 --- /dev/null +++ b/datafiles/mpx/tests/bulk-tests.txt @@ -0,0 +1 @@ +BUILDDIR/xed -64 -de 0F 1B 0C 07 diff --git a/datafiles/mpx/tests/make.tests b/datafiles/mpx/tests/make.tests new file mode 100755 index 0000000..dbb1709 --- /dev/null +++ b/datafiles/mpx/tests/make.tests @@ -0,0 +1 @@ +../../../tests/run-cmd.py --bulk-make-tests bulk-tests.txt --build-dir ../../../obj diff --git a/datafiles/mpx/tests/run.tests b/datafiles/mpx/tests/run.tests new file mode 100755 index 0000000..fcd72d7 --- /dev/null +++ b/datafiles/mpx/tests/run.tests @@ -0,0 +1 @@ +../../../tests/run-cmd.py --build-dir ../../../obj diff --git a/datafiles/mpx/tests/test-00000/cmd b/datafiles/mpx/tests/test-00000/cmd new file mode 100644 index 0000000..3e59254 --- /dev/null +++ b/datafiles/mpx/tests/test-00000/cmd @@ -0,0 +1 @@ +BUILDDIR/xed -64 -de 0F 1B 0C 07 diff --git a/datafiles/mpx/tests/test-00000/retcode.reference b/datafiles/mpx/tests/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/datafiles/mpx/tests/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/datafiles/mpx/tests/test-00000/stderr.reference b/datafiles/mpx/tests/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/datafiles/mpx/tests/test-00000/stdout.reference b/datafiles/mpx/tests/test-00000/stdout.reference new file mode 100644 index 0000000..d5faa47 --- /dev/null +++ b/datafiles/mpx/tests/test-00000/stdout.reference @@ -0,0 +1,5 @@ +0F1B0C07 +ICLASS: BNDSTX CATEGORY: MPX EXTENSION: MPX IFORM: BNDSTX_MEMbnd64_BND ISA_SET: MPX +SHORT: bndstx ptr [rdi], bnd1, rax +Encodable! 0F1B0C07 +Identical re-encoding diff --git a/datafiles/oc2-extras.txt b/datafiles/oc2-extras.txt new file mode 100644 index 0000000..f7f06e4 --- /dev/null +++ b/datafiles/oc2-extras.txt @@ -0,0 +1,114 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# ssz, asz are new oc2 widths +# pseudo is a new oc2 width +# +# col0: reg or nt +# col1: regname or nt name +# col2: oc2 width +# +# +imm_const AGEN pseudo +reg AH b +reg AL b +reg AX w +reg CL b +reg CR0 y +reg CS w +reg DS w +reg DX w +reg EAX d +reg EBX d +reg ECX d +reg EDX d +reg EIP d +reg ES w +reg FS w +reg GDTR pseudo +reg GS w +reg IDTR pseudo +reg LDTR pseudo +reg MSRS pseudo +reg MXCSR d +reg RAX q +reg RBX q +reg RCX q +reg RDX q +reg RIP q +reg XCR0 q +reg SS w +reg TR pseudo +reg TSC pseudo +reg TSCAUX pseudo +reg X87CONTROL pseudo +reg X87POP pseudo +reg X87POP2 pseudo +reg X87PUSH pseudo +reg X87STATUS pseudo +reg X87TAG pseudo +reg X87TOP pseudo +# +nt ArBP asz +nt ArAX asz +nt ArBX asz +nt ArCX asz +nt ArDI asz +nt ArSI asz +nt CR_R y +nt DR_R y +nt GPR16_B w +nt GPR16_R w +nt GPR32_B d +nt GPR32_R d +nt GPR64_B q +nt GPR64_R q +nt GPR8_B b +nt GPR8_R b +nt GPRv_B v +nt GPRv_R v +nt GPRy_B y +nt GPRy_R y +nt GPRz_B z +nt GPRz_R z +nt GPRv_SB v +nt GPRv_SR v +nt GPR64_SB q +nt GPR64_SR q +nt GPR32_SB d +nt GPR32_SR d +nt GPR16_SB w +nt GPR16_SR w +nt GPR8_SB b +nt GPR8_SR b +nt OeAX v +nt OeBP v +nt OeBX v +nt OeCX v +nt OeDI v +nt OeDX v +nt OeSI v +nt OeSP v +nt OrAX v +nt OrBP v +nt OrDX v +nt OrSP v +nt SEG w +nt SrSP ssz +nt rFLAGS y +nt rIP v diff --git a/datafiles/pku/cpuid.xed.txt b/datafiles/pku/cpuid.xed.txt new file mode 100644 index 0000000..c74939d --- /dev/null +++ b/datafiles/pku/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_PKU: pku.7.0.ecx.3 ospku.7.0.ecx.4 diff --git a/datafiles/pku/files.cfg b/datafiles/pku/files.cfg new file mode 100644 index 0000000..2fab56d --- /dev/null +++ b/datafiles/pku/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: pku-isa.xed.txt + enc-instructions: pku-isa.xed.txt + cpuid: cpuid.xed.txt + diff --git a/datafiles/pku/pku-isa.xed.txt b/datafiles/pku/pku-isa.xed.txt new file mode 100644 index 0000000..17fb619 --- /dev/null +++ b/datafiles/pku/pku-isa.xed.txt @@ -0,0 +1,44 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +{ +ICLASS: RDPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] +OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP +} + + +{ +ICLASS: WRPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] +OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP +} + diff --git a/datafiles/pt/files.cfg b/datafiles/pt/files.cfg new file mode 100644 index 0000000..1e67e4b --- /dev/null +++ b/datafiles/pt/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: intelpt-isa.xed.txt + enc-instructions: intelpt-isa.xed.txt + chip-models: future-chips.txt + diff --git a/datafiles/pt/future-chips.txt b/datafiles/pt/future-chips.txt new file mode 100644 index 0000000..bc97a9c --- /dev/null +++ b/datafiles/pt/future-chips.txt @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# This is intentionally *completely* inaccurate but Intel is not +# saying which chips will have these instructions publicly at this +# time and I had to put the new instructions on some chip so I made +# somethign up. + +FUTURE: ALL_OF(SKYLAKE_SERVER) PT diff --git a/datafiles/pt/intelpt-isa.xed.txt b/datafiles/pt/intelpt-isa.xed.txt new file mode 100644 index 0000000..8880456 --- /dev/null +++ b/datafiles/pt/intelpt-isa.xed.txt @@ -0,0 +1,31 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : PTWRITE +CPL : 3 +CATEGORY : PT +EXTENSION : PT +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:y + +} diff --git a/datafiles/sgx/cpuid.xed.txt b/datafiles/sgx/cpuid.xed.txt new file mode 100644 index 0000000..ffcaf59 --- /dev/null +++ b/datafiles/sgx/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_SGX: sgx.7.0.ebx.2 diff --git a/datafiles/sgx/files.cfg b/datafiles/sgx/files.cfg new file mode 100644 index 0000000..b53f841 --- /dev/null +++ b/datafiles/sgx/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions: sgx-isa.xed.txt + enc-instructions: sgx-isa.xed.txt + cpuid: cpuid.xed.txt + diff --git a/datafiles/sgx/sgx-isa.xed.txt b/datafiles/sgx/sgx-isa.xed.txt new file mode 100644 index 0000000..29d8a9d --- /dev/null +++ b/datafiles/sgx/sgx-isa.xed.txt @@ -0,0 +1,59 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +# Both read EAX +# Both may read or write or r/w RBX, RCX, RDX +# ENCLU 0f 01 D7 +# D7 = 1101 0111 + +# ENCLS 0f 01 CF +# CF = 1100_1111 + + + +{ +ICLASS: ENCLU +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP +} + +{ + +ICLASS: ENCLS +CPL: 0 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP + +} diff --git a/datafiles/sha/cpuid.xed.txt b/datafiles/sha/cpuid.xed.txt new file mode 100644 index 0000000..6f0f8da --- /dev/null +++ b/datafiles/sha/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_SHA: sha.7.0.ebx.29 diff --git a/datafiles/sha/files.cfg b/datafiles/sha/files.cfg new file mode 100644 index 0000000..d22c0b2 --- /dev/null +++ b/datafiles/sha/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions: sha-isa.xed.txt + enc-instructions: sha-isa.xed.txt +cpuid : cpuid.xed.txt diff --git a/datafiles/sha/sha-isa.xed.txt b/datafiles/sha/sha-isa.xed.txt new file mode 100644 index 0000000..ac53229 --- /dev/null +++ b/datafiles/sha/sha-isa.xed.txt @@ -0,0 +1,230 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SHA1MSG1 (SHA1MSG1-N/A-1) +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1MSG2 (SHA1MSG2-N/A-1) +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1) +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1) +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA +} + +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA +} + + +# EMITTING SHA256MSG1 (SHA256MSG1-N/A-1) +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256MSG2 (SHA256MSG2-N/A-1) +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1) +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA +} + + diff --git a/datafiles/skl/files.cfg b/datafiles/skl/files.cfg new file mode 100644 index 0000000..1ba6adc --- /dev/null +++ b/datafiles/skl/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + chip-models:skl-chips.txt + diff --git a/datafiles/skl/skl-chips.txt b/datafiles/skl/skl-chips.txt new file mode 100644 index 0000000..65f8593 --- /dev/null +++ b/datafiles/skl/skl-chips.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SKYLAKE: ALL_OF(BROADWELL) MPX XSAVEC XSAVES SGX CLFLUSHOPT diff --git a/datafiles/skx/files.cfg b/datafiles/skx/files.cfg new file mode 100644 index 0000000..c6a202d --- /dev/null +++ b/datafiles/skx/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + chip-models:skx-chips.txt diff --git a/datafiles/skx/skx-chips.txt b/datafiles/skx/skx-chips.txt new file mode 100644 index 0000000..ff15518 --- /dev/null +++ b/datafiles/skx/skx-chips.txt @@ -0,0 +1,42 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +SKYLAKE_SERVER: ALL_OF(SKYLAKE) PKU \ + AVX512F_512 \ + AVX512F_128 \ + AVX512F_128N \ + AVX512F_256 \ + AVX512F_KOP \ + AVX512F_SCALAR \ + AVX512BW_128 \ + AVX512BW_128N \ + AVX512BW_256 \ + AVX512BW_512 \ + AVX512BW_KOP \ + AVX512CD_128 \ + AVX512CD_256 \ + AVX512CD_512 \ + AVX512DQ_128 \ + AVX512DQ_128N \ + AVX512DQ_256 \ + AVX512DQ_512 \ + AVX512DQ_KOP \ + AVX512DQ_SCALAR + + diff --git a/datafiles/vpopcntdq-512/cpuid.xed.txt b/datafiles/vpopcntdq-512/cpuid.xed.txt new file mode 100644 index 0000000..1e09787 --- /dev/null +++ b/datafiles/vpopcntdq-512/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VPOPCNTDQ_512: avx512_vpopcntdq.7.0.ecx.14 diff --git a/datafiles/vpopcntdq-512/files.cfg b/datafiles/vpopcntdq-512/files.cfg new file mode 100644 index 0000000..1f84714 --- /dev/null +++ b/datafiles/vpopcntdq-512/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + dec-instructions: vpopcntdq-512-isa.xed.txt + enc-instructions: vpopcntdq-512-isa.xed.txt + + cpuid: cpuid.xed.txt + diff --git a/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt b/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt new file mode 100644 index 0000000..10e3309 --- /dev/null +++ b/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt @@ -0,0 +1,87 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-512-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-512-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + diff --git a/datafiles/xed-addr-width-enum.txt b/datafiles/xed-addr-width-enum.txt new file mode 100644 index 0000000..dd424ed --- /dev/null +++ b/datafiles/xed-addr-width-enum.txt @@ -0,0 +1,30 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-address-width-enum.h +cfn xed-address-width-enum.c +prefix XED_ADDRESS_WIDTH_ +typename xed_address_width_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID 0 +16b 2 ///< 16b addressing +32b 4 ///< 32b addressing +64b 8 ///< 64b addressing + diff --git a/datafiles/xed-addressing-modes-new.txt b/datafiles/xed-addressing-modes-new.txt new file mode 100644 index 0000000..e101a59 --- /dev/null +++ b/datafiles/xed-addressing-modes-new.txt @@ -0,0 +1,385 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-addressing-modes-new.txt +########################################################################### + +# inputs: +# REX = REX or NOREX +# REXB = REXB0 or REXB1 +# REXX = REXX0 or REXX1 +# MODE = MODE32 or MODE64 + +# outputs: +# SEG0, BASE0, INDEX, SCALE, DISP and +# a register id to be evaluated at a higher level + +# The 32b and 64b share SIB/SIB_BASE0 productions. The registers there +# have to be converted to the right width. Similarly, the rAX'es etc +# in the MODRM64alt32 need to be scaled by ASZ. So rAX is either RAX +# or EAX and r15 is either R15 or R15D depending on ASZ. + +# Sooo. for the BASE0/SIB_BASE0,INDEX, we need a lookup like: +# base_or_index_reg_lookup(rex,rexb/x,RM,mode,asz) +# The ASZ operand will do different things. In 32b mode it is not used +# because the ASZ would take use to 16 mode addressing. In 64b mode, +# it tells use to use 64 or 32b registers. + + + + +############################################################################ +MODRM():: +# +# NOTE: I set MODRM=1 so that we can tell if it was one of the +# instructions that has a memop, but no MODRM byte. +# +# NOTE: the RIP handling in 64b mode with effective addessing of 32b +# is different than the 32b addressing in 32b mode when MODRM.MOD=00_ +# and MODRM.RM=101, where it is just #a base, not RIP relative. +# +mode64 eamode64 MODRM64alt32() MEMDISP() | MODRM=1 +mode64 eamode32 MODRM64alt32() MEMDISP() | MODRM=1 +mode32 eamode32 MODRM32() MEMDISP() | MODRM=1 +mode32 eamode16 MODRM16() MEMDISP() | MODRM=1 +mode16 eamode32 MODRM32() MEMDISP() | MODRM=1 +mode16 eamode16 MODRM16() MEMDISP() | MODRM=1 + + +############################################################################ + +MODRM64alt32():: + REXB=0 MOD=0b00 RM=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b100 SIB() | + REXB=1 MOD=0b00 RM=0b100 SIB() | + +# Ignores rexb -- must duplicate to avoid dont-care problems + REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_RIP SEG0=FINAL_DSEG() enc + REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_RIP SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() + +############################################ + + REXB=0 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + REXB=1 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + + REXB=0 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=ArBP() SEG0=FINAL_SSEG() + REXB=1 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar13() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar15() SEG0=FINAL_DSEG() + + +############################################ + + REXB=0 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + REXB=1 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + + REXB=0 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=ArBP() SEG0=FINAL_SSEG() + REXB=1 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar13() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar15() SEG0=FINAL_DSEG() + +############################################ + + +MODRM32():: + MOD=0b00 RM=0b000 | BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b001 | BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b010 | BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b011 | BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b100 SIB() | + MOD=0b00 RM=0b101 | NEED_MEMDISP=32 SEG0=FINAL_DSEG() + MOD=0b00 RM=0b110 | BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b00 RM=0b111 | BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +#################################### + MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() + MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +#################################### + MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() + MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +############################################ + + + +################################################### +# 16 bit addressing MODRM bytes +MODRM16():: + MOD=0b00 RM=0b000 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b00 RM=0b001 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b00 RM=0b010 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b00 RM=0b011 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b00 RM=0b100 | BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b00 RM=0b101 | BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b00 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b00 RM=0b111 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + +############################################# + + MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b01 RM=0b100 | NEED_MEMDISP=8 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID + MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + +############################################# + MOD=0b10 RM=0b000 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b10 RM=0b001 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b10 RM=0b010 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b10 RM=0b011 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b10 RM=0b100 | NEED_MEMDISP=16 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b10 RM=0b101 | NEED_MEMDISP=16 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b10 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID + MOD=0b10 RM=0b111 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID +############################################ + +SIB():: + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 enc + REXX=1 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=1 + + + + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=2 + + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=2 + + + + + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=4 + + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=4 + + + + + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=8 + + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=8 + + +################################################### + +SIB_BASE0():: + + REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() + REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG() + REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG() + +# FIXME the d/8 for MOD=01_ and d/32 for MOD=10_ case are redundantly +# specified in the manuals. I removed them from here, but the d/32 for +# MOD=00_ is required as it is unique. + +# I redunantly specify DISP_WIDTH=8 or DISPWITH=32 for the MOD=01_ and +# MOD=10_ cases so that the encoder will pick the right one even though we +# accept the displacment at a higher level. + + REXB=0 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() enc + REXB=0 SIBBASE=0b101 MOD=0b01 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=8 + REXB=0 SIBBASE=0b101 MOD=0b10 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=32 + + REXB=1 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b101 MOD=0b01 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=8 + REXB=1 SIBBASE=0b101 MOD=0b10 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=32 + + REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() + +#FIXME: 2008-10-01 make these in to nops! +OVERRIDE_SEG0():: +mode16 | +mode32 | +mode64 | + +OVERRIDE_SEG1():: +mode16 | +mode32 | +mode64 | diff --git a/datafiles/xed-amd-3dnow.txt b/datafiles/xed-amd-3dnow.txt new file mode 100644 index 0000000..bd0d50a --- /dev/null +++ b/datafiles/xed-amd-3dnow.txt @@ -0,0 +1,412 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : FEMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : 3DNOW +ATTRIBUTES : x87_mmx_state_w +PATTERN : 0x0F 0x0E +OPERANDS : +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} diff --git a/datafiles/xed-amd-base.txt b/datafiles/xed-amd-base.txt new file mode 100644 index 0000000..34d7193 --- /dev/null +++ b/datafiles/xed-amd-base.txt @@ -0,0 +1,47 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# file: xed-amd-base.txt + +INSTRUCTIONS():: +# SYSCALL and SYSRET are supported in 32b mode only on AMD chips + +{ +ICLASS : SYSCALL_AMD +DISASM : syscall +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : AMD +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 not64 IGNORE66() +OPERANDS : REG0=rIP():w:SUPP +} + + +{ +ICLASS : SYSRET_AMD +DISASM : sysret +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 +EXTENSION : BASE +ISA_SET : AMD +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +} diff --git a/datafiles/xed-amd-clzero.txt b/datafiles/xed-amd-clzero.txt new file mode 100644 index 0000000..64edec3 --- /dev/null +++ b/datafiles/xed-amd-clzero.txt @@ -0,0 +1,27 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : CLZERO +CPL : 3 +CATEGORY : CLZERO +EXTENSION : CLZERO +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=OrAX():r:IMPL +COMMENT : AMD "Zen" ~2016 (expected) CPU +} diff --git a/datafiles/xed-amd-prefetch.txt b/datafiles/xed-amd-prefetch.txt new file mode 100644 index 0000000..fa936f5 --- /dev/null +++ b/datafiles/xed-amd-prefetch.txt @@ -0,0 +1,105 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : NOP +UNAME : NOP0F0D_reg +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : PREFETCH_NOP +COMMENT : AMD 3DNOW prefetches that do not touch memory. This is the reg/reg form. + +PATTERN : 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F0D +} + +# The rest are all mem forms (MODRM.MOD!=3) + +{ +ICLASS : PREFETCH_EXCLUSIVE +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW +COMMENT: : was PREFETCH_MODIFIED, prefetch on >=broadwell and >=silvermont +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr1 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr2 +UNAME : PREFETCH_RESERVED_0F0Dr2 +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW +COMMENT: : was PREFETCH_MODIFIED +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr3 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr4 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr5 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr6 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr7 +} + diff --git a/datafiles/xed-amd-sse4a.txt b/datafiles/xed-amd-sse4a.txt new file mode 100644 index 0000000..cbada6c --- /dev/null +++ b/datafiles/xed-amd-sse4a.txt @@ -0,0 +1,103 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib +# EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r + +{ +ICLASS : EXTRQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_R():w:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + +# INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib +# INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r + +{ +ICLASS : INSERTQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + + +# MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r +# MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r + +{ +ICLASS : MOVNTSD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +} +{ +ICLASS : MOVNTSS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +} + +######################################################################################################### +# These next one is not part of SSE4a or SSE5. + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : AMD +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 1 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} diff --git a/datafiles/xed-amd-svm.txt b/datafiles/xed-amd-svm.txt new file mode 100644 index 0000000..8ee9a48 --- /dev/null +++ b/datafiles/xed-amd-svm.txt @@ -0,0 +1,89 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : VMRUN +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] +OPERANDS : REG0=OrAX():r:IMPL +} +{ +ICLASS : VMMCALL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : +} +{ +ICLASS : VMLOAD +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] +OPERANDS : REG0=OrAX():r:IMPL +} +{ +ICLASS : VMSAVE +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] +OPERANDS : +} +{ +ICLASS : STGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] +OPERANDS : +} +{ +ICLASS : CLGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] +OPERANDS : +} +{ +ICLASS : SKINIT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] +OPERANDS : REG0=XED_REG_EAX:r:IMPL +} +{ +ICLASS : INVLPGA +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] +OPERANDS : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL +} diff --git a/datafiles/xed-chips.txt b/datafiles/xed-chips.txt new file mode 100644 index 0000000..6cef846 --- /dev/null +++ b/datafiles/xed-chips.txt @@ -0,0 +1,101 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# This file is for defining sets of extensions implemented by various chips +# +# The first column is a chip name. It will become the source for the enum xed_chip_t XED_CHIP_* +# The rest of the columns are ISA extensions that that CHIP implements +# ALL_OF(x) is a macro that refers to the set defined previously for some chip x. +# NOT(y) is a macro that removes a specific ISA extension (processed last) + +I86: I86 LAHF +I86FP: I86 LAHF X87 + +I186: ALL_OF(I86) I186 + # BOUND, ENTER, INS/INSB/INSW, LEAVE, OUTS/OUTSB/OUTSW, POPA, PUSHA +I186FP: ALL_OF(I186) X87 + +I286REAL: ALL_OF(I186) I286REAL X87 +I286: ALL_OF(I286REAL) I286PROTECTED + # ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, + # LOADALL(undoc), LSL, LTR, SGDT, SIDT,SLDT, SMSW, STR,VERR,VERW +I2186FP: ALL_OF(I286) X87 + +# 386 did not add any instr to real mode +I386REAL: ALL_OF(I286REAL) +I386: ALL_OF(I386REAL) ALL_OF(I286) I386 + # BSF, BSR, BT, BTC, BTR,BTS, CDQ, CMPSD,CWDE, INSD, IRET*, JECXZ, + # LFS, LGS,LSS, LOADALL(undoc), LODSD, LOOP, MOVSD + # MOVSX, OUTSD, POPAD POPFD, PUSHAD PUSHD PUSHFD, SCASD + # SETcc* SHLD, SHRD, STOSD +I386FP: ALL_OF(I386) X87 + +I486REAL: ALL_OF(I386REAL) I486REAL # BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM,WBINVD,XADD +I486: ALL_OF(I486REAL) ALL_OF(I386) I486 X87 # RSM + +PENTIUMREAL: ALL_OF(I486REAL) PENTIUMREAL # CMPXCHG8B, RDMSR, RDTSC, WRMSR +PENTIUM: ALL_OF(PENTIUMREAL) ALL_OF(I486) +# Quark is PENTIUM ISA, but not Pentium implementation. +QUARK: ALL_OF(PENTIUM) + +PENTIUMMMXREAL: ALL_OF(PENTIUMREAL) RDPMC # P55C++ RDPMC +PENTIUMMMX: ALL_OF(PENTIUMMMXREAL) ALL_OF(PENTIUM) PENTIUMMMX # P55C++ + +ALLREAL: ALL_OF(PENTIUMMMXREAL) + +# P6, PentiumPro, PPRO: +# The SSE_PREFETCH were on P6 as fat NOPs, but XED only recognizes them on >=PENTIUM3 +PENTIUMPRO: ALL_OF(PENTIUM) PPRO RDPMC FAT_NOP PREFETCH_NOP # NO MMX (Orig P6) + # FCMOV*, CMOV*, RDPMC, SYSCALL, SYSENTER, SYSEXIT,SYSRET, UD2, F[U]COMI[P] + # note conflict with PENTIUM2 addition of SYSENTER/SYSEXIT + + +PENTIUM2: ALL_OF(PENTIUM) PENTIUMMMX PPRO FAT_NOP RDPMC PREFETCH_NOP FXSAVE + # FXSAVE/FXRSTOR, SYSENTER,SYSEXIT P6 + +# we keep SSEMXCSR separate from SSE to accomodate chip-check for KNC +# which only implements LDMXCSR/STMXCSR from SSE. +# The SSE_PREFETCH came in as NOPs on P6/PPRO. innaccuracy... +PENTIUM3: ALL_OF(PENTIUM2) SSE SSEMXCSR SSE_PREFETCH # SSE(incl. ldmxcsr/stmxcsr) (KNI) + +PENTIUM4: ALL_OF(PENTIUM3) SSE2 CLFSH PAUSE +P4PRESCOTT: ALL_OF(PENTIUM4) SSE3 LONGMODE CMPXCHG16B FXSAVE64 + +# Made a chip for the P4's that omit LAHF in 64b mode +P4PRESCOTT_NOLAHF: ALL_OF(P4PRESCOTT) NOT(LAHF) + +P4PRESCOTT_VTX: ALL_OF(P4PRESCOTT) VTX + +CORE2: ALL_OF(P4PRESCOTT) VTX SSSE3 SMX + +PENRYN: ALL_OF(CORE2) SSE4 +PENRYN_E: ALL_OF(PENRYN) XSAVE +NEHALEM: ALL_OF(PENRYN) SSE42 POPCNT RDTSCP +WESTMERE: ALL_OF(NEHALEM) AES PCLMULQDQ + +# ATOM +BONNELL: ALL_OF(CORE2) MOVBE NOT(SMX) +SALTWELL: ALL_OF(BONNELL) + +# PREFETCHW semantics added to PREFETCHW opcode but not subject +# to chip-check because of prior implemntation as NOP. +SILVERMONT: ALL_OF(WESTMERE) MOVBE RDRAND + + +# AMD CHIPS??? +AMD: SVM SSE4A 3DNOW AMD PREFETCH_NOP PREFETCHW XOP TBM FMA4 CLZERO + diff --git a/datafiles/xed-convert.txt b/datafiles/xed-convert.txt new file mode 100644 index 0000000..f7106ac --- /dev/null +++ b/datafiles/xed-convert.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# empty file + diff --git a/datafiles/xed-eASZ.txt b/datafiles/xed-eASZ.txt new file mode 100644 index 0000000..ffbbb9c --- /dev/null +++ b/datafiles/xed-eASZ.txt @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-eASZ.txt +########################################################################### +# Call this after all legacy prefixes and before every instruction! + + +ASZ_NONTERM():: + +mode16 no67_prefix | eamode16 +mode16 67_prefix | eamode32 + +mode32 no67_prefix | eamode32 +mode32 67_prefix | eamode16 + +mode64 no67_prefix | eamode64 +mode64 67_prefix | eamode32 diff --git a/datafiles/xed-eOSZ.txt b/datafiles/xed-eOSZ.txt new file mode 100644 index 0000000..411ca2b --- /dev/null +++ b/datafiles/xed-eOSZ.txt @@ -0,0 +1,101 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-eOSZ.txt +########################################################################### + +OSZ_NONTERM():: + +mode16 no66_prefix | EOSZ=1 +mode16 66_prefix | EOSZ=2 + +mode32 66_prefix | EOSZ=1 +mode32 no66_prefix | EOSZ=2 + +# NOTE this can get overridden later if a DF64 NT shows up. +mode64 66_prefix norexw_prefix | EOSZ=1 +mode64 no66_prefix norexw_prefix | EOSZ=2 +mode64 66_prefix rexw_prefix | EOSZ=3 +mode64 no66_prefix rexw_prefix | EOSZ=3 + + +# Things that default to 64b mode invoke this nonterminal once they +# are identified to denote that fact. Placement of this nonterminal is +# critical for those operations and the ones the might collide with +# during decoding. See PUSHF/PUSHFD/PUSHFQ. +# +# Denote the DF64=1 (df64). +DF64():: +mode16 | +mode32 | +mode64 66_prefix norexw_prefix | EOSZ=1 df64 +mode64 no66_prefix norexw_prefix | EOSZ=3 df64 +mode64 66_prefix rexw_prefix | EOSZ=3 df64 +mode64 no66_prefix rexw_prefix | EOSZ=3 df64 + +# if we have a refining OSZ 0x66 prefix, then we must undo the effects +# of the OSZ_NONTERM(). DF64 is not used with anything that has refining 66 prefixes. +# We turn off the osze prefix because it is really behaving like a refining prefix for these instructions. +REFINING66():: +mode16 | EOSZ=1 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 norexw_prefix | EOSZ=2 no66_prefix +mode64 rexw_prefix | EOSZ=3 no66_prefix + +IGNORE66():: +mode16 | EOSZ=1 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 norexw_prefix | EOSZ=2 no66_prefix +mode64 rexw_prefix | EOSZ=3 no66_prefix + + +# IMMUNE66() is used to make 16b mode behave like 32b mode. +# Used for: +# cmpxchg8b / cmpxchg16b, +# NHM sttni instr: pcmpestri, pcmpistrm, pcmpestrm, pcmpistri, +# BDW adox, adcx. +# +IMMUNE66():: +mode16 | EOSZ=2 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 norexw_prefix | EOSZ=2 no66_prefix +mode64 rexw_prefix | EOSZ=3 no66_prefix + +CR_WIDTH():: +mode16 | EOSZ=2 DF32=1 no66_prefix +mode32 | EOSZ=2 DF32=1 no66_prefix +mode64 | EOSZ=3 DF64=1 no66_prefix + + +IMMUNE66_LOOP64():: +mode16 | +mode32 | +mode64 | EOSZ=3 no66_prefix + +IMMUNE_REXW():: +mode16 | +mode32 | +mode64 no66_prefix | EOSZ=2 +mode64 66_prefix rexw_prefix | EOSZ=2 +mode64 66_prefix norexw_prefix | EOSZ=1 + +# FORCE64() can only be used with mode64 stuff (else encode does not +# work). see IMMUNE66_LOOP64() for something that works in all modes. +FORCE64():: +mode64 | EOSZ=3 no66_prefix +otherwise | diff --git a/datafiles/xed-error-enum.txt b/datafiles/xed-error-enum.txt new file mode 100644 index 0000000..d9c2e77 --- /dev/null +++ b/datafiles/xed-error-enum.txt @@ -0,0 +1,45 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-error-enum.h +cfn xed-error-enum.c +prefix XED_ERROR_ +typename xed_error_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +density dense +NONE ///< There was no error +BUFFER_TOO_SHORT ///< There were not enough bytes in the given buffer +GENERAL_ERROR ///< XED could not decode the given instruction +INVALID_FOR_CHIP ///< The instruciton is not valid for the specified chip +BAD_REGISTER ///< XED could not decode the given instruction because an invalid register encoding was used. +BAD_LOCK_PREFIX ///< A lock prefix was found where none is allowed. +BAD_REP_PREFIX ///< An F2 or F3 prefix was found where none is allowed. +BAD_LEGACY_PREFIX ///< A 66, F2 or F3 prefix was found where none is allowed. +BAD_REX_PREFIX ///< A REX prefix was found where none is allowed. +BAD_EVEX_UBIT ///< An illegal value for the EVEX.U bit was present in the instruction. +BAD_MAP ///< An illegal value for the MAP field was detected in the instruction. +BAD_EVEX_V_PRIME ///< EVEX.V'=0 was detected in a non-64b mode instruction. +NO_OUTPUT_POINTER ///< The output pointer for xed_agen was zero +NO_AGEN_CALL_BACK_REGISTERED ///< One or both of the callbacks for xed_agen were missing. +BAD_MEMOP_INDEX ///< Memop indices must be 0 or 1. +CALLBACK_PROBLEM ///< The register or segment callback for xed_agen experienced a problem +GATHER_REGS ///< The index, dest and mask regs for AVX2 gathers must be different. +INSTR_TOO_LONG ///< Full decode of instruction would exeed 15B. +INVALID_MODE ///< The instruction was not valid for the specified mode diff --git a/datafiles/xed-exceptions.txt b/datafiles/xed-exceptions.txt new file mode 100644 index 0000000..65aeb2e --- /dev/null +++ b/datafiles/xed-exceptions.txt @@ -0,0 +1,277 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +## comments are double # signs in this file +## interrupt symbol name fault/trap/etc +## FIXME: add error code indicator? + +0 #DE "Divide Error Exception" fault +1 #DB "Debug Exception" trap-or-fault +2 NMI "NMI interrupt" other +3 #BP "Breakpoint Exception" trap +4 #OF "Overflow Exception" trap +5 #BR "Bound range exceeded exception" fault +6 #UD "Invalid opcode exception" fault +7 #NM "Device not available exception" fault +8 #DF "Double fault exception" abort +9 #9 "Coprocessor Segment Overrun - reserved" other +10 #TS "Invalid TSS exception" fault +11 #NP "Segment not present" fault +12 #SS "Stack fault exception" fault +13 #GP "General protection exception" fault +14 #PF "Page fault exception" fault +15 #15 "reserved" reserved +16 #MF "x87 FPU floating point error" fault +17 #AC "Alignment check exception" fault +18 #MC "Machine-check exception" abort +19 #XF "SIMD floating point exception" fault +20 #20 "reserved" reserved +21 #21 "reserved" reserved +22 #22 "reserved" reserved +23 #23 "reserved" reserved +24 #24 "reserved" reserved +25 #25 "reserved" reserved +26 #26 "reserved" reserved +27 #27 "reserved" reserved +28 #28 "reserved" reserved +29 #29 "reserved" reserved +30 #30 "reserved" reserved +31 #31 "reserved" reserved +32 #32 "user defined" interrupt +33 #33 "user defined" interrupt +34 #34 "user defined" interrupt +35 #35 "user defined" interrupt +36 #36 "user defined" interrupt +37 #37 "user defined" interrupt +38 #38 "user defined" interrupt +39 #39 "user defined" interrupt +40 #40 "user defined" interrupt +41 #41 "user defined" interrupt +42 #42 "user defined" interrupt +43 #43 "user defined" interrupt +44 #44 "user defined" interrupt +45 #45 "user defined" interrupt +46 #46 "user defined" interrupt +47 #47 "user defined" interrupt +48 #48 "user defined" interrupt +49 #49 "user defined" interrupt +50 #50 "user defined" interrupt +51 #51 "user defined" interrupt +52 #52 "user defined" interrupt +53 #53 "user defined" interrupt +54 #54 "user defined" interrupt +55 #55 "user defined" interrupt +56 #56 "user defined" interrupt +57 #57 "user defined" interrupt +58 #58 "user defined" interrupt +59 #59 "user defined" interrupt +60 #60 "user defined" interrupt +61 #61 "user defined" interrupt +62 #62 "user defined" interrupt +63 #63 "user defined" interrupt +64 #64 "user defined" interrupt +65 #65 "user defined" interrupt +66 #66 "user defined" interrupt +67 #67 "user defined" interrupt +68 #68 "user defined" interrupt +69 #69 "user defined" interrupt +70 #70 "user defined" interrupt +71 #71 "user defined" interrupt +72 #72 "user defined" interrupt +73 #73 "user defined" interrupt +74 #74 "user defined" interrupt +75 #75 "user defined" interrupt +76 #76 "user defined" interrupt +77 #77 "user defined" interrupt +78 #78 "user defined" interrupt +79 #79 "user defined" interrupt +80 #80 "user defined" interrupt +81 #81 "user defined" interrupt +82 #82 "user defined" interrupt +83 #83 "user defined" interrupt +84 #84 "user defined" interrupt +85 #85 "user defined" interrupt +86 #86 "user defined" interrupt +87 #87 "user defined" interrupt +88 #88 "user defined" interrupt +89 #89 "user defined" interrupt +90 #90 "user defined" interrupt +91 #91 "user defined" interrupt +92 #92 "user defined" interrupt +93 #93 "user defined" interrupt +94 #94 "user defined" interrupt +95 #95 "user defined" interrupt +96 #96 "user defined" interrupt +97 #97 "user defined" interrupt +98 #98 "user defined" interrupt +99 #99 "user defined" interrupt +100 #100 "user defined" interrupt +101 #101 "user defined" interrupt +102 #102 "user defined" interrupt +103 #103 "user defined" interrupt +104 #104 "user defined" interrupt +105 #105 "user defined" interrupt +106 #106 "user defined" interrupt +107 #107 "user defined" interrupt +108 #108 "user defined" interrupt +109 #109 "user defined" interrupt +110 #110 "user defined" interrupt +111 #111 "user defined" interrupt +112 #112 "user defined" interrupt +113 #113 "user defined" interrupt +114 #114 "user defined" interrupt +115 #115 "user defined" interrupt +116 #116 "user defined" interrupt +117 #117 "user defined" interrupt +118 #118 "user defined" interrupt +119 #119 "user defined" interrupt +120 #120 "user defined" interrupt +121 #121 "user defined" interrupt +122 #122 "user defined" interrupt +123 #123 "user defined" interrupt +124 #124 "user defined" interrupt +125 #125 "user defined" interrupt +126 #126 "user defined" interrupt +127 #127 "user defined" interrupt +128 #128 "user defined" interrupt +129 #129 "user defined" interrupt +130 #130 "user defined" interrupt +131 #131 "user defined" interrupt +132 #132 "user defined" interrupt +133 #133 "user defined" interrupt +134 #134 "user defined" interrupt +135 #135 "user defined" interrupt +136 #136 "user defined" interrupt +137 #137 "user defined" interrupt +138 #138 "user defined" interrupt +139 #139 "user defined" interrupt +140 #140 "user defined" interrupt +141 #141 "user defined" interrupt +142 #142 "user defined" interrupt +143 #143 "user defined" interrupt +144 #144 "user defined" interrupt +145 #145 "user defined" interrupt +146 #146 "user defined" interrupt +147 #147 "user defined" interrupt +148 #148 "user defined" interrupt +149 #149 "user defined" interrupt +150 #150 "user defined" interrupt +151 #151 "user defined" interrupt +152 #152 "user defined" interrupt +153 #153 "user defined" interrupt +154 #154 "user defined" interrupt +155 #155 "user defined" interrupt +156 #156 "user defined" interrupt +157 #157 "user defined" interrupt +158 #158 "user defined" interrupt +159 #159 "user defined" interrupt +160 #160 "user defined" interrupt +161 #161 "user defined" interrupt +162 #162 "user defined" interrupt +163 #163 "user defined" interrupt +164 #164 "user defined" interrupt +165 #165 "user defined" interrupt +166 #166 "user defined" interrupt +167 #167 "user defined" interrupt +168 #168 "user defined" interrupt +169 #169 "user defined" interrupt +170 #170 "user defined" interrupt +171 #171 "user defined" interrupt +172 #172 "user defined" interrupt +173 #173 "user defined" interrupt +174 #174 "user defined" interrupt +175 #175 "user defined" interrupt +176 #176 "user defined" interrupt +177 #177 "user defined" interrupt +178 #178 "user defined" interrupt +179 #179 "user defined" interrupt +180 #180 "user defined" interrupt +181 #181 "user defined" interrupt +182 #182 "user defined" interrupt +183 #183 "user defined" interrupt +184 #184 "user defined" interrupt +185 #185 "user defined" interrupt +186 #186 "user defined" interrupt +187 #187 "user defined" interrupt +188 #188 "user defined" interrupt +189 #189 "user defined" interrupt +190 #190 "user defined" interrupt +191 #191 "user defined" interrupt +192 #192 "user defined" interrupt +193 #193 "user defined" interrupt +194 #194 "user defined" interrupt +195 #195 "user defined" interrupt +196 #196 "user defined" interrupt +197 #197 "user defined" interrupt +198 #198 "user defined" interrupt +199 #199 "user defined" interrupt +200 #200 "user defined" interrupt +201 #201 "user defined" interrupt +202 #202 "user defined" interrupt +203 #203 "user defined" interrupt +204 #204 "user defined" interrupt +205 #205 "user defined" interrupt +206 #206 "user defined" interrupt +207 #207 "user defined" interrupt +208 #208 "user defined" interrupt +209 #209 "user defined" interrupt +210 #210 "user defined" interrupt +211 #211 "user defined" interrupt +212 #212 "user defined" interrupt +213 #213 "user defined" interrupt +214 #214 "user defined" interrupt +215 #215 "user defined" interrupt +216 #216 "user defined" interrupt +217 #217 "user defined" interrupt +218 #218 "user defined" interrupt +219 #219 "user defined" interrupt +220 #220 "user defined" interrupt +221 #221 "user defined" interrupt +222 #222 "user defined" interrupt +223 #223 "user defined" interrupt +224 #224 "user defined" interrupt +225 #225 "user defined" interrupt +226 #226 "user defined" interrupt +227 #227 "user defined" interrupt +228 #228 "user defined" interrupt +229 #229 "user defined" interrupt +230 #230 "user defined" interrupt +231 #231 "user defined" interrupt +232 #232 "user defined" interrupt +233 #233 "user defined" interrupt +234 #234 "user defined" interrupt +235 #235 "user defined" interrupt +236 #236 "user defined" interrupt +237 #237 "user defined" interrupt +238 #238 "user defined" interrupt +239 #239 "user defined" interrupt +240 #240 "user defined" interrupt +241 #241 "user defined" interrupt +242 #242 "user defined" interrupt +243 #243 "user defined" interrupt +244 #244 "user defined" interrupt +245 #245 "user defined" interrupt +246 #246 "user defined" interrupt +247 #247 "user defined" interrupt +248 #248 "user defined" interrupt +249 #249 "user defined" interrupt +250 #250 "user defined" interrupt +251 #251 "user defined" interrupt +252 #252 "user defined" interrupt +253 #253 "user defined" interrupt +254 #254 "user defined" interrupt +255 #255 "user defined" interrupt diff --git a/datafiles/xed-fields.txt b/datafiles/xed-fields.txt new file mode 100644 index 0000000..3bdcc84 --- /dev/null +++ b/datafiles/xed-fields.txt @@ -0,0 +1,225 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# @file xed-fields.txt + + +# visibilities are one of [EXPLICIT|IMPLICIT|SUPPRESSED] + +# Major properties of the fields are determined by the columns with +# the content {EI,EO} or {DI,DO,DS}. EI is encoder inputs and EO is +# for encoder outputs. DI is decoder inputs, DO is decoder +# outputs. And DS means "decoder skip" and is used for fields that +# show up in instruction pattern constraints but should be completely +# ignored by the decoder. + + +# INTERNAL means that the field is excluded from the instructions' +# operands array template. + + + +# ==== ====== ==== ========= ========== +# scalar default +# name array type bit-width visibility +# ==== ====== ==== ========= ========== +SEG_OVD SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO # FIXME: DO_EO? always an output + +# HINT: 0=no hint, +# 1=CS PREFIX OBSERVED (NOT TAKEN) +# 2=DS PREFIX OBSERVED (TAKEN) +# 3=NOT TAKEN HINT VALIDATED for a BRANCH +# 4=TAKEN HINT VALIDATED for a BRANCH +HINT SCALAR xed_bits_t 3 SUPPRESSED NOPRINT PUBLIC DO EI + +LOCK SCALAR xed_bits_t 1 SUPPRESSED PRINT PUBLIC DO EO + +NEED_MEMDISP SCALAR xed_bits_t 6 SUPPRESSED NOPRINT INTERNAL DO EO + +DISP SCALAR xed_int64_t 64 SUPPRESSED NOPRINT INTERNAL DO EI # MEMORY DISPLACEMENT + +DISP_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT PUBLIC DO EI # in bytes FIXME: could use log2 + +BRDISP_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # in bytes FIXME: could use log2 + +# DF32 is for MOV_CR & CR_WIDTH() NTs +DF32 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +DF64 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# NOREX is an unfortunate thing. It is only required to prevent +# encoding illegal instructions that have REX prefixes and use the +# AH/BH/CH/DH registers. It was not used for decoding + +NOREX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +NEEDREX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# 2013-09-25: This one is "DS" which means "decoder skip". It is +# ignored during parsing by the decoder. +# +SKIP_OSZ SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DS EO + + +REX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXW SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# refining must be used to interpret the REP output of decode +REP SCALAR xed_bits_t 2 SUPPRESSED PRINT PUBLIC DO EO # 0=no-rep, 2=F2, 3=F3 +OSZ SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +PREFIX66 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +ASZ SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# effective operand size and address size +EOSZ SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DO EI +EASZ SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DO EI + + + +#MODRM fields +MODRM SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +MOD SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +REG SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +# SRM is for partial-byte opcodes that capture a RM-like field. +SRM SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +RM SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +# Machine mode, addressing mode , stack addressing mode + +REALMODE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI +CHIP SCALAR xed_chip_enum_t 16 SUPPRESSED NOPRINT PUBLIC DI EI +MODE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DI EI +SMODE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DI EI +MODEP5 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI +# P55C introduced MMX - FIXME: unfinished support for MODEP55C +MODEP55C SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI + +# for PAUSE vs F3 NOP +P4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + +# for LZCNT/F3+BSR and TZCNT/F3+BSF +LZCNT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO +TZCNT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + +MODE_FIRST_PREFIX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI + +IMM0 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI # Indicator +IMM1 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI # Indicator ENTER instruction +IMM0SIGNED SCALAR xed_bits_t 1 EXPLICIT NOPRINT PUBLIC DO EO # Decode information only + +UIMM0 SCALAR xed_uint64_t 64 SUPPRESSED NOPRINT INTERNAL DO EI +UIMM1 SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # for ENTER's 2nd immediate, always 8b +IMM_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # in bits + + +# These two are decode outputs that tell us when there was an overridden segment +# selector that was not the default segment selector. + +USING_DEFAULT_SEGMENT0 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +USING_DEFAULT_SEGMENT1 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + + + +# MODRM/SIB field processing +DEFAULT_SEG SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL +SEG0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI + +# BASE0 & BASE1 must be PUBLIC because the string ops conditionally update them so users need the rw code + +BASE0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +INDEX SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI +SCALE SCALAR xed_bits_t 4 EXPLICIT PRINT INTERNAL DO EI #1/2/4/8 + +# SCALE is used by the user. SIBSCALE is internal + +SIB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL +SIBSCALE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL +SIBBASE SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL +SIBINDEX SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL + +# For the string ops: +SEG1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI +BASE1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI + +# Things that tell us to look at other fields +MEM0 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +MEM1 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +# MEM_WIDTH is not really a decoder-output; it is purely an encoder input. (see also ICLASS) +MEM_WIDTH SCALAR xed_uint16_t 16 SUPPRESSED NOPRINT PUBLIC DO EI # in bytes + +AGEN SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI + +# RELBR is used as a decode operand, but it is not required for encode +RELBR SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +# for CALL_FAR & JMP_FAR. Note UIM0 is also set by these +PTR SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI + +# NOTE: The arrays are experimental +# +#REGN ARRAY xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +# +REG0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG2 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG3 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG4 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG5 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG6 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG7 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG8 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI + +OUTREG SCALAR xed_reg_enum_t 16 SUPPRESSED NOPRINT INTERNAL DO EI # output for lookup-functions +ENCODER_PREFERRED SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI # encoder preference when underdetermined. +ERROR SCALAR xed_error_enum_t 8 SUPPRESSED NOPRINT INTERNAL DO EO # an error occurred + +# ICLASS is not really a decoder-output; it is purely an encoder input. (see also MEM_WIDTH) +ICLASS SCALAR xed_iclass_enum_t 16 SUPPRESSED NOPRINT PUBLIC DO EI # the instruction class + +NELEM SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +ELEMENT_SIZE SCALAR xed_bits_t 9 SUPPRESSED NOPRINT INTERNAL DO EO +TYPE SCALAR xed_operand_element_type_enum_t 4 SUPPRESSED NOPRINT INTERNAL DO EO + +#ILD-spesific operands +MAP SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +OUT_OF_BYTES SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +AMD3DNOW SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +FIRST_F2F3 SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +LAST_F2F3 SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_F2 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_F3 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +MAX_BYTES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_SEG SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NSEG_PREFIXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NREXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NPREFIXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NOMINAL_OPCODE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_NOMINAL_OPCODE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +HAS_MODRM SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +HAS_SIB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +POS_MODRM SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_SIB SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_DISP SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_IMM SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_IMM1 SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +IMM1_BYTES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +MODRM_BYTE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +ESRC SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +VEXVALID SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +DUMMY SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + diff --git a/datafiles/xed-flag-action-enum.txt b/datafiles/xed-flag-action-enum.txt new file mode 100644 index 0000000..3538f31 --- /dev/null +++ b/datafiles/xed-flag-action-enum.txt @@ -0,0 +1,35 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-flag-action-enum.h +cfn xed-flag-action-enum.c +prefix XED_FLAG_ACTION_ +typename xed_flag_action_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +u ///< undefined (treated as a write) +tst ///< test (read) +mod ///< modification (write) +0 ///< value will be zero (write) +pop ///< value comes from the stack (write) +ah ///< value comes from AH (write) +1 ///< value will be 1 (write) + + diff --git a/datafiles/xed-flag-enum.txt b/datafiles/xed-flag-enum.txt new file mode 100644 index 0000000..bf8b676 --- /dev/null +++ b/datafiles/xed-flag-enum.txt @@ -0,0 +1,49 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-flag-enum.h +cfn xed-flag-enum.c +prefix XED_FLAG_ +typename xed_flag_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +of ///<< overflow flag +sf ///< sign flag +zf ///< zero flag +af ///< auxilliary flag +pf ///< parity flag +cf ///< carry flag +df ///< direction flag +vif ///< virtual interrupt flag +iopl ///< I/O privilege level +if ///< interrupt flag +ac ///< alignment check +vm ///< virtual-8086 mode +rf ///< resume flag +nt ///< nested task +tf ///< traf flag +id ///< ID flag +vip ///< virtual interrupt pending +fc0 ///< x87 FC0 flag +fc1 ///< x87 FC1 flag +fc2 ///< x87 FC2 flag +fc3 ///< x87 FC3 flag + + diff --git a/datafiles/xed-gpr8-dec-reg-table.txt b/datafiles/xed-gpr8-dec-reg-table.txt new file mode 100644 index 0000000..8e963c9 --- /dev/null +++ b/datafiles/xed-gpr8-dec-reg-table.txt @@ -0,0 +1,98 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables.txt +######################################################################## + +xed_reg_enum_t GPR8_R():: + +REXR=0 REG=0x0 | OUTREG=XED_REG_AL +REXR=0 REG=0x1 | OUTREG=XED_REG_CL +REXR=0 REG=0x2 | OUTREG=XED_REG_DL +REXR=0 REG=0x3 | OUTREG=XED_REG_BL + +REXR=0 REG=0x4 REX=0 | OUTREG=XED_REG_AH +REXR=0 REG=0x5 REX=0 | OUTREG=XED_REG_CH +REXR=0 REG=0x6 REX=0 | OUTREG=XED_REG_DH +REXR=0 REG=0x7 REX=0 | OUTREG=XED_REG_BH + +REXR=0 REG=0x4 REX=1 | OUTREG=XED_REG_SPL +REXR=0 REG=0x5 REX=1 | OUTREG=XED_REG_BPL +REXR=0 REG=0x6 REX=1 | OUTREG=XED_REG_SIL +REXR=0 REG=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXR=1 REG=0x0 | OUTREG=XED_REG_R8B +REXR=1 REG=0x1 | OUTREG=XED_REG_R9B +REXR=1 REG=0x2 | OUTREG=XED_REG_R10B +REXR=1 REG=0x3 | OUTREG=XED_REG_R11B +REXR=1 REG=0x4 | OUTREG=XED_REG_R12B +REXR=1 REG=0x5 | OUTREG=XED_REG_R13B +REXR=1 REG=0x6 | OUTREG=XED_REG_R14B +REXR=1 REG=0x7 | OUTREG=XED_REG_R15B + +xed_reg_enum_t GPR8_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AL +REXB=0 RM=0x1 | OUTREG=XED_REG_CL +REXB=0 RM=0x2 | OUTREG=XED_REG_DL +REXB=0 RM=0x3 | OUTREG=XED_REG_BL + +REXB=0 RM=0x4 REX=0 | OUTREG=XED_REG_AH +REXB=0 RM=0x5 REX=0 | OUTREG=XED_REG_CH +REXB=0 RM=0x6 REX=0 | OUTREG=XED_REG_DH +REXB=0 RM=0x7 REX=0 | OUTREG=XED_REG_BH + +REXB=0 RM=0x4 REX=1 | OUTREG=XED_REG_SPL +REXB=0 RM=0x5 REX=1 | OUTREG=XED_REG_BPL +REXB=0 RM=0x6 REX=1 | OUTREG=XED_REG_SIL +REXB=0 RM=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXB=1 RM=0x0 | OUTREG=XED_REG_R8B +REXB=1 RM=0x1 | OUTREG=XED_REG_R9B +REXB=1 RM=0x2 | OUTREG=XED_REG_R10B +REXB=1 RM=0x3 | OUTREG=XED_REG_R11B +REXB=1 RM=0x4 | OUTREG=XED_REG_R12B +REXB=1 RM=0x5 | OUTREG=XED_REG_R13B +REXB=1 RM=0x6 | OUTREG=XED_REG_R14B +REXB=1 RM=0x7 | OUTREG=XED_REG_R15B + + +xed_reg_enum_t GPR8_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AL +REXB=0 SRM=0x1 | OUTREG=XED_REG_CL +REXB=0 SRM=0x2 | OUTREG=XED_REG_DL +REXB=0 SRM=0x3 | OUTREG=XED_REG_BL + +REXB=0 SRM=0x4 REX=0 | OUTREG=XED_REG_AH +REXB=0 SRM=0x5 REX=0 | OUTREG=XED_REG_CH +REXB=0 SRM=0x6 REX=0 | OUTREG=XED_REG_DH +REXB=0 SRM=0x7 REX=0 | OUTREG=XED_REG_BH + +REXB=0 SRM=0x4 REX=1 | OUTREG=XED_REG_SPL +REXB=0 SRM=0x5 REX=1 | OUTREG=XED_REG_BPL +REXB=0 SRM=0x6 REX=1 | OUTREG=XED_REG_SIL +REXB=0 SRM=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8B +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9B +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10B +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11B +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12B +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13B +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14B +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15B + diff --git a/datafiles/xed-gpr8-enc-reg-table.txt b/datafiles/xed-gpr8-enc-reg-table.txt new file mode 100644 index 0000000..427aa9e --- /dev/null +++ b/datafiles/xed-gpr8-enc-reg-table.txt @@ -0,0 +1,104 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +############################################################################ +#This is an experiment with an encoder table. It does not set fields +#that are initialized to zero (REXR, REXB). It sets NOREX, NEEDREX to +#indicated encoding constraints. +############################################################################ + + + +xed_reg_enum_t GPR8_R():: + +OUTREG=XED_REG_AL -> REG=0x0 +OUTREG=XED_REG_CL -> REG=0x1 +OUTREG=XED_REG_DL -> REG=0x2 +OUTREG=XED_REG_BL -> REG=0x3 + +OUTREG=XED_REG_AH -> REG=0x4 NOREX=1 +OUTREG=XED_REG_CH -> REG=0x5 NOREX=1 +OUTREG=XED_REG_DH -> REG=0x6 NOREX=1 +OUTREG=XED_REG_BH -> REG=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> REG=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> REG=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> REG=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> REG=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXR=1 REG=0x0 +OUTREG=XED_REG_R9B -> REXR=1 REG=0x1 +OUTREG=XED_REG_R10B -> REXR=1 REG=0x2 +OUTREG=XED_REG_R11B -> REXR=1 REG=0x3 +OUTREG=XED_REG_R12B -> REXR=1 REG=0x4 +OUTREG=XED_REG_R13B -> REXR=1 REG=0x5 +OUTREG=XED_REG_R14B -> REXR=1 REG=0x6 +OUTREG=XED_REG_R15B -> REXR=1 REG=0x7 + + +xed_reg_enum_t GPR8_B():: +OUTREG=XED_REG_AL -> RM=0x0 +OUTREG=XED_REG_CL -> RM=0x1 +OUTREG=XED_REG_DL -> RM=0x2 +OUTREG=XED_REG_BL -> RM=0x3 + +OUTREG=XED_REG_AH -> RM=0x4 NOREX=1 +OUTREG=XED_REG_CH -> RM=0x5 NOREX=1 +OUTREG=XED_REG_DH -> RM=0x6 NOREX=1 +OUTREG=XED_REG_BH -> RM=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> RM=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> RM=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> RM=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> RM=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXB=1 RM=0x0 +OUTREG=XED_REG_R9B -> REXB=1 RM=0x1 +OUTREG=XED_REG_R10B -> REXB=1 RM=0x2 +OUTREG=XED_REG_R11B -> REXB=1 RM=0x3 +OUTREG=XED_REG_R12B -> REXB=1 RM=0x4 +OUTREG=XED_REG_R13B -> REXB=1 RM=0x5 +OUTREG=XED_REG_R14B -> REXB=1 RM=0x6 +OUTREG=XED_REG_R15B -> REXB=1 RM=0x7 + + +xed_reg_enum_t GPR8_SB():: +OUTREG=XED_REG_AL -> SRM=0x0 +OUTREG=XED_REG_CL -> SRM=0x1 +OUTREG=XED_REG_DL -> SRM=0x2 +OUTREG=XED_REG_BL -> SRM=0x3 + +OUTREG=XED_REG_AH -> SRM=0x4 NOREX=1 +OUTREG=XED_REG_CH -> SRM=0x5 NOREX=1 +OUTREG=XED_REG_DH -> SRM=0x6 NOREX=1 +OUTREG=XED_REG_BH -> SRM=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> SRM=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> SRM=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> SRM=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> SRM=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXB=1 SRM=0x0 +OUTREG=XED_REG_R9B -> REXB=1 SRM=0x1 +OUTREG=XED_REG_R10B -> REXB=1 SRM=0x2 +OUTREG=XED_REG_R11B -> REXB=1 SRM=0x3 +OUTREG=XED_REG_R12B -> REXB=1 SRM=0x4 +OUTREG=XED_REG_R13B -> REXB=1 SRM=0x5 +OUTREG=XED_REG_R14B -> REXB=1 SRM=0x6 +OUTREG=XED_REG_R15B -> REXB=1 SRM=0x7 + diff --git a/datafiles/xed-ild-scanners.txt b/datafiles/xed-ild-scanners.txt new file mode 100755 index 0000000..09166aa --- /dev/null +++ b/datafiles/xed-ild-scanners.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +#Filename #priority, largest wins +%(xed_dir)s/datafiles/ild/include/xed-ild-scanners-base.h 0 + + diff --git a/datafiles/xed-immediates.txt b/datafiles/xed-immediates.txt new file mode 100644 index 0000000..f06f85a --- /dev/null +++ b/datafiles/xed-immediates.txt @@ -0,0 +1,96 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-immediates.txt +########################################################################### +# Immediates and displacements +# FIXME: when there are multiple immediates, need separate storage +# FIXME: record the width of the immediate + +# FIXME: for encode we'll sometimes have to choose between SIMMv and +# SIMMz to pick a MOV, for 16 and 32b widths. +########################################################################################## +## 2-BYTE STORAGE UNITS +########################################################################################## + +ONE():: +mode16 | IMM_WIDTH=8 UIMM0=1 +mode32 | IMM_WIDTH=8 UIMM0=1 +mode64 | IMM_WIDTH=8 UIMM0=1 + + +UIMMv():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 +EOSZ=3 UIMM0[i/64] | IMM_WIDTH=64 + +SIMMz():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 IMM0SIGNED=1 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 +EOSZ=3 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 + +SIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 IMM0SIGNED=1 + +UIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 + +# For ENTER. separate storage. +UIMM8_1():: + UIMM1[i/8] | true + +UIMM16():: + UIMM0[i/16] | IMM_WIDTH=16 + +UIMM32():: + UIMM0[i/32] | IMM_WIDTH=32 + +BRDISP8():: + DISP[d/8] |BRDISP_WIDTH=8 + +BRDISP32():: + DISP[d/32] | BRDISP_WIDTH=32 + +BRDISPz():: +EOSZ=1 DISP[d/16] | BRDISP_WIDTH=16 +EOSZ=2 DISP[d/32] | BRDISP_WIDTH=32 +EOSZ=3 DISP[d/32] | BRDISP_WIDTH=32 + + +MEMDISPv():: +EASZ=1 DISP[a/16] | DISP_WIDTH=16 +EASZ=2 DISP[a/32] | DISP_WIDTH=32 +EASZ=3 DISP[a/64] | DISP_WIDTH=64 + + +MEMDISP32():: +DISP[a/32] | DISP_WIDTH=32 + +MEMDISP16():: +DISP[a/16] | DISP_WIDTH=16 + +MEMDISP8():: +DISP[a/8] | DISP_WIDTH=8 + + +MEMDISP():: +NEED_MEMDISP=0 | DISP_WIDTH=0 +NEED_MEMDISP=8 DISP[a/8] | DISP_WIDTH=8 +NEED_MEMDISP=16 DISP[a/16] | DISP_WIDTH=16 +NEED_MEMDISP=32 DISP[a/32] | DISP_WIDTH=32 + diff --git a/datafiles/xed-isa.txt b/datafiles/xed-isa.txt new file mode 100644 index 0000000..3ef73f1 --- /dev/null +++ b/datafiles/xed-isa.txt @@ -0,0 +1,14723 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org) +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FCOM_ST0_X87_DCD0 +} + + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +COMMENT : UNDOC ALIASES +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DCD1 + +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DED0 +} + + +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC ALIASES +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD0 + +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD1 +} + +{ +ICLASS : FSTPNCE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +COMMENT : UNDOC ALIASES - empty top of stack behavior differs from FSTP. +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + + + +{ +ICLASS : FLDENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +COMMENT : UNDOC ALIAS +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DFC1 + +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DDC1 +} + + + +{ +ICLASS : FNOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP X87_CONTROL NOTSX +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000] +OPERANDS : +} +{ +ICLASS : FCHS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FABS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FTST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXAM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2T +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2E +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDPI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLG2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLN2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDZ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : F2XM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2X +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPTAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPATAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXTRACT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPREM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDECSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FINCSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FPREM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2XP1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSQRT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSINCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRNDINT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSCALE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSIN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNCLEX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010] +OPERANDS : REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNINIT +CPL : 3 +ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011] +OPERANDS : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSETPM287_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FENI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FDISI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001] +COMMENT : UNDOC +OPERANDS : +} + + +{ +ICLASS : FUCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +ATTRIBUTES : NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRSTOR +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FNSAVE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FFREE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADDP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FMULP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FSUBRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FSUBP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FDIVRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FDIVP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FFREEP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP +COMMENT : UNDOC +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FUCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_80r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_80r0 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : ADD_GPR8_IMMb_80r0 +} + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_80r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_80r1 +} + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_80r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_80r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_80r2 +} + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_80r2 +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_80r3 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_80r4 +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_80r5 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_80r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_80r7 + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_80r7 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADD_GPR8_IMMb_82r0 +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_82r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_82r2 +} + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_82r3 +} + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_82r4 +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_82r5 +} + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_82r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_82r7 + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_82r7 +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b:i8 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP + +PATTERN : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_8F +} + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +# 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPR8_ONE +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPRv_ONE +} + + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + + + + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROL_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPR8_ONE +} + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPRv_ONE +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08 +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + +################# + + + + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r4 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r6 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r4 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r6 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCL_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPR8_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPR8_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r4 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r4 + +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r6 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r6 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPR8_ONE +} + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SAR_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPR8_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPRv_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPRv_ONE +} + +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPRv_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r6 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r6 + +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r4 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r4 +} + + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SAR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPRv_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r4 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r6 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r4 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r6 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r0 + +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r1 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r0 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r1 +} + +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r1 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r1 +} +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : INC_GPRv_FFr0 +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : DEC_GPRv_FFr1 +} +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0xE8 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() +OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP +} +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() +OPERANDS : MEM0:r:v REG0=rIP():w:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() +OPERANDS : REG0=GPRv_B():r REG1=rIP():w:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +ATTRIBUTES : FAR_XFER NOTSX +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=rIP():w:SUPP +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP + +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_FFr6 +} +{ +ICLASS : SLDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP +} +{ +ICLASS : STR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_TR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP +} +{ +ICLASS : LLDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP +} +{ +ICLASS : LTR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_TR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : LGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP +} +{ +ICLASS : LMSW +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_CR0:w:SUPP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:r:v IMM0:r:b +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b +} +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +# NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66 +# on VMXON. It should be (and is) a VMXON. VMCLEAR is required to +# "not have" f2/f3; osz_refining_prefix handles this. + +{ +ICLASS : VMCLEAR +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRLD +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRST +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:q +} + + +{ +ICLASS : VMXON +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : CMPXCHG8B_LOCK +DISASM : cmpxchg8b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG8B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B_LOCK +DISASM : cmpxchg16b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP + +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():w IMM0:r:b +IFORM : MOV_GPR8_IMMb_C6r0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP HLE_REL_ABLE +PATTERN : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b IMM0:r:b +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():w IMM0:r:z +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:w:v IMM0:r:z +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSRLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSLLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : FXSAVE +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FXSAVE64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} + + + + + +{ +ICLASS : LDMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : STMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR_RD +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +{ +ICLASS : PREFETCHNTA +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT0 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT1 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT2 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r0 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r1 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r2 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r3 + + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r6 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r6 + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r7 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r7 +} +{ +ICLASS : NOP +UNAME : NOP0F19 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F19 + +PATTERN : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F19 +} +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F1A +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1A + +PATTERN : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A +} +{ +ICLASS : NOP +UNAME : NOP0F1B +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} +{ +ICLASS : NOP +UNAME : NOP0F1C +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C + +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} +{ +ICLASS : NOP +UNAME : NOP0F1D +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1D + +PATTERN : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1D +} +{ +ICLASS : NOP +UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + +{ +ICLASS : NOP +UNAME : NOP0F1F +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1F +PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1F +} +{ +ICLASS : VMCALL +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] +OPERANDS : +} +{ +ICLASS : VMLAUNCH +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] +OPERANDS : +} +{ +ICLASS : VMRESUME +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] +OPERANDS : +} +{ +ICLASS : VMXOFF +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] +OPERANDS : +} +{ +ICLASS : SGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP +} +{ +ICLASS : LIDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP +} +{ +ICLASS : MONITOR +CPL : 0 +CATEGORY : MISC +EXTENSION : SSE3 +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAIT +CPL : 0 +CATEGORY : MISC +EXTENSION : SSE3 +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : INVLPG +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b +} +{ +ICLASS : SWAPGS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : LONGMODE +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 +OPERANDS : +} +{ +ICLASS : RDTSCP +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : RDTSCP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP +} +{ +ICLASS : SFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : CLFLUSH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : CLFSH +ISA_SET : CLFSH +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : LFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MOVHLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : MOVLHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADD_GPR8_GPR8_00 +} + + + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADD_GPRv_GPRv_01 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADD_GPR8_GPR8_02 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADD_GPRv_GPRv_03 +} + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x04 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x05 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x06 not64 +OPERANDS : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x07 not64 +OPERANDS : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : OR_GPR8_GPR8_08 +} + + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : OR_GPRv_GPRv_09 +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : OR_GPR8_GPR8_0A +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : OR_GPRv_GPRv_0B +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0C UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0E not64 +OPERANDS : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADC_GPR8_GPR8_10 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADC_GPRv_GPRv_11 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADC_GPR8_GPR8_12 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADC_GPRv_GPRv_13 +} + + + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x14 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x15 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x16 not64 +OPERANDS : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x17 not64 +COMMENT : Inhibits all interrupts until after next instr +OPERANDS : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SBB_GPR8_GPR8_18 +} + + + + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SBB_GPRv_GPRv_19 +} + + +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SBB_GPR8_GPR8_1A + +PATTERN : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SBB_GPRv_GPRv_1B + +PATTERN : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x1E not64 +OPERANDS : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x1F not64 +OPERANDS : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : AND_GPR8_GPR8_20 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : AND_GPRv_GPRv_21 +} + + + +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : AND_GPR8_GPR8_22 + +PATTERN : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : AND_GPRv_GPRv_23 + +PATTERN : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x24 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x25 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x27 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SUB_GPR8_GPR8_28 +} + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SUB_GPRv_GPRv_29 +} + + + +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SUB_GPR8_GPR8_2A +PATTERN : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SUB_GPRv_GPRv_2B + +PATTERN : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x2F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : XOR_GPR8_GPR8_30 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : XOR_GPRv_GPRv_31 +} + + + +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : XOR_GPR8_GPR8_32 + +PATTERN : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : XOR_GPRv_GPRv_33 + +PATTERN : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x34 UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x35 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : AAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x37 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r + +PATTERN : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +IFORM : CMP_GPR8_GPR8_38 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : CMP_GPRv_GPRv_39 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():r MEM0:r:b +PATTERN : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():r REG1=GPR8_B():r +IFORM : CMP_GPR8_GPR8_3A +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:v +PATTERN : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():r REG1=GPRv_B():r +IFORM : CMP_GPRv_GPRv_3B +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3C SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3D SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} +{ +ICLASS : AAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x3F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_0 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : INC_GPRv_40 +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_1 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : DEC_GPRv_48 +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_0 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_50 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_1 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_51 +} +{ +ICLASS : PUSHA +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x60 EOSZ=1 not64 +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP +} +{ +ICLASS : PUSHAD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x60 EOSZ=2 not64 +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP +} +{ +ICLASS : POPA +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x61 EOSZ=1 not64 +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : POPAD +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x61 EOSZ=2 not64 +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : BOUND +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ATTRIBUTES: EXCEPTION_BR +ISA_SET : I186 +PATTERN : 0x62 mode16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a16 +PATTERN : 0x62 mode32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a32 +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:rw:w REG0=GPR16_R():r +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR16_B():rw REG1=GPR16_R():r +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:d +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +OPERANDS : REG0=GPRv_R():w REG1=GPR32_B():r +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x68 DF64() SIMMz() +OPERANDS : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:z + +PATTERN : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x6A DF64() SIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8 +} + + +{ +ICLASS : REP_INSB +DISASM : insb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6C repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D EOSZ=1 repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D EOSZ=1 repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D EOSZ=1 norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSD +DISASM : insd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D EOSZ=2 repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D EOSZ=3 repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D EOSZ=2 repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D EOSZ=3 repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D EOSZ=2 norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP + +PATTERN : 0x6D EOSZ=3 norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_OUTSB +DISASM : outsb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6E repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6E repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6E norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSW +DISASM : outsw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F EOSZ=1 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F EOSZ=1 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSW +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F EOSZ=1 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSD +DISASM : outsd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F EOSZ=2 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F EOSZ=3 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F EOSZ=2 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F EOSZ=3 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : OUTSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F EOSZ=2 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP + +PATTERN : 0x6F EOSZ=3 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w REG1=GPR8_R():r +IFORM : MOV_GPR8_GPR8_88 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b REG0=GPR8_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=GPRv_R():r +IFORM : MOV_GPRv_GPRv_89 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():w MEM0:r:b + +PATTERN : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():w REG1=GPR8_B():r +IFORM : MOV_GPR8_GPR8_8A +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +IFORM : MOV_GPRv_GPRv_8B +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=SEG():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=SEG():r +} +{ +ICLASS : LEA +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT() +OPERANDS : REG0=GPRv_R():w AGEN:r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr +PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=SEG():w MEM0:r:w +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=SEG():w REG1=GPR16_B():r +} + + + +{ +ICLASS : NOP +UNAME : NOP90 +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix +OPERANDS : +IFORM : NOP_90 +} +{ +ICLASS : PAUSE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : PAUSE +ISA_SET : PAUSE +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 +OPERANDS : +COMMENT : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4 +} +{ +ICLASS : NOP +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 +OPERANDS : +IFORM : NOP_90 +COMMENT : This is the encoding of PAUSE on pre-P4 systems + +} + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0b1001_0 SRM[rrr] SRM!=0 +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL + +PATTERN : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL +} +{ +ICLASS : CBW +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x98 EOSZ=1 +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +} +{ +ICLASS : CDQE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x98 EOSZ=3 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} +{ +ICLASS : CWDE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x98 EOSZ=2 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CWD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x99 EOSZ=1 +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CQO +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x99 EOSZ=3 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP +} +{ +ICLASS : CDQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x99 EOSZ=2 +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +PATTERN : 0x9A not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : FWAIT +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +PATTERN : 0x9B +OPERANDS : +} +{ +ICLASS : PUSHF +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9C DF64() EOSZ=1 +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +} +{ +ICLASS : PUSHFD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9C DF64() EOSZ=2 not64 +OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP +} +{ +ICLASS : PUSHFQ +CPL : 3 +CATEGORY : PUSH +EXTENSION : LONGMODE +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9C DF64() EOSZ=3 mode64 +OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP +} +{ +ICLASS : POPF +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0x9D DF64() EOSZ=1 +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +} +{ +ICLASS : POPFD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0x9D DF64() EOSZ=2 not64 +OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP +} +{ +ICLASS : POPFQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0x9D DF64() EOSZ=3 mode64 +OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP +} +{ +ICLASS : SAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ] +PATTERN : 0x9E +OPERANDS : REG0=XED_REG_AH:r:SUPP +} +{ +ICLASS : LAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9F +OPERANDS : REG0=XED_REG_AH:w:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA0 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA1 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA2 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA3 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:v REG0=OrAX():r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} + + +{ +ICLASS : REP_MOVSB +DISASM : movsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA4 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSW +DISASM : movsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=1 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 EOSZ=1 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=1 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSD +DISASM : movsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=2 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 EOSZ=2 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=2 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_MOVSQ +DISASM : movsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=3 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 EOSZ=3 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : MOVSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 EOSZ=3 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA6 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=1 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=1 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xA7 EOSZ=1 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + + +{ +ICLASS : REPE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=2 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=2 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + + +{ +ICLASS : CMPSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA7 EOSZ=2 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=3 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 EOSZ=3 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : CMPSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xA7 EOSZ=3 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA8 SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA9 SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} + +{ +ICLASS : REP_STOSB +DISASM : stosb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAA repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP +} + + + +{ +ICLASS : REP_STOSW +DISASM : stosw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=1 repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB EOSZ=1 repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=1 norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSD +DISASM : stosd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=2 repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB EOSZ=2 repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=2 norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSQ +DISASM : stosq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=3 repe +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB EOSZ=3 repne +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB EOSZ=3 norep +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP +} + + + + +{ +ICLASS : REP_LODSB +DISASM : lodsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAC repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSW +DISASM : lodsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=1 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD EOSZ=1 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=1 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSD +DISASM : lodsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=2 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD EOSZ=2 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=2 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REP_LODSQ +DISASM : lodsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=3 repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD EOSZ=3 repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD EOSZ=3 norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REPE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repe +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repne +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : SCASB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAE norep +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=1 repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=1 repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF EOSZ=1 norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=2 repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=2 repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF EOSZ=2 norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=3 repe +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF EOSZ=3 repne +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF EOSZ=3 norep +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_0 SRM[rrr] UIMM8() +OPERANDS : REG0=GPR8_SB():w IMM0:r:b +# i had to come up with a partial nibble name +IFORM : MOV_GPR8_IMMb_D0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_1 SRM[rrr] UIMMv() +OPERANDS : REG0=GPRv_SB():w IMM0:r:v +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC3 DF64() IMMUNE66_LOOP64() +OPERANDS : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : LES +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP +} +{ +ICLASS : LDS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP +} +{ +ICLASS : ENTER +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +PATTERN : 0xC8 DF64() UIMM16() UIMM8_1() +OPERANDS : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP +} +{ +ICLASS : LEAVE +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 +PATTERN : 0xC9 DF64() +# Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of +# the initial copy of rBP to rSP as part of the LEAVE's execution. +OPERANDS : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +COMMENT : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented) +PATTERN : 0xCA UIMM16() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xCB +OPERANDS : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : INT3 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCC +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : INT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCD UIMM8() +OPERANDS : IMM0:r:b REG0=rIP():w:SUPP +} +{ +ICLASS : INTO +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ] +PATTERN : 0xCE not64 +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : IRET +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF EOSZ=1 +OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF EOSZ=2 +OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF EOSZ=3 mode64 +# FIXME: This is only an approximate width for the stack pops +OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : AAM +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD4 not64 SIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP +} +{ +ICLASS : AAD +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD5 not64 SIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : SALC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst ] +PATTERN : 0xD6 not64 +OPERANDS : REG0=XED_REG_AL:w:SUPP +COMMENT : UNDOC - "The Undocumented PC", 2nd ed 1997, says it is present on all Intel CPUs of that time. +} +{ +ICLASS : XLAT +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xD7 OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP INDEX=XED_REG_AL:r:SUPP REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP +} + + +{ +ICLASS : LOOPNE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +# REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC +PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} +{ +ICLASS : LOOPE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +# REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC +PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + + + +{ +ICLASS : LOOP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + +{ +ICLASS : JCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode16 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=rIP():rw:SUPP +} +{ +ICLASS : JECXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode32 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=rIP():rw:SUPP +} +{ +ICLASS : JRCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : LONGMODE +PATTERN : 0xE3 eamode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=rIP():rw:SUPP +} + +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE4 UIMM8() IMMUNE_REXW() +OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE5 UIMM8() IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL IMM0:r:b +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE6 UIMM8() IMMUNE_REXW() +OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE7 UIMM8() IMMUNE_REXW() +OPERANDS : IMM0:r:b REG0=OeAX():r:IMPL +} + +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xE9 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +PATTERN : 0xE9 mode64 FORCE64() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +CATEGORY : UNCOND_BR +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEA not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=rIP():w:SUPP +} +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEB DF64() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEC IMMUNE_REXW() +OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xED IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEE IMMUNE_REXW() +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEF IMMUNE_REXW() +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL +} +{ +ICLASS : INT1 +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF1 +OPERANDS : +COMMENT : UNDOC by Intel, but in AMD's opcode map +} +{ +ICLASS : HLT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ATTRIBUTES : RING0 NOTSX +ISA_SET : I86 +PATTERN : 0xF4 +OPERANDS : +} +{ +ICLASS : CMC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst cf-mod ] +PATTERN : 0xF5 +OPERANDS : +} +{ +ICLASS : CLC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-0 ] +PATTERN : 0xF8 +OPERANDS : +} +{ +ICLASS : STC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-1 ] +PATTERN : 0xF9 +OPERANDS : +} +{ +ICLASS : CLI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFA +OPERANDS : +} +{ +ICLASS : STI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +COMMENT : Inhibits all interrupts until after next instr +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFB +OPERANDS : +} +{ +ICLASS : CLD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-0 ] +PATTERN : 0xFC +OPERANDS : +} +{ +ICLASS : STD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-1 ] +PATTERN : 0xFD +OPERANDS : +} +{ +ICLASS : LAR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +COMMENT : LAR only sometimes writes its destination register. +PATTERN : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:w +PATTERN : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : LSL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:w + +PATTERN : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRz_B():r +} +{ +ICLASS : SYSCALL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 mode64 FORCE64() +OPERANDS : REG0=rIP():w:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : CLTS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x06 +OPERANDS : +} +{ +ICLASS : SYSRET +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 mode64 eosz64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP +PATTERN : 0x0F 0x07 mode64 eosz32 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : MOVUPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F10 + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F11 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 +} +{ +ICLASS : UNPCKLPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 +} +{ +ICLASS : MOVSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:ss + +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +IFORM : MOVSS_XMMss_XMMss_0F10 + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:ss REG0=XMM_R():r:ss + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:ss REG1=XMM_R():r:ss +IFORM : MOVSS_XMMss_XMMss_0F11 +} +{ +ICLASS : MOVSLDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVSHDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVUPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F10 + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F11 +} +{ +ICLASS : MOVLPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : UNPCKLPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : MOVHPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : MOVSD_XMM +DISASM : movsd +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:sd + +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F10 + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:sd REG0=XMM_R():r:sd + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:sd REG1=XMM_R():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F11 +} +{ +ICLASS : MOVDDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=CR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=CR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=GPR32_B():w REG1=CR_R():r + +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=GPR64_B():w REG1=CR_R():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() not64 +OPERANDS : REG0=DR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 +OPERANDS : REG0=DR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() not64 +OPERANDS : REG0=GPR32_B():w REG1=DR_R():r + +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 +OPERANDS : REG0=GPR64_B():w REG1=DR_R():r +} + + +{ +ICLASS : WRMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x30 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP +} +{ +ICLASS : RDTSC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +PATTERN : 0x0F 0x31 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP +} +{ +ICLASS : RDMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x32 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : RDPMC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : RDPMC +PATTERN : 0x0F 0x33 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : SYSENTER +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ vm-0 rf-0 if-0 ] +PATTERN : 0x0F 0x34 +OPERANDS : REG0=rIP():w:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : SYSEXIT +CPL : 0 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x35 +OPERANDS : REG0=rIP():w:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : CMOVO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVMSKPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:ps +} +{ +ICLASS : SQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RSQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RCPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ANDPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ANDNPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : XORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : SQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RSQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RCPSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MOVMSKPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:pd +} +{ +ICLASS : SQRTPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ANDPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ANDNPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : XORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : SQRTSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKLBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8 + +PATTERN : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8 +} +{ +ICLASS : PUNPCKLWD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16 +PATTERN : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16 +} +{ +ICLASS : PUNPCKLDQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32 +PATTERN : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32 +} +{ +ICLASS : PACKSSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +} +{ +ICLASS : PCMPGTB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPGTW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PCMPGTW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PCMPGTD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : PACKUSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PUNPCKLBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPGTW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSHUFW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b +PATTERN : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : PCMPEQB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPEQW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPEQD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +PATTERN : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : EMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : x87_mmx_state_w NOTSX +PATTERN : 0x0F 0x77 no_refining_prefix +OPERANDS : +} +{ +ICLASS : PSHUFD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b +} +{ +ICLASS : PCMPEQB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPEQW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPEQD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PSHUFLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : PSHUFHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP + +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP + +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + + +{ +ICLASS : SETO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA0 DF64() +OPERANDS : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA1 DF64() +OPERANDS : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : CPUID +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0xA2 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP +} + + + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP +} + + + +{ +ICLASS : LSS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + +{ +ICLASS : LFS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP +} +{ +ICLASS : LGS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP +} +{ +ICLASS : MOVZX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +PATTERN : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +PATTERN : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +PATTERN : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + + +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : CMPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : MOVNTI +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : IGNORES_OSFXSR NOTSX +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ!=3 MODRM() +OPERANDS : MEM0:w:d REG0=GPR32_R():r +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ=3 MODRM() +OPERANDS : MEM0:w:q REG0=GPR64_R():r +} +{ +ICLASS : PINSRW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : SHUFPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : CMPSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b +} +{ +ICLASS : CMPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : PINSRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : SHUFPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : CMPSD_XMM +DISASM : cmpsd +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PADDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : PMULLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMOVMSKB +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : SSE +COMMENT : KNI on PentiumIII. MMX instructions intro'd w/SSE +PATTERN : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:i8 +} +{ +ICLASS : ADDSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PADDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMOVMSKB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : MOVQ2DQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : ADDSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVDQ2Q +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64 +} +{ +ICLASS : PAVGB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q +} +{ +ICLASS : PAVGW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PAVGW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMULHUW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16 +} +{ +ICLASS : PMULHUW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16 +} +{ +ICLASS : PMULHW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PMULHW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : MOVNTQ +EXCEPTIONS: mmx-nofp2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +} +{ +ICLASS : PAVGB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +} + + +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PAVGW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : CVTTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : MOVNTDQ +ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq +} +{ +ICLASS : CVTDQ2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32 +} +{ +ICLASS : CVTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PMULUDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32 +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32 +} +{ +ICLASS : PMADDWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PSADBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : MASKMOVQ +EXCEPTIONS: mmx-nofp2 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : fixed_base0 maskop NOTSX +PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() +OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64 +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : PMULUDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : MASKMOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : fixed_base0 maskop NOTSX +PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} +{ +ICLASS : LDDQU +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : +PATTERN : 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix +OPERANDS : REG0=XMM_R():w:pd MEM0:r:dq +} +{ +ICLASS : INVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x08 +OPERANDS : +} +{ +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 +OPERANDS : +} +{ +ICLASS : UD2 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x0B +OPERANDS : +} +{ +ICLASS : MOVAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F28 + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F29 +} + +{ +ICLASS : CVTPI2PS +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPS +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:ps +} +{ +ICLASS : CVTTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 +PATTERN : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:f32 REG1=XMM_B():r:q:i32 +} +{ +ICLASS : UCOMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : COMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSI2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():w:ss:f32 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():w:ss:f32 REG1=GPR64_B():r:q:i32 +} +{ +ICLASS : CVTTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : MOVAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F28 + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F29 +} +{ +ICLASS : CVTPI2PD +EXCEPTIONS: mmx-nofp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPD +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:pd +} +{ +ICLASS : CVTTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : UCOMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : COMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSI2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():w:sd:f64 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:q:i64 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():w:sd:f64 REG1=GPR64_B():r:q:i64 +} +{ +ICLASS : CVTTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CVTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : PPRO +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : ADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MULPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : CVTPS2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +ATTRIBUTES: MXCSR +PATTERN : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32 +PATTERN : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTDQ2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : SUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MINPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : DIVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MAXPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ADDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MULSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSS2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd:f64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MINSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : DIVSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MAXSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : ADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MULPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : CVTPD2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MINPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : DIVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MAXPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MXCSR +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ADDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MULSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSD2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss:f32 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : SUBSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MINSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : DIVSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MAXSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKHBW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHDQ +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PACKSSDW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d +} + + +{ +ICLASS : MOVQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F6E + +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0F7E + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=XMM_R():r:q + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0FD6 + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : MOVQ_XMMdq_XMMq_0FD6 + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F7E + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : MOVQ_XMMdq_XMMq_0F7E +} + + +{ +ICLASS : MOVQ +EXCEPTIONS: mmx-nofp2 # FIXME guessing here... +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6E + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7E + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=MMX_R():r:q + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6F + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +IFORM : MOVQ_MMXq_MMXq_0F6F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_B():w:q REG1=MMX_R():r:q +IFORM : MOVQ_MMXq_MMXq_0F7F +} + +{ +ICLASS : PUNPCKHBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PUNPCKLQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : MOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F6F + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F7F +} +{ +ICLASS : VMREAD +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : MEM0:rw:q REG0=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_B():rw REG1=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : MEM0:rw:d REG0=GPR32_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_B():rw REG1=GPR32_R():r +} +{ +ICLASS : VMWRITE +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:q + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_R():r REG1=GPR64_B():r + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:d + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : HADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : HSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MOVDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F7F + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F6F +} +{ +ICLASS : HADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : HSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + + +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP +} + + +{ +ICLASS : SETS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA8 DF64() +OPERANDS : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA9 DF64() +OPERANDS : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : RSM +CPL : 3 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : I486 +ATTRIBUTES: NOTSX +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xAA +OPERANDS : REG0=rIP():w:SUPP +} + +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + + +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v + +PATTERN : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +} + +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + +{ +ICLASS : BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : BSWAP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0b1100_1 SRM[rrr] +OPERANDS : REG0=GPRv_SB():rw +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMINUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAND +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMAXUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PANDN +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PANDN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : POR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PXOR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : POR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDUBSW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PMADDUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PMULHRSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSHUFB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSHUFB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +EXCEPTIONS: mmx-mem +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGND +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PALIGNR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b +} +{ +ICLASS : PALIGNR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : PABSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSD +EXCEPTIONS: mmx-mem +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + +#################################################################################### +{ +ICLASS : POPCNT +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : POPCNT +ATTRIBUTES: IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. +FLAGS : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} +#################################################################################### +{ +ICLASS : PCMPGTQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : CRC32 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +ATTRIBUTES : IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. + +COMMENT: The dest min size is 32b, even for EOSZ 16b. + +# The byte-readers + +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:b +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPR8_B():r:b + + +# The scalable readers + +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPRv_B():r:v + +} + + + +{ +ICLASS : BLENDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : BLENDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#######################################################################33 +{ +ICLASS : BLENDVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64 + +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64 +} + +{ +ICLASS : BLENDVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32 + +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32 +} +#################################################################################### +{ +ICLASS : PCMPEQQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq + +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : DPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : DPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#################################################################################### +{ +ICLASS : MOVNTDQA +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX +PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : EXTRACTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:ps IMM0:r:b + +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +#################################################################################### +{ +ICLASS : INSERTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : MPSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : PACKUSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 + +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +############################################################################ +{ +ICLASS : PBLENDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PBLENDVB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP + +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP +} +############################################################################ +{ +ICLASS : PEXTRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRW_SSE4 +DISASM_INTEL: pextrw +DISASM_ATTSV: pextrw +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +# this one aliases with the SSE2 version so we made a new name + +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_MEMw_XMMdq_IMMb + +# this one aliases with the SSE2 version so we made a new name +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_GPR32_XMMdq_IMMb +} + +############################################################################ +{ +ICLASS : PEXTRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:b IMM0:r:b + +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:q IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +FLAGS : MUST [ cf-mod zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq +} +############################################################################ +{ +ICLASS : PHMINPOSUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + + +{ +ICLASS : PMAXSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMINSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMULLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PMOVSXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +} +{ +ICLASS : PMOVSXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +} +{ +ICLASS : PMOVSXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +} + +{ +ICLASS : PMOVSXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +} +{ +ICLASS : PMOVSXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +} +{ +ICLASS : PMOVSXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +} + +{ +ICLASS : PMOVZXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +} +{ +ICLASS : PMOVZXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +} +{ +ICLASS : PMOVZXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +} + +{ +ICLASS : PMOVZXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +} +{ +ICLASS : PMOVZXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +} +{ +ICLASS : PMOVZXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +} + + + + + + + +{ +ICLASS : PCMPESTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : PCMPISTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : PCMPESTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +} +{ +ICLASS : PCMPISTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### +{ +ICLASS : XGETBV +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XSETBV +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVE +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP +} + + +{ +ICLASS : XSAVE +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length store +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} +{ +ICLASS : XRSTOR +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVE64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length store +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XRSTOR64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +#################################################################################### + +{ +ICLASS : MOVBE +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MOVBE +COMMENT : Intro on Atom Silverthorne. Intercepted by Haswell. +# +# must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes. +# +PATTERN : 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} + + +{ +ICLASS : GETSEC +CPL : 3 +CATEGORY : SYSTEM +ATTRIBUTES: PROTECTED_MODE NOTSX +EXTENSION : SMX +PATTERN : 0x0F 0x37 +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP +} + + +#################################################################################### +{ +ICLASS : AESKEYGENASSIST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : AESENC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESENCLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDEC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDECLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESIMC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : PCLMULQDQ +CPL : 3 +CATEGORY : PCLMULQDQ +EXTENSION : PCLMULQDQ +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +} + + +####################################################################### +{ +ICLASS : INVEPT +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} +{ +ICLASS : INVVPID +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} + + + + diff --git a/datafiles/xed-machine-modes-enum.txt b/datafiles/xed-machine-modes-enum.txt new file mode 100644 index 0000000..1f4af55 --- /dev/null +++ b/datafiles/xed-machine-modes-enum.txt @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-machine-mode-enum.h +cfn xed-machine-mode-enum.c +prefix XED_MACHINE_MODE_ +typename xed_machine_mode_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +LONG_64 ///< 64b operating mode +LONG_COMPAT_32 ///< 32b protected mode +LONG_COMPAT_16 ///< 16b protected mode +LEGACY_32 ///< 32b protected mode +LEGACY_16 ///< 16b protected mode +REAL_16 ///< 16b real mode + diff --git a/datafiles/xed-modrm-encode.txt b/datafiles/xed-modrm-encode.txt new file mode 100644 index 0000000..e71ec5f --- /dev/null +++ b/datafiles/xed-modrm-encode.txt @@ -0,0 +1,460 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# Decoder ring +# @ = null = invalid register +# * = any valid register or value for this field +# nothing = encode nothing in this case +# error = cannot encode + +SEQUENCE MODRM_BIND + SIB_REQUIRED_ENCODE_BIND() + SIBSCALE_ENCODE_BIND() + SIBINDEX_ENCODE_BIND() + SIBBASE_ENCODE_BIND() + MODRM_RM_ENCODE_BIND() + MODRM_MOD_ENCODE_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + SIB_NT_BIND() # FIXME 2007-06-30 + DISP_NT_BIND() + +SEQUENCE MODRM_EMIT + #MODRM_NT_EMIT() # FIXME: 2007-06-30 the instruction will emit this as part of the INSTRUCTIONS NT + SIB_NT_EMIT() + DISP_NT_EMIT() + +SEGMENT_DEFAULT_ENCODE():: +BASE0=XED_REG_RIP -> nothing # no segment for RIP +BASE0=ArSP() -> default_ss # default to SS +BASE0=ArBP() -> default_ss # default to SS +BASE0=@ -> default_ds # default to DS -- baseless +# +BASE0=ArAX() -> default_ds # everything else defaults to DS +BASE0=ArCX() -> default_ds +BASE0=ArDX() -> default_ds +BASE0=ArBX() -> default_ds +BASE0=ArSI() -> default_ds +BASE0=ArDI() -> default_ds +BASE0=Ar8() -> default_ds +BASE0=Ar9() -> default_ds +BASE0=Ar10() -> default_ds +BASE0=Ar11() -> default_ds +BASE0=Ar12() -> default_ds +BASE0=Ar13() -> default_ds +BASE0=Ar14() -> default_ds +BASE0=Ar15() -> default_ds + +SEGMENT_ENCODE():: +default_ss SEG0=@ -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # assume this is what the user wanted +default_ss SEG0=XED_REG_CS -> cs_prefix +default_ss SEG0=XED_REG_DS -> ds_prefix +default_ss SEG0=XED_REG_SS -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # matches default +default_ss SEG0=XED_REG_ES -> es_prefix +default_ss SEG0=XED_REG_FS -> fs_prefix +default_ss SEG0=XED_REG_GS -> gs_prefix +# +default_ds SEG0=@ -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # assume this is what the user wanted +default_ds SEG0=XED_REG_CS -> cs_prefix +default_ds SEG0=XED_REG_DS -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # matches default +default_ds SEG0=XED_REG_SS -> ss_prefix +default_ds SEG0=XED_REG_ES -> es_prefix +default_ds SEG0=XED_REG_FS -> fs_prefix +default_ds SEG0=XED_REG_GS -> gs_prefix +otherwise -> no_seg_prefix # was "nothing" 2007-0x08-0x14 + + +SIB_REQUIRED_ENCODE():: +eamode32 INDEX=GPR32e() -> SIB=1 +eamode64 INDEX=GPR64e() -> SIB=1 +# base-less memop in 64b mode requires a SIB + +eamode64 BASE0=@ DISP_WIDTH=32 -> SIB=1 +eamode32 mode64 BASE0=@ DISP_WIDTH=32 -> SIB=1 +eamode32 mode16 -> nothing +eamode32 mode32 -> nothing + +# Denote the need of a SIB byte if base is rSP or r12 +eanot16 BASE0=ArSP() -> SIB=1 +eanot16 BASE0=Ar12() -> SIB=1 + +# When the displacement is omitted, we supply one for these r13 and rBP. +#eanot16 BASE0=ArBP() DISP_WIDTH=0 -> SIB=1 +#eanot16 BASE0=Ar13() DISP_WIDTH=0 -> SIB=1 + +otherwise -> nothing # FIXME: could set SIB=0 + +SIBBASE_ENCODE():: +SIB=0 -> nothing +SIB=1 -> SIBBASE_ENCODE_SIB1() + +SIBBASE_ENCODE_SIB1():: +BASE0=ArAX() -> SIBBASE=0 REXB=0 +BASE0=Ar8() -> SIBBASE=0 REXB=1 +BASE0=ArCX() -> SIBBASE=1 REXB=0 +BASE0=Ar9() -> SIBBASE=1 REXB=1 +BASE0=ArDX() -> SIBBASE=2 REXB=0 +BASE0=Ar10() -> SIBBASE=2 REXB=1 +BASE0=ArBX() -> SIBBASE=3 REXB=0 +BASE0=Ar11() -> SIBBASE=3 REXB=1 +BASE0=ArSP() -> SIBBASE=4 REXB=0 +BASE0=Ar12() -> SIBBASE=4 REXB=1 + +# The mod values are really gotten by the MOD rule, only requiring one +# addition. +## BAD MODIFIES DISP! SIB=1 BASE0=@ DISP_WIDTH=8 -> SIBBASE=5 REXB=0 DISP_WIDTH=32 # MOD=0 +BASE0=@ -> DISP_WIDTH_32() SIBBASE=5 REXB=0 # MOD=0 +# The MOD rule handles the DISP arg modification for rBP and r13 +BASE0=ArBP() -> DISP_WIDTH_0_8_32() SIBBASE=5 REXB=0 # MOD=1 # ARG MODIFICATION LATER IN MOD RULE + +# SIB=1 BASE0=@ DISP_WIDTH=32 -> SIBBASE=5 REXB=0 # MOD=0 redundant with the above +# The MOD rule handles the DISP arg modification for rBP and r13 +BASE0=Ar13() -> DISP_WIDTH_0_8_32() SIBBASE=5 REXB=1 # MOD=1 # ARG MODIFICATION LATER IN MOD RULE + +BASE0=ArSI() -> SIBBASE=6 REXB=0 +BASE0=Ar14() -> SIBBASE=6 REXB=1 +BASE0=ArDI() -> SIBBASE=7 REXB=0 +BASE0=Ar15() -> SIBBASE=7 REXB=1 +otherwise -> error # BASE0 was some other register + +SIBINDEX_ENCODE():: +SIB=0 -> nothing +SIB=1 -> SIBINDEX_ENCODE_SIB1() + +SIBINDEX_ENCODE_SIB1():: +INDEX=ArAX() -> SIBINDEX=0 REXX=0 +INDEX=Ar8() -> SIBINDEX=0 REXX=1 +INDEX=ArCX() -> SIBINDEX=1 REXX=0 +INDEX=Ar9() -> SIBINDEX=1 REXX=1 +INDEX=ArDX() -> SIBINDEX=2 REXX=0 +INDEX=Ar10() -> SIBINDEX=2 REXX=1 +INDEX=ArBX() -> SIBINDEX=3 REXX=0 +INDEX=Ar11() -> SIBINDEX=3 REXX=1 +INDEX=@ -> SIBINDEX=4 REXX=0 # the "no index" option +INDEX=Ar12() -> SIBINDEX=4 REXX=1 +INDEX=ArBP() -> SIBINDEX=5 REXX=0 +INDEX=Ar13() -> SIBINDEX=5 REXX=1 +INDEX=ArSI() -> SIBINDEX=6 REXX=0 +INDEX=Ar14() -> SIBINDEX=6 REXX=1 +INDEX=ArDI() -> SIBINDEX=7 REXX=0 +INDEX=Ar15() -> SIBINDEX=7 REXX=1 +otherwise -> error # INDEX was some other register + + +SIBSCALE_ENCODE():: +SIB=0 -> nothing +SIB=1 SCALE=0 -> SIBSCALE=0 # this allows for default unset scales +SIB=1 SCALE=1 -> SIBSCALE=0 +SIB=1 SCALE=2 -> SIBSCALE=1 +SIB=1 SCALE=4 -> SIBSCALE=2 +SIB=1 SCALE=8 -> SIBSCALE=3 +otherwise -> error # SCALE was some other value + +############################################################################## +MODRM_MOD_ENCODE():: +eamode16 DISP_WIDTH=0 -> MODRM_MOD_EA16_DISP0() +eamode16 DISP_WIDTH=8 -> MODRM_MOD_EA16_DISP8() +eamode16 DISP_WIDTH=16 -> MODRM_MOD_EA16_DISP16() +eamode16 DISP_WIDTH=32 -> ERROR() +eamode16 DISP_WIDTH=64 -> ERROR() + +eamode32 DISP_WIDTH=0 -> MODRM_MOD_EA32_DISP0() +eamode32 DISP_WIDTH=8 -> MODRM_MOD_EA32_DISP8() +eamode32 DISP_WIDTH=16 -> ERROR() +eamode32 DISP_WIDTH=32 -> MODRM_MOD_EA32_DISP32() +eamode32 DISP_WIDTH=64 -> ERROR() + +eamode64 DISP_WIDTH=0 -> MODRM_MOD_EA64_DISP0() +eamode64 DISP_WIDTH=8 -> MODRM_MOD_EA64_DISP8() +eamode64 DISP_WIDTH=16 -> ERROR() +eamode64 DISP_WIDTH=32 -> MODRM_MOD_EA64_DISP32() +eamode64 DISP_WIDTH=64 -> ERROR() +############################################################################## +#### EAMODE16 +############################################################################## +MODRM_MOD_EA16_DISP0():: +BASE0=XED_REG_BX INDEX=@ -> MOD=0 +BASE0=XED_REG_SI INDEX=@ -> MOD=0 +BASE0=XED_REG_DI INDEX=@ -> MOD=0 +BASE0=XED_REG_BP INDEX=@ -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=0 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=0 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=0 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=0 + +MODRM_MOD_EA16_DISP8():: +BASE0=XED_REG_BX INDEX=@ -> MOD=1 +BASE0=XED_REG_SI INDEX=@ -> MOD=1 +BASE0=XED_REG_DI INDEX=@ -> MOD=1 +BASE0=XED_REG_BP INDEX=@ -> MOD=1 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=1 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=1 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=1 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=1 + +MODRM_MOD_EA16_DISP16():: +BASE0=@ INDEX=@ -> MOD=0 +BASE0=XED_REG_BX INDEX=@ -> MOD=2 +BASE0=XED_REG_SI INDEX=@ -> MOD=2 +BASE0=XED_REG_DI INDEX=@ -> MOD=2 +BASE0=XED_REG_BP INDEX=@ -> MOD=2 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=2 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=2 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=2 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=2 + + +############################################################################## +#### EAMODE32 +############################################################################## +MODRM_MOD_EA32_DISP0():: +# Add a fake 1B displacement to rBP and r13 if they do not have one already. +BASE0=XED_REG_EBP mode32 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_EBP mode64 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_R13D mode64 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +# All these 32b and 64b base regs can handle no displacement +BASE0=XED_REG_EAX mode32 -> MOD=0 +BASE0=XED_REG_EBX mode32 -> MOD=0 +BASE0=XED_REG_ECX mode32 -> MOD=0 +BASE0=XED_REG_EDX mode32 -> MOD=0 +BASE0=XED_REG_ESI mode32 -> MOD=0 +BASE0=XED_REG_EDI mode32 -> MOD=0 +BASE0=XED_REG_ESP mode32 -> MOD=0 # our choice to use MOD=0 (w/sib) + +BASE0=XED_REG_EAX mode64 -> MOD=0 +BASE0=XED_REG_EBX mode64 -> MOD=0 +BASE0=XED_REG_ECX mode64 -> MOD=0 +BASE0=XED_REG_EDX mode64 -> MOD=0 +BASE0=XED_REG_ESI mode64 -> MOD=0 +BASE0=XED_REG_EDI mode64 -> MOD=0 +BASE0=XED_REG_ESP mode64 -> MOD=0 # our choice to use MOD=0 (w/sib) + +BASE0=XED_REG_R8D mode64 -> MOD=0 +BASE0=XED_REG_R9D mode64 -> MOD=0 +BASE0=XED_REG_R10D mode64 -> MOD=0 +BASE0=XED_REG_R11D mode64 -> MOD=0 +BASE0=XED_REG_R12D mode64 -> MOD=0 # our choice to use MOD=0 (w/sib) +BASE0=XED_REG_R14D mode64 -> MOD=0 +BASE0=XED_REG_R15D mode64 -> MOD=0 + +MODRM_MOD_EA32_DISP8():: +otherwise -> MOD=1 # might use SIB + +MODRM_MOD_EA32_DISP32():: +BASE0=@ -> MOD=0 #no base (handles SIB=1 case) +BASE0=GPR32e() -> MOD=2 #some base, not RIP, might use SIB +BASE0=XED_REG_RIP mode64 -> MOD=0 + +############################################################################## +#### EAMODE64 +############################################################################## + +MODRM_MOD_EA64_DISP0():: +BASE0=XED_REG_RIP -> MOD=0 DISP_WIDTH=32 DISP=0 # base rip +BASE0=XED_REG_RBP -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_R13 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_RAX -> MOD=0 +BASE0=XED_REG_RBX -> MOD=0 +BASE0=XED_REG_RCX -> MOD=0 +BASE0=XED_REG_RDX -> MOD=0 +BASE0=XED_REG_RSI -> MOD=0 +BASE0=XED_REG_RDI -> MOD=0 +BASE0=XED_REG_RSP -> MOD=0 +BASE0=XED_REG_R8 -> MOD=0 +BASE0=XED_REG_R9 -> MOD=0 +BASE0=XED_REG_R10 -> MOD=0 +BASE0=XED_REG_R11 -> MOD=0 +BASE0=XED_REG_R12 -> MOD=0 +BASE0=XED_REG_R14 -> MOD=0 +BASE0=XED_REG_R15 -> MOD=0 + +MODRM_MOD_EA64_DISP8():: +BASE0=GPR64e() -> MOD=1 + +MODRM_MOD_EA64_DISP32():: +BASE0=@ -> MOD=0 #no base, SIB=1 required (provided elsewhere) +BASE0=XED_REG_RIP -> MOD=0 #base rip +BASE0=XED_REG_RAX -> MOD=2 +BASE0=XED_REG_RBX -> MOD=2 +BASE0=XED_REG_RCX -> MOD=2 +BASE0=XED_REG_RDX -> MOD=2 +BASE0=XED_REG_RSI -> MOD=2 +BASE0=XED_REG_RDI -> MOD=2 +BASE0=XED_REG_RSP -> MOD=2 # SIB=1 required (and is provided elsewhere) +BASE0=XED_REG_RBP -> MOD=2 +BASE0=XED_REG_R8 -> MOD=2 +BASE0=XED_REG_R9 -> MOD=2 +BASE0=XED_REG_R10 -> MOD=2 +BASE0=XED_REG_R11 -> MOD=2 +BASE0=XED_REG_R12 -> MOD=2 # SIB=1 required (and is provided elsewhere) +BASE0=XED_REG_R13 -> MOD=2 +BASE0=XED_REG_R14 -> MOD=2 +BASE0=XED_REG_R15 -> MOD=2 +######################################################################################################## + + +#If we didn't already encode the base in the SIB! +MODRM_RM_ENCODE():: + +eamode16 SIB=0 -> MODRM_RM_ENCODE_EA16_SIB0() +eamode32 SIB=0 -> MODRM_RM_ENCODE_EA32_SIB0() +eamode64 SIB=0 -> MODRM_RM_ENCODE_EA64_SIB0() +eanot16 SIB=1 -> MODRM_RM_ENCODE_EANOT16_SIB1() + +############################################# + +MODRM_RM_ENCODE_EA16_SIB0():: +BASE0=XED_REG_BX INDEX=XED_REG_SI -> RM=0 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> RM=1 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> RM=2 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> RM=3 +BASE0=XED_REG_SI INDEX=@ -> RM=4 +BASE0=XED_REG_DI INDEX=@ -> RM=5 +BASE0=@ INDEX=@ -> DISP_WIDTH_16() RM=6 + + +# for BP without an index, we add an imm8=0 when encoding the MOD +BASE0=XED_REG_BP INDEX=@ -> DISP_WIDTH_0_8_16() RM=6 +BASE0=XED_REG_BX INDEX=@ -> RM=7 + +MODRM_RM_ENCODE_EA64_SIB0():: +BASE0=XED_REG_RAX -> RM=0 REXB=0 +BASE0=XED_REG_R8 -> RM=0 REXB=1 +BASE0=XED_REG_RCX -> RM=1 REXB=0 +BASE0=XED_REG_R9 -> RM=1 REXB=1 +BASE0=XED_REG_RDX -> RM=2 REXB=0 +BASE0=XED_REG_R10 -> RM=2 REXB=1 +BASE0=XED_REG_RBX -> RM=3 REXB=0 +BASE0=XED_REG_R11 -> RM=3 REXB=1 + + +BASE0=XED_REG_RSI -> RM=6 REXB=0 +BASE0=XED_REG_R14 -> RM=6 REXB=1 +BASE0=XED_REG_RDI -> RM=7 REXB=0 +BASE0=XED_REG_R15 -> RM=7 REXB=1 + +# case RM=5 is tricky. The mode,base and disp width play a role +BASE0=@ -> DISP_WIDTH_32() RM=5 # not setting REXB FIXME? + +# for rBP without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_RBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0 + + +# When we do the MOD encoding, we fix the displacement at 4B. +BASE0=XED_REG_RIP -> RM=5 # not setting REXB FIXME? + +# for r13 without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_R13 -> DISP_WIDTH_0_8_32() RM=5 REXB=1 + +MODRM_RM_ENCODE_EA32_SIB0():: +BASE0=XED_REG_EAX -> RM=0 REXB=0 +BASE0=XED_REG_R8D -> RM=0 REXB=1 +BASE0=XED_REG_ECX -> RM=1 REXB=0 +BASE0=XED_REG_R9D -> RM=1 REXB=1 +BASE0=XED_REG_EDX -> RM=2 REXB=0 +BASE0=XED_REG_R10D -> RM=2 REXB=1 +BASE0=XED_REG_EBX -> RM=3 REXB=0 +BASE0=XED_REG_R11D -> RM=3 REXB=1 + + +BASE0=XED_REG_ESI -> RM=6 REXB=0 +BASE0=XED_REG_R14D -> RM=6 REXB=1 +BASE0=XED_REG_EDI -> RM=7 REXB=0 +BASE0=XED_REG_R15D -> RM=7 REXB=1 + +# case RM=5 is tricky. The mode,base and disp width play a role +BASE0=@ -> DISP_WIDTH_32() RM=5 # not setting REXB FIXME? + +# for rBP without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_EBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0 + +# for r13 without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_R13D -> DISP_WIDTH_0_8_32() RM=5 REXB=1 + +BASE0=XED_REG_RIP mode64 -> RM=5 + +MODRM_RM_ENCODE_EANOT16_SIB1():: +otherwise -> RM=4 # SIB will specify the REXB etc. + +############################################# + + + +# These are good, seemingly: + +# FIXME: these are semi-redundant with field bindings that I need for decode. +# I was thinking about using something like: +# MODRM[mm,rrr,nnn] & SIB[ss,iii,bbb] +# coupled with: +# MODRM = (MOD,2), (REG,3), (RM,3) +# SIB = (SIBSCALE,2), (SIBINDEX,3), (SIBBASE,3) + +#FIXME: don't require =*??? +#FIXME: handle "nothing" option + +## SIB_EMIT():: +## SIB=1 SIBBASE[bbb]=* SIBSCALE[ss]=* SIBINDEX[iii]=* -> ss_iii_bbb +## SIB=0 -> nothing +## +## MODRM_EMIT():: +## MODRM=1 MOD[xx]=* REG[rrr]=* RM[mmm]=* -> xx_rrr_mmm +## MODRM=0 -> nothing + +# ... OR ... + +SIB_NT():: +SIB=1 SIBBASE[bbb] SIBSCALE[ss] SIBINDEX[iii] -> ss_iii_bbb +SIB=0 -> nothing + + + +# 2 bytes storage +DISP_NT():: +#DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 DISP[d/8] -> d/8 +DISP_WIDTH=16 DISP[d/16] -> d/16 +DISP_WIDTH=32 DISP[d/32] -> d/32 +DISP_WIDTH=64 DISP[d/64] -> d/64 +otherwise -> nothing + +ERROR():: +otherwise -> ERROR=XED_ERROR_GENERAL_ERROR + +DISP_WIDTH_0():: +DISP_WIDTH=0 -> nothing + +DISP_WIDTH_8():: +DISP_WIDTH=8 -> nothing + +DISP_WIDTH_16():: +DISP_WIDTH=16 -> nothing + +DISP_WIDTH_32():: +DISP_WIDTH=32 -> nothing + +DISP_WIDTH_0_8_16():: +DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 -> nothing +DISP_WIDTH=16 -> nothing + + +DISP_WIDTH_0_8_32():: +DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 -> nothing +DISP_WIDTH=32 -> nothing + diff --git a/datafiles/xed-nops.txt b/datafiles/xed-nops.txt new file mode 100644 index 0000000..e819857 --- /dev/null +++ b/datafiles/xed-nops.txt @@ -0,0 +1,92 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#################################################################### +# SPECIFIC WIDE NOPS RECOMMENDED BY THE PROGRAMMERS REFERENCE MANUAL +#################################################################### +#{ +#ICLASS : NOP1 +#CPL : 3 +#CATEGORY : WIDENOP +#EXTENSION : BASE +#PATTERN : 90 +#OPERANDS : +#} +{ +ICLASS : NOP2 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x66 0x90 +OPERANDS : +} +{ +ICLASS : NOP3 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x0F 0x1F 0x00 +OPERANDS : +} +{ +ICLASS : NOP4 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x0F 0x1F 0x40 0x00 +OPERANDS : +} +{ +ICLASS : NOP5 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x0F 0x1F 0x44 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP6 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x66 0x0F 0x1F 0x44 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP7 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP8 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP9 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +PATTERN : 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 +OPERANDS : +} diff --git a/datafiles/xed-operand-action-enum.txt b/datafiles/xed-operand-action-enum.txt new file mode 100644 index 0000000..8bfbbec --- /dev/null +++ b/datafiles/xed-operand-action-enum.txt @@ -0,0 +1,33 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-operand-action-enum.h +cfn xed-operand-action-enum.c +prefix XED_OPERAND_ACTION_ +typename xed_operand_action_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +RW ///< Read and written (must write) +R ///< Read-only +W ///< Write-only (must write) +RCW ///< Read and conditionlly written (may write) +CW ///< Conditionlly written (may write) +CRW ///< Conditionlly read, always written (must write) +CR ///< Conditional read diff --git a/datafiles/xed-operand-element-type-enum-base.txt b/datafiles/xed-operand-element-type-enum-base.txt new file mode 100644 index 0000000..97d5e80 --- /dev/null +++ b/datafiles/xed-operand-element-type-enum-base.txt @@ -0,0 +1,34 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-operand-element-type-enum.h +cfn xed-operand-element-type-enum.c +prefix XED_OPERAND_ELEMENT_TYPE_ +typename xed_operand_element_type_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +UINT ///< Unsigned integer +INT ///< Signed integer +SINGLE ///< 32b FP single precision +DOUBLE ///< 64b FP double precision +LONGDOUBLE ///< 80b FP x87 +LONGBCD ///< 80b decimal BCD +STRUCT ///< a structure of various fields +VARIABLE ///< depends on other fields in the instruction diff --git a/datafiles/xed-operand-types.txt b/datafiles/xed-operand-types.txt new file mode 100644 index 0000000..3f83317 --- /dev/null +++ b/datafiles/xed-operand-types.txt @@ -0,0 +1,41 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +#XTYPE TYPE BITS-PER-ELEM +# +var VARIABLE 0 # instruction must set NELEM and ELEMENT_SIZE +struct STRUCT 0 # many elements of different widths +int INT 0 # one element, all the bits, width varies +uint UINT 0 # one element, all the bits, width varies +# +i1 INT 1 +i8 INT 8 +i16 INT 16 +i32 INT 32 +i64 INT 64 +u8 UINT 8 +u16 UINT 16 +u32 UINT 32 +u64 UINT 64 +u128 UINT 128 +u256 UINT 256 +f32 SINGLE 32 +f64 DOUBLE 64 +f80 LONGDOUBLE 80 +b80 LONGBCD 80 diff --git a/datafiles/xed-operand-visibility-enum.txt b/datafiles/xed-operand-visibility-enum.txt new file mode 100644 index 0000000..0257080 --- /dev/null +++ b/datafiles/xed-operand-visibility-enum.txt @@ -0,0 +1,31 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-operand-visibility-enum.h +cfn xed-operand-visibility-enum.c +prefix XED_OPVIS_ +typename xed_operand_visibility_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +EXPLICIT ///< Shows up in operand encoding +IMPLICIT ///< Part of the opcode, but listed as an operand +SUPPRESSED ///< Part of the opcode, but not typically listed as an operand + + diff --git a/datafiles/xed-operand-width.txt b/datafiles/xed-operand-width.txt new file mode 100644 index 0000000..ac96141 --- /dev/null +++ b/datafiles/xed-operand-width.txt @@ -0,0 +1,109 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# @file xed-operand-width.txt + +# the default xtype can be overridden in each operand using a ":" followed by an explicit xtype +## +## the width defaults to bytes. But it can be bits if it has a "bits" suffix +## +# +# default +#oc2-code XTYPE width16 width32 width64 (if only one width is shown, it is for all widths) +# +INVALID INVALID 0 +# +# 3 strange things: +# +asz int 2 4 8 # varies with the effective address width +ssz int 2 4 8 # varies with the stack address width +pseudo struct 0 # these are for unusual registers +pseudox87 struct 0 # these are for unusual registers +# +# +# +#1 i1 1 # FIXME: this is not used... +a16 i16 4 # bound +a32 i32 8 # bound +b u8 1 +d i32 4 +# +dq i32 16 +# +xub u8 16 +xuw u16 16 +xud u32 16 +xuq u64 16 +x128 u128 16 +# +xb i8 16 +xw i16 16 +xd i32 16 +xq i64 16 +# +# +mb i8 8 +mw i16 8 +md i32 8 +mq i64 8 +# +m64int i64 8 +m64real f64 8 +mem108 struct 108 +mem14 struct 14 +mem16 struct 2 +mem16int i16 2 +mem28 struct 28 +mem32int i32 4 +mem32real f32 4 +mem80dec b80 10 +mem80real f80 10 +f80 f80 10 # for X87 registers: +mem94 struct 94 +mfpxenv struct 512 +mxsave struct 576 +mprefetch i64 64 # made up width for prefetches +p struct 4 6 6 +p2 struct 4 6 10 +pd f64 16 +ps f32 16 +pi i32 8 +q i64 8 +s struct 6 6 10 +s64 struct 10 +sd f64 8 +si i32 4 +ss f32 4 +v int 2 4 8 +y int 4 4 8 +w i16 2 +z int 2 4 4 +spw8 int 16 32 0 # varies (64b invalid) STACK POINTER WIDTH +spw int 2 4 8 # varies STACK POINTER WIDTH +spw3 int 6 12 24 # varies (IRET approx) STACK POINTER WIDTH +spw2 int 4 8 16 # varies (FAR call/ret approx) STACK POINTER WIDTH +i1 int 1bits +i2 int 2bits +i3 int 3bits +i4 int 4bits +i5 int 5bits +i6 int 6bits +i7 int 7bits +i8 int 8bits +var var 0 # relies on NELEM * ELEMENT_SIZE to get the number of bits. +bnd32 u32 12 # MPX 32b BNDLDX/BNDSTX memop 3x4B +bnd64 u64 24 # MPX 32b BNDLDX/BNDSTX memop 3x8B diff --git a/datafiles/xed-pointer-width.txt b/datafiles/xed-pointer-width.txt new file mode 100644 index 0000000..9e60288 --- /dev/null +++ b/datafiles/xed-pointer-width.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +1 byte b +2 word w +4 dword l +8 qword q +16 xmmword x diff --git a/datafiles/xed-prefixes-encode.txt b/datafiles/xed-prefixes-encode.txt new file mode 100755 index 0000000..1a2dcd8 --- /dev/null +++ b/datafiles/xed-prefixes-encode.txt @@ -0,0 +1,234 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# any of the things in {} can trigger the action for these +# the letters in square brackets are bound to the bits after the arrow. +# The [] brackets are like an OR-triggering function. + +# For encoding, we spell out the order of the legacy prefixes and rex +# prefixes. On decode, the sequential semantics were used to zero out +# the effects of rex prefixes but that doesn't work for encode. So we +# have to make a different table for encoding. + + +SEQUENCE ISA_ENCODE + ISA_BINDINGS + ISA_EMIT + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + REX_PREFIX_ENC_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + REX_PREFIX_ENC_EMIT() + INSTRUCTIONS_EMIT() # THIS TAKES CARE OF MODRM/SIB/DISP/IMM + + +FIXUP_EOSZ_ENC():: +mode16 EOSZ=0 -> EOSZ=1 +mode32 EOSZ=0 -> EOSZ=2 +mode64 EOSZ=0 -> EOSZ=2 +otherwise -> nothing + +FIXUP_EASZ_ENC():: +mode16 EASZ=0 -> EASZ=1 +mode32 EASZ=0 -> EASZ=2 +mode64 EASZ=0 -> EASZ=3 +otherwise -> nothing + +FIXUP_SMODE_ENC():: +mode64 SMODE=0 -> SMODE=2 +mode64 SMODE=1 -> error +otherwise -> nothing + +# FIXME: make ICLASS a possible field? +# Remove the segment override if any supplied, from an LEA +REMOVE_SEGMENT():: +AGEN=0 -> nothing +AGEN=1 -> REMOVE_SEGMENT_AGEN1() + +REMOVE_SEGMENT_AGEN1():: +SEG0=@ -> nothing +SEG0=SEGe() -> error + + +# need to emit a segment override if the segment is not the default segment for the operation. +# These are only meant for use with the things that do not use MODRM (like xlat, A0-A3 MOVs, and the string ops). +# (MODRM encoding handles this stuff much better). +OVERRIDE_SEG0():: +SEG0=@ -> SEG_OVD=0 +SEG0=XED_REG_DS -> SEG_OVD=0 +SEG0=XED_REG_CS -> SEG_OVD=1 +SEG0=XED_REG_ES -> SEG_OVD=3 +SEG0=XED_REG_FS -> SEG_OVD=4 +SEG0=XED_REG_GS -> SEG_OVD=5 +SEG0=XED_REG_SS -> SEG_OVD=6 + +OVERRIDE_SEG1():: +SEG1=@ -> SEG_OVD=0 +SEG1=XED_REG_DS -> SEG_OVD=0 +SEG1=XED_REG_CS -> SEG_OVD=1 +SEG1=XED_REG_ES -> SEG_OVD=3 +SEG1=XED_REG_FS -> SEG_OVD=4 +SEG1=XED_REG_GS -> SEG_OVD=5 +SEG1=XED_REG_SS -> SEG_OVD=6 + + + +REX_PREFIX_ENC():: +mode64 NOREX=0 NEEDREX=1 REXW[w] REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REX=1 REXW[w] REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w]=1 REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b]=1 REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b] REXX[x]=1 REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b] REXX[x] REXR[r]=1 -> 0b0100 wrxb +mode64 NOREX=1 NEEDREX=1 -> error +mode64 NOREX=1 REX=1 -> error +mode64 NOREX=1 REXW=1 -> error +mode64 NOREX=1 REXB=1 -> error +mode64 NOREX=1 REXX=1 -> error +mode64 NOREX=1 REXR=1 -> error +mode64 NEEDREX=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + +# If any REX bit shows up in 32 or 16b mode, we have an error. ensure everything is zero +mode32 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing +mode16 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + +# or die...1 +otherwise -> error + +# This checks that we didn't try to use a byte register that requires +# we do not have a rex with something else that requires we have a REX +# prefix. + +# FIXME: need to allow repeated prefixes + +# FIXME: optionally allow for prefix order to be specified (from decode) + +PREFIX_ENC():: +# create an "OR" of REFINING=2 and REP=2 +REP=2 -> 0xf2 no_return +REP=3 -> 0xf3 no_return +# +66_prefix -> 0x66 no_return +67_prefix -> 0x67 no_return +lock_prefix -> 0xf0 no_return +fs_prefix -> 0x64 no_return +gs_prefix -> 0x65 no_return +#################################################### +mode64 HINT=3 -> 0x2e no_return +mode64 HINT=4 -> 0x3e no_return +##################################################### +not64 cs_prefix -> 0x2e no_return +not64 HINT=3 -> 0x2e no_return +not64 ds_prefix -> 0x3e no_return +not64 HINT=4 -> 0x3e no_return +not64 es_prefix -> 0x26 no_return +not64 ss_prefix -> 0x36 no_return +otherwise -> nothing + + +########################################################################## +# +# +# This is the encode version. It just sets DF64 for later use by the +# OSZ_NONTERM_ENC() nonterminal. +# +DF64():: +mode16 -> nothing +mode32 -> nothing +mode64 -> DF64=1 ### EOSZ=3 -- removed EOSZ=3 because it broke encoding pop 16b dx in 64b mode. + +# +# If an instruction pattern sets W to zero or 1, we make sure it also +# sets SKIP_OSZ=1 so that we do not do any overwrite of that value for +# the EOSZ computation. +# +OSZ_NONTERM_ENC():: +mode16 EOSZ=1 -> nothing +mode16 EOSZ=2 DF32=1 -> nothing + +# We don't use SKIP_OSZ=1 with the MOV_CR instructions but this is +# here for completeness. +mode16 EOSZ=2 DF32=0 SKIP_OSZ=1 -> nothing +mode16 EOSZ=2 DF32=0 SKIP_OSZ=0 -> 66_prefix + +mode32 EOSZ=1 SKIP_OSZ=1 -> nothing +mode32 EOSZ=1 SKIP_OSZ=0 -> 66_prefix + +mode32 EOSZ=2 -> nothing + +mode64 EOSZ=1 SKIP_OSZ=1 -> nothing +mode64 EOSZ=1 SKIP_OSZ=0 -> 66_prefix + +mode64 EOSZ=2 DF64=1 -> error +mode64 EOSZ=2 DF64=0 -> nothing +mode64 EOSZ=3 DF64=1 -> nothing + +mode64 EOSZ=3 DF64=0 SKIP_OSZ=1 -> nothing +mode64 EOSZ=3 DF64=0 SKIP_OSZ=0 -> REXW=1 + + +# The REFINING66() decode version is required for when we have a 66 +# prefix that should not change the EOSZ. The REFINING66() decode +# nonterminal restores that EOSZ. +# +# This one, the REFINING66() encode version is required for +# compatibility, but it doesn't do anything. The EOSZ is an input to +# the endoder. +# +# Turn off the REP prefix in case we are switching forms. +REFINING66():: +otherwise -> nothing # norep works too +IGNORE66():: +otherwise -> nothing + +# Same for IMMUNE66() used for sttni/cmpxchg8B/cmpxchg16b. We do not want to emit a 66 prefix in 32b mode +IMMUNE66():: +mode16 -> EOSZ=2 DF32=1 +otherwise -> nothing + + +IMMUNE66_LOOP64():: +otherwise -> nothing + +IMMUNE_REXW():: +otherwise -> nothing + +CR_WIDTH():: +mode16 -> DF32=1 EOSZ=2 +mode32 -> nothing +mode64 -> DF64=1 EOSZ=3 + +FORCE64():: +otherwise -> DF64=1 EOSZ=3 + + +# the prefix encoder does all the required work. +BRANCH_HINT():: +otherwise -> nothing + +# end of xed-prefixes-encode.txt +########################################################################## diff --git a/datafiles/xed-prefixes.txt b/datafiles/xed-prefixes.txt new file mode 100644 index 0000000..f14872f --- /dev/null +++ b/datafiles/xed-prefixes.txt @@ -0,0 +1,143 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +################################################################# +## file: xed-prefixes.txt +################################################################# + +# SYNTAX: +# conditions and input bytes | output-mode-state and captures... + + +# FIXME: make ICLASS a possible field? +# Remove the segment override if any supplied, from an LEA +REMOVE_SEGMENT():: +mode16 | SEG0=XED_REG_INVALID +mode32 | SEG0=XED_REG_INVALID +mode64 | SEG0=XED_REG_INVALID +# FIXME 2007-07-10 full "otherwise" RHS's are not supported yet in decoder. +#otherwise | SEG0=XED_REG_INVALID + + + +PREFIXES():: + +# The presence of the REX itself and the REXW are state bits because +# they control decoding downstream. + +# +# 64b mode prefixes +# + +# rex prefixes +mode64 0b0100 wrxb | XED_RESET REX=1 REXW=w REXR=r REXX=x REXB=b + +# Note that because of the REX rules, if we see a legacy prefix after +# a rex prefix, we have to ignore the rex prefix and all its captures! +# (reset_rex). The new state bits override existing captures and state +# bits. That explains all the rex stuff. + +# other prefixes + +# NOTE: double denotation of f2/f3/osz.(eg f2_prefix and +# f2_refining_prefix). That 2nd allows for table lookups indexing to +# the 2B table. + +mode64 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET reset_rex f2_prefix refining_f2 +mode64 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET reset_rex f3_prefix refining_f3 +mode64 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET reset_rex f2_prefix refining_f2 +mode64 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET reset_rex f3_prefix refining_f3 +mode64 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET reset_rex +mode64 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET reset_rex + + +# 2009-08-17: The 66_prefix (OSZ=1) gets zero'ed by some instructions +# that use 66 as a refining prefix. To ensure we have a 66 prefix +# indicator, we also set PREFIX66=1. +mode64 0x66 | XED_RESET 66_prefix PREFIX66=1 reset_rex + +mode64 0x67 | XED_RESET 67_prefix reset_rex +mode64 0xf0 | XED_RESET lock_prefix reset_rex + +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode64 0x2e | XED_RESET HINT=1 reset_rex +mode64 0x3e | XED_RESET HINT=2 reset_rex + +mode64 0x26 | XED_RESET reset_rex +mode64 0x64 | XED_RESET fs_prefix reset_rex +mode64 0x65 | XED_RESET gs_prefix reset_rex +mode64 0x36 | XED_RESET reset_rex + +# +# 32b mode prefixes +# + +mode32 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET f2_prefix refining_f2 +mode32 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET f3_prefix refining_f3 +mode32 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f2_prefix refining_f2 +mode32 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f3_prefix refining_f3 +mode32 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET +mode32 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET + +mode32 0x66 | XED_RESET 66_prefix PREFIX66=1 +mode32 0x67 | XED_RESET 67_prefix +mode32 0xf0 | XED_RESET lock_prefix +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode32 0x2e | XED_RESET cs_prefix HINT=1 +mode32 0x3e | XED_RESET ds_prefix HINT=2 + +mode32 0x26 | XED_RESET es_prefix +mode32 0x64 | XED_RESET fs_prefix +mode32 0x65 | XED_RESET gs_prefix +mode32 0x36 | XED_RESET ss_prefix + +# +# 16b mode prefixes +# + + +mode16 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET f2_prefix refining_f2 +mode16 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET f3_prefix refining_f3 +mode16 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f2_prefix refining_f2 +mode16 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f3_prefix refining_f3 +mode16 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET +mode16 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET + +mode16 0x66 | XED_RESET 66_prefix PREFIX66=1 +mode16 0x67 | XED_RESET 67_prefix +mode16 0xf0 | XED_RESET lock_prefix +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode16 0x2e | XED_RESET cs_prefix HINT=1 +mode16 0x3e | XED_RESET ds_prefix HINT=2 + +mode16 0x26 | XED_RESET es_prefix +mode16 0x64 | XED_RESET fs_prefix +mode16 0x65 | XED_RESET gs_prefix +mode16 0x36 | XED_RESET ss_prefix + +# This is the epsilon action indicating that it is okay to +# accept nothing at this point in the traversal. +otherwise | + +BRANCH_HINT():: +HINT=0 | +HINT=1 | HINT=3 +HINT=2 | HINT=4 + diff --git a/datafiles/xed-reg-role.enum.txt b/datafiles/xed-reg-role.enum.txt new file mode 100644 index 0000000..775b05d --- /dev/null +++ b/datafiles/xed-reg-role.enum.txt @@ -0,0 +1,34 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-reg-role-enum.h +cfn xed-reg-role-enum.c +prefix XED_REG_ROLE_ +typename xed_reg_role_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +NORMAL ///< Register is a normal register +SEGREG0 ///< The segment register associated with the first memop +SEGREG1 ///< The segment register associated with the second memop +BASE0 ///< The base register associated with the first memop +BASE1 ///< The base register associated with the second memop +INDEX ///< The index register associated with the first memop + + diff --git a/datafiles/xed-reg-tables-xmm.txt b/datafiles/xed-reg-tables-xmm.txt new file mode 100644 index 0000000..62e117b --- /dev/null +++ b/datafiles/xed-reg-tables-xmm.txt @@ -0,0 +1,85 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R():: +mode16 | OUTREG=XMM_R_32() +mode32 | OUTREG=XMM_R_32() +mode64 | OUTREG=XMM_R_64() + +xed_reg_enum_t XMM_R_32():: +REG=0x0 | OUTREG=XED_REG_XMM0 +REG=0x1 | OUTREG=XED_REG_XMM1 +REG=0x2 | OUTREG=XED_REG_XMM2 +REG=0x3 | OUTREG=XED_REG_XMM3 +REG=0x4 | OUTREG=XED_REG_XMM4 +REG=0x5 | OUTREG=XED_REG_XMM5 +REG=0x6 | OUTREG=XED_REG_XMM6 +REG=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R_64():: +REXR=0 REG=0x0 | OUTREG=XED_REG_XMM0 +REXR=0 REG=0x1 | OUTREG=XED_REG_XMM1 +REXR=0 REG=0x2 | OUTREG=XED_REG_XMM2 +REXR=0 REG=0x3 | OUTREG=XED_REG_XMM3 +REXR=0 REG=0x4 | OUTREG=XED_REG_XMM4 +REXR=0 REG=0x5 | OUTREG=XED_REG_XMM5 +REXR=0 REG=0x6 | OUTREG=XED_REG_XMM6 +REXR=0 REG=0x7 | OUTREG=XED_REG_XMM7 +REXR=1 REG=0x0 | OUTREG=XED_REG_XMM8 +REXR=1 REG=0x1 | OUTREG=XED_REG_XMM9 +REXR=1 REG=0x2 | OUTREG=XED_REG_XMM10 +REXR=1 REG=0x3 | OUTREG=XED_REG_XMM11 +REXR=1 REG=0x4 | OUTREG=XED_REG_XMM12 +REXR=1 REG=0x5 | OUTREG=XED_REG_XMM13 +REXR=1 REG=0x6 | OUTREG=XED_REG_XMM14 +REXR=1 REG=0x7 | OUTREG=XED_REG_XMM15 + + +xed_reg_enum_t XMM_B():: +mode16 | OUTREG=XMM_B_32() +mode32 | OUTREG=XMM_B_32() +mode64 | OUTREG=XMM_B_64() + +xed_reg_enum_t XMM_B_32():: +RM=0x0 | OUTREG=XED_REG_XMM0 +RM=0x1 | OUTREG=XED_REG_XMM1 +RM=0x2 | OUTREG=XED_REG_XMM2 +RM=0x3 | OUTREG=XED_REG_XMM3 +RM=0x4 | OUTREG=XED_REG_XMM4 +RM=0x5 | OUTREG=XED_REG_XMM5 +RM=0x6 | OUTREG=XED_REG_XMM6 +RM=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B_64():: +REXB=0 RM=0x0 | OUTREG=XED_REG_XMM0 +REXB=0 RM=0x1 | OUTREG=XED_REG_XMM1 +REXB=0 RM=0x2 | OUTREG=XED_REG_XMM2 +REXB=0 RM=0x3 | OUTREG=XED_REG_XMM3 +REXB=0 RM=0x4 | OUTREG=XED_REG_XMM4 +REXB=0 RM=0x5 | OUTREG=XED_REG_XMM5 +REXB=0 RM=0x6 | OUTREG=XED_REG_XMM6 +REXB=0 RM=0x7 | OUTREG=XED_REG_XMM7 +REXB=1 RM=0x0 | OUTREG=XED_REG_XMM8 +REXB=1 RM=0x1 | OUTREG=XED_REG_XMM9 +REXB=1 RM=0x2 | OUTREG=XED_REG_XMM10 +REXB=1 RM=0x3 | OUTREG=XED_REG_XMM11 +REXB=1 RM=0x4 | OUTREG=XED_REG_XMM12 +REXB=1 RM=0x5 | OUTREG=XED_REG_XMM13 +REXB=1 RM=0x6 | OUTREG=XED_REG_XMM14 +REXB=1 RM=0x7 | OUTREG=XED_REG_XMM15 + diff --git a/datafiles/xed-reg-tables.txt b/datafiles/xed-reg-tables.txt new file mode 100644 index 0000000..d979c64 --- /dev/null +++ b/datafiles/xed-reg-tables.txt @@ -0,0 +1,663 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables.txt +######################################################################## + +# Need to handle flags, rIP, seg-selectors, pseudo regs +# Also does not specify register width + +# What about something like this: +# op1=GPRv_R():rw +# we need to know what to bind the result to ultimately. +# Just specifying a register is confusing to me. Don't know where to store it. +# Have a "store-here" location for this kind of thing? + +####################################################################### +# Expand the generic registers using the effective address size EASZ +####################################################################### +xed_reg_enum_t ArAX():: +EASZ=1 | OUTREG=XED_REG_AX +EASZ=2 | OUTREG=XED_REG_EAX +EASZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t ArBX():: +EASZ=1 | OUTREG=XED_REG_BX +EASZ=2 | OUTREG=XED_REG_EBX +EASZ=3 | OUTREG=XED_REG_RBX +xed_reg_enum_t ArCX():: +EASZ=1 | OUTREG=XED_REG_CX +EASZ=2 | OUTREG=XED_REG_ECX +EASZ=3 | OUTREG=XED_REG_RCX +xed_reg_enum_t ArDX():: +EASZ=1 | OUTREG=XED_REG_DX +EASZ=2 | OUTREG=XED_REG_EDX +EASZ=3 | OUTREG=XED_REG_RDX + +xed_reg_enum_t ArSI():: +EASZ=1 | OUTREG=XED_REG_SI +EASZ=2 | OUTREG=XED_REG_ESI +EASZ=3 | OUTREG=XED_REG_RSI +xed_reg_enum_t ArDI():: +EASZ=1 | OUTREG=XED_REG_DI +EASZ=2 | OUTREG=XED_REG_EDI +EASZ=3 | OUTREG=XED_REG_RDI +xed_reg_enum_t ArSP():: +EASZ=1 | OUTREG=XED_REG_SP +EASZ=2 | OUTREG=XED_REG_ESP +EASZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t ArBP():: +EASZ=1 | OUTREG=XED_REG_BP +EASZ=2 | OUTREG=XED_REG_EBP +EASZ=3 | OUTREG=XED_REG_RBP + +xed_reg_enum_t SrSP():: +smode16 | OUTREG=XED_REG_SP +smode32 | OUTREG=XED_REG_ESP +smode64 | OUTREG=XED_REG_RSP +xed_reg_enum_t SrBP():: +smode16 | OUTREG=XED_REG_BP +smode32 | OUTREG=XED_REG_EBP +smode64 | OUTREG=XED_REG_RBP + +xed_reg_enum_t Ar8():: +EASZ=1 | OUTREG=XED_REG_R8W +EASZ=2 | OUTREG=XED_REG_R8D +EASZ=3 | OUTREG=XED_REG_R8 +xed_reg_enum_t Ar9():: +EASZ=1 | OUTREG=XED_REG_R9W +EASZ=2 | OUTREG=XED_REG_R9D +EASZ=3 | OUTREG=XED_REG_R9 +xed_reg_enum_t Ar10():: +EASZ=1 | OUTREG=XED_REG_R10W +EASZ=2 | OUTREG=XED_REG_R10D +EASZ=3 | OUTREG=XED_REG_R10 +xed_reg_enum_t Ar11():: +EASZ=1 | OUTREG=XED_REG_R11W +EASZ=2 | OUTREG=XED_REG_R11D +EASZ=3 | OUTREG=XED_REG_R11 +xed_reg_enum_t Ar12():: +EASZ=1 | OUTREG=XED_REG_R12W +EASZ=2 | OUTREG=XED_REG_R12D +EASZ=3 | OUTREG=XED_REG_R12 +xed_reg_enum_t Ar13():: +EASZ=1 | OUTREG=XED_REG_R13W +EASZ=2 | OUTREG=XED_REG_R13D +EASZ=3 | OUTREG=XED_REG_R13 +xed_reg_enum_t Ar14():: +EASZ=1 | OUTREG=XED_REG_R14W +EASZ=2 | OUTREG=XED_REG_R14D +EASZ=3 | OUTREG=XED_REG_R14 +xed_reg_enum_t Ar15():: +EASZ=1 | OUTREG=XED_REG_R15W +EASZ=2 | OUTREG=XED_REG_R15D +EASZ=3 | OUTREG=XED_REG_R15 + +xed_reg_enum_t rIP():: +EASZ=1 | OUTREG=XED_REG_IP +EASZ=2 | OUTREG=XED_REG_EIP +EASZ=3 | OUTREG=XED_REG_RIP + + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 32b +####################################################################### + + +xed_reg_enum_t OeAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_EAX + + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 64b +####################################################################### + +xed_reg_enum_t OrAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t OrDX():: +EOSZ=1 | OUTREG=XED_REG_DX +EOSZ=2 | OUTREG=XED_REG_EDX +EOSZ=3 | OUTREG=XED_REG_RDX + +xed_reg_enum_t OrSP():: +EOSZ=1 | OUTREG=XED_REG_SP +EOSZ=2 | OUTREG=XED_REG_ESP +EOSZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t OrBP():: +EOSZ=1 | OUTREG=XED_REG_BP +EOSZ=2 | OUTREG=XED_REG_EBP +EOSZ=3 | OUTREG=XED_REG_RBP + + +##################################################### + +xed_reg_enum_t rFLAGS():: +mode16 | OUTREG=XED_REG_FLAGS +mode32 | OUTREG=XED_REG_EFLAGS +mode64 | OUTREG=XED_REG_RFLAGS + +##################################################### + + +xed_reg_enum_t MMX_R():: +REG=0x0 | OUTREG=XED_REG_MMX0 +REG=0x1 | OUTREG=XED_REG_MMX1 +REG=0x2 | OUTREG=XED_REG_MMX2 +REG=0x3 | OUTREG=XED_REG_MMX3 +REG=0x4 | OUTREG=XED_REG_MMX4 +REG=0x5 | OUTREG=XED_REG_MMX5 +REG=0x6 | OUTREG=XED_REG_MMX6 +REG=0x7 | OUTREG=XED_REG_MMX7 + +xed_reg_enum_t MMX_B():: +RM=0x0 | OUTREG=XED_REG_MMX0 +RM=0x1 | OUTREG=XED_REG_MMX1 +RM=0x2 | OUTREG=XED_REG_MMX2 +RM=0x3 | OUTREG=XED_REG_MMX3 +RM=0x4 | OUTREG=XED_REG_MMX4 +RM=0x5 | OUTREG=XED_REG_MMX5 +RM=0x6 | OUTREG=XED_REG_MMX6 +RM=0x7 | OUTREG=XED_REG_MMX7 + +################################# + +# Things that scale with effective operand size + + + +# When used as the MODRM.REG register +xed_reg_enum_t GPRv_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +xed_reg_enum_t GPRv_SB():: +EOSZ=3 | OUTREG=GPR64_SB() +EOSZ=2 | OUTREG=GPR32_SB() +EOSZ=1 | OUTREG=GPR16_SB() + +xed_reg_enum_t GPRz_R():: +EOSZ=3 | OUTREG=GPR32_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +# When used as the MOD=11/RM register +xed_reg_enum_t GPRv_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRz_B():: +EOSZ=3 | OUTREG=GPR32_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRy_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR32_B() + +xed_reg_enum_t GPRy_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR32_R() + +##################################### + +xed_reg_enum_t GPR64_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_RAX +REXR=0 REG=0x1 | OUTREG=XED_REG_RCX +REXR=0 REG=0x2 | OUTREG=XED_REG_RDX +REXR=0 REG=0x3 | OUTREG=XED_REG_RBX +REXR=0 REG=0x4 | OUTREG=XED_REG_RSP +REXR=0 REG=0x5 | OUTREG=XED_REG_RBP +REXR=0 REG=0x6 | OUTREG=XED_REG_RSI +REXR=0 REG=0x7 | OUTREG=XED_REG_RDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8 +REXR=1 REG=0x1 | OUTREG=XED_REG_R9 +REXR=1 REG=0x2 | OUTREG=XED_REG_R10 +REXR=1 REG=0x3 | OUTREG=XED_REG_R11 +REXR=1 REG=0x4 | OUTREG=XED_REG_R12 +REXR=1 REG=0x5 | OUTREG=XED_REG_R13 +REXR=1 REG=0x6 | OUTREG=XED_REG_R14 +REXR=1 REG=0x7 | OUTREG=XED_REG_R15 + + +xed_reg_enum_t GPR64_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_RAX +REXB=0 RM=0x1 | OUTREG=XED_REG_RCX +REXB=0 RM=0x2 | OUTREG=XED_REG_RDX +REXB=0 RM=0x3 | OUTREG=XED_REG_RBX +REXB=0 RM=0x4 | OUTREG=XED_REG_RSP +REXB=0 RM=0x5 | OUTREG=XED_REG_RBP +REXB=0 RM=0x6 | OUTREG=XED_REG_RSI +REXB=0 RM=0x7 | OUTREG=XED_REG_RDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8 +REXB=1 RM=0x1 | OUTREG=XED_REG_R9 +REXB=1 RM=0x2 | OUTREG=XED_REG_R10 +REXB=1 RM=0x3 | OUTREG=XED_REG_R11 +REXB=1 RM=0x4 | OUTREG=XED_REG_R12 +REXB=1 RM=0x5 | OUTREG=XED_REG_R13 +REXB=1 RM=0x6 | OUTREG=XED_REG_R14 +REXB=1 RM=0x7 | OUTREG=XED_REG_R15 + +xed_reg_enum_t GPR64_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX +REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP +REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI +REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8 +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9 +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10 +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11 +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12 +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13 +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14 +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15 + + + +xed_reg_enum_t GPR64_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8 +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9 +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10 +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11 +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12 +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13 +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14 +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15 + + +################################# + + +xed_reg_enum_t GPR32_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_EAX +REXR=0 REG=0x1 | OUTREG=XED_REG_ECX +REXR=0 REG=0x2 | OUTREG=XED_REG_EDX +REXR=0 REG=0x3 | OUTREG=XED_REG_EBX +REXR=0 REG=0x4 | OUTREG=XED_REG_ESP +REXR=0 REG=0x5 | OUTREG=XED_REG_EBP +REXR=0 REG=0x6 | OUTREG=XED_REG_ESI +REXR=0 REG=0x7 | OUTREG=XED_REG_EDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8D +REXR=1 REG=0x1 | OUTREG=XED_REG_R9D +REXR=1 REG=0x2 | OUTREG=XED_REG_R10D +REXR=1 REG=0x3 | OUTREG=XED_REG_R11D +REXR=1 REG=0x4 | OUTREG=XED_REG_R12D +REXR=1 REG=0x5 | OUTREG=XED_REG_R13D +REXR=1 REG=0x6 | OUTREG=XED_REG_R14D +REXR=1 REG=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_EAX +REXB=0 RM=0x1 | OUTREG=XED_REG_ECX +REXB=0 RM=0x2 | OUTREG=XED_REG_EDX +REXB=0 RM=0x3 | OUTREG=XED_REG_EBX +REXB=0 RM=0x4 | OUTREG=XED_REG_ESP +REXB=0 RM=0x5 | OUTREG=XED_REG_EBP +REXB=0 RM=0x6 | OUTREG=XED_REG_ESI +REXB=0 RM=0x7 | OUTREG=XED_REG_EDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8D +REXB=1 RM=0x1 | OUTREG=XED_REG_R9D +REXB=1 RM=0x2 | OUTREG=XED_REG_R10D +REXB=1 RM=0x3 | OUTREG=XED_REG_R11D +REXB=1 RM=0x4 | OUTREG=XED_REG_R12D +REXB=1 RM=0x5 | OUTREG=XED_REG_R13D +REXB=1 RM=0x6 | OUTREG=XED_REG_R14D +REXB=1 RM=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX +REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP +REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI +REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D + + + + + +xed_reg_enum_t GPR32_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D + + +############################# + + +xed_reg_enum_t GPR16_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_AX +REXR=0 REG=0x1 | OUTREG=XED_REG_CX +REXR=0 REG=0x2 | OUTREG=XED_REG_DX +REXR=0 REG=0x3 | OUTREG=XED_REG_BX +REXR=0 REG=0x4 | OUTREG=XED_REG_SP +REXR=0 REG=0x5 | OUTREG=XED_REG_BP +REXR=0 REG=0x6 | OUTREG=XED_REG_SI +REXR=0 REG=0x7 | OUTREG=XED_REG_DI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8W +REXR=1 REG=0x1 | OUTREG=XED_REG_R9W +REXR=1 REG=0x2 | OUTREG=XED_REG_R10W +REXR=1 REG=0x3 | OUTREG=XED_REG_R11W +REXR=1 REG=0x4 | OUTREG=XED_REG_R12W +REXR=1 REG=0x5 | OUTREG=XED_REG_R13W +REXR=1 REG=0x6 | OUTREG=XED_REG_R14W +REXR=1 REG=0x7 | OUTREG=XED_REG_R15W + + + +xed_reg_enum_t GPR16_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AX +REXB=0 RM=0x1 | OUTREG=XED_REG_CX +REXB=0 RM=0x2 | OUTREG=XED_REG_DX +REXB=0 RM=0x3 | OUTREG=XED_REG_BX +REXB=0 RM=0x4 | OUTREG=XED_REG_SP +REXB=0 RM=0x5 | OUTREG=XED_REG_BP +REXB=0 RM=0x6 | OUTREG=XED_REG_SI +REXB=0 RM=0x7 | OUTREG=XED_REG_DI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8W +REXB=1 RM=0x1 | OUTREG=XED_REG_R9W +REXB=1 RM=0x2 | OUTREG=XED_REG_R10W +REXB=1 RM=0x3 | OUTREG=XED_REG_R11W +REXB=1 RM=0x4 | OUTREG=XED_REG_R12W +REXB=1 RM=0x5 | OUTREG=XED_REG_R13W +REXB=1 RM=0x6 | OUTREG=XED_REG_R14W +REXB=1 RM=0x7 | OUTREG=XED_REG_R15W + +xed_reg_enum_t GPR16_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AX +REXB=0 SRM=0x1 | OUTREG=XED_REG_CX +REXB=0 SRM=0x2 | OUTREG=XED_REG_DX +REXB=0 SRM=0x3 | OUTREG=XED_REG_BX +REXB=0 SRM=0x4 | OUTREG=XED_REG_SP +REXB=0 SRM=0x5 | OUTREG=XED_REG_BP +REXB=0 SRM=0x6 | OUTREG=XED_REG_SI +REXB=0 SRM=0x7 | OUTREG=XED_REG_DI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W + + + +############################# + +# GPR8_R and GPR8_B are handled in separate files -- grep for them. + +###########################a + +xed_reg_enum_t CR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_CR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x2 | OUTREG=XED_REG_CR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_CR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_CR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_CR8 +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +# FIXME: not used +xed_reg_enum_t CR_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_CR0 +REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x2 | OUTREG=XED_REG_CR2 +REXB=0 RM=0x3 | OUTREG=XED_REG_CR3 +REXB=0 RM=0x4 | OUTREG=XED_REG_CR4 +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_CR8 +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + +######################## + +xed_reg_enum_t DR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_DR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_DR1 +REXR=0 REG=0x2 | OUTREG=XED_REG_DR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_DR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_DR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_DR5 +REXR=0 REG=0x6 | OUTREG=XED_REG_DR6 +REXR=0 REG=0x7 | OUTREG=XED_REG_DR7 +REXR=1 REG=0x0 | OUTREG=XED_REG_DR8 +REXR=1 REG=0x1 | OUTREG=XED_REG_DR9 +REXR=1 REG=0x2 | OUTREG=XED_REG_DR10 +REXR=1 REG=0x3 | OUTREG=XED_REG_DR11 +REXR=1 REG=0x4 | OUTREG=XED_REG_DR12 +REXR=1 REG=0x5 | OUTREG=XED_REG_DR13 +REXR=1 REG=0x6 | OUTREG=XED_REG_DR14 +REXR=1 REG=0x7 | OUTREG=XED_REG_DR15 + +xed_reg_enum_t DR_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_DR0 +REXB=0 RM=0x1 | OUTREG=XED_REG_DR1 +REXB=0 RM=0x2 | OUTREG=XED_REG_DR2 +REXB=0 RM=0x3 | OUTREG=XED_REG_DR3 +REXB=0 RM=0x4 | OUTREG=XED_REG_DR4 +REXB=0 RM=0x5 | OUTREG=XED_REG_DR5 +REXB=0 RM=0x6 | OUTREG=XED_REG_DR6 +REXB=0 RM=0x7 | OUTREG=XED_REG_DR7 +REXB=1 RM=0x0 | OUTREG=XED_REG_DR8 +REXB=1 RM=0x1 | OUTREG=XED_REG_DR9 +REXB=1 RM=0x2 | OUTREG=XED_REG_DR10 +REXB=1 RM=0x3 | OUTREG=XED_REG_DR11 +REXB=1 RM=0x4 | OUTREG=XED_REG_DR12 +REXB=1 RM=0x5 | OUTREG=XED_REG_DR13 +REXB=1 RM=0x6 | OUTREG=XED_REG_DR14 +REXB=1 RM=0x7 | OUTREG=XED_REG_DR15 + +####################### + + +xed_reg_enum_t X87():: +RM=0x0 | OUTREG=XED_REG_ST0 +RM=0x1 | OUTREG=XED_REG_ST1 +RM=0x2 | OUTREG=XED_REG_ST2 +RM=0x3 | OUTREG=XED_REG_ST3 +RM=0x4 | OUTREG=XED_REG_ST4 +RM=0x5 | OUTREG=XED_REG_ST5 +RM=0x6 | OUTREG=XED_REG_ST6 +RM=0x7 | OUTREG=XED_REG_ST7 + +################### + +xed_reg_enum_t SEG():: +REG=0x0 | OUTREG=XED_REG_ES +REG=0x1 | OUTREG=XED_REG_CS +REG=0x2 | OUTREG=XED_REG_SS +REG=0x3 | OUTREG=XED_REG_DS +REG=0x4 | OUTREG=XED_REG_FS +REG=0x5 | OUTREG=XED_REG_GS +REG=0x6 | OUTREG=XED_REG_ERROR enc +REG=0x7 | OUTREG=XED_REG_ERROR + + +################################################### + +# We have two versions of FINAL_DSEG called FINAL_DSEG and +# FINAL_DSEG1. This is required because in the nonterminal function, I +# don't know if which memop (MEM0 or MEM1) the segment selector is +# being applied to. I set USING_DEFAULT_SEGMENT0 for MEM0 and +# USING_DEFAULT_SEGMENT1 for MEM1. + + +# These set USING_DEFAULT_SEGMENT0 + +xed_reg_enum_t FINAL_DSEG():: +mode16 | OUTREG=FINAL_DSEG_NOT64() +mode32 | OUTREG=FINAL_DSEG_NOT64() +mode64 | OUTREG=FINAL_DSEG_MODE64() + +xed_reg_enum_t FINAL_DSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=0 + +xed_reg_enum_t FINAL_DSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + + +# These set USING_DEFAULT_SEGMENT1 + +xed_reg_enum_t FINAL_DSEG1():: +mode16 | OUTREG=FINAL_DSEG1_NOT64() +mode32 | OUTREG=FINAL_DSEG1_NOT64() +mode64 | OUTREG=FINAL_DSEG1_MODE64() + +xed_reg_enum_t FINAL_DSEG1_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=0 + +xed_reg_enum_t FINAL_DSEG1_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + + + + + +################################################### + +# FINAL_ESEG is only called for STRING OPS and only specifies MEM0's SEG0. + +xed_reg_enum_t FINAL_ESEG():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +xed_reg_enum_t FINAL_ESEG1():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For synthesized stack operands (see generator.py) +xed_reg_enum_t FINAL_SSEG1():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For stack operands that cannot be overridden +xed_reg_enum_t FINAL_SSEG0():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +# This is only called for MODRM BYTEs and they only set MEM0's SEG0. + +xed_reg_enum_t FINAL_SSEG():: +mode16 | OUTREG=FINAL_SSEG_NOT64() +mode32 | OUTREG=FINAL_SSEG_NOT64() +mode64 | OUTREG=FINAL_SSEG_MODE64() + +xed_reg_enum_t FINAL_SSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 enc # default stack seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 # explicit ss seg + +xed_reg_enum_t FINAL_SSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + diff --git a/datafiles/xed-regs-enc.txt b/datafiles/xed-regs-enc.txt new file mode 100644 index 0000000..4ffa845 --- /dev/null +++ b/datafiles/xed-regs-enc.txt @@ -0,0 +1,87 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t SEGe():: +OUTREG=XED_REG_DS -> nothing +OUTREG=XED_REG_CS -> nothing +OUTREG=XED_REG_ES -> nothing +OUTREG=XED_REG_FS -> nothing +OUTREG=XED_REG_GS -> nothing +OUTREG=XED_REG_SS -> nothing + +xed_reg_enum_t GPR16e():: +OUTREG=XED_REG_AX -> nothing +OUTREG=XED_REG_BX -> nothing +OUTREG=XED_REG_CX -> nothing +OUTREG=XED_REG_DX -> nothing +OUTREG=XED_REG_SP -> nothing +OUTREG=XED_REG_BP -> nothing +OUTREG=XED_REG_SI -> nothing +OUTREG=XED_REG_DI -> nothing + + +xed_reg_enum_t GPR32e():: +mode32 OUTREG=GPR32e_m32() -> nothing +mode64 OUTREG=GPR32e_m64() -> nothing + + +xed_reg_enum_t GPR32e_m32():: +OUTREG=XED_REG_EAX -> nothing +OUTREG=XED_REG_EBX -> nothing +OUTREG=XED_REG_ECX -> nothing +OUTREG=XED_REG_EDX -> nothing +OUTREG=XED_REG_ESP -> nothing +OUTREG=XED_REG_EBP -> nothing +OUTREG=XED_REG_ESI -> nothing +OUTREG=XED_REG_EDI -> nothing + +xed_reg_enum_t GPR32e_m64():: +OUTREG=XED_REG_EAX -> nothing +OUTREG=XED_REG_EBX -> nothing +OUTREG=XED_REG_ECX -> nothing +OUTREG=XED_REG_EDX -> nothing +OUTREG=XED_REG_ESP -> nothing +OUTREG=XED_REG_EBP -> nothing +OUTREG=XED_REG_ESI -> nothing +OUTREG=XED_REG_EDI -> nothing +OUTREG=XED_REG_R8D -> nothing +OUTREG=XED_REG_R9D -> nothing +OUTREG=XED_REG_R10D -> nothing +OUTREG=XED_REG_R11D -> nothing +OUTREG=XED_REG_R12D -> nothing +OUTREG=XED_REG_R13D -> nothing +OUTREG=XED_REG_R14D -> nothing +OUTREG=XED_REG_R15D -> nothing + +xed_reg_enum_t GPR64e():: +OUTREG=XED_REG_RAX -> nothing +OUTREG=XED_REG_RBX -> nothing +OUTREG=XED_REG_RCX -> nothing +OUTREG=XED_REG_RDX -> nothing +OUTREG=XED_REG_RSP -> nothing +OUTREG=XED_REG_RBP -> nothing +OUTREG=XED_REG_RSI -> nothing +OUTREG=XED_REG_RDI -> nothing +OUTREG=XED_REG_R8 -> nothing +OUTREG=XED_REG_R9 -> nothing +OUTREG=XED_REG_R10 -> nothing +OUTREG=XED_REG_R11 -> nothing +OUTREG=XED_REG_R12 -> nothing +OUTREG=XED_REG_R13 -> nothing +OUTREG=XED_REG_R14 -> nothing +OUTREG=XED_REG_R15 -> nothing \ No newline at end of file diff --git a/datafiles/xed-regs-xmm.txt b/datafiles/xed-regs-xmm.txt new file mode 100644 index 0000000..f18fb0a --- /dev/null +++ b/datafiles/xed-regs-xmm.txt @@ -0,0 +1,38 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +XMM0 xmm 128 XMM0 0 +XMM1 xmm 128 XMM1 1 +XMM2 xmm 128 XMM2 2 +XMM3 xmm 128 XMM3 3 + +XMM4 xmm 128 XMM4 4 +XMM5 xmm 128 XMM5 5 +XMM6 xmm 128 XMM6 6 +XMM7 xmm 128 XMM7 7 + +XMM8 xmm 128 XMM8 8 +XMM9 xmm 128 XMM9 9 +XMM10 xmm 128 XMM10 10 +XMM11 xmm 128 XMM11 11 + +XMM12 xmm 128 XMM12 12 +XMM13 xmm 128 XMM13 13 +XMM14 xmm 128 XMM14 14 +XMM15 xmm 128 XMM15 15 diff --git a/datafiles/xed-regs.txt b/datafiles/xed-regs.txt new file mode 100644 index 0000000..749e885 --- /dev/null +++ b/datafiles/xed-regs.txt @@ -0,0 +1,230 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +############################################################################ +# file: xed-regs.txt +############################################################################ + +# h is for the "h" byte regs + +#name class width max-enclosing-reg-64b/32b-mode regid [h] +INVALID INVALID 0 +ERROR INVALID 0 # used to denote errors in lookup functions + +RAX gpr 64 RAX 0 +EAX gpr 32 RAX/EAX 0 +AX gpr 16 RAX/EAX 0 +AH gpr 8 RAX/EAX 4 h +AL gpr 8 RAX/EAX 0 + +RCX gpr 64 RCX 1 +ECX gpr 32 RCX/ECX 1 +CX gpr 16 RCX/ECX 1 +CH gpr 8 RCX/ECX 5 h +CL gpr 8 RCX/ECX 1 + +RDX gpr 64 RDX 2 +EDX gpr 32 RDX/EDX 2 +DX gpr 16 RDX/EDX 2 +DH gpr 8 RDX/EDX 6 h +DL gpr 8 RDX/EDX 2 + +RBX gpr 64 RBX 3 +EBX gpr 32 RBX/EBX 3 +BX gpr 16 RBX/EBX 3 +BH gpr 8 RBX/EBX 7 h +BL gpr 8 RBX/EBX 3 + +RSP gpr 64 RSP 4 +ESP gpr 32 RSP/ESP 4 +SP gpr 16 RSP/ESP 4 +SPL gpr 8 RSP/ESP 4 + +RBP gpr 64 RBP 5 +EBP gpr 32 RBP/EBP 5 +BP gpr 16 RBP/EBP 5 +BPL gpr 8 RBP/EBP 5 + +RSI gpr 64 RSI 6 +ESI gpr 32 RSI/ESI 6 +SI gpr 16 RSI/ESI 6 +SIL gpr 8 RSI/ESI 6 + +RDI gpr 64 RDI 7 +EDI gpr 32 RDI/EDI 7 +DI gpr 16 RDI/EDI 7 +DIL gpr 8 RDI/EDI 7 + + +R8 gpr 64 R8 8 +R8D gpr 32 R8/R8D 8 +R8W gpr 16 R8/R8D 8 +R8B gpr 8 R8/R8D 8 + +R9 gpr 64 R9 9 +R9D gpr 32 R9/R9D 9 +R9W gpr 16 R9/R9D 9 +R9B gpr 8 R9/R9D 9 + +R10 gpr 64 R10 10 +R10D gpr 32 R10/R10D 10 +R10W gpr 16 R10/R10D 10 +R10B gpr 8 R10/R10D 10 + +R11 gpr 64 R11 11 +R11D gpr 32 R11/R11D 11 +R11W gpr 16 R11/R11D 11 +R11B gpr 8 R11/R11D 11 + +R12 gpr 64 R12 12 +R12D gpr 32 R12/R12D 12 +R12W gpr 16 R12/R12D 12 +R12B gpr 8 R12/R12D 12 + +R13 gpr 64 R13 13 +R13D gpr 32 R13/R13D 13 +R13W gpr 16 R13/R13D 13 +R13B gpr 8 R13/R13D 13 + +R14 gpr 64 R14 14 +R14D gpr 32 R14/R14D 14 +R14W gpr 16 R14/R14D 14 +R14B gpr 8 R14/R14D 14 + +R15 gpr 64 R15 15 +R15D gpr 32 R15/R15D 15 +R15W gpr 16 R15/R15D 15 +R15B gpr 8 R15/R15D 15 + + +RIP ip 64 RIP +EIP ip 32 RIP/EIP +IP ip 16 RIP/EIP + +FLAGS flags 16 RFLAGS/EFLAGS +EFLAGS flags 32 RFLAGS/EFLAGS +RFLAGS flags 64 RFLAGS + +CS sr 16 CS +DS sr 16 DS +ES sr 16 ES +SS sr 16 SS +FS sr 16 FS +GS sr 16 GS + + + + +MMX0 mmx 64 MMX0 0 +MMX1 mmx 64 MMX1 1 +MMX2 mmx 64 MMX2 2 +MMX3 mmx 64 MMX3 3 + +MMX4 mmx 64 MMX4 4 +MMX5 mmx 64 MMX5 5 +MMX6 mmx 64 MMX6 6 +MMX7 mmx 64 MMX7 7 + + +ST0 x87 80 ST0 0 - st(0) +ST1 x87 80 ST1 1 - st(1) +ST2 x87 80 ST2 2 - st(2) +ST3 x87 80 ST3 3 - st(3) +ST4 x87 80 ST4 4 - st(4) +ST5 x87 80 ST5 5 - st(5) +ST6 x87 80 ST6 6 - st(6) +ST7 x87 80 ST7 7 - st(7) + +CR0 cr 32/64 CR0 0 +CR1 cr 32/64 CR1 1 +CR2 cr 32/64 CR2 2 +CR3 cr 32/64 CR3 3 +CR4 cr 32/64 CR4 4 +CR5 cr 32/64 CR5 5 +CR6 cr 32/64 CR6 6 +CR7 cr 32/64 CR7 7 +CR8 cr 32/64 CR8 8 +CR9 cr 32/64 CR9 9 +CR10 cr 32/64 CR10 10 +CR11 cr 32/64 CR11 11 +CR12 cr 32/64 CR12 12 +CR13 cr 32/64 CR13 13 +CR14 cr 32/64 CR14 14 +CR15 cr 32/64 CR15 15 + +DR0 dr 32/64 DR0 0 +DR1 dr 32/64 DR1 1 +DR2 dr 32/64 DR2 2 +DR3 dr 32/64 DR3 3 +DR4 dr 32/64 DR4 4 +DR5 dr 32/64 DR5 5 +DR6 dr 32/64 DR6 6 +DR7 dr 32/64 DR7 7 +DR8 dr 32/64 DR8 8 +DR9 dr 32/64 DR9 9 +DR10 dr 32/64 DR10 10 +DR11 dr 32/64 DR11 11 +DR12 dr 32/64 DR12 12 +DR13 dr 32/64 DR13 13 +DR14 dr 32/64 DR14 14 +DR15 dr 32/64 DR15 15 + +STACKPUSH pseudo NA +STACKPOP pseudo NA +GDTR pseudo 80 +LDTR pseudo 80 +IDTR pseudo 80 +TR pseudo 80 +TSC pseudo 32 +# TSC_AUX was added in 3.10 version of AMD's manual +TSCAUX pseudo 32 +MSRS pseudo NA + +X87CONTROL pseudox87 16 +X87STATUS pseudox87 16 # includes TOP field for x87 stack +X87TAG pseudox87 16 +X87PUSH pseudox87 NA +X87POP pseudox87 NA +X87POP2 pseudox87 NA + +X87OPCODE pseudox87 11 # These 5 are not used by XED +X87LASTCS pseudox87 16 +X87LASTIP pseudox87 32/64 # 16b mode is wrong +X87LASTDS pseudox87 16 +X87LASTDP pseudox87 32/64 # 16b mode is wrong + +XCR0 xcr 64 # previously known as XFEM + +MXCSR mxcsr 32 + +# Some dummy registers for someone to play with if they ever want to +TMP0 tmp NA TMP0 0 +TMP1 tmp NA TMP1 1 +TMP2 tmp NA TMP2 2 +TMP3 tmp NA TMP3 3 +TMP4 tmp NA TMP4 4 +TMP5 tmp NA TMP5 5 +TMP6 tmp NA TMP6 6 +TMP7 tmp NA TMP7 7 +TMP8 tmp NA TMP8 8 +TMP9 tmp NA TMP9 9 +TMP10 tmp NA TMP10 10 +TMP11 tmp NA TMP11 11 +TMP12 tmp NA TMP12 12 +TMP13 tmp NA TMP13 13 +TMP14 tmp NA TMP14 14 +TMP15 tmp NA TMP15 15 diff --git a/datafiles/xed-spine.txt b/datafiles/xed-spine.txt new file mode 100644 index 0000000..04b13bb --- /dev/null +++ b/datafiles/xed-spine.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ISA():: +PREFIXES() OSZ_NONTERM() ASZ_NONTERM() INSTRUCTIONS() | diff --git a/datafiles/xed-state-bits.txt b/datafiles/xed-state-bits.txt new file mode 100644 index 0000000..ec07f28 --- /dev/null +++ b/datafiles/xed-state-bits.txt @@ -0,0 +1,127 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-state-bits.txt +########################################################################### + +# These are just shorthand for some conditions or captures. +# Simple macro replacement +#all_modes ALL_MODES=1 +not64 MODE!=2 +mode64 MODE=2 +mode32 MODE=1 +mode16 MODE=0 + +# effective addressing mode +eanot16 EASZ!=1 +eamode16 EASZ=1 +eamode32 EASZ=2 +eamode64 EASZ=3 + +# stack addressing mode +smode16 SMODE=0 +smode32 SMODE=1 +smode64 SMODE=2 + +eosz8 EOSZ=0 +eosz16 EOSZ=1 +not_eosz16 EOSZ!=1 +eosz32 EOSZ=2 +eosz64 EOSZ=3 +eosznot64 EOSZ!=3 + + +# for OD expansion in graph partitioning FIXME +mod0 MOD=0 +mod1 MOD=1 +mod2 MOD=2 +mod3 MOD=3 + +rex_reqd REX=1 +no_rex REX=0 +reset_rex REX=0 REXW=0 REXB=0 REXR=0 REXX=0 + +rexb_prefix REXB=1 +rexx_prefix REXX=1 +rexr_prefix REXR=1 + +# 2013-09-25 FIXME: we were inconsistent. some things use W0/W1, some +# use the more verbose form. We should converge on W0/W1. +# +rexw_prefix REXW=1 SKIP_OSZ=1 +norexw_prefix REXW=0 SKIP_OSZ=1 +W1 REXW=1 SKIP_OSZ=1 +W0 REXW=0 SKIP_OSZ=1 + +norexb_prefix REXB=0 +norexx_prefix REXX=0 +norexr_prefix REXR=0 +############################################################3333 +f2_prefix REP=2 # REPNZ, REPNE +f3_prefix REP=3 # REPZ, REPNZ +repne REP=2 +repe REP=3 +norep REP=0 +66_prefix OSZ=1 +nof3_prefix REP!=3 +no66_prefix OSZ=0 +not_refining REP=0 # dummy setting for state values 2007-08-06 FIXME +refining_f2 REP=2 +refining_f3 REP=3 +not_refining_f3 REP!=3 # for pause vs xchg +no_refining_prefix REP=0 OSZ=0 # critical:REP must be first for decoding partitioning +osz_refining_prefix REP=0 OSZ=1 +f2_refining_prefix REP=2 +f3_refining_prefix REP=3 + +no67_prefix ASZ=0 +67_prefix ASZ=1 + +lock_prefix LOCK=1 +nolock_prefix LOCK=0 + +default_ds DEFAULT_SEG=0 +default_ss DEFAULT_SEG=1 +default_es DEFAULT_SEG=2 # for string ops +no_seg_prefix SEG_OVD=0 +some_seg_prefix SEG_OVD!=0 +cs_prefix SEG_OVD=1 +ds_prefix SEG_OVD=2 +es_prefix SEG_OVD=3 +fs_prefix SEG_OVD=4 +gs_prefix SEG_OVD=5 +ss_prefix SEG_OVD=6 + +# default (or not) to 64b width in 64b mode +nrmw DF64=0 +df64 DF64=1 + +# default choice for encoder when there are multiple choices for a +# nonterminal. The ISA is not uniquely determined for encoding so we +# must express preferences for certain forms! +enc ENCODER_PREFERRED=1 + +# for the legacy prefix encoder, tell it to keep trying rules and not +# return after successfully finding one that applies +no_return NO_RETURN=1 + +# indicate an encoding or decoding error occurred +error ERROR=XED_ERROR_GENERAL_ERROR + +# dummy constraint which always satisfies +true DUMMY=0 diff --git a/datafiles/xed-syntax-enum.txt b/datafiles/xed-syntax-enum.txt new file mode 100644 index 0000000..2b73938 --- /dev/null +++ b/datafiles/xed-syntax-enum.txt @@ -0,0 +1,31 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-syntax-enum.h +cfn xed-syntax-enum.c +prefix XED_SYNTAX_ +typename xed_syntax_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +XED ///< XED disassembly syntax +ATT ///< ATT SYSV disassembly syntax +INTEL ///< Intel disassembly syntax + + diff --git a/datafiles/xsavec/cpuid.xed.txt b/datafiles/xsavec/cpuid.xed.txt new file mode 100644 index 0000000..c35ac7b --- /dev/null +++ b/datafiles/xsavec/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVEC: xsavec.d.1.eax.1 diff --git a/datafiles/xsavec/files.cfg b/datafiles/xsavec/files.cfg new file mode 100644 index 0000000..ff35e20 --- /dev/null +++ b/datafiles/xsavec/files.cfg @@ -0,0 +1,25 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + dec-instructions: xsavec-isa.txt + enc-instructions: xsavec-isa.txt + + + cpuid: cpuid.xed.txt + diff --git a/datafiles/xsavec/xsavec-isa.txt b/datafiles/xsavec/xsavec-isa.txt new file mode 100644 index 0000000..00302df --- /dev/null +++ b/datafiles/xsavec/xsavec-isa.txt @@ -0,0 +1,44 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEC +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : variable length store +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +{ +ICLASS : XSAVEC64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : variable length store +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + diff --git a/datafiles/xsaveopt/cpuid.xed.txt b/datafiles/xsaveopt/cpuid.xed.txt new file mode 100644 index 0000000..8359adc --- /dev/null +++ b/datafiles/xsaveopt/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVEOPT: xsaveopt.d.1.eax.0 diff --git a/datafiles/xsaveopt/files.cfg b/datafiles/xsaveopt/files.cfg new file mode 100644 index 0000000..05542f3 --- /dev/null +++ b/datafiles/xsaveopt/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions:xsaveopt-isa.txt + enc-instructions:xsaveopt-isa.txt + + + cpuid: cpuid.xed.txt + diff --git a/datafiles/xsaveopt/xsaveopt-isa.txt b/datafiles/xsaveopt/xsaveopt-isa.txt new file mode 100644 index 0000000..dc73c5b --- /dev/null +++ b/datafiles/xsaveopt/xsaveopt-isa.txt @@ -0,0 +1,43 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEOPT +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVEOPT64 +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX + +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + diff --git a/datafiles/xsaves/cpuid.xed.txt b/datafiles/xsaves/cpuid.xed.txt new file mode 100644 index 0000000..b95eca4 --- /dev/null +++ b/datafiles/xsaves/cpuid.xed.txt @@ -0,0 +1,18 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVES: xsaves.d.1.eax.3 diff --git a/datafiles/xsaves/files.cfg b/datafiles/xsaves/files.cfg new file mode 100644 index 0000000..a295f54 --- /dev/null +++ b/datafiles/xsaves/files.cfg @@ -0,0 +1,25 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + dec-instructions: xsaves-isa.txt + enc-instructions: xsaves-isa.txt + + + + cpuid: cpuid.xed.txt + diff --git a/datafiles/xsaves/xsaves-isa.txt b/datafiles/xsaves/xsaves-isa.txt new file mode 100644 index 0000000..1eba853 --- /dev/null +++ b/datafiles/xsaves/xsaves-isa.txt @@ -0,0 +1,69 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVES +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVES64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +{ +ICLASS : XRSTORS +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XRSTORS64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditianal reg write +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + diff --git a/docsrc/Doxyfile b/docsrc/Doxyfile new file mode 100644 index 0000000..f3853ef --- /dev/null +++ b/docsrc/Doxyfile @@ -0,0 +1,1081 @@ +# Doxyfile 1.3.6 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = "X86 Encoder Decoder" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = $(XED_GENDOC) + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, +# Finnish, French, German, Greek, Hungarian, Italian, Japanese, Japanese-en +# (Japanese with English messages), Korean, Korean-en, Norwegian, Polish, Portuguese, +# Romanian, Russian, Serbian, Slovak, Slovene, Spanish, Swedish, and Ukrainian. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is used +# as the annotated text. Otherwise, the brief description is used as-is. If left +# blank, the following values are used ("$name" is automatically replaced with the +# name of the entity): "The $name class" "The $name widget" "The $name file" +# "is" "provides" "specifies" "contains" "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited +# members of a class in the documentation of that class as if those members were +# ordinary class members. Constructors, destructors and assignment operators of +# the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = NO + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. It is allowed to use relative paths in the argument list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = YES + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +#DETAILS_AT_TOP = YES + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 8 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = YES + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = YES + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = YES + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = $(XED_KITDIR)/include $(XED_INPUT_TOP) + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp +# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc + +FILE_PATTERNS = *.C *.H *.h *.cpp *.hh *.c + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories +# that are symbolic links (a Unix filesystem feature) are excluded from the input. + +EXCLUDE_SYMLINKS = YES + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. + +EXCLUDE_PATTERNS = *init.cpp *.cpp *.c + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = $(XED_KITDIR)/examples + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = *.cpp *.c + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. + +INPUT_FILTER = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES (the default) +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES (the default) +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 1 + +# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be +# generated containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. + +GENERATE_TREEVIEW = YES + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = pdflatex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = letter + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_PREDEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse the +# parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = $(XED_GENDOC)/xed.tag + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or +# super classes. Setting the tag to NO turns the diagrams off. Note that this +# option is superseded by the HAVE_DOT option below. This is only a fallback. It is +# recommended to install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found on the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes that +# lay further from the root node will be omitted. Note that setting this option to +# 1 or 2 may greatly reduce the computation time needed for large code bases. Also +# note that a graph may be further truncated if the graph's image dimensions are +# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT). +# If 0 is used for the depth value (the default), the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. If set to NO the values of all tags below this one will be ignored. + +# See: http://www.stack.nl/~dimitri/doxygen/manual/searching.html +# set up for client searching... only works for symbols though. +SEARCHENGINE = YES +SERVER_BASED_SEARCH = NO + +OPTIMIZE_OUTPUT_FOR_C = YES diff --git a/docsrc/Doxyfile.build b/docsrc/Doxyfile.build new file mode 100644 index 0000000..661f7ee --- /dev/null +++ b/docsrc/Doxyfile.build @@ -0,0 +1,1075 @@ +# Doxyfile 1.3.6 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = XED-BUILD + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = $(XED_GENDOC) + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, +# Finnish, French, German, Greek, Hungarian, Italian, Japanese, Japanese-en +# (Japanese with English messages), Korean, Korean-en, Norwegian, Polish, Portuguese, +# Romanian, Russian, Serbian, Slovak, Slovene, Spanish, Swedish, and Ukrainian. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is used +# as the annotated text. Otherwise, the brief description is used as-is. If left +# blank, the following values are used ("$name" is automatically replaced with the +# name of the entity): "The $name class" "The $name widget" "The $name file" +# "is" "provides" "specifies" "contains" "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited +# members of a class in the documentation of that class as if those members were +# ordinary class members. Constructors, destructors and assignment operators of +# the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = NO + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. It is allowed to use relative paths in the argument list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = YES + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +#DETAILS_AT_TOP = YES + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 8 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = YES + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = YES + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = EXTERNAL + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = YES + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = $(XED_TOPSRCDIR)/docsrc/xed-build.txt + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp +# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc + +FILE_PATTERNS = *.C *.H *.cpp *.hh + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories +# that are symbolic links (a Unix filesystem feature) are excluded from the input. + +EXCLUDE_SYMLINKS = YES + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. + +EXCLUDE_PATTERNS = *.cpp *.c *.H *.h + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = . $(XED_TOPSRCDIR)/examples + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = *.cpp + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. + +INPUT_FILTER = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES (the default) +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES (the default) +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 1 + +# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be +# generated containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_PREDEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse the +# parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or +# super classes. Setting the tag to NO turns the diagrams off. Note that this +# option is superseded by the HAVE_DOT option below. This is only a fallback. It is +# recommended to install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found on the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes that +# lay further from the root node will be omitted. Note that setting this option to +# 1 or 2 may greatly reduce the computation time needed for large code bases. Also +# note that a graph may be further truncated if the graph's image dimensions are +# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT). +# If 0 is used for the depth value (the default), the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. If set to NO the values of all tags below this one will be ignored. + +SEARCHENGINE = NO diff --git a/docsrc/external-requirements.txt b/docsrc/external-requirements.txt new file mode 100644 index 0000000..25cdbec --- /dev/null +++ b/docsrc/external-requirements.txt @@ -0,0 +1,13 @@ + +On linux: + + +memcmp +memset +memcpy +strcmp +strncat +strlen +stderr -- variable used by printf during abort +fprintf -- optional -- only for abort msg +abort -- for xed's internal assert diff --git a/docsrc/xed-build.txt b/docsrc/xed-build.txt new file mode 100644 index 0000000..2321e08 --- /dev/null +++ b/docsrc/xed-build.txt @@ -0,0 +1,402 @@ +#BEGIN_LEGAL +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#END_LEGAL +// +// This file does not contain any code +// it just contains additional information for +// inclusion with doxygen + + +// ======================================================================================== +/*! +@mainpage XED Build Guide +by Mark Charney + +2016-12-14 + +@section INTRO Introduction + +XED can build with many compilers: + - GNU Gcc + - Microsoft Visual Studio + - Intel ICL/ICC + - LLVM/Clang + +XED also works with the following operating systems: + - Linux + - Microsoft Windows (with or without cygwin) + - Apple Mac OS/X + - FreeBSD + +The default compiler on Linux and FreeBSD is GNU gcc. The default on +Windows is to use MSVS. The default compiler on OS X is clang. + + +The build system uses the compilers from your PATH by default. You can +override this with various command line options. + + +Table of Contents + - @ref REPOS "REPOS" Repository access + - @ref MBUILD "MBUILD" Using mbuild to build XED + - @ref INSTALL "INSTALL" Making XED kits + - @ref WINDOWS "WINDOWS" Windows notes + - @ref SHARED "SHARED" Shared libraries and DLLs + - @ref HELP "HELP" The mbuild options + +@section REPOS Repository Access + +XED is stored in an GIT repository. Request access from +me if you want to build XED. + +It is a good idea to set up an ssh-agent and cache your private keys +so you do not have to repeatedly type your ssh passphrase when doing the +git clone operations. + +Here's how to check out XED and mbuild, as sibling directories: + +@if (EXTERNAL) +@code +git clone https://github.com/intelxed/xed.git xed +git clone https://github.com/intelxed/mbuild.git mbuild +@endcode +@else +@code +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-xed xed +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-mbuild mbuild +@endcode +@endif + + +If you are working in a directory called foo, then after the clones, +your trees should look like this: +@code + |-mbuild-|-mbuild---- + foo-| |-tests----- + | + |-xed----|-datafiles-|-avx-------- + | |-avxivb----- + | |-avxhsw----- + |-docsrc---- + |-enumer.d-- + |-examples-- + | + |-include---|-private---- + | |-public----- + |-misc------ + |-scripts--- + | + |-tests-----|-test-00000- + | |-test-00001- + + ... + + | |-test-00147- + |-use------- +@endcode + + +@section MBUILD Introduction to using mbuild + +Mbuild is a python-based build system. For more information about mbuild see: +https://intelxed.github.io (or inside Intel http://mjc.intel.com/mjcharne/mbuild ). + +The XED build using mbuild is dependence driven It uses file and +command signatures to detect the need to rebuild files. + +The mbuild script requires python version 2.7 or later. + +Assuming you checked out the tree as described above, you can build +XED using mbuild as follows on linux: +@code +mkdir build +cd build +../xed/mfile.py +../xed/mfile.py examples (optional) +../xed/mfile.py doc (optional, requires doxygen) +../xed/mfile.py doc-build (optional, requires doxygen) +../xed/mfile.py install (optional) +../xed/mfile.py install zip (optional, makes a zip file) +../xed/mfile.py examples install zip (optional, makes a zip file that includes the examples) +@endcode + +Actual windows example (password prompts omitted): + +@if (EXTERNAL) +@code +git clone https://github.com/intelxed/xed.git xed +git clone https://github.com/intelxed/mbuild.git mbuild +mkdir test +cd test +C:/Python27/python ../xed/mfile.py examples install zip +@endcode +@else +@code +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-xed xed +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-mbuild mbuild +mkdir test +cd test +C:/Python27/python ../xed/mfile.py examples install zip +@endcode +@endif + +For more information on building for windows see section @ref WINDOWS + +Actual linux example (password prompts omitted): + +@if (EXTERNAL) +@code +git clone https://github.com/intelxed/xed.git xed +git clone https://github.com/intelxed/mbuild.git mbuild +mkdir test +cd test +python ../xed/mfile.py examples install zip +@endcode +@else +@code +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-xed xed +git clone ssh://git-ger-3.devtools.intel.com:29418/ssgsde-mbuild mbuild +mkdir test +cd test +python ../xed/mfile.py examples install zip +@endcode +@endif + +To build 32b on a 64b platform, add to the mfile.py execution "host_cpu=ia32": +@code +C:/Python27/python ../xed/mfile.py examples install zip host_cpu=ia32 +@endcode + +@section INSTALL Making XED kits + +Some of the headers are private (for building XED), some are public +and some are generated. To simplify use, I recommend that all users +work from XED kits, rather from the XED sources. This section +describes how to build XED kits using the "install" target. + +The install target collects up all pieces and puts them in one +subdirectory. The static public headers and dynamically generated +public header files are put in an "include" subdirectory. + +Static libraries are put the "lib" directory. If you are doing a +shared object or DLL build, the shared object or DLL is put in the bin +directory. This simplifies using the examples. + +The manual and examples, if generated, are also included in doc +directory. + +The structure of a XED kit is as follows: + @code + |-bin------ + |-doc------|-html- + |-examples- + |-xed-kit-name--|-include-- + |-lib------ + |-misc----- + @endcode + + +You can also combine the various targets in one invocation. It will be +quicker than the sequence of commands. +@code +../xed/mfile.py doc doc-build examples install +@endcode + + +@section WINDOWS Windows notes + + +For building on windows, the easiest build method assumes that you've +configured your environment by running the appropriate BAT file, such +as vcvars32.bat or vcvarsamd64.bat from the bin directory of your MSVS +installation, by opening a Visual Studio command prompt or by having +installed the compiler environment in to the default environment +during MSVS installation. + + +On windows you can build from a cmd.exe or a cygwin window, with MSVS or GNU gcc. +@code +/* Run the Visual Studio setup script (vcvars32.bat or vcvarsamd64.bat) from your compiler installation */ +C:/Python27/python ../xed/mfile.py examples ( from a cmd.exe window using win32 python) + +/* or from cygwin, using MSVS, you must ensure your MSVS compiler environment is set up properly */ +../xed/mfile.py examples ( from a cygwin window, using cygwin's python) + +/* if you installed the compiler in a standard place, you can have MBUILD set it up*/ +C:/Python27/python ../xed/mfile.py --setup-msvs --msvs-version 10 examples + +/* or from cygwin, using GCC */ +../xed/mfile.py --compiler=gnu examples ( from a cygwin window, using cygwin's gcc) +@endcode + +The cygwin builds will use cygwin's python to launch the mfile, but +win32 c:/Python27/python to run the generators. I try to avoid +building using cygwin's python because those builds are single +threaded because of long standing bugs in cygwin. + +If you want to have symbols in the xed command line example, you must +build with MSVS 8 (2005) or later and supply the "--dbghelp" option to +the build line. During execution, dbghelp.dll version 6.9.3.113 or +later, is required. Dbghelp.dll must be placed in the same directory +as xed.exe. Dbghelp.dll is available from Microsoft. + + +@section SHARED Shared libraries and DLLs + +If you build XED using the \-\-shared object you'll get a libxed.so on +Linux or a libxed.dll on Windows. When you link against these shared +objects/DLL you are required to define XED_DLL (/DXED_DLL on Windows +or -DXED_DLL on Linux). + +@section HELP The mbuild options + + +If you supply the \-\-help message to the ../xed/mfile.py you'll +see the various options controlling compilation. Some options are +build into to mbuild and are not relevant for the XED0 build (like the +assembler overrides). I've omitted the irrelevant ones in the +following options listing: + +@code +% ./mfile.py --help +Usage: mfile.py [options] + +Options: + -h, --help show this help message and exit + -j JOBS, --jobs=JOBS Number of concurrent worker threads to use. + --mbuild-version Emit the version information + --build-dir=BUILD_DIR + Build directory, default is 'obj' + --src-dir=SRC_DIR The directory where the sources are located. + --gen-dir=GEN_DIR The directory where generated sources are assumed to + be located. + -v VERBOSE, --verbose=VERBOSE + Verbosity level. Defaults to value passed to env_t() + --compiler=COMPILER Compiler (ms,gnu,clang,icc,icl,iclang). Default is gnu + on linux and ms on windows. Default is: gnu + --debug Debug build + --shared Shared DLL build + --static Statically link executables + --opt=OPT Optimization level noopt, 0, 1, 2, 3 + -s, --silent Silence all but the most important messages + --extra-defines=EXTRA_DEFINES + Extra preprocessor defines + --extra-flags=EXTRA_FLAGS + Extra values for CXXFLAGS and CCFLAGS + --extra-cxxflags=EXTRA_CXXFLAGS + Extra values for CXXFLAGS + --extra-ccflags=EXTRA_CCFLAGS + Extra values for CCFLAGS + --extra-linkflags=EXTRA_LINKFLAGS + Extra values for LINKFLAGS + --extra-libs=EXTRA_LIBS + Extra values for LIBS + --toolchain=TOOLCHAIN + Compiler toolchain + --vc-dir=VC_DIR MSVS Compiler VC directory. For finding libraries and + setting the toolchain + --msvs-version=MSVS_VERSION, --msvc-version=MSVS_VERSION, --msvsversion=MSVS_VERSION, --msvcversion=MSVS_VERSION + MSVS version 6=VC98, 7=VS .Net 2003, 8=VS 2005, 9=VS + 2008, 10=VS 2010/DEV10, 11=VS2012/DEV11This sets + certain flags and idioms for quirks in some compilers. + --setup-msvc, --setup-msvs, --msvs-setup, --msvc-setup + Use the value of the --msvc-version to initialize the + MSVC configuration. + --icc-version=ICC_VERSION, --iccver=ICC_VERSION, --icc-ver=ICC_VERSION + ICC/ICL version 7, 8, 9, 10, 11 + --gcc-version=GCC_VERSION, --gccversion=GCC_VERSION, --gcc-ver=GCC_VERSION + GCC version, with dots as in 2.96, 3.4.3, 4.2.0, etc. + --cc=CC full path to C compiler + --cxx=CXX full path to C++ compiler + --linker=LINKER full path to linker + --ar=AR full path to archiver (lib/ar) + --as=AS full path to assembler (gas/as/ml/ml64) + --yasm Use yasm + --no-cygwin-limit Do not limit cygwin to one job at a time. Default is + to limit cygwin to one job. + --host-cpu=ARG_HOST_CPU + Host CPU, typically ia32, intel64 or x86-64 + --host-os=ARG_HOST_OS + Host OS (where the binary runs) + --doxygen-install=DOXYGEN_INSTALL + Doxygen installation directory + --doxygen=DOXYGEN Doxygen command name + -c, --clean Clean targets + -k, --keep-going Keep going after errors occur when building + --messages Enable use xed's debug messages + --asserts Enable use xed's asserts + --clr Compile for Microsoft CLR + --no-werror Disable use of -Werror on GNU compiles + --gen-ild-storage Dump ILD storage data file. + --show-dag Show the dependence DAG + --ext=EXT Add extension files of the form + pattern-name:file-name.txt + --extf=EXTF Add extension configuration files that contain + lines of form pattern-name:file-name.txt. All files + references will be made relative to the directory in + which the config file is located + --default-isa-extf=DEFAULT_ISA + Override the default ISA files.cfg file + --knc Include KNC support + --no-avx Do not include AVX + --no-xsaveopt Do not include XSAVEOPT + --no-ivbavx Do not include AVX for IVB. + --no-ivbint Do not include integer (nonAVX) IVB NI. + --no-avxhsw Do not include AVX for HSW. + --no-mpx Do not include MPX. + --no-sha Do not include SHA. + --no-bdw Do not include BDW NI. + --no-glm Do not include GLM. + --knl Include KNL AVX512{PF,ER} on top of AVX512{F,CD}. + Default: Currently enabled. + --no-knl Do no include KNL AVX512{PF,ER}. Default: KNL enabled. + --no-skl Do not include SKL. + --no-skx Do not include SKX. + --no-memory-future Do not include future memory NI. + --no-avx512-future Do not include future avx512 instructions. + --dbghelp Use dbghelp.dll on windows. + --install-dir=INSTALL_DIR + XED Install directory. + Default: kits/xed-install-date-os-cpu + --kit-kind=KIT_KIND Kit version string. + The default is 'base' + --no-amd Disable AMD public instructions + --limit-strings Remove some strings to save space. + --no-encoder Disable the encoder + --no-decoder Disable the decoder + --generator-options=GENERATOR_OPTIONS + Options to pass through for + the decode generator + --legal-header=LEGAL_HEADER + Use this special legal header + on public header files and examples. + --python=PYTHONARG Use a specific version of python + for subprocesses. + --elf-dwarf, --dwarf Use libelf/libdwarf. (Linux only) + --dev Developer knob. Updates VERISON file + --elf-dwarf-precompiled + Use precompiled libelf/libdwarf from the XED source + distribution. This is the currently required if you + are installing a kit. Implies the --elf-dwarf knob. + (Linux only) + --strip=STRIP Path to strip binary. (Linux only) + --pti-test INTERNAL TESTING OPTION. + --compress-operands use bit-fields to compress the operand storage. + --test-perf Do performance test (on linux). Requires specific + external test binary. +@endcode + + +*/ diff --git a/docsrc/xed-doc-top.txt b/docsrc/xed-doc-top.txt new file mode 100644 index 0000000..441bc80 --- /dev/null +++ b/docsrc/xed-doc-top.txt @@ -0,0 +1,1207 @@ +#BEGIN_LEGAL +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#END_LEGAL + +// This file does not contain any code +// it just contains additional information for +// inclusion with doxygen + + +// =========================================================================== +/*! +@mainpage X86 Encoder Decoder User Guide +by Mark Charney + +2016-02-02 + +@section INTRO Introduction + + +XED is an acronym for X86 Encoder Decoder. The +latter part is pronounced like the (British) English "z". + +Intel XED is a software library (and associated headers) written in C +for encoding and decoding X86 (IA-32 instruction set and Intel® 64 +instruction set) instructions. The decoder takes sequences of 1-15 +bytes along with machine mode information and produces a data +structure describing the opcode and operands, and flags. The encoder +takes a similar data structure and produces a sequence of 1 to 15 +bytes. Intel XED is multi-thread safe. + +Intel XED was designed to be very fast and extensible. + +Intel XED compiles with the following compilers: +
    +
  • GNU Gcc +
  • Microsoft Visual Studio +
  • Intel ICL/ICC +
  • LLVM/Clang +
+ + +Intel XED works with the following operating systems: +
    +
  • Linux +
  • Microsoft Windows (with and without cygwin) +
  • Apple Mac OS X* +
  • FreeBSD +
+ +The Intel XED examples (@ref EXAMPLES) also include binary image readers for +Windows PECOFF, ELF and Mac OS X* MACHO binary file formats for 32b and +64b. These allow Intel XED to be used as a simple (not symbolic) +disassembler. The Intel XED disassembler supports 3 output formats: Intel, +ATT SYSV, and a more detailed internal format describing all resources +read and written. + + +@section TOC Table of Contents + - @ref BUILD "Building" Building your program with Intel XED + - @ref EXTERN "External" External Requirements + - @ref TERMS "Terms" Terminology + - @ref OVERVIEW "Overview" Overview of the Intel XED approach + - @ref API_REF "API reference" Detailed descriptions of the API + - @ref EXAMPLES "Examples" Examples + - @ref LEGAL "Disclaimer and Legal Information" + + +@section BUILD Building your program using Intel XED. + +This section describes the requirements for compiling with Intel XED and +linking the libxed.a library. It assumes you are building from a +Intel XED kit, and not directly from the sources. (See the "install" +option in the Intel XED build manual for information on making kits). + +The structure of a Intel XED kit is as follows: +@code + + |-bin------ + |-doc------|-html- + |-examples- + |-xed-kit-name-|-include-- + |-lib------ + |-misc----- +@endcode + + +To use Intel XED your sources should include the top-most header file: xed-interface.h. + +Your compilation statement must include: +@code +-Ixed-kit-name/include +@endcode +where "xed-kit-name" is the place you've unpacked the Intel XED kit. + +Your Linux or Mac OS X* link statement must reference the libxed library: +@code +-lxed-kit-name/lib/libxed.a +@endcode + +(or link against libxed.lib for Windows). + +Intel XED uses base types with the following names: xed_uint8_t, +xed_uint16_t, xed_uint32_t, xed_uint64_t xed_int8_t, xed_int16_t, +xed_int32_t, and xed_int64_t. Intel XED also defines a "xed_uint_t" type +that is shorthand for "unsigned int". + + +Please see the section @ref INIT for more information about using +Intel XED, and also the examples in @ref EXAMPLES. + +@section EXTERN External Requirements + +Intel XED was designed to have minimal external requirements. Intel XED makes no +system calls. Intel XED allocates no memory. (The examples are +different). The following external functions/symbols are required for +linking a program with libxed, with one caveat: The functions fprint +and abort and the data object stderr are optional. If users register +their own abort handler using #xed_register_abort_function () , then +fprintf, stderr and abort are not required and can be stubbed out to +satisfy the linker. + +Required: +
    +
  • memcmp +
  • memcpy +
  • memset +
  • strcmp +
  • strlen +
  • strncat +
+ +Optional: +
    +
  • abort +
  • fprintf +
  • stderr +
+ +@section TERMS Terminology + + +X86 instructions are 1-15 byte values. They consist of several well +defined components: +
    +
  • Prefix bytes. +
      +
    • Legacy prefix bytes used for many purposes (described further below). + +
    • REX prefix byte but only in 64b mode. It has 4 1-bit + fields: W, R, X, and B. The W bit modifies the operation + width. The R, X and B fields extend the register + encodings. The REX byte must be right before the opcode + bytes else it is ignored. + +
    • VEX prefix byte sequence. The VEX prefix is used + mostly for AVX1 and AVX2 instructions as well as BMI1/2 + instructions and mask operations in Intel® AVX512. The VEX prefix + comes in two forms. The 2-byte sequence begins with an + 0xC5 byte. The 3-byte sequence begins with an 0xC4 byte. + +
    • EVEX prefix. The EVEX 3-byte sequence used for + encoding Intel AVX512 instructions and begins with an 0x62 byte. + +
    + + There are somewhat complex rules about which prefixes are + allowed, in what order, and in what modes. Intel XED handles that + complexity. + +
  • 1-3 opcode bytes. When more than one opcode byte is required + the leading bytes (called escapes) are either 0x0F, 0x0F 0x38 or + 0x0F 0x3A. With VEX and EVEX prefixes, the escape bytes are + encoded differently. + +
  • MODRM byte. Used for addressing memory, refining opcodes, + specifying registers. Optional, but common. It has 3 fields: the + 2-bit "mod", the 3-bit "reg" and 3-bit "r/m" fields. + +
  • SIB byte. Used for specifying memory addressing, optional. + It has 3 fields: the 2-bit scale, 3-bit index and 3-bit base. + +
  • Displacement bytes. Used for specifying memory offsets, optional. +
  • Immediate bytes. Optional +
+ + +Immediates and displacements are usually limited to 4 bytes, but there +are several variants of the MOV instruction that can take 8B +values. The AMD 3DNow ISA extension uses the immediate field to +provide additional opcode information. + +The legacy prefix bytes are used for: +
    +
  • operand size overrides (1 prefix), +
  • address size overrides (1 prefix), +
  • atomic locking (1 prefix), +
  • default segment overrides (6 prefixes), +
  • repeating certain instructions (2 prefixes), and +
  • opcode refinement. +
+ +There are 11 distinct legacy prefixes. Three of them (operand size, +and the two repeat prefixes) have different meanings in different +contexts; Sometimes they are used for opcode refinement and do not +have their default meaning. Less frequently. two of the segment +overrides can be used for conditional branch hints. + +There are also multiple ways to encode certain instructions, with the +same or differing length. + +For additional information on the instruction semantics and encodings: + + + + +@section OVERVIEW Overview of XED approach + +XED has two fundamental interfaces: encoding and decoding. Supporting +these interfaces are many data structures, but the two starting points +are the #xed_encoder_request_t and the #xed_decoded_inst_t . The +#xed_decoded_inst_t has more information than the +#xed_encoder_request_t , but both types are derived from a set of +common fields called the #xed_operand_values_t. + +The output of the decoder, the #xed_decoded_inst_t , includes additional +information that is not required for encoding, but provides more +information about the instruction resources. + +The common operand fields, used by both the encoder and decoder, hold +the operands and the memory addressing information. + + +The decoder has an operands array that holds order of the decoded +operands. This array indicates whether or not the operands are read or +written. + +The encoder has an operand array where the encoder user must specify +the order of the operands used for encoding. + +// =========================================================================== +@section ICLASS Instruction classes + +The #xed_iclass_enum_t class describes the instruction names. The +names are (mostly) taken from the Intel manual, with exceptions only +for certain ambiguities. This is what is typically thought of as the +instruction mnemonic. Note, Intel XED does not typically distinguish +instructions based on width unless the ISA manuals do so as well. For +example, #xed_iclass_enum_t's are not suffixed with "w", "l" or "q" +typically. There are instructions whose #xed_iclass_enum_t ends in a +"B" or a "Q" (including all byte operations and certain string +operations) and those names are preserved as described in the Intel +programmers' reference manuals. + + + + +@subsection SPECIAL Special Cases + +There are many special cases that must be accounted for in attempting +to handle all the nuances of the ISA. This is an attempt to explain +the nonstandard handling of certain instruction names. + +The FAR versions of 3 opcodes (really 6 distinct opcodes) are given +the opcode names CALL_FAR, JMP_FAR and RET_FAR. The AMD documentation +lists the far return as RETF. I call that RET_FAR to be consistent +with the other far operations. + +To distinguish the SSE2 MOVSD instruction from the base string +instruction MOVSD, Intel XED calls the SSE version MOVSD_XMM. + +In March 2015, a change was made to certain Intel XED iclasses to simplify +the implementation. The changes are as follows: +
    +
  • XED_ICLASS_JRCXZ was split in to 3 distinct iclasses: + XED_ICLASS_JCXZ, XED_ICLASS_JECXZ and XED_ICLASS_JRCXZ. +
  • The REP-prefixed (0xF2, 0xF3) string instructions were split + in to new iclasses making tqhem distinct from the underlying + non-REP-prefixed instructions. For example XED_ICLASS_REP_STOSW + is distinct from XED_ICLASS_STOSW. And the CMPS{B,W,D,Q} and + SCAS{B,W,D,Q} instructions have "REPE_" or "REPNE_" prefixes to + correspond to REPE (0xF3) or REPNE (0xF2). +
  • LOCK-prefixed (0xF0) atomic read-modify-write memory + instructions were split in to separate iclasses that contain the + substring "_LOCK". LOCK-prefixed instructions have an attribute + XED_ATTRIBUTE_LOCK. Memory instructions that could have a lock + prefix added to them when encoding, have an attribute + XED_ATTRIBUTE_LOCKABLE. For example XED_ICLASS_CMPXCHG16B_LOCK + has a lock prefix, but XED_ICLASS_CMPXCHG16B does not have a lock + prefix. As always XCHG is atomic with our without a LOCK prefix + as per the rules of the ISA, so XED_ICLASS_XCHG does not have a + _LOCK suffix in the xed_iclass_enum_t name. +
+ +@subsection NOPs + +NOPs are very special. Intel XED allows for encoding NOPs of 1 to 9 bytes +through the use of the XED_ICLASS_NOP (the one byte nop), and +XED_ICLASS_NOP2 ... XED_ICLASS_NOP9. These use the recommended NOP +sequences from the Intel® 64 and IA-32 Architectures Software Developers Manual. + +The instruction 0x90 is very special in the instruction set because it +gets special treatment in 64b mode. In 64b mode, 32b register writes +normally zero the upper 32 bits of a 64b register. No so for 0x90. If +it did zero the upper 32 bits, it would not be a NOP. + +There are two important NOP categories. XED_CATEGORY_NOP and +XED_CATEGORY_WIDENOP. The XED_CATEGORY_NOP applies only to the 0x90 +opcode. The WIDENOP category applies to the NOPs in the two byte table +row 0F19...0F1F. The WIDENOPs take MODRM bytes, and optional SIB and +displacements. + +// =========================================================================== +// @section X86-OPERANDS Operands + + +Intel XED uses the operand order documented in the Intel Programmers' +Reference Manual. In most cases, the first operand is a source and +destination (read and written) and the second operand is just a source +(read). + +For decode requests (#xed_decoded_inst_t), the operands array is +stored in the #xed_inst_t strcture once the instruction is +decoded. For encode requests, the request's operand order is stored in +the #xed_encoder_request_t. + +There are several types of operands: +
    +
  • registers (#xed_reg_enum_t) +
  • branch displacements +
  • memory operations (which include base, index, segment and memory displacements) +
  • immediates +
  • pseudo resources (which are listed in the #xed_reg_enum_t) +
+ +Each operand has two associated attributes: the R/W action and a +visibility. The R/W actions (#xed_operand_action_enum_t) indicate +whether the operand is read, written or both read-and-written, or +conditionally read or written. The visibility attribute +(#xed_operand_visibility_enum_t) is described in the next subsection. + +The memory operation operand is really a pointer to separate fields +that hold the memory operation information. The memory operation information is comprised of: +
    +
  • a segment register +
  • a base register +
  • an index register +
  • a displacement +
+ +There are several important things to note: +
    +
  • There can only be two memory operations, MEM0 and MEM1. +
  • MEM0 could also be an AGEN -- a special operand that uses memory information + but does not actually read memory. This is only used for the LEA instruction. +
  • There can only be an index and displacement associated with MEM0. +
  • There is just one displacement associated with the common fields. It could + be associated with either the AGEN/MEM0 or with a branch or call instruction. +
+ +@subsection AVX512_OPERANDS Intel® AVX512 Operands + +Intel® AVX512 adds write masking, merging and zeroing to the +instruction set via the EVEX encodings. Write masking, merging and +zeroing are properties of the instruction encoding and are not visible +by looking at individual operands. Write masking with merging makes it +possible for values of the destination register to live on from prior +to the execution of the instruction. Write masking with merging +results in an extra register read of the destination operand. In +contrast write masking with zeroing always completely overwrites the +destination operand, either with values computed by the instruction or +with zeros for elements that are "masked off". + +For most operands, to learn if the operand reads or writes its +associated resource, one can use #xed_operand_rw(const xed_operand_t* +p). However because masking, merging and zeroing are properties of the +instruction, and not just the operand, use of a different function is +required. + +To handle this, Intel XED has a new interface function +#xed_decoded_inst_operand_action() which takes a #xed_decoded_inst_t +pointer and an operand index and indicates how the read/write behavior +is modified in the presense of masking with merging or masking with +zeroing. + +The following list attempts to summarize how the value returned from +xed_operand_rw() is internally modified for the 0th operand, except +for stores: +
    +
  • no masking: no change. +
  • masking with zeroing: no change. +
  • masking with merging : destination register operands + that are nominally "rw" or "w" become "rcw" indicating + a read with a conditional write. +
+ + +@subsection OPERAND_VISIBILITY Operand Resource Visibilities + +See #xed_operand_visibility_enum_t . + +There are 3 basic types of resource visibilites: +
    +
  • EXPLICIT (EXPL), +
  • IMPLICIT (IMPL), and +
  • IMPLICIT SUPPRESSED (SUPP) (usually referred to as just "SUPPRESSED"). +
+ +Explicit are what you think they are: resources that +are required for the encoding and for each explicit resource, there is +field in the corresponding instruction encoding. The implicit and +suppressed resources are a more subtle. + + +SUPP operands are: +
    +
  • not used in picking an encoding, +
  • not printed in disassembly, +
  • not represented using operand bits in the encoding. +
+IMPL operands are: +
    +
  • used in picking an encoding, +
  • expressed in disassembly, and +
  • not represented using operand bits in the encoding (like SUPP). +
+ +The implicit resources are required for selecting an encoding, but do +not show up as a specific field in the instruction +representation. Implicit resources do show up in a conventional +instruction disassembly. In the IA-32 instruction set or Intel64 +instruction set, there are many instructions that use EAX or RAX +implicitly, for example. Sometimes the CL or RCX register is +implicit. Also, some instructions have an implicit 1 immediate. The +opcode you chose fixes your choice of implicit register or immediate. + +The suppressed resources are a form of implicit resource, but they are +resources not required for encoding. The suppressed operands are not +normally displayed in a conventional disassembly. The suppressed +operands are emitted by the decoder but are not used when +encoding. They are ignored by the encoder. Examples are the stack +pointer for PUSH and POP operations. There are many others, like +pseudo resources. + + +The explicit and implicit resources are expressed resources -- they show +up in disassembly and are required for encoding. +The suppressed resources are considered a kind of implicit +resources that are not expressed in ATT System V or Intel disassembly formats. + +The suppressed operands are always after the implicit and explicit operands +in the operand order. + + + +@subsection X87_REG_STACK x87 Register stack popping + +The Intel® 64 and IA-32 Architectures Software Developers Manual indicates that "FADDP st2", +reads st0, st2 writes st2 and pops the x87 stack. The result ends up +in st1 after the instruction executes. That is not how Intel XED represents +the operation. Intel XED will say that "FADDP st2" reads st0 and st2 and +writes st2. The output register that Intel XED provides is essentially "pre +pop". The pop occurs afterward, conceptually. The actual result ends +up in the st1 register after the stack pop operation. Intel XED also lists +the pseudo resources indicating that a stack pop has occurred. This +behavior affects the output register of following instructions: FADDP, +FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP. + +@subsection PSEUDO_RESOURCES Pseudo Resources + +Some instructions reference machine registers or perform interesting +operations that we need to represent. For example, the IDTR and GDTR +are represented as pseudo resources. Operations that pop the x87 +floating point register stack can have a X87POP or X87POP2 "register" +to indicate if the x87 register stack is popped once or twice. These +are part of the #xed_reg_enum_t. + +@subsection IMM_DIS Immediates and Displacements + +Using the API functions for setting immediates, memory displacements +and branch displacements. Immediates and Displacements are stored in +normal integers internally, but they are stored endian swapped and +left justified. The API functions take care of all the endian +swapping and positioning so you don't have to worry about that detail. + +Immediates and displacements are different things in the ISA. They can +be 1, 2, 4 or 8 bytes. Branch displacements (1, 2 or 4 bytes) and +Memory displacements (1, 2, 4 or 8 bytes) refer to the signed +constants that are used for relative distances or memory "offsets" +from a base register (including the instruction pointer) or start of a +memory region. + +Immediates are signed or unsigned and are used for numerical +computations, shift distances, and also hold things like segment +selectors for far pointers for certain jump or call instructions. + +There is also a second 1B immedate used only for the ENTER +instruction. + +Intel XED will try to use the shortest allowed width for a displacement or +immediate. You can control Intel XED's selection of allowed widths using a +notion of "legal widths". A "legal width" is a binary number where +each bit represents a legal desired width. For example, when you have +a valid base register in 32 or 64b addressing, and a displacement is +required, your displacement must be either 1 byte or 4 bytes +long. This is expressed by OR'ing 1 and 4 together to get 0101 (base +2) or 5 (base 10). + +If a four byte displacement was required, but the value was +representable in fewer than four bytes, then the legal width should be +set to 0100 (base 2) or 4 (base 10). + +@section API_REF API Reference + + - @ref INIT "INIT" Initialization + - @ref DEC "DEC" Decoding instructions + - @ref ENC "ENC" Encoding instructions + - @ref ENCHL "ENCHL" High level API for encoding instructions + - @ref OPERANDS "OPERANDS" Operand storage fields + - @ref IFORM "IFORM" Iforms + - @ref ISASET "ISASET" ISA-sets and chips + - @ref PRINT "PRINT" Printing (disassembling) instructions + - @ref REGINTFC "REGINTFC" Register interface functions + - @ref FLAGS "FLAGS" Flags interface functions + - @ref AGEN "AGEN" Address generation calculation support + - @ref ENUM "ENUM" Enumerations + - @ref EXAMPLES "Examples" Examples + + + +@section LEGAL Disclaimer and Legal Information + +The information in this manual is subject to change without notice and +Intel Corporation assumes no responsibility or liability for any +errors or inaccuracies that may appear in this document or any +software that may be provided in association with this document. This +document and the software described in it are furnished under license +and may only be used or copied in accordance with the terms of the +license. No license, express or implied, by estoppel or otherwise, to +any intellectual property rights is granted by this document. The +information in this document is provided in connection with Intel +products and should not be construed as a commitment by Intel +Corporation. + +EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH +PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS +ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL +PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A +PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, +COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not +intended for use in medical, life saving, life sustaining, critical +control or safety systems, or in nuclear facility applications. + +Designers must not rely on the absence or characteristics of any +features or instructions marked "reserved" or "undefined." Intel +reserves these for future definition and shall have no responsibility +whatsoever for conflicts or incompat- ibilities arising from future +changes to them. + +The software described in this document may contain software defects +which may cause the product to deviate from published +specifications. Current characterized software defects are available +on request. + +Intel, the Intel logo, Intel SpeedStep, Intel NetBurst, Intel +NetStructure, MMX, Intel386, Intel486, Celeron, Intel Centrino, Intel +Xeon, Intel XScale, Itanium, Pentium, Pentium II Xeon, Pentium III +Xeon, Pentium M, and VTune are trademarks or registered trademarks of +Intel Corporation or its subsidiaries in the United States and other +countries. + +Other names and brands may be claimed as the property of others. + +Copyright (c) 2002-2016 Intel Corporation. All Rights Reserved. + +*/ + +// ============================================================= +/*! @defgroup DEC Decoding Instructions + + To decode an instruction you are required to provide +
    +
  • a machine state (operating mode and stack addressing width) +
  • a pointer to the instruction text array of bytes +
  • a length of the text array +
+ + The machine state is passed in to decoder via the class + #xed_state_t . + That + state is set via the constructor of each + #xed_decoded_inst_t . + + The + #xed_decoded_inst_t + contains the results of decoding after a successful decode. + + The #xed_decoded_inst_t includes an array of #xed_operand_values_t + and that is where most of the information about the operands, + resources etc. are stored. See the @ref OPERANDS interface. The + array is indexed by the #xed_operand_enum_t enumeration. Do not + access it directly though; use the interface functions in the @ref + OPERANDS interface for portability. + + After decoding the #xed_decoded_inst_t contains a pointer to the + #xed_inst_t which acts like a kind of template giving static + information about the decoded instruction: what are the types of + the operands, the iclass, category extension, etc. The #xed_inst_t + is accessed via the #xed_decoded_inst_inst(cont + xed_decoded_inst_t* xedd) function. + + Before every decode, you must call one of the initialization + functions. The most common case would be to use + #xed_decoded_inst_zero_keep_mode() or maybe + #xed_decoded_inst_zero_set_mode(). + + */ + + +/*! @defgroup ENC Encoding Instructions + + When you call xed_encode() to encode instruction you must pass: +
    +
  • an encode structure that includes a machine state ( #xed_state_t ) +
  • a pointer to the instruction text +
  • a length of the text array +
+ The class #xed_encoder_request_t includes a #xed_operand_values_t and + that is where most of the information about the operands, + resources etc. are stored. + + To add a REP or REPNE prefix to a an encoder request, set it in + the encoder request directly by calling + #xed_encoder_request_set_rep() or + #xed_encoder_request_set_repne(). + + To get nondefault width operands, during encoding, you have to + call #xed_encoder_request_set_effective_operand_width() . + + + To set nondefault addressing widths, you must call + #xed_encoder_request_set_effective_address_size(). + + + + To encode instructions you must set the following +in the #xed_encoder_request_t. +
    +
  1. the machine mode (machine width, and stack addressing width) +
  2. the effective operand width +
  3. the iclass +
  4. for some instructions you need to specify prefixes (like REP, + REPNE or LOCK). +
  5. the operands: +
      + +
    1. operand kind + (XED_OPERAND_{AGEN,MEM0,MEM1,IMM0,IMM1,RELBR,PTR,REG0...REG15} + +
    2. operand order
      + xed_encoder_request_set_operand_order(&req,operand_index, XED_OPERAND_*); + where the operand_index is a sequential index starting at zero. + +
    3. operand details +
        +
      1. FOR MEMOPS: base,segment,index,scale,displacement + for memops, +
      2. FOR REGISTERS: register name +
      3. FOR IMMEDIATES: immediate values +
      +
    +
+ + See @ref ENCODE_EXAMPLE for an example of using the encoder. + + */ + +/*! @defgroup ENCHL High Level API for Encoding Instructions + +This is a higher level API for encoding instructions. + +A full example is present in examples/xed-ex5-enc.c + +In the following example we create one instructions template that can +be passed to the encoder. + + @code + xed_encoder_instruction_t x; + xed_encoder_request_t enc_req; + xed_state_t dstate; + + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_32b; + + xed_inst2(&x, dstate, XED_ICLASS_ADD, 0, + xreg(XED_REG_EAX), + xmem_bd(XED_REG_EDX, xdisp(0x11223344, 32), 32)); + + xed_encoder_request_zero_set_mode(&enc_req, &dstate); + convert_ok = xed_convert_to_encoder_request(&enc_req, &x); + if (!convert_ok) { + fprintf(stderr,"conversion to encode request failed\n"); + continue; + } + xed_error = xed_encode(&enc_req, itext, ilen, &olen); + + @endcode + + +The high-level encoder interface allows passing the effective operand +width for the xed_inst*() function as 0 (zero) when the effective +operand width is the default. + +The default width in 16b mode is 16b. The default width in 32b or 64b +modes is 32b. So if you do a 16b operation in 32b/64b mode, you must +set the effective operand width. If you do a 64b operation in 64b +mode, you must set it (the default is 32). Or if you do a more rare +32b operation in 16b mode you must also set it. + +When all the operands are "suppressed" operands, then the effective +operand width must be supplied for nondefault operation widths. + +*/ + +/*! @defgroup OPERANDS Operand storage fields + +The operand storage fields are an array of values used for decoding +and for encoding. This holds derived semantic information from decode +or required fields used during encoding. They are accessible from a +#xed_decoded_inst_t or a #xed_encoder_request_t . */ + + +/*! @defgroup IFORM Iforms + +Intel XED classifies instructions as iclasses (ADD, SUB, MUL, etc.) of type +#xed_iclass_enum_t. To get more information about instructions and +their operands, Intel XED creates iforms of type #xed_iform_enum_t. The +iforms are supposed to aid in creating dispatch tables for +instructions. You can often use a flat array indexed by iform. The +maximum iform is #XED_IFORM_LAST. + +The iforms some times do not uniquely identify instructions. For +example, many instructions in the ISA are "scalable" in that their +operand width depends on the machine mode and the prefixes. The memory +operation of these scalable opcodes is either 16 bits, 32 bits or 64 +bits. The same opcode can represent several instructions if you factor +in the machine mode and prefixes. Those instructions often map to a +single iform and need to be further refined by the +#xed_operand_values_get_effective_operand_width function. + +The names of the iforms are derived from information about the +#xed_iclass_enum_t and the names of their explicit operands (the name of of +nonterminals in the Intel XED internal grammar) and the data types of those +operands. Other information is sometimes included to disambiguate +similar instructions. For example, there are several opcodes and +operands for encoding certain a 1-byte register-register ADD +instruction as well as the 1-byte register-immediate ADD, so to +differentiate those, Intel XED includes the opcode bytes as suffixes for the +iform name: + +@code + ADD_GPR8_GPR8_00 + ADD_GPR8_GPR8_02 + ADD_GPR8_IMMb_80r0 + ADD_GPR8_IMMb_82r0 +@endcode + +The naming scheme for iforms can get rather complex and continues to +evolve over time as the instruction set architecture grows. They +mostly use the lower-case letter codes found in the opcode map found +in the appendix to the Intel® 64 and IA-32 Architectures Software +Developers Manual. For example the scalable instructions +mentioned above use the "v" code which the manuals describe as +representing 16, 32 or 64b operands depending on the effective operand +size. The code "z" implies either 16 or 32b operation; When the +effective operand size is 64, the operand is still 32b. Other common +suffixes one might see are "d" for 32b and "q" for 64b. The codes "ps" +and "pd" stand for packed scalar (single precision floating point) and +packed double (double precision floating point). The code "dq" is used +to describe 128b (16B) quantities typically in memory or an XMM +register. Similarly "qq" describes a 256b (32B) quantity in memory or +a YMM register. In many cases the codes were sufficient to describe +what is needed; in other cases I had to improvise. + +All the iclasses and iforms are listed in the misc/idata.txt file in +the Intel XED kit. + +The iform enumeration #xed_iform_enum_t is dense and it has some +built-in structure. All the iforms for a particular iclass are sequential. +The function #xed_iform_max_per_iclass() indicates the number of iforms +for a particular iclass. + +To get the first iform of a particular iclass you can use +#xed_iform_first_per_iclass() at runtime. There is also the +#xed_iformfl_enum_t which indicates for every iclass, the first and +last iform in the #xed_iform_enum_t. + +Given an iform, to get #xed_category_enum_t, #xed_extension_enum_t, +and #xed_iclass_enum_t information, you can use #xed_iform_map(), or +there are accessors listed below to get the iclass, category or +extension from that table directly. */ + + +/*! @defgroup ISASET Groupings of features for chips + +Every Intel XED iform belongs to one #xed_isa_set_enum_t. Each Intel XED chip of +type #xed_chip_enum_t represents a collection of xed "isa-sets". If +you have a #xed_decoded_inst_t, you can get the isa set via +the function #xed_decoded_inst_get_isa_set. + +*/ + +/*! @defgroup PRINT Printing (disassembling) Instructions + + There are two primary instruction printing + functions: #xed_format_generic() and #xed_format_context() . + Both emit disassembly to a user specified buffer. + #xed_format_generic() takes all the required information in a + pointer to a structure of type #xed_print_info_t. In contrast, + #xed_format_context(), takes its arguments individually. Both + versions can take a void* context argument that is passed to + an optional symbolic disassembly callback function. + + The disassembly dialect (order of operands and formatting) is + specified by the #xed_syntax_enum_t parameter. For finer control + on certain aspects of disassembly, the parameter to + #xed_format_generic() has a field specifing lower level formatting + options (#xed_format_options_t). + + */ + +/*! @defgroup REGINTFC Register Interface + + There are several functions that provide more information about + the GPRs and the nesting of GPRs. + + */ + +/*! @defgroup FLAGS Flags Interface + + There are several functions that provide more information about + the flags read and written. + + The flags are available from the #xed_decoded_inst_t via the + #xed_decoded_inst_get_rflags_info() function which + returns a #xed_simple_flag_t pointer. + + The type #xed_flag_set_t keeps the integer flags in the order + specified by the RFLAGS register. The x87 flags are stored in the + most signficant 4 bits of the flag set. This should not affect use + by the normal integer operations; Those bits are reserved as zero + in the RFLAGS. + + */ + + +/*! @defgroup AGEN Address generation calculation support + + There are several functions available that help with computation + of addresses. Note the "big real" or "unreal" address calculation + is not currently supported. Two callbacks are defined for + providing register values or segment base values. For real mode, + the selector value is usedin the address computation. In protected + mode or long mode, the segment descriptor callbacks are used. + + */ + + +/*! @defgroup ENUM Intel XED enumerations + +Almost all the enumerations in Intel XED are automatically generated and +have conversion functions to and from strings. There is also a +function for finding out what the last element of the enumeration is. + + */ + + +/*! @defgroup INIT Intel XED initialization + + This section describes the base class used for initializing the + encoder / decoder requests and the Intel XED library initialization + function. + + To use Intel XED, you must + include "xed-interface.h" + + @code + #include "xed-interface.h" + @endcode + + If you are calling Intel XED from C++, you must wrap this include: + + @code + extern "C" { + #include "xed-interface.h" + } + @endcode + + Once, before using Intel XED, you must call #xed_tables_init() to + initialize the tables Intel XED uses for encoding and decoding: + @code + xed_tables_init(); + @endcode + + Once initialized, Intel XED is reentrant (multithread safe). All values + used for encoding and decoding live on the caller's stack or in + the passed-in parameters. + + If your program is multithreaded, initialize Intel XED once (and only + once) using the above call before you attempt to decode or encode + from any thread. Each thread does NOT need to initialize Intel XED. The + idea is to initialize Intel XED before creating your threads. + + */ + +/*! @defgroup CMDLINE Intel XED command interface + +The command line tool called xed or xed.exe is built when you build +the examples (@ref EXAMPLES) that come with Intel XED. The xed-ex3 is just +encode portion of the xed command line tool. + + +This tool is useful for encoding and decoding or even +decoding-then-re-encoding a single instruction or all the instructions +in the text segment of an ELF binary (32 or 64b). For decoding, just +jump to the examples. + + +This section also explains a little language for writing the +instructions for encode requests (-e option). I am constantly using +this tool and updating it. The xed-ex3 (xed-ex3.exe) example is just +the encoder portion of the xed command line tool. + +The SUPPRESSED operands emitted by the decoder are not used when +encoding. They are ignored. They are not required to select an +encoding. + +The syntax for encodable strings is as follows: +@code + Opcode[/width] [operand [operand]] +@endcode + +The width is a 8, 16, 32 or 64, indicating the effective operand width +if it differs from the default. 8b operations generally require +this. Or since most operations that default to 32b widths in 64b mode, +it is required for 64b operation widths in 64b mode. + +The operand specifier is one of the following. + +- A register name such as EAX or R8B, etc. Case does not matter. + +- An immediate specifier such as IMM:12ff + +- A branch displacement specifier such as BRDISP:0000001f + +- A memory specifier that indicates the base register, index register, +scale value, and displacement value. If one of the fields is not +required, a - is necessary. The displacement is omittable. For +example: MEM4:ESI,EAX,8,ff or MEM4:EBX. The first one specifies that +the memory address 4 bytes and should be ESI + EAX * 8 + 0xff. The +second one specifies that EBX should be used to access 4 bytes of +memory; note the displacement is omitted. A segment override can be +specified as follows: MEM4:GS:EAX by using a segment-name followed by +a ":" before the base register. If there is no base register, you can +use a "-", for example: MEM4:GS:-,-,11223344. One also needs to +specify a memory operation width. This can be accomplished by +indicating a number of bytes just after the MEM specifier. For +example: MEM2:EAX indicates a 2 byte memory operation. + +- If the Haswell gather instructions are included in the build, then +you can also specify a VSIB memop as follows: VSIB4:RAX,YMM2,2,ff. +This would be a memory operand for a gather with RAX as the base, YMM2 +as the gather index register. The scale is 2 and the displacement is +0xff. The element size is 4 (dwords, 4 bytes). Use 8 for qwords (8 +bytes). + +- An address generation specifer that has the same syntax as the above +MEM: specifier, but is only used for LEA instructions. Example: +AGEN:EAX,EBX,2,- + + +Here is the help message: + +@code + +% obj/xed -h +Usage: obj/xed [options] +One of the following is required: + -i input_file (decode file) + -ide input_file (decode/encode file) + -d hex-string (decode one instruction) + -e instruction (encode, must be last) + -de hex-string (decode-then-encode) + +Optional arguments: + -v verbosity (0=quiet, 1=errors, 2=useful-info, 3=trace, 5=very verbose) + -n number-of-instructions-to-decode (default 10,000, accepts K/M/G qualifiers) + -I (Intel SYSV syntax for disassembly) + -A (ATT SYSV syntax for disassembly) + -16 (for LEGACY_16 mode) + -32 (for LEGACY_32 mode, default) + -64 (for LONG_64 mode w/64b addressing) + -s32 (32b stack addressing, default, not in LONG_64 mode) + -s16 (16b stack addressing, not in LONG_64 mode) +@endcode + +Here are a couple of examples: + +@code +% xed -d 0000 +ADD INT_ALU BASE Opcode: 00 MODRM: 00 Bytes: 2 + Eb/EXPLICIT/RW Gb/EXPLICIT/R + ADD EffWidth: 8b + MachineMode: LEGACY_32 AddrWidth: 32b StackAddrWidth: 32b + MEM/EXPLICIT/RW REG/AL(REG8)/EXPLICIT/R + Read Write BASE= EAX(REG32) MemopLength = 1 + + rFLAGS: of-mod sf-mod zf-mod af-mod pf-mod cf-mod \ + Read: Written: of sf zf af pf cf writes + +% xed -e ADD EAX EBX +Encodable! 01d8 + +xed -e ADD EAX MEM4:ESP,EBX,4 +Encodable! 03049c + +% xed -d 6a00 +PUSH INT_ALU BASE Opcode: 6a Immed: 00 Bytes: 2 + Ib/EXPLICIT/R STACKPUSH/SUPPRESSED/R + PUSH EffWidth: 32b + MachineMode: LEGACY_32 AddrWidth: 32b StackAddrWidth: 32b + MEM/SUPPRESSED/W REG/ESP(REG32)/SUPPRESSED/RW IMM/EXPLICIT/R + Write SEG= SS BASE= ESP(REG32) MemopLength = 4 + IMMED: 00 + + Does not use rFLAGS + +% xed -e MOV EAX MEM4:SS:ESP +Encodable! 8b0424 +@endcode + +Or using the xed-ex3 example tool: +@code +% obj/xed-ex3 +Usage: obj/xed-ex3 [-16|-32|-64] [-s16|-s32] encode-string +@endcode + +The -16, -32 or -64 are for specifying the major mode of the machine. +The major mode of the machine determines the default data operand +size and default addressing width. In 64b mode, the default data +size is 32b and the default addressing mode is 64b +addressing. In 32b mode, the default addressing width is 32b. In 16b +mode, the default addressing width is 16b. In 32b mode or 16b mode, +the stack addressing width must also be specified. Usually it matches +the major mode. The -s16 option is for specifying 16b stack +addressing in 32b mode. The -s32 is for specifying 32b stack +addressing in 16 bit mode. + +@code +% obj/xed-ex3 -64 PUSH/64 RAX +Encode request: +PUSH Prefixes: EffOpWidth: 64b EffAddrWidth: 64b + MachineMode: LONG_64 AddrWidth: 64b StackAddrWidth: 32b + REG/RAX(REG64)/EXPLICIT/RW + MemopLength = 0 + +Encodable! 50 + +% obj/xed-ex3 MOV MEM4:EAX IMM:11223344 +Encode request: +MOV Prefixes: EffOpWidth: 32b EffAddrWidth: 32b + MachineMode: LEGACY_32 AddrWidth: 32b StackAddrWidth: 32b + MEM0/EXPLICIT/RW IMM/EXPLICIT/RW + TmpltIdx=0 BASE= EAX(REG32) MemopLength = 0 + IMMED: 0x11223344 signed: 1144201745 starts@byte: 1 + +Encodable! c70011223344 +@endcode + +@section ENCODE_EXAMPLE An example of using the encoder + +The encoder language file which is part of the xed command line tool +shows how to build up instructions from scratch. The example uses a +string to drive the creation of the instruction, but that is just an +example. Look at the parse_encode_request function for the required +pieces. + +\include xed-enc-lang.c + + + */ + +/*! @defgroup EXAMPLES Examples of using Intel XED + +The source code for the examples is in the "examples" subdirectory. + +There is a makefile that will build all the examples on linux or +windows. + +There are several examples: +
    + +
  • xed-ex1.c: a simple decoder that prints the decode data + structure. This is included in the "Small Examples" section + below. It is a good example for using the major decoder APIs. + +
  • xed-ex4.c:a simple decoder with different disassmebly output formats +
  • xed-ex5-enc.c: encoder example using the high-level encoding API. +
  • xed.c: a decoder, encoder, image file reader, etc. +
  • xed-ex3.c: an encoder (subset of the xed command line + tool). Documented with "xed" on the @ref CMDLINE page. +
+ +The examples are described in the following subsections: + - @ref SMALLEXAMPLES "Small Examples" Small Examples + - @ref CMDLINE "Command line" Intel XED's command line testing tool + - @ref ENCODE_EXAMPLE "Encode Example" An example of using the encoder + +*/ + +/*! @defgroup SMALLEXAMPLES Small Examples of using Intel XED + +Here is a minimal example of using Intel XED from the file examples/xed-min.c. + +\include xed-min.c + +There is a makefile in the examples directory. Here's how to compile +it from a kit: +@code +% gcc -Ipath-to-xed-kit/include -Ipath-to-xed-kit/examples \ + -c path-to-xed-kit/examples/xed-min.c +% gcc -o xed-min xed-min.o path-to-xed-kit/lib/libxed.a +@endcode +where path-to-xed-kit is where you have your include, examples and +lib directories from an installed Intel XED kit. + + +Here is a more detailed example (examples/xed-ex1.c) that walks the +operands much like the printing routines do for the +#xed_decoded_inst_t . + +\include xed-ex1.c + +Here are a few examples of running the program: + +@code + +% ./xed-ex1 0 0 +iclass ADD category INT_ALU ISA-extension BASE +instruction-length 2 +effective-operand-width 8b +effective-address-width 32b +Operands + 0 MEM0 EXPLICIT / RW + 1 REG AL EXPLICIT / R + 2 REG EFLAGS SUPPRESSED / W +Memory Operands + 0 read SEG= DS BASE= EAX/REG32 + MemopLength = 1 +FLAGS: + must-write-rflags of-mod sf-mod zf-mod af-mod pf-mod cf-mod + read: + written: of sf zf af pf cf +=============================================================================== + +% ./xed-ex1 f2 0f 58 9c 24 e0 00 00 00 +iclass ADDSD category SSE ISA-extension SSE2 +instruction-length 9 +effective-operand-width 32b +effective-address-width 32b +Operands + 0 REG XMM3 EXPLICIT / RW + 1 MEM0 EXPLICIT / R +Memory Operands + 0 read SEG= SS BASE= ESP/REG32 DISPLACEMENT= DISP32 0x000000e0 + MemopLength = 8 +=============================================================================== +./xed-ex1 f3 90 +iclass PAUSE category INT_ALU ISA-extension BASE +instruction-length 2 +effective-operand-width 32b +effective-address-width 32b +Operands +Memory Operands + MemopLength = 0 +=============================================================================== + +@endcode + + + + +*/ diff --git a/docsrc/xed-doxygen-header.txt b/docsrc/xed-doxygen-header.txt new file mode 100644 index 0000000..2bd9215 --- /dev/null +++ b/docsrc/xed-doxygen-header.txt @@ -0,0 +1,6 @@ + + +XED: XED User Guide - $datetime + + + diff --git a/examples/README.txt b/examples/README.txt new file mode 100644 index 0000000..75b207e --- /dev/null +++ b/examples/README.txt @@ -0,0 +1,32 @@ + + +To build the examples, a relatively recent version of python 2.7 is required. + +================================ +STATIC LIBRARY XED BUILD: +================================ + + Linux or Mac: + + % ./mfile.py + + Windows: + + % C:/python27/python mfile.py + +================================ +DYNAMIC LIBRARY XED BUILD: +================================ + +If you have a a shared-object (or DLL build on windows) you must also include +"--shared" on the command line: + + Linux or Mac: + + % ./mfile.py --shared + + Windows: + + % C:/python27/python mfile.py --shared + +Add "--help" (no quotes) for more build options. diff --git a/examples/avltree.c b/examples/avltree.c new file mode 100644 index 0000000..eba3d3f --- /dev/null +++ b/examples/avltree.c @@ -0,0 +1,397 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "avltree.h" +#include +#include +#include +#include + +typedef struct avl_node_s { + avl_key_t key; + void* data; + int32_t balance_factor; + uint32_t height; + struct avl_node_s* left; + struct avl_node_s* right; +} avl_node_t; + +static void pad(int d) { + int i; + for(i=0;iheight, + n->balance_factor, + (uint64_t) n->key, + n->data); + print_node(n->left, cur_depth+1); + print_node(n->right, cur_depth+1); + } + else + fprintf(stdout, "*empty*\n"); + +} +#if 0 +static void print_tree(avl_tree_t* tree) { + printf("=============\n"); + if (tree->top) + print_node(tree->top, 0); + else + fprintf(stdout, "*empty tree*\n"); + printf("=============\n"); +} +#endif + +void avl_tree_init(avl_tree_t* tree) +{ + tree->top = 0; +} + +static void clear(avl_node_t* n, int free_data) // recursive +{ + if (n->left) + clear(n->left, free_data); + if (n->right) + clear(n->right, free_data); + if (free_data && n->data) + free((void*)n->data); + free((void*)n); +} +void avl_tree_clear(avl_tree_t* tree, int free_data) +{ + if (tree->top) { + clear(tree->top, free_data); + } + tree->top = 0; +} + +static avl_node_t* find_node(avl_node_t* n, avl_key_t key) //recursive +{ + if (n->key == key) + return n; + else if (n->key > key && n->left) + return find_node(n->left, key); + else if (n->right) + return find_node(n->right, key); + return 0; +} + +static void* find(avl_node_t* n, avl_key_t key) //recursive +{ + if (n) + { + avl_node_t* x = find_node(n,key); + if (x) + return x->data; + } + return 0; +} + +void* avl_find (avl_tree_t* tree, avl_key_t key) +{ + return find(tree->top, key); +} + + + + + + + + + + +static avl_node_t* find_node_lower_bound(avl_node_t* n, avl_key_t key, + avl_node_t** lb) //recursive +{ + //printf("NODE KEY=%lld\n", n->key); + if (n->key == key){ + *lb = n; + return n; + } + else if (n->key > key && n->left) { + //printf("\tGO LEFT\n"); + return find_node_lower_bound(n->left, key, lb); + } + + if (n->key < key) { + // store the max lower bound we encounter when node key is < search + // key. + if (*lb && (*lb)->key < n->key) + *lb = n; + else if (*lb == 0) + *lb = n; + } + + if (n->right) { + //printf("\tGO RIGHT\n"); + return find_node_lower_bound(n->right, key, lb); + } + return *lb; +} + +static void* find_lower_bound(avl_node_t* n, avl_key_t key, + avl_key_t* lbkey) // output +{ + avl_node_t* lbound = 0; + if (n) + { + (void) find_node_lower_bound(n,key, &lbound); + if (lbound) { + *lbkey = lbound->key; + return lbound->data; + } + } + return 0; +} +void* avl_find_lower_bound (avl_tree_t* tree, avl_key_t key, + avl_key_t* lbkey) // output +{ + return find_lower_bound(tree->top, key, lbkey); +} + + + + + + +static avl_node_t* make_node(avl_key_t key, void* value) +{ + avl_node_t* n = (avl_node_t*) malloc(sizeof(avl_node_t)); + n->key = key; + n->data = value; + n->balance_factor = 0; + n->height = 1; + n->left = n->right = 0; + return n; +} + +static uint32_t mmax(uint32_t a, uint32_t b) { + return (a>b)?a:b; +} + +static uint32_t update_height(avl_node_t* n) +{ + avl_node_t* a = n->left; + avl_node_t* b = n->right; + return 1 + mmax((a?a->height:0), (b?b->height:0)); +} +static int32_t update_balance(avl_node_t* n) +{ + avl_node_t* a = n->left; + avl_node_t* b = n->right; + return (int32_t)(a?a->height:0) - (int32_t)(b?b->height:0); +} +static void update_height_and_balance(avl_node_t* n) +{ + n->height = update_height(n); + n->balance_factor = update_balance(n); +} +static avl_node_t* left_left(avl_node_t* n) // changes top node +{ + // knock the tree over to the right, making n->left in to the new top node. + // juggle subtrees + + avl_node_t* new_top = n->left; + avl_node_t* old_top = n; + old_top->left = new_top->right; + new_top->right = old_top; + update_height_and_balance(old_top); + update_height_and_balance(new_top); + return new_top; +} +static avl_node_t* left_right(avl_node_t* n) +{ + // replace n->left with n->left->right, juggle subtrees + avl_node_t* l_node = n->left; + avl_node_t* lr_node = n->left->right; + n->left = lr_node; + l_node->right = lr_node->left; + lr_node->left = l_node; + update_height_and_balance(l_node); + update_height_and_balance(lr_node); + return n; +} +static avl_node_t* right_left(avl_node_t* n) +{ + // replace n->right with n->right->left, juggle subtrees + avl_node_t* r_node = n->right; + avl_node_t* rl_node = n->right->left; + n->right = rl_node; + r_node->left = rl_node->right; + rl_node->right = r_node; + update_height_and_balance(r_node); + update_height_and_balance(rl_node); + return n; +} +static avl_node_t* right_right(avl_node_t* n) // changes top node +{ + // knock the tree over to the left, making n->right in to the new top node. + // juggle subtrees + avl_node_t* new_top = n->right; + avl_node_t* old_top = n; + old_top->right = new_top->left; + new_top->left = old_top; + update_height_and_balance(old_top); + update_height_and_balance(new_top); + return new_top; +} + +static avl_node_t* insert(avl_node_t* n, + avl_key_t key, void* value, int free_data) +{ + if (n->key == key) { + if (n->data && free_data) + free((void*)n->data); + n->data = value; + } + else if (n->key > key) { + if (n->left) { + n->left = insert(n->left, key, value, free_data); + update_height_and_balance(n); + } + else { + n->left = make_node(key,value); + update_height_and_balance(n); + } + } + else if (n->key < key) { + if (n->right) { + n->right = insert(n->right, key, value, free_data); + update_height_and_balance(n); + } + else { + n->right = make_node(key,value); + update_height_and_balance(n); + } + } + // rebalancing might change the current node + if (n->balance_factor >= 2) // heavy on the left + { + if (n->left->balance_factor == -1) { + // subtree is heavy right, make it heavy left, then knock it over + n = left_right(n); + n = left_left(n); + } + else if (n->left->balance_factor == 1) { + // subtree is heavy left, knock it over + n = left_left(n); + } + } + else if (n->balance_factor <= -2) // heavy on the right + { + if (n->right->balance_factor == 1) { + // subtree is heavy left, make it heavy right, then knock it over + n = right_left(n); + n = right_right(n); + } + else if (n->right->balance_factor == -1) { + // subtree is heavy right, knock it over + n = right_right(n); + } + } + update_height_and_balance(n); // FIXME: redundant, remove this + if (n->balance_factor <= -2 || n->balance_factor >= 2) { + printf("FAIL\n"); + print_node(n, 0); + assert (n->balance_factor < 2 && n->balance_factor > -2); + } + return n; +} + +void avl_insert(avl_tree_t* tree, avl_key_t key, void* value, int free_data) +{ + //rebalancing can change what the 'tree' points to as its top node. + if (tree->top) + tree->top = insert(tree->top, key, value, free_data); + else + tree->top = make_node(key,value); + //print_tree(tree); +} + + +typedef struct avl_link_node_s { + avl_node_t* node; + struct avl_link_node_s* next; +} avl_link_node_t; + +void avl_iter_begin( avl_iter_t* iter, avl_tree_t* tree) +{ + iter->head = 0; + iter->tail = 0; + if (tree->top) { + avl_link_node_t* n = (avl_link_node_t*)malloc(sizeof(avl_link_node_t)); + n->node = tree->top; + n->next = 0; + iter->head = n; + iter->tail = n; + } + +} + +void* avl_iter_current(avl_iter_t* iter) +{ + return iter->head->node->data; +} + +static void add_link_node(avl_iter_t* iter, avl_node_t* anode) +{ + if (anode) + { + avl_link_node_t* n = (avl_link_node_t*)malloc(sizeof(avl_link_node_t)); + n->next = 0; + n->node = anode; + iter->tail->next = n; + iter->tail = n; + } + } +void avl_iter_increment(avl_iter_t* iter) +{ + avl_link_node_t* p; + add_link_node(iter, iter->head->node->left); + add_link_node(iter, iter->head->node->right); + p = iter->head; + iter->head = p->next; + free(p); +} +int avl_iter_done(avl_iter_t* iter) +{ + return (iter->head == 0); +} + +void avl_iter_cleanup(avl_iter_t* iter) // call if end iteration early +{ + struct avl_link_node_s* p = iter->head; + while(p) { + struct avl_link_node_s* t = p; + p = t->next; + free(t); + } +} diff --git a/examples/avltree.h b/examples/avltree.h new file mode 100644 index 0000000..6a247db --- /dev/null +++ b/examples/avltree.h @@ -0,0 +1,74 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#if !defined(_AVL_TREE_H_) +# define _AVL_TREE_H_ + +#include +#if defined(AVL_KEY_32_BIT) +typedef uint32_t avl_key_t; +#else +typedef uint64_t avl_key_t; +#endif + + +struct avl_node_s; // fwd decl + +typedef struct { + struct avl_node_s* top; +} avl_tree_t; + +void avl_tree_init(avl_tree_t* tree); + +// clear removes the tree nodes, not the data +void avl_tree_clear(avl_tree_t* tree, int free_data); + +void* avl_find(avl_tree_t* tree, avl_key_t key); + +// find the node with a key <= the given key. Returns found key value in +// lbkey and the data payoad as a return value. +void* avl_find_lower_bound(avl_tree_t* tree, avl_key_t key, + avl_key_t* lbkey); // output + + +// insert notices key collisions and will free the associated data if +// free_data is nonzero. +void avl_insert(avl_tree_t* tree, avl_key_t key, void* value, int free_data); + +#if 0 // DELETE not done yet. +// return 1 on failure, 0 on success +int avl_delete(avl_tree_t* tree, avl_key_t key, int free_data); +#endif + + +struct avl_link_node_s; // fwd decl + +typedef struct avl_iter_s { + struct avl_link_node_s* head; + struct avl_link_node_s* tail; +} avl_iter_t; + + +void avl_iter_begin( avl_iter_t* iter,avl_tree_t* tree); +void* avl_iter_current(avl_iter_t* iter); +void avl_iter_increment(avl_iter_t* iter); +int avl_iter_done(avl_iter_t* iter); +void avl_iter_cleanup(avl_iter_t* iter); // call if end iteration early + +#endif diff --git a/examples/makefile b/examples/makefile new file mode 100644 index 0000000..816f2e0 --- /dev/null +++ b/examples/makefile @@ -0,0 +1,188 @@ +#BEGIN_LEGAL +#Copyright (c) 2004-2015, Intel Corporation. All rights reserved. +# +#Redistribution and use in source and binary forms, with or without +#modification, are permitted provided that the following conditions are +#met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +#"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +#LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +#A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +#OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +#SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +#LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +#DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +#THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +#OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#END_LEGAL + +# Makefile for examples + +#################################################################### +# External tools +COMPILER=gnu +#COMPILER=ms + +SHARED=0 +#SHARED=1 +ifeq ($(COMPILER),gnu) + CC = gcc + CXX = g++ + CXX_LINKER = $(CXX) + CC_LINKER = $(CC) + RM=rm + OBJEXT=o + EXEEXT= + CXXSRCEXT=cpp + CCSRCEXT=c + ifeq ($(SHARED),1) + LIBEXT=so + else + LIBEXT=a + endif + LINKOUT=-o + OUTOPT=-o + COPT=-c + IOPT=-I + DOPT=-D + CXXFLAGS = -MMD + CCFLAGS = -MMD + + # + # Uncomment these next 2 if you want 32b object and executable + # files and are on a 64b system. (You must be using the ia32 + # version of libxed). + # + #CCFLAGS += -m32 + #CXXFLAGS += -m32 + + LDFLAGS = + #The windows library does not work with cygwin, but in general on cygwin, + # enable these: + #CXXFLAGS += -mno-cygwin + #CCFLAGS += -mno-cygwin + #LDFLAGS += -mno-cygwin +else + CC = cl + CXX = cl + # you want MSVS's link, not cygwin's link. + # make sure you move cygwin's /bin/link command out of the way! + CXX_LINKER = link + CC_LINKER = link + RM=rm + OBJEXT=obj + EXEEXT=.exe + CXXSRCEXT=cpp + CCSRCEXT=c + LIBEXT=lib + LINKOUT=/OUT: + OUTOPT=/Fo + COPT=/c + IOPT=/I + DOPT=/D + CXXFLAGS = /nologo /EHsc + CCFLAGS = /nologo + LDFLAGS = /nologo +endif +################################################################### +CXXFLAGS += $(IOPT)../include +CCFLAGS += $(IOPT)../include +LIBXED = ../lib/libxed.${LIBEXT} +EXTRA_LDLIBS_TARGET = +################################################################### +.PHONY: demos cmdline clean-examples test-xed + +XED = xed +XED_DEMOS = xed-min xed-tester xed-ex1 xed-ex3 xed-ex4 \ + xed-ex5-enc xed-ex6 xed-ex7 + +XED_DEMOS_SUFFIXED= $(XED_DEMOS:%=%$(EXEEXT)) +XED_SUFFIXED= $(XED:%=%$(EXEEXT)) + +XED_TEST_APPS = ${XED_SUFFIXED} ${XED_DEMOS_SUFFIXED} +all: ${XED_TEST_APPS} +demos: ${XED_DEMOS_SUFFIXED} +cmdline: ${XED_SUFFIXED} + +###################################################################### + +%.${OBJEXT}: %.${CXXSRCEXT} + ${CXX} ${COPT} ${CXXFLAGS} $< ${OUTOPT}$@ +%.${OBJEXT}: %.${CCSRCEXT} + ${CC} ${COPT} ${CCFLAGS} $< ${OUTOPT}$@ + +######################################################################## +XED_CXX_COMMON_OBJ = +XED_CCC_COMMON_OBJ = +XED_CC_COMMON_OBJ += xed-enc-lang.${OBJEXT} +XED_CC_COMMON_OBJ += xed-disas-hex.${OBJEXT} +XED_CC_COMMON_OBJ += xed-examples-util.${OBJEXT} +XED_CC_COMMON_OBJ += xed-dot-prep.${OBJEXT} +XED_CC_COMMON_OBJ += xed-dot.${OBJEXT} + +xed-min${EXEEXT}: xed-min.${OBJEXT} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +xed-tester${EXEEXT}: xed-tester.${OBJEXT} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +xed-ex1${EXEEXT}: xed-ex1.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +xed-ex3${EXEEXT}: xed-ex3.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +xed-ex4${EXEEXT}: xed-ex4.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} +xed-ex5-enc${EXEEXT}: xed-ex5-enc.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} +xed-ex6${EXEEXT}: xed-ex6.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} +xed-ex7${EXEEXT}: xed-ex7.${OBJEXT} ${XED_CC_COMMON_OBJ} ${LIBXED} + ${CC_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +################################################################# + +XED_OBJ = xed.${OBJEXT} +XED_OBJ += xed-disas-macho.${OBJEXT} +XED_OBJ += xed-disas-pecoff.${OBJEXT} +XED_OBJ += xed-disas-raw.${OBJEXT} +XED_OBJ += xed-disas-elf.${OBJEXT} +XED_OBJ += xed-symbol-table.${OBJEXT} +XED_OBJ += avltree.${OBJEXT} +XED_OBJ += ${XED_CC_COMMON_OBJ} +XED_OBJ += ${XED_CXX_COMMON_OBJ} + +# define DBGHELP=1 on the command line to enable using dbghelp.dll on windows +DBGHELP ?= 0 +ifeq ($(DBGHELP),1) + XED_OBJ += udhelp.${OBJEXT} + CXXFLAGS += /DXED_DBGHELP + EXTRA_LDLIBS_TARGET += dbghelp.lib version.lib +endif + +xed${EXEEXT}: ${XED_OBJ} ${LIBXED} + ${CXX_LINKER} ${LDFLAGS} ${LINKOUT}$@ $^ ${EXTRA_LDLIBS_TARGET} + +################################################################# + +clean: + -${RM} *.o *.obj *.d *.exe > /dev/null 2>&1 + -${RM} ${XED_TEST_APPS} > /dev/null 2>&1 + +################################################################# +-include *.d diff --git a/examples/mfile.py b/examples/mfile.py new file mode 100755 index 0000000..441e47b --- /dev/null +++ b/examples/mfile.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +#Copyright (c) 2004-2015, Intel Corporation. All rights reserved. +# +#Redistribution and use in source and binary forms, with or without +#modification, are permitted provided that the following conditions are +#met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +#"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +#LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +#A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +#OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +#SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +#LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +#DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +#THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +#OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#END_LEGAL + +import sys +import os + +def _find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +def _fatal(m): + sys.stderr.write("\n\nXED build error: %s\n\n" % (m) ) + sys.exit(1) + +def _try_mbuild_import(): + try: + import mbuild + return True + except: + return False + +def _find_add_import(d): + p = _find_dir(d) + if p and os.path.exists(p): + sys.path = [p] + sys.path + return + _fatal("Could not find {} directory".format(d)) + +def _find_mbuild_import(): + if _try_mbuild_import(): + return + _find_add_import('mbuild') + + +def _find_common(): + p = os.path.dirname(_find_dir('xed_build_common.py')) + if p and os.path.exists(p): + sys.path = [p] + sys.path + return + _fatal("Could not find xed_build_common.py") + +def setup(): + if sys.version_info[0] >= 3: + _fatal("Python version 3.x not supported.") + if sys.version_info[0] == 2 and sys.version_info[1] < 7: + _fatal("Need python version 2.7 or later.") + _find_mbuild_import() + # when building in the source tree the xed_build_common.py file is + # in the parent directory of the examples. When building in the + # kit that file is in the example source directory. + _find_common() + + +def work(): + import xed_build_common + import xed_examples_mbuild + try: + retval = xed_examples_mbuild.execute() + except Exception, e: + xed_build_common.handle_exception_and_die(e) + return retval + +if __name__ == "__main__": + setup() + retval = work() + sys.exit(retval) + diff --git a/examples/udhelp.H b/examples/udhelp.H new file mode 100644 index 0000000..e18a737 --- /dev/null +++ b/examples/udhelp.H @@ -0,0 +1,80 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#if !defined(_UDHELP_H_) +#define _UDHELP_H_ + +#if defined(_MSC_VER) && defined(XED_DBGHELP) +// only try to use dbghelp on MSVS8 (2005) or later versions. +# if _MSC_VER >= 1400 +# define XED_USING_DEBUG_HELP +# endif +#endif + +#if defined(XED_USING_DEBUG_HELP) +#include +#include +extern "C" { +#include "xed-symbol-table.h" +} +class dbg_help_client_t { + + DWORD error; + HANDLE hProcess; + DWORD processId; + + DWORD64 gBaseOfDll; + DWORD64 actual_base; + char* gModule; + + bool initialized; + + static BOOL CALLBACK enum_modules( + LPSTR ModuleName, + DWORD64 BaseOfDll, + PVOID UserContext ); + + static BOOL CALLBACK dbg_help_client_t::enum_sym( + PSYMBOL_INFO pSymInfo, + ULONG SymbolSize, + PVOID UserContext); + + public: + + xed_symbol_table_t sym_tab; // EXPOSED + + dbg_help_client_t(); + + // returns 1 on success and 0 on failure. sets "initialized" to true on + // success + int init(char const* const fpath, + char const* const search_path); + bool valid() const { return initialized; } + + // if offset is nonzero, it will return best-fit symbols. If offset=0 + // then only exact symbols are returned. + bool get_symbol(DWORD64 address, char* symbol_name, + int sym_name_buflen, DWORD64* offset=0); + + xed_bool_t get_file_and_line(xed_uint64_t address, + char** filename, + xed_uint32_t* line, + xed_uint32_t* column); + bool cleanup(); +}; +#endif +#endif diff --git a/examples/udhelp.cpp b/examples/udhelp.cpp new file mode 100644 index 0000000..5c935a0 --- /dev/null +++ b/examples/udhelp.cpp @@ -0,0 +1,323 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "udhelp.H" +#include +extern "C" { +#include "xed-interface.h" +#include "xed-examples-util.h" // xed_strdup +} +#include +#include +#include +#include +#include +#include + +#if defined(XED_USING_DEBUG_HELP) && defined(XED_DECODER) +BOOL CALLBACK dbg_help_client_t::enum_modules( + LPSTR ModuleName, + DWORD64 BaseOfDll, + PVOID UserContext ) +{ + dbg_help_client_t* pthis = (dbg_help_client_t*)UserContext; + pthis->gBaseOfDll = BaseOfDll; + pthis->gModule=ModuleName; + return TRUE; +} + + + + +BOOL CALLBACK dbg_help_client_t::enum_sym( + PSYMBOL_INFO pSymInfo, + ULONG SymbolSize, + PVOID UserContext) +{ + dbg_help_client_t* pthis = (dbg_help_client_t*)UserContext; + xed_uint64_t addr = static_cast(pSymInfo->Address); + + xst_add_global_symbol(&pthis->sym_tab, + addr, + xed_strdup(pSymInfo->Name)); + return TRUE; + (void)SymbolSize; //pacify compiler warning about unused param +} + + +dbg_help_client_t::dbg_help_client_t() { + xed_symbol_table_init(&sym_tab); + initialized=false; +} + + +char* find_base_path(char* driver_name) { + char* x; + char* path = xed_strdup(driver_name); + x = strrchr(path,'\\'); + if (x) { + *x = 0; + } + else { + x = strrchr(path,'/'); + if (x) { + *x = 0; + } + else { + /* FIXME */ + } + } + return path; +} + +static char* append3(const char* s1, const char* s2, const char* s3) { + xed_uint_t n = 1; + char* p = 0; + assert(s1 != 0); + n += xed_strlen(s1); + if (s2) n += xed_strlen(s2); + if (s3) n += xed_strlen(s3); + p = (char*) malloc(sizeof(char)*n); + n=xed_strncpy(p,s1,n); + if (s2) n=xed_strncat(p,s2,n); + if (s3) n=xed_strncat(p,s3,n); + return p; +} + + + + +typedef union { + short a[2]; + int i; +} union16_t; + +void get_dll_version(char* file_name, short u[4]) { + VS_FIXEDFILEINFO* vsf; + DWORD verlen, error, handle; + UINT len; + BOOL ret; + char* ver; + + verlen = GetFileVersionInfoSize(file_name,&handle); + if (verlen == 0) { + error = GetLastError(); + fprintf(stderr,"GetFileVersionInfoSize: error code was %d (0x%x)\n", + error, error); + exit(1); + } + + ver = new char[verlen]; + ret = GetFileVersionInfo(file_name,handle,verlen,ver); + if (!ret) { + error = GetLastError(); + fprintf(stderr, + "GetFileVersionInfo: error code was %d (0x%x)\n", error, error); + exit(1); + } + + // get a pointer to a location in ver stored in vsf + ret = VerQueryValue(ver,"\\",(LPVOID*)&vsf,&len); + if (!ret) { + error = GetLastError(); + fprintf(stderr, + "VerQueryValue: error code was %d (0x%x)\n", error, error); + exit(1); + } + assert(len == sizeof(VS_FIXEDFILEINFO)); + + union16_t upper,lower; + upper.i = vsf->dwFileVersionMS; + lower.i = vsf->dwFileVersionLS; + u[0] = upper.a[1]; + u[1] = upper.a[0]; + u[2] = lower.a[1]; + u[3] = lower.a[0]; + + delete[] ver; +} + + + +int dbg_help_client_t::init(char const* const path, + char const* const search_path) +{ + DWORD64 dwBaseAddr=0; + + int chars; + char exe_path[MAX_PATH]; + chars = GetModuleFileName(NULL, exe_path, MAX_PATH); + if (chars == 0) { + fprintf(stderr,"Could not find base path for XED executable\n"); + fflush(stderr); + exit(1); + } + + char* dir = find_base_path(exe_path); + + char* dbghelp = append3(dir,"\\","dbghelp.dll"); +#if defined(PIN_CRT) + if (access(dbghelp,4) != 0) +#else + if (_access_s(dbghelp,4) != 0) +#endif + { + return 0; + } + + SymSetOptions(SYMOPT_UNDNAME | SYMOPT_LOAD_LINES ); + hProcess = GetCurrentProcess(); + + if (SymInitialize(hProcess, NULL, FALSE)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymInitialize returned error : %d 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + if (search_path) + { + if (SymSetSearchPath(hProcess, search_path)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymSetSearchPath returned error : %d 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + } + + actual_base = SymLoadModuleEx(hProcess, NULL, path, NULL, + dwBaseAddr, 0, NULL, 0); + if (actual_base) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymLoadModuleEx returned error : %d 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + + if (SymEnumerateModules64(hProcess, + (PSYM_ENUMMODULES_CALLBACK64)enum_modules, this)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymEnumerateModules64 returned error : %d 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + if (SymEnumSymbols(hProcess, actual_base, 0, enum_sym, this)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymEnumSymbols failed: %d 0x%x\n", error, error); + fflush(stderr); + return 0; + } + + initialized = true; + return 1; +} + +bool dbg_help_client_t::get_symbol(DWORD64 address, char* symbol_name, + int sym_name_buflen, DWORD64* offset) +{ + DWORD64 displacement; + ULONG64 n = (sizeof(SYMBOL_INFO) + + sym_name_buflen*sizeof(TCHAR) + + sizeof(ULONG64) - 1) / sizeof(ULONG64); + ULONG64* buffer = new ULONG64[n]; + PSYMBOL_INFO pSymbol = (PSYMBOL_INFO)buffer; + + pSymbol->SizeOfStruct = sizeof(SYMBOL_INFO); + pSymbol->MaxNameLen = sym_name_buflen; + + if (SymFromAddr(hProcess, address, &displacement, pSymbol)) { + if (offset) + *offset = displacement; + if (offset || displacement == 0) { + xed_strncpy(symbol_name, pSymbol->Name, sym_name_buflen); + // force a null. WINDOWS doesn't have strlcpy() + symbol_name[sym_name_buflen-1] = 0; + delete [] buffer; + return 0; + } + else { + /* not at the beginning of a symbol and no offset was supplied */ + delete [] buffer; + return 1; + } + } + else { + error = GetLastError(); + fprintf(stderr, + "SymFromAddr returned error : %d 0x%x for address %llx\n", + error, error, address); + delete [] buffer; + return 1; + } + + +} + +bool dbg_help_client_t::cleanup() { + if (SymCleanup(hProcess)) { + return 0; + } + else { + error = GetLastError(); + fprintf(stderr, + "SymCleanup returned error : %d 0x%x\n", error,error); + return 1; + } +} + +xed_bool_t dbg_help_client_t::get_file_and_line(xed_uint64_t address, + char** filename, + xed_uint32_t* line, + xed_uint32_t* column) +{ + DWORD dw_column; + IMAGEHLP_LINE64 imgline; + imgline.SizeOfStruct = sizeof(IMAGEHLP_LINE64); + if (SymGetLineFromAddr64(hProcess, address, &dw_column, &imgline)) + { + xed_uint32_t len = xed_strlen(imgline.FileName); + *column = dw_column; + *line = imgline.LineNumber; + *filename =(char*) malloc(len+1); + xed_strncpy(*filename, imgline.FileName, len+1); + return 1; //success + } + return 0; //failed +} + +#endif diff --git a/examples/xed-dec-print.c b/examples/xed-dec-print.c new file mode 100644 index 0000000..621642a --- /dev/null +++ b/examples/xed-dec-print.c @@ -0,0 +1,62 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-dec-print.c +// decode and print + +#include "xed-interface.h" +#include "xed-examples-util.h" +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + // example instructions + xed_uint_t bytes = 2; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES] = { 0x00, 0x00 }; + + xed_tables_init(); + + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_error = xed_decode(&xedd, itext,bytes); + if (xed_error == XED_ERROR_NONE) + { + ok = xed_format_context(XED_SYNTAX_ATT, &xedd, buffer, BUFLEN, 0, 0, 0); + if (ok) { + printf("%s\n", buffer); + return 0; + } + printf("Error disassembling\n"); + return 1; + } + printf("Decoding error\n"); + return 1; + (void) argv; (void)argc; +} diff --git a/examples/xed-disas-elf.c b/examples/xed-disas-elf.c new file mode 100644 index 0000000..3e823ac --- /dev/null +++ b/examples/xed-disas-elf.c @@ -0,0 +1,647 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-disas-elf.h" // early, to get defines + +#if defined(XED_DECODER) && defined(XED_ELF_READER) + +//////////////////////////////////////////////////////////////////////////// + + +#include "xed-disas-elf.h" +#include +#if defined(XED_DWARF) +# include +# include +# include +#endif + +#include "xed-interface.h" +#include "xed-portability.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" +#include "avltree.h" + +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////// + + +// DWARF HANDLING + +#if defined(XED_DWARF) +static void dwarf_handler(Dwarf_Error err, Dwarf_Ptr errarg) +{ +} + +/* file 0 does not exist */ +typedef struct { + xed_uint32_t line; + xed_uint32_t file; +} line_number_entry_t; + +void line_number_entry_init(line_number_entry_t*p, + xed_uint32_t a_line, + xed_uint32_t a_file) +{ + p->line=a_line; + p->file=a_file; +} + +/* addresses -> line_number_entry_t values */ +static avl_tree_t line_number_table; //xed_uint64_t -> line_number_entry_t* + +/* start at 1, 0 means no file */ +static xed_uint32_t global_file_num = 1; + +/* global file num -> string */ +static avl_tree_t global_file_name_table; // xed_uint64_t -> char* + +/* local file num -> global file num. This one is restarted for each + * compilation unit. */ +static avl_tree_t file_name_table; // xed_uint64_t -> xed_uint64_t + +static char const* unknown = "Unknown"; + +static int find_line_number(xed_uint64_t addr, + char** file, + xed_uint32_t* line) +{ + line_number_entry_t* p = + (line_number_entry_t*) avl_find(&line_number_table, + addr); + if (!p) + return 0; + + char *q = (char*) avl_find(&global_file_name_table,p->file); + if (q) + *file = q; + else + *file = (char*)unknown; + *line = p->line; + return 1; +} + +//external interface, called indirectly +void find_line_number_info(xed_uint64_t addr) +{ + char* file_name; + xed_uint32_t line_number; + if (find_line_number(addr, + &file_name, + &line_number)) + { + printf(" # %s:%d", file_name, line_number); + } +} + + +static void read_dwarf_line_numbers(void* region, + unsigned int region_bytes) +{ + int dres; + Dwarf_Debug dbg; + Dwarf_Unsigned next_cu_offset;; + + elf_version(EV_CURRENT); + + Elf* elf = elf_memory(XED_STATIC_CAST(char*,region), region_bytes); + dres = dwarf_elf_init(elf, DW_DLC_READ, dwarf_handler, 0, &dbg, 0); + if (dres != DW_DLV_OK) + return; + + avl_tree_init(&line_number_table); + avl_tree_init(&global_file_name_table); + avl_tree_init(&file_name_table); + + while (1) + { + int i; + Dwarf_Die cu_die; + Dwarf_Half tag; + Dwarf_Line* line_buf; + Dwarf_Signed line_count; + + dres = dwarf_next_cu_header(dbg, 0, 0, 0, 0, &next_cu_offset, 0); + if (dres != DW_DLV_OK) + break; + // Doc says first die is compilation unit + if (dwarf_siblingof(dbg, 0, &cu_die, 0) != DW_DLV_OK) + continue; + if ( (dwarf_tag(cu_die, &tag, 0) != DW_DLV_OK) || + (tag != DW_TAG_compile_unit)) + { + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + continue; + } + dres = dwarf_srclines(cu_die, &line_buf, &line_count, 0); + if (dres != DW_DLV_OK) + { + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + continue; + } + for (i = 0; i < line_count; i++) + { + Dwarf_Addr line_addr; + Dwarf_Unsigned line_num, file_num; + Dwarf_Signed line_off; + Dwarf_Bool line_end; + char* file_name; + + dwarf_lineaddr(line_buf[i], &line_addr, 0); + dwarf_lineno(line_buf[i], &line_num, 0); + dwarf_line_srcfileno(line_buf[i], &file_num, 0); + dwarf_lineoff(line_buf[i], &line_off, 0); + dwarf_lineendsequence(line_buf[i], &line_end, 0); + + if (file_num) + { + dres = dwarf_linesrc(line_buf[i], &file_name, 0); + if (dres == DW_DLV_OK) { + + if ( avl_find(&file_name_table, file_num) == 0) + { + avl_insert(&file_name_table, + file_num, + (void*)(xed_addr_t)global_file_num,0); + + avl_insert(&global_file_name_table, + global_file_num, + xed_strdup(file_name),1); + global_file_num++; + } + dwarf_dealloc(dbg, file_name, DW_DLA_STRING); + } + } + xed_uint32_t gfn = (xed_uint32_t) (xed_addr_t) avl_find( + &file_name_table, file_num); + line_number_entry_t* p = + (line_number_entry_t*)malloc(sizeof(line_number_entry_t)); + line_number_entry_init(p, line_num, gfn); + avl_insert(&line_number_table, line_addr, p, 1); + + } /* for */ + avl_tree_clear(&file_name_table,0); + dwarf_srclines_dealloc(dbg, line_buf, line_count); + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + } /* while */ + dwarf_finish(dbg, 0); + elf_end(elf); +} + +#endif +//////////////////////////////////////////////////////////////////////////// + + +char* +lookup32(Elf32_Word stoffset, + void* start, + Elf32_Off offset) +{ + char* p = (char*)start + offset; + char* q = p + stoffset; + return q; +} + +char* +lookup64(Elf64_Word stoffset, + void* start, + Elf64_Off offset) +{ + char* p = (char*)start + offset; + char* q = p + stoffset; + return q; +} + +void xed_disas_elf_init(void) { + xed_register_disassembly_callback(xed_disassembly_callback_function); +} + + + +void +disas_test32(xed_disas_info_t* fi, + void* start, + Elf32_Off offset, + Elf32_Word size, + Elf32_Addr runtime_vaddr, + xed_symbol_table_t* symbol_table) +{ + + fi->s = (unsigned char*)start; + fi->a = (unsigned char*)start + offset; + fi->q = fi->a + size; // end of region + fi->runtime_vaddr = runtime_vaddr + fi->fake_base; + fi->runtime_vaddr_disas_start = fi->addr_start; + fi->runtime_vaddr_disas_end = fi->addr_end; + fi->symfn = get_symbol; + fi->caller_symbol_data = symbol_table; + fi->line_number_info_fn = 0; +#if defined(XED_DWARF) + fi->line_number_info_fn = find_line_number_info; +#endif + // pass in a function to retreive valid symbol names + xed_disas_test(fi); +} + +void +disas_test64(xed_disas_info_t* fi, + void* start, + Elf64_Off offset, + Elf64_Word size, + Elf64_Addr runtime_vaddr, + xed_symbol_table_t* symbol_table) +{ + fi->s = (unsigned char*)start; + fi->a = (unsigned char*)start + offset; + fi->q = fi->a + size; // end of region + fi->runtime_vaddr = runtime_vaddr + fi->fake_base; + fi->runtime_vaddr_disas_start = fi->addr_start; + fi->runtime_vaddr_disas_end = fi->addr_end; + fi->symfn = get_symbol; + fi->caller_symbol_data = symbol_table; + + fi->line_number_info_fn = 0; +#if defined(XED_DWARF) + fi->line_number_info_fn = find_line_number_info; +#endif + // pass in a function to retreive valid symbol names + xed_disas_test(fi); +} + +#if !defined(EM_IAMCU) +# define EM_IAMCU 3 +#endif + +int check_binary_32b(void* start) { + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + if ( elf_hdr->e_machine == EM_386 || + elf_hdr->e_machine == EM_IAMCU ) + return 1; + return 0; +} + + +void +process_elf32(xed_disas_info_t* fi, + void* start, + unsigned int length, + xed_symbol_table_t* symbol_table) +{ + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + Elf32_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf32_Shdr* shp = (Elf32_Shdr*) ((char*)start + shoff); + int sect_strings = elf_hdr->e_shstrndx; + int nsect = elf_hdr->e_shnum; + int i; + for(i=0;itarget_section) { + if (strcmp(fi->target_section, name)==0) + text = 1; + } + else if (shp[i].sh_flags & SHF_EXECINSTR) + text = 1; + } + + if (text) { + if (fi->xml_format == 0) { + printf("# SECTION " XED_FMT_D " ", i); + printf("%25s ", name); + printf("addr " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_addr)); + printf("offset " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_offset)); + printf("size " XED_FMT_LU " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_size)); + printf("type " XED_FMT_LU "\n", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_type)); + } + + xst_set_current_table(symbol_table,i); + disas_test32(fi, + start, shp[i].sh_offset, shp[i].sh_size, + shp[i].sh_addr, + symbol_table); + + } + + } + + (void) length;// pacify compiler +} + +/*-----------------------------------------------------------------*/ + +int check_binary_64b(void* start) { +#if !defined(EM_X86_64) /* EM_X86_64 is not present on android */ +# define EM_X86_64 62 +#endif +#if !defined(EM_L1OM) /* Oh, not zero */ +# define EM_L1OM 180 +#endif +#if !defined(EM_K1OM) /* Oh, not zero */ +# define EM_K1OM 181 +#endif + + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + if (elf_hdr->e_machine == EM_X86_64 || + elf_hdr->e_machine == EM_L1OM || + elf_hdr->e_machine == EM_K1OM) + return 1; + return 0; +} + +/*-----------------------------------------------------------------*/ +void +process_elf64(xed_disas_info_t* fi, + void* start, + unsigned int length, + xed_symbol_table_t* symbol_table) +{ + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + Elf64_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf64_Shdr* shp = (Elf64_Shdr*) ((char*)start + shoff); + Elf64_Half sect_strings = elf_hdr->e_shstrndx; + Elf64_Half nsect = elf_hdr->e_shnum; + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + unsigned int i; + xed_bool_t text = 0; + for( i=0;itarget_section) { + if (strcmp(fi->target_section, name)==0) + text = 1; + } + else if (shp[i].sh_flags & SHF_EXECINSTR) + text = 1; + } + + if (text) { + if (fi->xml_format == 0) { + printf("# SECTION " XED_FMT_U " ", i); + printf("%25s ", name); + printf("addr " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_addr)); + printf("offset " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_offset)); + printf("size " XED_FMT_LU "\n", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_size)); + } + xst_set_current_table(symbol_table,i); + disas_test64(fi, + start, shp[i].sh_offset, shp[i].sh_size, + shp[i].sh_addr, symbol_table); + } + } + (void) length;// pacify compiler +} + + +void read_symbols64(void* start, + Elf64_Off offset, + Elf64_Word size, + Elf64_Off string_table_offset, + xed_symbol_table_t* symtab) +{ + char* a = XED_STATIC_CAST(char*,start); + Elf64_Sym* p = XED_STATIC_CAST(Elf64_Sym*,a + offset); + Elf64_Sym* q = XED_STATIC_CAST(Elf64_Sym*,a + offset + size); + while(pst_info) == STT_FUNC) { + char* name = lookup64(p->st_name, start, string_table_offset); + if (xed_strlen(name) > 0) { + xst_add_local_symbol( + symtab, + XED_STATIC_CAST(xed_uint64_t,p->st_value), + name, p->st_shndx); + } + } + p++; + } +} + + +/*-----------------------------------------------------------------*/ + +static void print_comment64(unsigned int i, Elf64_Shdr* shp, char const* const s) +{ + fprintf(stdout,"# Found %s: %u",s, i); + // NOTE: casts required here because android gcc4.8.0 uses long long + // int for 64b integer and android-5 gcc490 uses long int. + fprintf(stdout," offset " XED_FMT_LX, (xed_uint64_t) shp[i].sh_offset); + fprintf(stdout," size " XED_FMT_LX "\n", (xed_uint64_t) shp[i].sh_size); +} +static void print_comment32(unsigned int i, Elf32_Shdr* shp, char const* const s) +{ + fprintf(stdout,"# Found %s: %u",s,i); + fprintf(stdout," offset %u",shp[i].sh_offset); + fprintf(stdout," size %u\n", shp[i].sh_size); +} + + + +void symbols_elf64(xed_disas_info_t* fi, + void* start, + xed_symbol_table_t* symtab) { + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + Elf64_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf64_Shdr* shp = (Elf64_Shdr*) ((char*)start + shoff); + Elf64_Half nsect = elf_hdr->e_shnum; + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + unsigned int i; + Elf64_Half sect_strings = elf_hdr->e_shstrndx; + Elf64_Off string_table_offset=0; + Elf64_Off dynamic_string_table_offset=0; + + /* find the string_table_offset and the dynamic_string_table_offset */ + for( i=0;ixml_format == 0) { + print_comment64(i,shp, "strtab"); + } + string_table_offset = shp[i].sh_offset; + } + if (strcmp(name,".dynstr")==0) { + if (fi->xml_format == 0) { + print_comment64(i,shp, "dynamic strtab"); + } + dynamic_string_table_offset = shp[i].sh_offset; + } + } + } + + /* now read the symbols */ + for( i=0;ixml_format == 0) { + print_comment64(i,shp, "symtab"); + } + read_symbols64(start,shp[i].sh_offset, shp[i].sh_size, + string_table_offset,symtab); + } + else if (shp[i].sh_type == SHT_DYNSYM) { + if (fi->xml_format == 0) { + print_comment64(i,shp, "dynamic symtab"); + } + read_symbols64(start,shp[i].sh_offset, shp[i].sh_size, + dynamic_string_table_offset, symtab); + } + } +} + + + +void read_symbols32(void* start, + Elf32_Off offset, + Elf32_Word size, + Elf32_Off string_table_offset, + xed_symbol_table_t* symtab) { + char* a = XED_STATIC_CAST(char*,start); + Elf32_Sym* p = XED_STATIC_CAST(Elf32_Sym*,a + offset); + Elf32_Sym* q = XED_STATIC_CAST(Elf32_Sym*,a + offset + size); + while(pst_info) == STT_FUNC) { + char* name = lookup32(p->st_name, start, string_table_offset); + if (xed_strlen(name) > 0) { + xst_add_local_symbol( + symtab, + XED_STATIC_CAST(xed_uint64_t,p->st_value), + name, p->st_shndx); + } + } + p++; + } +} + +void symbols_elf32(xed_disas_info_t* fi, + void* start, + xed_symbol_table_t* symtab) +{ + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + Elf32_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf32_Shdr* shp = (Elf32_Shdr*) ((char*)start + shoff); + Elf32_Half nsect = elf_hdr->e_shnum; + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + unsigned int i; + Elf32_Off string_table_offset=0; + Elf32_Off dynamic_string_table_offset=0; + int sect_strings = elf_hdr->e_shstrndx; + + /* find the string_table_offset and the dynamic_string_table_offset */ + for( i=0;ixml_format == 0) { + print_comment32(i,shp, "strtab"); + } + string_table_offset = shp[i].sh_offset; + } + if (strcmp(name,".dynstr")==0) { + if (fi->xml_format == 0) { + print_comment32(i,shp, "dynamic strtab"); + } + dynamic_string_table_offset = shp[i].sh_offset; + } + } + } + + /* now read the symbols */ + for( i=0;ixml_format == 0) { + print_comment32(i,shp, "symtab"); + } + read_symbols32(start,shp[i].sh_offset, shp[i].sh_size, + string_table_offset, symtab); + } + else if (shp[i].sh_type == SHT_DYNSYM) { + if (fi->xml_format == 0) { + print_comment32(i,shp, "dynamic symtab"); + } + read_symbols32(start,shp[i].sh_offset, shp[i].sh_size, + dynamic_string_table_offset, symtab); + } + } +} + + +void +xed_disas_elf(xed_disas_info_t* fi) +{ + void* region = 0; + unsigned int len = 0; + xed_symbol_table_t symbol_table; + + xed_disas_elf_init(); + xed_map_region(fi->input_file_name, ®ion, &len); + xed_symbol_table_init(&symbol_table); + +#if defined(XED_DWARF) + if (fi->line_numbers) + read_dwarf_line_numbers(region,len); +#endif + + if (check_binary_64b(region)) { + if (fi->sixty_four_bit == 0 && fi->use_binary_mode) { + /* modify the default dstate values because we were not expecting a + * 64b binary */ + fi->dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + + symbols_elf64(fi,region, &symbol_table); + process_elf64(fi, region, len, &symbol_table); + } + else if (check_binary_32b(region)) { + symbols_elf32(fi, region, &symbol_table); + process_elf32(fi, region, len, &symbol_table); + } + else { + fprintf(stderr,"Not a recognized 32b or 64b ELF binary.\n"); + exit(1); + } + if (fi->xml_format == 0){ + xed_print_decode_stats(fi); + xed_print_encode_stats(fi); + } +} + + + +#endif +//////////////////////////////////////////////////////////////////////////// + diff --git a/examples/xed-disas-elf.h b/examples/xed-disas-elf.h new file mode 100644 index 0000000..95a101b --- /dev/null +++ b/examples/xed-disas-elf.h @@ -0,0 +1,34 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-elf.h + +#if !defined(_XED_DISAS_ELF_H_) +# define _XED_DISAS_ELF_H_ +#if defined(__linux) || defined(__linux__) || defined(__FreeBSD__) +# define XED_ELF_READER +#endif +# if defined(XED_ELF_READER) + + +#include "xed-interface.h" +#include "xed-examples-util.h" + +void xed_disas_elf(xed_disas_info_t* fi); + +# endif +#endif diff --git a/examples/xed-disas-hex.c b/examples/xed-disas-hex.c new file mode 100644 index 0000000..b09157e --- /dev/null +++ b/examples/xed-disas-hex.c @@ -0,0 +1,111 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// to avoid empty compilation unit on no-decoder compiles +#include "xed-interface.h" + +#if defined(XED_DECODER) +#include "xed-portability.h" +#include "xed-examples-util.h" +#include "xed-disas-hex.h" + +#include +#include + + + +static FILE* +open_file(char const* const path, char const* const mode) +{ + FILE* f; +#if defined(XED_MSVC8_OR_LATER) && !defined(PIN_CRT) + errno_t err; + err = fopen_s(&f,path, mode); +#else + int err=0; + f = fopen(path, mode); + err = (f==0); +#endif + if (err) { + fprintf(stderr, "Could not open file: %s\n", path); + exit(1); + } + return f; +} + +static int read_byte(FILE* f, xed_uint8_t* b) { + int r; + unsigned int i; +#if defined(_WIN32) && !defined(PIN_CRT) + r = fscanf_s(f,"%2x", &i); +#else + r = fscanf(f,"%2x", &i); +#endif + if (b) + *b = (xed_uint8_t)i; + return r; +} + +void +xed_disas_hex(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + unsigned int len = 0; + unsigned int i = 0; + xed_uint8_t b = 0; + FILE* f = 0; + + // read file once to get length + f = open_file(fi->input_file_name, "r"); + while (read_byte(f,0) != -1) + { + len++; + } + fclose(f); + + region = (xed_uint8_t*) malloc(len); + if (region == 0) { + fprintf(stderr,"ERROR: Could not malloc region for hex file\n"); + exit(1); + } + + // read file again to read the bytes + f = open_file(fi->input_file_name, "r"); + while (read_byte(f,&b) != -1) + { + assert(i < len); + region[i++] = b; + } + fclose(f); + assert(i==len); + + fi->s = (unsigned char*)region; + fi->a = (unsigned char*)region; + fi->q = (unsigned char*)(region) + len; // end of region + fi->runtime_vaddr = 0; + fi->runtime_vaddr_disas_start = 0; + fi->runtime_vaddr_disas_end = 0; + fi->symfn = 0; + fi->caller_symbol_data = 0; + fi->line_number_info_fn = 0; + xed_disas_test(fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + +#endif diff --git a/examples/xed-disas-hex.h b/examples/xed-disas-hex.h new file mode 100644 index 0000000..d4debfe --- /dev/null +++ b/examples/xed-disas-hex.h @@ -0,0 +1,30 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_DISAS_HEX_H_) +# define _XED_DISAS_HEX_H_ + + +#include "xed-interface.h" +#include "xed-examples-util.h" + +void +xed_disas_hex(xed_disas_info_t* fi); + + +#endif diff --git a/examples/xed-disas-macho.c b/examples/xed-disas-macho.c new file mode 100644 index 0000000..f8a0dbd --- /dev/null +++ b/examples/xed-disas-macho.c @@ -0,0 +1,458 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-macho.cpp + +#include "xed-interface.h" // to get defines +#if defined(__APPLE__) && defined(XED_DECODER) + +// mac specific headers +#include +#include +#include +#include + +#include "xed-disas-macho.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" + +#include + +//////////////////////////////////////////////////////////////////////////// + +xed_uint32_t +swap_endian(xed_uint32_t x) +{ + xed_uint32_t r = 0; + xed_uint32_t t = x; + xed_uint_t i; + for(i=0;i<4;i++) + { + xed_uint8_t b = t; + r =(r << 8) | b; + t = t >> 8; + } + return r; +} + +xed_uint32_t +read_fat_header_narch(xed_uint8_t const* const current_position) +{ + struct fat_header* fh = + XED_CAST(struct fat_header*,current_position); + + // we are little endian looking at big endian data + if (fh->magic == FAT_CIGAM) + { + xed_uint32_t narch = swap_endian(fh->nfat_arch); + return narch; + } + return 0; +} + +xed_bool_t +read_fat_header(xed_uint8_t const* const current_position, + xed_uint32_t fat_arch_slot, + xed_uint32_t* offset, + xed_uint32_t* size) +{ + struct fat_header* fh = + XED_CAST(struct fat_header*,current_position); + + // we are little endian looking at big endian data + if (fh->magic == FAT_CIGAM) + { + struct fat_arch* fa = + XED_CAST(struct fat_arch*,current_position + + sizeof(struct fat_header) + + fat_arch_slot*sizeof(struct fat_arch) ); + const cpu_type_t cpu_type = swap_endian(fa->cputype); + + if ((cpu_type & CPU_TYPE_I386) != 0) + { + if ((cpu_type & CPU_ARCH_ABI64) != 0) + printf ("# x86 64b\n"); + else + printf ("# x86 32b\n"); + *offset = swap_endian(fa->offset); + *size = swap_endian(fa->size); + return 1; + } + } + return 0; +} + + +static xed_bool_t +executable(xed_uint32_t flags) +{ + return ( (flags & S_ATTR_PURE_INSTRUCTIONS) !=0 || + (flags & S_ATTR_SOME_INSTRUCTIONS) !=0 ); +} + +void +process_segment32( xed_uint_t* sectoff, + xed_disas_info_t* decode_info, + xed_uint8_t* start, + xed_uint8_t* segment_position, + unsigned int bytes, + xed_symbol_table_t* symbol_table, + xed_uint64_t vmaddr) +{ + struct segment_command* sc = + XED_CAST(struct segment_command*,segment_position); + xed_uint8_t* start_of_section_data = + segment_position + sizeof(struct segment_command); + unsigned int i; + // look through the array of section headers for this segment. + for( i=0; i< sc->nsects;i++) + { + struct section* sp = + XED_CAST(struct section*, + start_of_section_data + i *sizeof(struct section)); + + if (executable(sp->flags)) + { + // this section is executable. Go get it and process it. + xed_uint8_t* section_text = start + sp->offset; + xed_uint32_t runtime_vaddr = sp->addr; + + decode_info->s = start; + decode_info->a = section_text; + decode_info->q = section_text + sp->size; + decode_info->runtime_vaddr = runtime_vaddr + decode_info->fake_base; + decode_info->runtime_vaddr_disas_start = decode_info->addr_start; + decode_info->runtime_vaddr_disas_end = decode_info->addr_end; + decode_info->symfn = get_symbol; + decode_info->caller_symbol_data = symbol_table; + decode_info->input_file_name = decode_info->input_file_name; + decode_info->line_number_info_fn = 0; + xst_set_current_table(symbol_table,i+1 + *sectoff); + xed_disas_test(decode_info); + + } + } + *sectoff += sc->nsects; +} + + +void +process_segment64( xed_uint_t* sectoff, + xed_disas_info_t* decode_info, + xed_uint8_t* start, + xed_uint8_t* segment_position, + unsigned int bytes, + xed_symbol_table_t* symbol_table, + xed_uint64_t vmaddr) +{ + struct segment_command_64* sc = + XED_CAST(struct segment_command_64*,segment_position); + xed_uint8_t* start_of_section_data = + segment_position + sizeof(struct segment_command_64); + unsigned int i; + /* modify the default dstate values because we were not expecting a + * 64b binary */ + decode_info->dstate.mmode = XED_MACHINE_MODE_LONG_64; + // look through the array of section headers for this segment. + for( i=0; i< sc->nsects;i++) + { + struct section_64* sp = + XED_CAST(struct section_64*, + start_of_section_data + i *sizeof(struct section_64)); + if (executable(sp->flags)) + { + + // this section is executable. Go get it and process it. + xed_uint8_t* section_text = start + sp->offset; + xed_uint64_t runtime_vaddr = sp->addr; + + decode_info->s = start; + decode_info->a = section_text; + decode_info->q = section_text + sp->size; + decode_info->runtime_vaddr = runtime_vaddr + decode_info->fake_base; + decode_info->runtime_vaddr_disas_start = decode_info->addr_start; + decode_info->runtime_vaddr_disas_end = decode_info->addr_end; + decode_info->symfn = get_symbol; + decode_info->caller_symbol_data = symbol_table; + decode_info->input_file_name = decode_info->input_file_name; + decode_info->line_number_info_fn = 0; + xst_set_current_table(symbol_table,i + 1 + *sectoff); + xed_disas_test(decode_info); + + } + + } + *sectoff += sc->nsects; +} + +//////////////////////////////////////////////////////////////////////////// + + +void process_symbols32(xed_disas_info_t* decode_info, + xed_uint8_t* pos, + xed_uint8_t* current_position, + xed_symbol_table_t* symbol_table) { + struct symtab_command* symtab = + XED_CAST(struct symtab_command*,current_position); + /* symbols */ + xed_uint32_t nsyms = symtab->nsyms; + xed_uint8_t* symoff = pos + symtab->symoff; + /* strings table */ + xed_uint8_t* stroff = pos + symtab->stroff; + /* xed_uint8_t* stroff_end = stroff + symtab->strsize; */ + xed_uint32_t i; + struct nlist* p; + p = XED_CAST(struct nlist*, symoff); + for(i=0;in_type & N_STAB) == 0 && + (p->n_type & N_TYPE) == N_SECT) + { + char* str=0; + str = XED_CAST(char*,stroff + p->n_un.n_strx); + + xst_add_local_symbol( + symbol_table, + XED_CAST(xed_uint64_t,p->n_value), + str, + p->n_sect); + } + p++; + } +} + +void process_symbols64(xed_disas_info_t* decode_info, + xed_uint8_t* pos, + xed_uint8_t* current_position, + xed_symbol_table_t* symbol_table) { + struct symtab_command* symtab = + XED_CAST(struct symtab_command*,current_position); + /* symbols */ + xed_uint32_t nsyms = symtab->nsyms; + xed_uint8_t* symoff = pos + symtab->symoff; + /* strings table */ + xed_uint8_t* stroff = pos + symtab->stroff; + xed_uint32_t i; + struct nlist_64* p; + + p = XED_CAST(struct nlist_64*, symoff); + for(i=0;in_type & N_STAB) == 0 && + (p->n_type & N_TYPE) == N_SECT) + { + char* str=0; + str = XED_CAST(char*,stroff + p->n_un.n_strx); + + xst_add_local_symbol( + symbol_table, + XED_CAST(xed_uint64_t,p->n_value), + str, + p->n_sect); + } + p++; + } +} + + +void process32(xed_disas_info_t* decode_info, + xed_uint8_t* current_position, + struct mach_header* mh, + xed_uint8_t* pos) +{ + xed_symbol_table_t symbol_table; + xed_uint_t i, sectoff=0; + if (CLIENT_VERBOSE2) + printf("Number of load command sections = %d\n", mh->ncmds); + // load commands point to segments which contain sections. + decode_info->dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + xed_uint8_t* tmp_current_position = current_position; + xed_symbol_table_init(&symbol_table); + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,tmp_current_position); + // FIXME: not handling LD_DYSYMTAB + if (lc->cmd == LC_SYMTAB) { + process_symbols32(decode_info, + pos, + tmp_current_position, + &symbol_table); + } + tmp_current_position += lc->cmdsize; + } + + for(i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,current_position); + + if (CLIENT_VERBOSE2) + printf("load command %d\n", i); + if (lc->cmd == LC_SEGMENT) { + if (CLIENT_VERBOSE2) + printf("\tload command %d is a LC_SEGMENT\n", i); + // we add the FAT offset to the start pointer to get to the + // relative start point. + struct segment_command* sc = + XED_CAST(struct segment_command*,lc); + process_segment32( §off, + decode_info, + pos, + current_position, + lc->cmdsize , + &symbol_table, + sc->vmaddr); + } + current_position += lc->cmdsize; + } +} +void process64(xed_disas_info_t* decode_info, + xed_uint8_t* current_position, + struct mach_header_64* mh, + xed_uint8_t* pos) +{ + + xed_uint_t i, sectoff=0; + xed_symbol_table_t symbol_table; + if (CLIENT_VERBOSE2) + printf("Number of load command sections = %d\n", mh->ncmds); + // load commands point to segments which contain sections. + xed_uint8_t* tmp_current_position = current_position; + xed_symbol_table_init(&symbol_table); + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,tmp_current_position); + // FIXME: not handling LD_DYSYMTAB + if ( lc->cmd == LC_SYMTAB ) { + process_symbols64(decode_info, + pos, + tmp_current_position, + &symbol_table); + } + tmp_current_position += lc->cmdsize; + } + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,current_position); + + if (CLIENT_VERBOSE2) + printf("load command %x\n", i); + if (lc->cmd == LC_SEGMENT_64) { + if (CLIENT_VERBOSE2) + printf("\tload command %d is a LC_SEGMENT\n", i); + // we add the FAT offset to the start pointer to get to the + // relative start point. + struct segment_command_64* sc = + XED_CAST(struct segment_command_64*,lc); + process_segment64( §off, + decode_info, + pos, + current_position, + lc->cmdsize, + &symbol_table, + sc->vmaddr ); + } + current_position += lc->cmdsize; + } +} + + +void +process_macho(xed_uint8_t* start, + unsigned int length, + xed_disas_info_t* decode_info) + +{ + xed_uint8_t* base_pos = start; + xed_uint32_t narch = read_fat_header_narch(base_pos); + + + xed_uint32_t lim = 1; + + // we have one section if not a fat binary. + if (narch > lim) + lim = narch; + + for (xed_uint32_t fat_arch_slot = 0; fat_arch_slot < lim; fat_arch_slot++) + { + xed_uint32_t offset=0; + xed_uint32_t size; + xed_bool_t okay = 0; + + if (narch) // for fat binaries + okay = read_fat_header(base_pos, fat_arch_slot, &offset, &size); + + if (CLIENT_VERBOSE2 && !okay) + if (decode_info->xml_format == 0) + xedex_dwarn("Could not find x86 section of fat binary " + "-- checking for mach header"); + if (CLIENT_VERBOSE2) + printf("Offset of load sections = %x\n", offset); + + xed_uint8_t* current_position = base_pos + offset; + + if (narch > 0) + printf("# FAT ARCH SECTION = %d\n", fat_arch_slot); + struct mach_header* mh = + XED_CAST(struct mach_header*,current_position); + struct mach_header_64* mh64 = + XED_CAST(struct mach_header_64*,current_position); + if (mh->magic == MH_MAGIC) { + current_position += sizeof(struct mach_header); + process32(decode_info, + current_position, + mh, + start+offset); + } + else if (mh64->magic == MH_MAGIC_64) { + current_position += sizeof(struct mach_header_64); + process64(decode_info, + current_position, + mh64, + start+offset); + } + else + xedex_derror("Could not find mach header"); + } // for + +} + +void xed_disas_macho_init() { + xed_register_disassembly_callback(xed_disassembly_callback_function); +} + + +void +xed_disas_macho(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + void* vregion = 0; + unsigned int len = 0; + + xed_disas_macho_init(); + xed_map_region(fi->input_file_name, &vregion, &len); + + region = XED_CAST(xed_uint8_t*,vregion); + process_macho(region, len, fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + + + +#endif diff --git a/examples/xed-disas-macho.h b/examples/xed-disas-macho.h new file mode 100644 index 0000000..f5b484d --- /dev/null +++ b/examples/xed-disas-macho.h @@ -0,0 +1,29 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-macho.H +#if !defined(_XED_DISAS_MACHO_H_) +# define _XED_DISAS_MACHO_H_ + +# if defined(__APPLE__) +# include "xed-interface.h" +# include "xed-examples-util.h" + +void +xed_disas_macho(xed_disas_info_t* fi); +# endif +#endif diff --git a/examples/xed-disas-pecoff.cpp b/examples/xed-disas-pecoff.cpp new file mode 100644 index 0000000..94a7869 --- /dev/null +++ b/examples/xed-disas-pecoff.cpp @@ -0,0 +1,701 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-pecoff.cpp + +//// ONLY COMPILES IF -mno-cygwin is thrown on to GCC compilations + +#include "xed-build-defines.h" // for XED_DECODER +#if defined(XED_DECODER) +#include +#include + + +extern "C" { +#include "xed-portability.h" // for the XED_ macros used on next line +} +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + // to enable the wow64 redirection function on MSVC8 +# define _WIN32_WINNT 0x0501 +#endif +#include +#include + +// xed headers -- THESE MUST BE AFTER THE WINDOWS HEADERS + +extern "C" { +#include "xed-disas-pecoff.h" + +// This really must be after the windows.h include +#include "xed-symbol-table.h" +} + +#if defined(XED_DBGHELP) +# include "udhelp.H" // dbghelp interface +#endif +using namespace std; + +static void +windows_error(const char* syscall, + const char* filename) +{ + printf("Mapped file:: %s",syscall); + printf(" for file %s failed: ", filename); + switch (GetLastError()) + { + case 2: + printf("File not found"); + break; + case 3: + printf("Path not found"); + break; + case 5: + printf("Access denied"); + break; + case 15: + printf("Invalid drive"); + break; + default: + printf("error code %u", + XED_STATIC_CAST(xed_uint32_t,GetLastError())); + break; + } + xedex_derror("Exiting."); +} + +typedef int (WINAPI *fptr_t)(void*); + +static fptr_t find_fn_ptr(const char* function_name) { + fptr_t p; + + p = (fptr_t) GetProcAddress( + GetModuleHandle(TEXT("kernel32.dll")), + function_name); + return p; +} + +static int find_wow64_redir(fptr_t* disable, fptr_t* revert) { + *disable = find_fn_ptr("Wow64DisableWow64FsRedirection"); + *revert = find_fn_ptr("Wow64RevertWow64FsRedirection"); + if (*disable && *revert) + return 1; // success + return 0; +} + +class pecoff_reader_t +{ + /// NT handle for the open file. + void* file_handle_; + + /// NT handle for the memory mapping. + void* map_handle_; + + void* base_; + xed_bool_t okay_; + xed_bool_t sixty_four_bit_; + + const IMAGE_FILE_HEADER* ifh; + const IMAGE_SECTION_HEADER* hdr; + const IMAGE_SECTION_HEADER* orig_hdr; + unsigned int nsections; + xed_uint64_t image_base; + xed_bool_t verbose; + + +public: + xed_uint32_t section_index; + + pecoff_reader_t(int arg_verbose=1) + { + verbose = arg_verbose; + init(); + } + ~pecoff_reader_t() + { + close(); + } + + void* base() const { return base_; } + xed_bool_t okay() const { return okay_; } + xed_bool_t sixty_four_bit() const { return sixty_four_bit_; } + + void + init() + { + file_handle_ = INVALID_HANDLE_VALUE; + map_handle_ = INVALID_HANDLE_VALUE; + okay_ = false; + sixty_four_bit_ = false; + + hdr=0; + orig_hdr=0; + nsections=0; + image_base=0; + section_index=0; + } + + void + close() + { + if (base_) + { + UnmapViewOfFile(base_); + } + if (map_handle_ != INVALID_HANDLE_VALUE) + { + CloseHandle(map_handle_); + } + if (file_handle_ != INVALID_HANDLE_VALUE) + { + CloseHandle(file_handle_); + } + + init(); + } + + + xed_bool_t + map_region(const char* input_file_name, + void*& vregion, + xed_uint32_t& len) + { + okay_ = false; + +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + bool disabled_redirection = false; + void* old=0; + fptr_t disable, revert; + if (find_wow64_redir(&disable, &revert)) + if ( (*disable)(&old) ) + disabled_redirection = true; +#endif + + file_handle_ = CreateFile(input_file_name, + GENERIC_READ, + FILE_SHARE_READ, + NULL, + OPEN_EXISTING, + FILE_FLAG_NO_BUFFERING + FILE_ATTRIBUTE_READONLY, + NULL); + +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + if (disabled_redirection) { + if (! (*revert)(old)) { + fprintf(stderr,"Could not re-enable wow64 redirection. Dying...\n"); + exit(1); + } + } +#endif + if (file_handle_ == INVALID_HANDLE_VALUE) { + windows_error("CreateFile", input_file_name); + } + + map_handle_ = CreateFileMapping(file_handle_, + NULL, + PAGE_READONLY, + 0, + 0, + NULL); + + if (map_handle_ == INVALID_HANDLE_VALUE) { + windows_error("CreateFileMapping", input_file_name); + } + + base_ = MapViewOfFile(map_handle_, + FILE_MAP_READ, 0, 0, 0); + if (base_ != NULL) { + okay_ = true; + vregion = base_; + len = 0; //FIXME + return true; + } + CloseHandle(map_handle_); + map_handle_ = INVALID_HANDLE_VALUE; + + CloseHandle(file_handle_); + file_handle_ = INVALID_HANDLE_VALUE; + return false; + + } + + + xed_bool_t read_header() { + if (! parse_nt_file_header(&nsections, &image_base, &hdr)) { + xedex_derror("Could not read nt file header"); + return false; + } + + orig_hdr=hdr; + return true; + } + + + void read_coff_symbols() { + xed_uint32_t i; + xed_uint32_t sym_offset = ifh->PointerToSymbolTable; + xed_uint32_t nsym = ifh->NumberOfSymbols; + PIMAGE_SYMBOL p = (PIMAGE_SYMBOL)((char*)base() + sym_offset); + char* string_table_base = (char*)(p+nsym); + for(i=0;iCharacteristics); + if ((jhdr->Characteristics & IMAGE_SCN_CNT_CODE) == IMAGE_SCN_CNT_CODE) + { + printf(" CODE"); + xed_uint8_t* section_start; + xed_uint32_t section_size; + xed_uint64_t virtual_addr; + + virtual_addr = jhdr->VirtualAddress + image_base; + section_size = (jhdr->Misc.VirtualSize > 0 ? + jhdr->Misc.VirtualSize + : jhdr->SizeOfRawData); + section_start = (xed_uint8_t*)ptr_add(base_, + jhdr->PointerToRawData); + + printf(" VAddr " XED_FMT_LX16, virtual_addr); + printf(" SecStart %p" , section_start); + printf(" %016I64x" , (xed_uint64_t)jhdr->PointerToRawData); + printf(" SecSize " XED_FMT_08X,section_size); + } + printf("\n"); + } + } + + xed_bool_t + module_section_info( + const char* secname, + xed_uint8_t*& section_start, + xed_uint32_t& section_size, + xed_uint64_t& virtual_addr) + { + unsigned int i,ii; + char my_name[IMAGE_SIZEOF_SHORT_NAME]; + unsigned int match_len = 0; + + // Extract the name into a 0-padded 8 byte string. + if (secname) { + memset(my_name,0,IMAGE_SIZEOF_SHORT_NAME); + for( i=0;i(strlen(secname)); + if (match_len > IMAGE_SIZEOF_SHORT_NAME) + match_len = IMAGE_SIZEOF_SHORT_NAME; + } + + // There are section names that LOOK like .text$x but they really have + // a null string embedded in them. So when you strcmp, you hit the + // null. + + + for ( ii = section_index; ii < nsections; ii++, hdr++) + { + int found = 0; + if (hdr->SizeOfRawData == 0) + continue; + /* If no section name, match codde sections. If we have a + section name that matches , just disasssemble whatever they + want. */ + if (secname==0) { + if ((hdr->Characteristics & IMAGE_SCN_CNT_CODE) == + IMAGE_SCN_CNT_CODE) + found = 1; + } + else if (strncmp(reinterpret_cast(hdr->Name), + my_name, match_len) == 0) + { + found = 1; + } + if (found) { + // Found it. Extract the info and return. + virtual_addr = hdr->VirtualAddress + image_base; + section_size = (hdr->Misc.VirtualSize > 0 ? + hdr->Misc.VirtualSize + : hdr->SizeOfRawData); + section_start = (xed_uint8_t*)ptr_add(base_, + hdr->PointerToRawData); + section_index = ii+1; + hdr++; + return true; + } + } + section_index = ii; + return false; + } + +private: + static inline const void* + ptr_add(const void* ptr, unsigned int n) { + return static_cast(ptr)+n; + } + + xed_bool_t + is_valid_module() { + // Point to the DOS header and check it. + const IMAGE_DOS_HEADER* dh = static_cast(base_); + if (dh->e_magic != IMAGE_DOS_SIGNATURE) + return false; + + // Point to the PE signature word and check it. + const DWORD* sig = static_cast(ptr_add(base_, dh->e_lfanew)); + + // This must be a valid PE file with a valid DOS header. + if (*sig != IMAGE_NT_SIGNATURE) + return false; + + return true; + } + xed_bool_t + parse_nt_file_header(unsigned int* pnsections, + xed_uint64_t* pimage_base, + const IMAGE_SECTION_HEADER** phdr) + { + // Oh joy - the format of a .obj file on Windows is *different* + // from the format of a .exe file. Deal with that. + + // Check the header to see if this is a valid .exe file + if (is_valid_module()) + { + // Point to the DOS header. + const IMAGE_DOS_HEADER* dh = + static_cast(base_); + + // Point to the COFF File Header (just after the signature) + ifh = static_cast(ptr_add(base_, + dh->e_lfanew + 4)); + } + else + { + // Maybe this is a .obj file, which starts with the image file header + ifh = static_cast(base_); + } + + + +#if !defined(IMAGE_FILE_MACHINE_AMD64) +# define IMAGE_FILE_MACHINE_AMD64 0x8664 +#endif + + if (ifh->Machine == IMAGE_FILE_MACHINE_I386) { + if (verbose) + printf("# IA32 format\n"); + sixty_four_bit_ = false; + } + else if (ifh->Machine == IMAGE_FILE_MACHINE_AMD64) { + if (verbose) + printf("# Intel64 format\n"); + sixty_four_bit_ = true; + } + else { + // We only support Windows formats on IA32 and Intel64 + return false; + } + + *pimage_base = 0; + + // Very important to use the 32b header here because the + // unqualified IMAGE_OPTIONAL_HEADER gets the wrong version on + // win64! + const IMAGE_OPTIONAL_HEADER32* opthdr32 + = static_cast(ptr_add(ifh, sizeof(*ifh))); + + // Cygwin's w32api winnt.h header doesn't distinguish 32 and 64b. +#if !defined(IMAGE_NT_OPTIONAL_HDR32_MAGIC) +# define IMAGE_NT_OPTIONAL_HDR32_MAGIC IMAGE_NT_OPTIONAL_HDR_MAGIC +#endif + // And it lacks the definition for 64b headers +#if !defined(IMAGE_NT_OPTIONAL_HDR64_MAGIC) +# define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b +#endif + + if (ifh->SizeOfOptionalHeader > 0) + { + if (opthdr32->Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) + { + *pimage_base = opthdr32->ImageBase; + } + else if (opthdr32->Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) + { +#if defined(_MSC_VER) +# if _MSC_VER >= 1400 + const IMAGE_OPTIONAL_HEADER64* opthdr64 = + static_cast( + ptr_add(ifh, sizeof(*ifh))); + *pimage_base = opthdr64->ImageBase; +# else + xedex_derror("No support for 64b optional headers because " + "older MS compilers do not have the type yet"); +# endif +#else + xedex_derror("No support for 64b optional headers because " + "cygwin does nt have the type yet"); + return false; +#endif + } + else + { + // Optional header is not a form we recognize, so punt. + return false; + } + } + + // Point to the first of the Section Headers + *phdr = static_cast(ptr_add(opthdr32, + ifh->SizeOfOptionalHeader)); + *pnsections = ifh->NumberOfSections; + return true; + } + + + +}; + +//////////////////////////////////////////////////////////////////////////// +#if defined(XED_USING_DEBUG_HELP) +static dbg_help_client_t dbg_help; + +extern "C" void +print_file_and_line(xed_uint64_t addr) +{ + char* filename; + xed_uint32_t line, column; + + if (dbg_help.get_file_and_line(addr, &filename, &line, &column)) + { + if (column) + printf( " # %s:%d.%d", filename, line, column); + else + printf( " # %s:%d", filename, line); + free(filename); + } +} + +char* windows_symbols_callback(xed_uint64_t addr, void* closure) { + dbg_help_client_t* p = (dbg_help_client_t*)closure; + char buffer[2000]; + int r = p->get_symbol(addr, buffer, sizeof(char)*2000); + if (r == 0) { + int n = (int)strlen(buffer)+1; + char* symbol = new char[n]; + symbol[0]=0; + xed_strncat(symbol, buffer, n); + return symbol; + } + else { + return 0; + } +} + +int xed_pecoff_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data) +{ + dbg_help_client_t* p = (dbg_help_client_t*)caller_data; + int r = p->get_symbol(address, symbol_buffer, buffer_length, offset); + if (r == 0) + return 1; + return 0; +} +#endif + +void xed_disas_pecoff_init() { +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) { + //xed_register_disassembly_callback(xed_pecoff_callback_function); + xed_register_disassembly_callback(xed_disassembly_callback_function); + } +#endif +} + +bool dot_obj(const char* s) { + int len = (int)strlen(s); + const char* p = s + len - 4; + if (strcmp(p,".obj") == 0 || + strcmp(p,".OBJ") == 0) + return true; + return false; +} + +void +process_pecoff(xed_uint8_t* start, + unsigned int length, + xed_disas_info_t& decode_info, + pecoff_reader_t& reader) +{ + xed_uint8_t* section_start = 0; + xed_uint32_t section_size = 0; + xed_uint64_t runtime_vaddr = 0; + + xed_bool_t okay = true; + xed_bool_t found = false; +#if defined(XED_USING_DEBUG_HELP) + int init_ok = dbg_help.init( decode_info.input_file_name, + decode_info.symbol_search_path); + if (init_ok == 0) { + if (CLIENT_VERBOSE0) { + if (dot_obj(decode_info.input_file_name)) + fprintf(stderr, + "WARNING: No COFF symbol support yet for OBJ files.\n"); + else + fprintf(stderr, + "WARNING: DBGHELP initialization failed. " + "Please copy the appropriate\n" + " (ia32,intel64) dbghelp.dll to the directory " + "where your xed.exe exists.\n" + " Version 6.9.3.113 or later is required.\n"); + fflush(stderr); + } + } +#endif + xed_disas_pecoff_init(); + + while(okay) { + okay = reader.module_section_info(decode_info.target_section, + section_start, + section_size, + runtime_vaddr); + if (okay) { + if (decode_info.xml_format == 0) + printf ("# SECTION %u\n", reader.section_index-1); + found = true; + + decode_info.s = XED_REINTERPRET_CAST(unsigned char*,start); + decode_info.a = + XED_REINTERPRET_CAST(unsigned char*,section_start); + decode_info.q = XED_REINTERPRET_CAST(unsigned char*, + section_start + section_size); + + decode_info.runtime_vaddr = runtime_vaddr + decode_info.fake_base; + decode_info.runtime_vaddr_disas_start = decode_info.addr_start; + decode_info.runtime_vaddr_disas_end = decode_info.addr_end; + +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) { + decode_info.line_number_info_fn = print_file_and_line; + + // This version is slow + //decode_info.symfn = windows_symbols_callback; + //decode_info.caller_symbol_data = &dbg_help; + + // This version is faster + decode_info.symfn = get_symbol; + decode_info.caller_symbol_data = &(dbg_help.sym_tab); + } +#endif + + xed_disas_test(&decode_info); + } + } + if (!found) + xedex_derror("text section not found"); +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) + dbg_help.cleanup(); +#endif + (void) length; +} + + + + +extern "C" void +xed_disas_pecoff(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + void* vregion = 0; + xed_uint32_t len = 0; + pecoff_reader_t image_reader(fi->xml_format==0); + xed_bool_t okay = image_reader.map_region(fi->input_file_name, + vregion, + len); + if (!okay) + xedex_derror("image read failed"); + if (CLIENT_VERBOSE1) + printf("Mapped image\n"); + image_reader.read_header(); + //image_reader.print_section_headers(); + + //image_reader.read_coff_symbols(); + region = XED_REINTERPRET_CAST(xed_uint8_t*,vregion); + + if (image_reader.sixty_four_bit() && + fi->sixty_four_bit == 0 && + fi->use_binary_mode) + { + /* modify the default dstate values because we were not expecting a + * 64b binary */ + fi->dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + + process_pecoff(region, len, *fi, image_reader); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + + + +#endif diff --git a/examples/xed-disas-pecoff.h b/examples/xed-disas-pecoff.h new file mode 100644 index 0000000..7ee3a66 --- /dev/null +++ b/examples/xed-disas-pecoff.h @@ -0,0 +1,30 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-pecoff.h + + +#if !defined(_XED_DISAS_PECOFF_H_) +# define _XED_DISAS_PECOFF_H_ + +# include "xed-interface.h" +# include "xed-examples-util.h" + +void xed_disas_pecoff(xed_disas_info_t* fi); + +#endif + diff --git a/examples/xed-disas-raw.c b/examples/xed-disas-raw.c new file mode 100644 index 0000000..29fd404 --- /dev/null +++ b/examples/xed-disas-raw.c @@ -0,0 +1,46 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file disas-raw.c + +#include "xed-interface.h" +#if defined(XED_DECODER) +#include "xed-portability.h" +#include "xed-examples-util.h" +#include "xed-disas-raw.h" + +void xed_disas_raw(xed_disas_info_t* fi) +{ + void* region = 0; + unsigned int len = 0; + xed_map_region(fi->input_file_name, ®ion, &len); + + fi->s = (unsigned char*)region; + fi->a = (unsigned char*)region; + fi->q = (unsigned char*)(region) + len; // end of region + fi->runtime_vaddr = 0; + fi->runtime_vaddr_disas_start = 0; + fi->runtime_vaddr_disas_end = 0; + fi->symfn = 0; + fi->caller_symbol_data = 0; + fi->line_number_info_fn = 0; + xed_disas_test(fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + +#endif diff --git a/examples/xed-disas-raw.h b/examples/xed-disas-raw.h new file mode 100644 index 0000000..1a2e5fc --- /dev/null +++ b/examples/xed-disas-raw.h @@ -0,0 +1,28 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_DISAS_RAW_H_) +# define _XED_DISAS_RAW_H_ + +#include "xed-interface.h" +#include "xed-examples-util.h" + +void xed_disas_raw(xed_disas_info_t* fi); + + +#endif diff --git a/examples/xed-dll-discovery.c b/examples/xed-dll-discovery.c new file mode 100644 index 0000000..038de69 --- /dev/null +++ b/examples/xed-dll-discovery.c @@ -0,0 +1,120 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-min.cpp +/// @brief how to discover enum names for xed_iclass_enum_t + +/************************************************************************* + When using XED as a DLL or shared object, the enumerations can change + from one version of XED to another if instructions (or features) are + added. Each XED enumeration must be mapped to something your XED client + can use for indepedent compilation. This example shows how to discover + the XED values for the xed_iclass_enum_t and construct a mapping from + names that are constant to your tool to names that can vary. You would + need to this for each XED enumeration that your XED client uses. + + This builds a one map so that you can map things from your clients code + to XED's names as would be required for an encoder. For a decoder you'd + also need to invert the mapping so that you can mape from XED names to + your client's names. +**************************************************************************/ + +#include "xed-interface.h" +#include +#include +#include + +int main(int argc, char** argv); + + +typedef enum { /* these are the names that'll use in my code */ + MY_ICLASS_ADD, + MY_ICLASS_SUB, + MY_ICLASS_LAST +} my_iclass_enum_t; + +/* A mapping from my (simple) client names to the XED names which can + * vary. */ +typedef struct { + char const* const string_name; + int xed_name; /* discovered and passed to XED n*/ +} iclass_interface_t; + + +iclass_interface_t xed_iclass_interface[] = { + { "ADD", -1}, + { "SUB", -1} +}; + +void dump_inst(const xed_inst_t* p) { + /* N-squared maching... */ + xed_iclass_enum_t ic = xed_inst_iclass(p); + char const* const xed_name = xed_iclass_enum_t2str(ic); + iclass_interface_t* table_base = xed_iclass_interface; + int j=0; + + while( j < MY_ICLASS_LAST) { + if (strcmp(table_base[j].string_name, xed_name) == 0) { + if (table_base[j].xed_name == -1) { + printf("%s maps to %d\n", xed_name, (int)ic); + table_base[j].xed_name = ic; + } + break; + } + j++; + } +} + +void build_map_to_xed(void) { + int i; + for(i=0;i +#include +#include + +/* each write replaces the last node for that input */ + + +xed_dot_graph_supp_t* xed_dot_graph_supp_create( + xed_syntax_enum_t arg_syntax) +{ + xed_dot_graph_supp_t* gs = 0; + + gs = (xed_dot_graph_supp_t*)malloc(sizeof(xed_dot_graph_supp_t)); + assert( gs != 0 ); + gs->g = xed_dot_graph(); + gs->syntax = arg_syntax; + memset(gs->xed_reg_to_node, + 0, + sizeof(xed_dot_node_t*)*XED_REG_LAST); + + gs->start = xed_dot_node(gs->g, "start"); + return gs; +} + +void xed_dot_graph_supp_deallocate(xed_dot_graph_supp_t* gg) +{ + if (!gg) + return; + xed_dot_graph_deallocate(gg->g); +} + + +static xed_bool_t add_edge(xed_dot_graph_supp_t* gg, + xed_dot_node_t* n, + xed_reg_enum_t r, + xed_dot_edge_style_t s) +{ + xed_reg_enum_t r_enclosing; + xed_bool_t found = 0; + xed_dot_node_t* src = 0; + /* add edge to n */ + r_enclosing = xed_get_largest_enclosing_register(r); + src = gg->xed_reg_to_node[r_enclosing]; + if (src) { + xed_dot_edge(gg->g,src,n,s); + found = 1; + } + return found; +} + +static void add_read_operands(xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_dot_node_t* n) +{ + xed_uint_t i, noperands; + xed_reg_enum_t r; + const xed_inst_t* xi = 0; + xed_bool_t found = 0; + xi = xed_decoded_inst_inst(xedd); + noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + int memop = -1; + const xed_operand_t* op = xed_inst_operand(xi,i); + xed_operand_enum_t opname = xed_operand_name(op); + if (xed_operand_is_register(opname) || + xed_operand_is_memory_addressing_register(opname)) { + + if (xed_operand_read(op)) { + /* add edge to n */ + r = xed_decoded_inst_get_reg(xedd, opname); + found |= add_edge(gg, n, r, XED_DOT_EDGE_SOLID); + } + continue; + } + if (opname == XED_OPERAND_MEM0) + memop = 0; + else if (opname == XED_OPERAND_MEM1 ) + memop = 1; + + if (memop != -1) { + /* get reads of base/index regs, if any */ + xed_reg_enum_t base, indx; + + base = xed_decoded_inst_get_base_reg(xedd,memop); + indx = xed_decoded_inst_get_index_reg(xedd,memop); + if (base != XED_REG_INVALID) + found |= add_edge(gg, n, base, XED_DOT_EDGE_SOLID); + + indx = xed_decoded_inst_get_index_reg(xedd,memop); + if (indx != XED_REG_INVALID) + found |= add_edge(gg, n, indx, XED_DOT_EDGE_SOLID); + } + } /* for */ + if (!found) { + /* add an edge from start */ + xed_dot_edge(gg->g, gg->start, n, XED_DOT_EDGE_SOLID); + } +} + +static void add_write_operands(xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_dot_node_t* n) +{ + xed_uint_t i, noperands; + xed_reg_enum_t r, r_enclosing; + const xed_inst_t* xi = 0; + xi = xed_decoded_inst_inst(xedd); + noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + const xed_operand_t* op = xed_inst_operand(xi,i); + xed_operand_enum_t opname = xed_operand_name(op); + if (xed_operand_is_register(opname) || + xed_operand_is_memory_addressing_register(opname)) { + + if (xed_operand_written(op)) { + /* set n as the source of the value. */ + /* ignoring partial writes */ + r = xed_decoded_inst_get_reg(xedd, opname); + + /* output dependences */ + (void) add_edge(gg,n,r,XED_DOT_EDGE_DASHED); + + r_enclosing = xed_get_largest_enclosing_register(r); + gg->xed_reg_to_node[r_enclosing] = n; + } + } + } /* for */ +} + + +#define XED_DOT_TMP_BUF_LEN (1024U) + +void xed_dot_graph_add_instruction( + xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instr_addr, + void* caller_data, + xed_disassembly_callback_fn_t disas_symbol_cb) +{ + /* + make a new node + + for each operand: + if read: + make edge from src node for that reg to the new node + for each operand: + if write: + install this node as the writer + + what about partial writes? + what about register nesting? + */ + char disasm_str[XED_DOT_TMP_BUF_LEN]; + char* p = 0; + size_t alen = 0; + int ok; + xed_dot_node_t* n = 0; + xed_uint32_t remaining_buffer_bytes = XED_DOT_TMP_BUF_LEN; + + // put addr on separate line in node label +#if defined(XED_WINDOWS) && !defined(PIN_CRT) + ok = sprintf_s(disasm_str, + XED_DOT_TMP_BUF_LEN, + XED_FMT_LX "\\n", + runtime_instr_addr); +#else + ok = sprintf(disasm_str, + XED_FMT_LX "\\n", + runtime_instr_addr); + +#endif + assert(ok > 0); + alen = strlen(disasm_str); + p = disasm_str + alen; + remaining_buffer_bytes -= XED_CAST(xed_uint32_t, alen); + + ok = xed_format_context(gg->syntax, + xedd, + p, + remaining_buffer_bytes, + runtime_instr_addr, + caller_data, + disas_symbol_cb); + if (!ok) { + (void)xed_strncpy(disasm_str,"???", XED_DOT_TMP_BUF_LEN); + } + + n = xed_dot_node(gg->g, disasm_str); + add_read_operands(gg,xedd,n); + add_write_operands(gg,xedd,n); +} + +void xed_dot_graph_dump( + FILE* f, + xed_dot_graph_supp_t* gg) +{ + xed_dot_dump(f, gg->g); +} diff --git a/examples/xed-dot-prep.h b/examples/xed-dot-prep.h new file mode 100644 index 0000000..6f5e640 --- /dev/null +++ b/examples/xed-dot-prep.h @@ -0,0 +1,51 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_DOT_PREP_H_) +# define _XED_DOT_PREP_H_ +#include "xed-interface.h" +#include "xed-dot.h" + +typedef struct { + xed_syntax_enum_t syntax; + xed_dot_graph_t* g; + + // node that is last writer of the register + xed_dot_node_t* xed_reg_to_node[XED_REG_LAST]; + + xed_dot_node_t* start; +} xed_dot_graph_supp_t; + +xed_dot_graph_supp_t* xed_dot_graph_supp_create( + xed_syntax_enum_t arg_syntax); + +void xed_dot_graph_supp_deallocate( + xed_dot_graph_supp_t* gg); + +void xed_dot_graph_add_instruction( + xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instr_addr, + void* caller_data, + xed_disassembly_callback_fn_t disas_symbol_cb); + +void xed_dot_graph_dump( + FILE* f, + xed_dot_graph_supp_t* gg); + +#endif diff --git a/examples/xed-dot.c b/examples/xed-dot.c new file mode 100644 index 0000000..bd1a65e --- /dev/null +++ b/examples/xed-dot.c @@ -0,0 +1,118 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/* + take xed_decoded_inst_t* and add it to a graph. + The input operands are input edges. + The output operands are output edges. + Careful with "special" operands in new technologies + */ + +#include "xed-dot.h" +#include "xed-examples-util.h" +#include +#include + +xed_dot_graph_t* xed_dot_graph(void) { + xed_dot_graph_t* g = 0; + g = (xed_dot_graph_t*)malloc(sizeof(xed_dot_graph_t)); + assert(g != 0); + g->edges = 0; + g->nodes = 0; + return g; +} +static void delete_nodes(xed_dot_graph_t* g) { + xed_dot_node_t* p = g->nodes; + while(p) { + xed_dot_node_t* t = p; + p = p->next; + free(t); + } +} +static void delete_edges(xed_dot_graph_t* g) { + xed_dot_edge_t* p = g->edges; + while(p) { + xed_dot_edge_t* t = p; + p = p->next; + free(t); + } +} +void xed_dot_graph_deallocate(xed_dot_graph_t* g) +{ + delete_nodes(g); + delete_edges(g); + free(g); +} + +xed_dot_node_t* xed_dot_node(xed_dot_graph_t* g, + char const* const name) { + xed_dot_node_t* n = 0; + n = (xed_dot_node_t*)malloc(sizeof(xed_dot_node_t)); + assert(n != 0); + n->name = xed_strdup(name); + + n->next = g->nodes; + g->nodes = n; + return n; +} + + +void xed_dot_edge(xed_dot_graph_t* g, + xed_dot_node_t* src, + xed_dot_node_t* dst, + xed_dot_edge_style_t style) +{ + xed_dot_edge_t* e = 0; + e = (xed_dot_edge_t*)malloc(sizeof(xed_dot_edge_t)); + assert(e != 0); + e->src = src; + e->dst = dst; + e->style = style; + + e->next = g->edges; + g->edges = e; +} + + + +void xed_dot_dump(FILE* f, xed_dot_graph_t* g) { + xed_dot_edge_t* p = g->edges; + fprintf(f,"digraph {\n"); + while(p) { + fprintf(f, "\"%s\" -> \"%s\"", + p->src->name, + p->dst->name); + + switch(p->style) { + case XED_DOT_EDGE_SOLID: + break; /* nothing required */ + case XED_DOT_EDGE_DASHED: + fprintf(f, "[ style = dashed ]"); + break; + case XED_DOT_EDGE_DOTTED: + fprintf(f, "[ style = dotted ]"); + break; + default: + break; + } + + fprintf(f, ";\n"); + + p = p->next; + } + fprintf(f,"}\n"); +} diff --git a/examples/xed-dot.h b/examples/xed-dot.h new file mode 100644 index 0000000..8968102 --- /dev/null +++ b/examples/xed-dot.h @@ -0,0 +1,61 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#if !defined(_XED_DOT_H_) +# define _XED_DOT_H_ + +#include "xed-interface.h" +#include + +typedef struct xed_dot_node_s { + char* name; + struct xed_dot_node_s* next; +} xed_dot_node_t; + +typedef enum { + XED_DOT_EDGE_SOLID, + XED_DOT_EDGE_DASHED, + XED_DOT_EDGE_DOTTED +} xed_dot_edge_style_t; + + +typedef struct xed_dot_edge_s { + xed_dot_node_t* src; + xed_dot_node_t* dst; + xed_dot_edge_style_t style; + struct xed_dot_edge_s* next; +} xed_dot_edge_t; + +typedef struct { + xed_dot_edge_t* edges; + xed_dot_node_t* nodes; +} xed_dot_graph_t; + + +xed_dot_graph_t* xed_dot_graph(void); +void xed_dot_graph_deallocate(xed_dot_graph_t* gg); + +xed_dot_node_t* xed_dot_node(xed_dot_graph_t* g, + char const* const name); + +void xed_dot_edge(xed_dot_graph_t* g, + xed_dot_node_t* src, + xed_dot_node_t* dst, + xed_dot_edge_style_t style); + +void xed_dot_dump(FILE* f, xed_dot_graph_t* g); +#endif diff --git a/examples/xed-enc-lang.c b/examples/xed-enc-lang.c new file mode 100644 index 0000000..f67c2b4 --- /dev/null +++ b/examples/xed-enc-lang.c @@ -0,0 +1,602 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// This is an example of how to use the encoder from scratch in the context +// of parsing a string from the command line. + +#include +#include +#include +#include "xed-interface.h" +#include "xed-portability.h" +#include "xed-examples-util.h" +#include "xed-enc-lang.h" + + +static char xed_enc_lang_toupper(char c) { + if (c >= 'a' && c <= 'z') + return c-'a'+'A'; + return c; +} + +static void upcase(char* s) { + char* p = s; + for( ; *p ; p++ ) + *p = xed_enc_lang_toupper(*p); +} + +xed_str_list_t* +tokenize(char const* const s, + char const* const delimiter) +{ + xed_str_list_t* slist = xed_tokenize(s, delimiter); + return slist; +} + +void slash_split(char const* const src, + char** first, // output + char** second) //output +{ + xed_str_list_t* sv = tokenize(src, "/"); + xed_str_list_t* p = sv; + xed_uint_t i=0; + for(; p ; i++, p=p->next) + { + if (i==0) { + *first = p->s; + *second = 0; + } + else if (i==1) + *second = p->s; + } +} + + + +typedef struct { + xed_bool_t valid; + unsigned int width_bits; + xed_uint64_t immed_val; +} immed_parser_t; + +static void immed_parser_init(immed_parser_t* self, + char const* const s, + char const* const tok0) +{ + xed_str_list_t* sv = tokenize(s,":"); + xed_uint_t sz = xed_str_list_size(sv); + self->valid = 0; + if (sz==2) { + xed_str_list_t* p = sv; + xed_uint_t i = 0; + for(; p ; i++, p=p->next) + { + if (i == 0 && strcmp(p->s,tok0) != 0) + return; + else if (i == 1) { + self->immed_val = convert_ascii_hex_to_int(p->s); + // nibbles to bits + self->width_bits = XED_CAST(unsigned int,strlen(p->s)*4); + self->valid = 1; + } + } + } +} + + +typedef struct { + xed_bool_t valid; + xed_reg_enum_t segment_reg; + xed_uint_t segno; +} seg_parser_t; + +static void seg_parser_init(seg_parser_t* self, + char const* const s) +{ + xed_str_list_t* sv = tokenize(s,":"); + xed_uint_t ntokens = xed_str_list_size(sv); + + self->valid=0; + self->segment_reg= XED_REG_INVALID; + self->segno=0; + + if (ntokens == 2) + { + xed_str_list_t* p = sv; + xed_uint_t i = 0; + xed_uint_t segid = 99; + for(; p ; i++, p=p->next) + { + if (i == 0) + { + if (strcmp(p->s,"SEG")==0 || strcmp(p->s,"SEG0")==0) + segid = 0; + else if (strcmp(p->s,"SEG1")==0) + segid = 1; + } + else if (i == 1 && segid < 2) + { + self->segno = segid; + self->segment_reg = str2xed_reg_enum_t(p->s); + + if (self->segment_reg != XED_REG_INVALID && + xed_reg_class(self->segment_reg) == XED_REG_CLASS_SR) + { + self->valid=1; + } + } + } + } + +} + + +static void +list2array(char** array, xed_str_list_t* sl, xed_uint_t n) +{ + xed_uint_t i=0; + xed_str_list_t* p = sl; + for( ; p && i < n ; i++, p=p->next) + array[i] = p->s; +} + +static xed_uint_t match(char const* const s, char const* const b) +{ + if (strcmp(s,b)==0) + return 1; + return 0; +} +static xed_uint_t skip(char const* const s) +{ + if (match(s,"-") || match(s,"NA")) + return 1; + return 0; +} + +typedef struct +{ + xed_bool_t valid; + xed_bool_t mem; + xed_bool_t agen; + xed_bool_t disp_valid; + char const* segment; + char const* base; + char const* indx; + char const* scale; + char const* disp; //displacement + xed_reg_enum_t segment_reg; + xed_reg_enum_t base_reg; + xed_reg_enum_t index_reg; + xed_uint8_t scale_val; + + xed_int64_t disp_val; + unsigned int disp_width_bits; + + unsigned int mem_len; +} mem_bis_parser_t; + // parse: MEMlength:[segment:]base,index,scale[,displacement] + // parse: AGEN:base,index,scale[,displacement] + // The displacement is optional + + // split on colons first + // MEM4:FS:EAX,EBX,4,223344 mem4 fs eax,ebx,4,22334455 -> 3 tokens + // MEM4:FS:EAX,EBX,4 mem4 fs eax,ebx,4 -> 3 tokens + // MEM4:EAX,EBX,4,223344 mem4 eax,ebx,4,223344.. -> 2 tokens + // MEM4:FS:EAX,EBX,4 mem4 fs eas,ebx,4 -> 3 tokens +static void mem_bis_parser_init(mem_bis_parser_t* self, char* s) +{ + xed_str_list_t* sv=0; + xed_uint_t ntokens=0; + xed_uint_t n_addr_tokens=0; + char* addr_token=0; + char* main_token=0; + xed_uint_t i=0; + xed_str_list_t* p = 0; + xed_str_list_t* sa = 0; + char* astr[4]; + + + self->valid = 0; + self->mem = 0; + self->agen = 0; + self->disp_valid = 0; + self->segment = "INVALID"; + self->base = "INVALID"; + self->indx = "INVALID"; + self->scale = "1"; + self->segment_reg = XED_REG_INVALID; + self->base_reg = XED_REG_INVALID; + self->index_reg = XED_REG_INVALID; + self->disp_val = 0; + self->disp_width_bits = 0; + self->mem_len = 0; + + upcase(s); + // split on colon first + sv = tokenize(s,":"); + ntokens = xed_str_list_size(sv); + + i=0; + p = sv; + if (ntokens !=2 && ntokens != 3) // 3 has segbase + return; + for( ; p ; i++, p=p->next) { + if (i==0) + main_token = p->s; + else if (i==1 && ntokens == 3) + self->segment = p->s; + else if (i==1 && ntokens == 2) + addr_token = p->s; + else if (i==2) + addr_token = p->s; + } + + if (strcmp(main_token,"AGEN")==0) + self->agen=1; + else if (strncmp(main_token,"MEM",3)==0) { + self->mem = 1; + } + else + return; + if (self->mem && strlen(main_token) > 3) { + char* mlen = main_token+3; + self->mem_len = strtol(mlen,0,0); + } + + if (self->agen && strcmp(self->segment,"INVALID")!=0) + xedex_derror("AGENs cannot have segment overrides"); + + sa = tokenize(addr_token,","); + n_addr_tokens = xed_str_list_size(sa); + + if (n_addr_tokens == 0 || n_addr_tokens > 4) + xedex_derror("Bad addressing mode syntax for memop"); + + list2array(astr, sa, n_addr_tokens); + + if (!skip(astr[0])) + self->base = astr[0]; + + if (n_addr_tokens > 2) + if (!skip(astr[1])) + self->indx = astr[1]; + + if (n_addr_tokens > 2) + self->scale = astr[2]; + if (skip(self->scale)) + self->scale = "1"; + if (match(self->scale,"1") || match(self->scale,"2") || + match(self->scale,"4") || match(self->scale,"8") ) { + self->valid=1; + self->scale_val = XED_CAST(xed_uint8_t,strtol(self->scale, 0, 10)); + self->segment_reg = str2xed_reg_enum_t(self->segment); + self->base_reg = str2xed_reg_enum_t(self->base); + self->index_reg = str2xed_reg_enum_t(self->indx); + + // look for a displacement + if (n_addr_tokens == 4 && strcmp(astr[3], "-") != 0) { + xed_uint64_t unsigned64_disp=0; + unsigned int nibbles = 0; + self->disp = astr[3]; + self->disp_valid = 1; + nibbles = XED_STATIC_CAST(int,strlen(self->disp)); + if (nibbles & 1) + xedex_derror("Displacement must have an even number of nibbles"); + unsigned64_disp = convert_ascii_hex_to_int(self->disp); + self->disp_width_bits = nibbles*4; // nibbles to bits + switch (self->disp_width_bits){ + case 8: self->disp_val = xed_sign_extend8_64(unsigned64_disp); + break; + case 16: self->disp_val = xed_sign_extend16_64(unsigned64_disp); + break; + case 32: self->disp_val = xed_sign_extend32_64(unsigned64_disp); + break; + case 64: self->disp_val = unsigned64_disp; + break; + } + } + } +} + + + +xed_encoder_request_t +parse_encode_request(ascii_encode_request_t areq) +{ + unsigned int i; + xed_encoder_request_t req; + char* cfirst=0; + char* csecond=0; + xed_str_list_t* tokens = 0; + unsigned int token_index = 0; + xed_str_list_t* p = 0; + xed_uint_t memop = 0; + xed_uint_t regnum = 0; + xed_uint_t operand_index = 0; + xed_iclass_enum_t iclass = XED_ICLASS_INVALID; + + // this calls xed_encoder_request_zero() + xed_encoder_request_zero_set_mode(&req,&(areq.dstate)); + + /* This is the important function here. This encodes an instruction + from scratch. + + You must set: + the machine mode (machine width, addressing widths) + the iclass + for some instructions you need to specify prefixes (like REP or LOCK). + the operands: + + operand kind (XED_OPERAND_{AGEN,MEM0,MEM1,IMM0,IMM1, + RELBR,PTR,REG0...REG15} + + operand order + + xed_encoder_request_set_operand_order(&req,operand_index, + XED_OPERAND_*); + where the operand_index is a sequential index starting at zero. + + operand details + FOR MEMOPS: base,segment,index,scale, + displacement for memops, + FOR REGISTERS: register name + FOR IMMEDIATES: immediate values + */ + + tokens = tokenize(areq.command," "); + p = tokens; + + for ( ; p ; token_index++, p=p->next ) { + slash_split(p->s, &cfirst, &csecond); + upcase(cfirst); + if (CLIENT_VERBOSE3) + printf( "[%s][%s][%s]\n", p->s, cfirst, csecond); + + if (token_index == 0 && strcmp(cfirst,"REP")==0) { + xed_encoder_request_set_rep(&req); + continue; + } + else if (token_index == 0 && strcmp(cfirst,"REPNE")==0) { + xed_encoder_request_set_repne(&req); + continue; + } + // consumed token, advance & exit + p = p->next; + break; + } + + // we can attempt to override the mode + if (csecond) + { + if (strcmp(csecond,"8")==0) + xed_encoder_request_set_effective_operand_width(&req, 8); + else if (strcmp(csecond,"16")==0) + xed_encoder_request_set_effective_operand_width(&req, 16); + else if (strcmp(csecond, "32")==0) + xed_encoder_request_set_effective_operand_width(&req, 32); + else if (strcmp(csecond,"64")==0) + xed_encoder_request_set_effective_operand_width(&req, 64); + } + + + iclass = str2xed_iclass_enum_t(cfirst); + if (iclass == XED_ICLASS_INVALID) { + fprintf(stderr,"[XED CLIENT ERROR] Bad instruction name: %s\n", + cfirst); + exit(1); + } + xed_encoder_request_set_iclass(&req, iclass ); + + + // put the operands in the request. Loop through tokens + // (skip the opcode iclass, handled above) + for( i=token_index; p ; i++, operand_index++, p=p->next ) { + mem_bis_parser_t mem_bis; + seg_parser_t seg_parser; + immed_parser_t imm; + immed_parser_t simm; + immed_parser_t imm2; + immed_parser_t disp; + immed_parser_t ptr_disp; + xed_reg_enum_t reg = XED_REG_INVALID; + xed_operand_enum_t r; + + char* cres_reg=0; + char* csecond_x=0; //FIXME: not used + slash_split(p->s, &cres_reg, &csecond_x); + upcase(cres_reg); + // prune the AGEN or MEM(base,index,scale[,displacement]) text from + // cres_reg + + // FIXME: add MEM(immed) for the OC1_A and OC1_O types???? + mem_bis_parser_init(&mem_bis,cres_reg); + if (mem_bis.valid) { + xed_reg_class_enum_t rc = XED_REG_CLASS_INVALID; + xed_reg_class_enum_t rci = XED_REG_CLASS_INVALID; + + + if (mem_bis.mem) { + if (memop == 0) { + // Tell XED that we have a memory operand + xed_encoder_request_set_mem0(&req); + // Tell XED that the mem0 operand is the next operand: + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_MEM0); + } + else { + xed_encoder_request_set_mem1(&req); + // Tell XED that the mem1 operand is the next operand: + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_MEM1); + } + memop++; + } + else if (mem_bis.agen) { + // Tell XED we have an AGEN + xed_encoder_request_set_agen(&req); + // The AGEN is the next operand + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_AGEN); + } + else + assert(mem_bis.agen || mem_bis.mem); + + rc = xed_gpr_reg_class(mem_bis.base_reg); + rci = xed_gpr_reg_class(mem_bis.index_reg); + + if (rc == XED_REG_CLASS_GPR32 || rci == XED_REG_CLASS_GPR32) + xed_encoder_request_set_effective_address_size(&req, 32); + if (rc == XED_REG_CLASS_GPR16 || rci == XED_REG_CLASS_GPR16) + xed_encoder_request_set_effective_address_size(&req, 16); + + // fill in the memory fields + xed_encoder_request_set_base0(&req, mem_bis.base_reg); + xed_encoder_request_set_index(&req, mem_bis.index_reg); + xed_encoder_request_set_scale(&req, mem_bis.scale_val); + xed_encoder_request_set_seg0(&req, mem_bis.segment_reg); + + if (mem_bis.mem_len) + xed_encoder_request_set_memory_operand_length( + &req, + mem_bis.mem_len ); // BYTES + if (mem_bis.disp_valid) + xed_encoder_request_set_memory_displacement( + &req, + mem_bis.disp_val, + mem_bis.disp_width_bits/8); + continue; + } + + + seg_parser_init(&seg_parser,cres_reg); + if (seg_parser.valid) { + if (CLIENT_VERBOSE3) + printf("Setting segment to %s\n", + xed_reg_enum_t2str(seg_parser.segment_reg)); + if (seg_parser.segno == 0) + xed_encoder_request_set_seg0(&req, seg_parser.segment_reg); + else + /* need SEG1 for MOVS[BWDQ]*/ + xed_encoder_request_set_seg1(&req, seg_parser.segment_reg); + + /* SEG/SEG0/SEG1 is NOT a normal operand. It is a setting, like + * the lock prefix. Normally the segment will be specified with + * normal memory operations. With memops without MODRM, or + * impliclit memops, we need a way of specifying the segment + * when it is not the default. This is the way. it does not + * change encoding forms. (When segments are "moved", they are + * REG operands, not SEG0/1, and are specified by name like EAX + * is.) */ + continue; + } + + + immed_parser_init(&imm,cres_reg, "IMM"); + + if (imm.valid) { + if (CLIENT_VERBOSE3) + printf("Setting immediate value to " XED_FMT_LX "\n", + imm.immed_val); + xed_encoder_request_set_uimm0_bits(&req, + imm.immed_val, + imm.width_bits); + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM0); + continue; + } + immed_parser_init(&simm,cres_reg, "SIMM"); + if (simm.valid) { + if (CLIENT_VERBOSE3) + printf("Setting immediate value to " XED_FMT_LX "\n", + simm.immed_val); + xed_encoder_request_set_simm( + &req, + XED_STATIC_CAST(xed_int32_t,simm.immed_val), + simm.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM0); + continue; + } + + immed_parser_init(&imm2,cres_reg, "IMM2"); + if (imm2.valid) { + if (imm2.width_bits != 8) + xedex_derror("2nd immediate must be just 1 byte long"); + xed_encoder_request_set_uimm1(&req, imm2.immed_val); + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM1); + continue; + } + + + immed_parser_init(&disp,cres_reg, "BRDISP"); + if (disp.valid) { + if (CLIENT_VERBOSE3) + printf("Setting displacement value to " XED_FMT_LX "\n", + disp.immed_val); + xed_encoder_request_set_branch_displacement( + &req, + XED_STATIC_CAST(xed_uint32_t,disp.immed_val), + disp.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_RELBR); + xed_encoder_request_set_relbr(&req); + continue; + } + + + immed_parser_init(&ptr_disp,cres_reg, "PTR"); + if (ptr_disp.valid) { + if (CLIENT_VERBOSE3) + printf("Setting pointer displacement value to " XED_FMT_LX "\n", + ptr_disp.immed_val); + xed_encoder_request_set_branch_displacement( + &req, + XED_STATIC_CAST(xed_uint32_t,ptr_disp.immed_val), + ptr_disp.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_PTR); + xed_encoder_request_set_ptr(&req); + continue; + } + + reg = str2xed_reg_enum_t(cres_reg); + if (reg == XED_REG_INVALID) { + fprintf(stderr, + "[XED CLIENT ERROR] Bad register name: %s on operand %u\n", + cres_reg, i); + exit(1); + } + // The registers operands aer numbered starting from the first one + // as XED_OPERAND_REG0. We incremenet regnum (below) every time we + // add a register operands. + r = XED_CAST(xed_operand_enum_t,XED_OPERAND_REG0 + regnum); + // store the register identifer in the operand storage field + xed_encoder_request_set_reg(&req, r, reg); + // store the operand storage field name in the encode-order array + xed_encoder_request_set_operand_order(&req, operand_index, r); + regnum++; + } // for loop + + return req; +} diff --git a/examples/xed-enc-lang.h b/examples/xed-enc-lang.h new file mode 100644 index 0000000..dfed2b1 --- /dev/null +++ b/examples/xed-enc-lang.h @@ -0,0 +1,36 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-enc-lang.h + +#if !defined(_XED_ENC_LANG_H_) +# define _XED_ENC_LANG_H_ + +#include "xed-interface.h" + +typedef struct +{ + xed_state_t dstate; + char const* command; +} ascii_encode_request_t; + + +xed_encoder_request_t +parse_encode_request(ascii_encode_request_t areq); + +#endif diff --git a/examples/xed-ex-agen.c b/examples/xed-ex-agen.c new file mode 100644 index 0000000..d9cd9dd --- /dev/null +++ b/examples/xed-ex-agen.c @@ -0,0 +1,294 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-ex-agen.c + +// decoder example with agen callbacks. + +#include "xed-interface.h" +#include "xed-examples-util.h" +#include +#include +#include //strcmp +#include + +int main(int argc, char** argv); + + +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + +xed_uint64_t register_callback(xed_reg_enum_t reg, void* context, xed_bool_t* error) { + (void) context; // pacify compiler + (void) error; + + /* these are all the registers you are going to have to provide values + for in this callback. Note that AL is required for the XLAT + instruction. That is the only byte reg needed. Also note, that for real + mode, raw segement selectors are returned by this function. */ + + /* in reality, you'd have to return valid valies for each case */ + + /* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + + switch(reg) { + case XED_REG_RAX: + case XED_REG_EAX: + case XED_REG_AX: + return 0xAABBCC00; + break; + case XED_REG_AL: // FOR XLAT + break; + + case XED_REG_RCX: + case XED_REG_ECX: + case XED_REG_CX: + return 0xAABBCCDD; + break; + case XED_REG_RDX: + case XED_REG_EDX: + case XED_REG_DX: + break; + case XED_REG_RBX: + case XED_REG_EBX: + case XED_REG_BX: + return 0x11223344; + break; + case XED_REG_RSP: + case XED_REG_ESP: + case XED_REG_SP: + break; + case XED_REG_RBP: + case XED_REG_EBP: + case XED_REG_BP: + break; + case XED_REG_RSI: + case XED_REG_ESI: + case XED_REG_SI: + return 0x1122334455; + break; + case XED_REG_RDI: + case XED_REG_EDI: + case XED_REG_DI: + return 0x6655443322; + break; + case XED_REG_R8: + case XED_REG_R8D: + case XED_REG_R8W: + break; + case XED_REG_R9: + case XED_REG_R9D: + case XED_REG_R9W: + break; + case XED_REG_R10: + case XED_REG_R10D: + case XED_REG_R10W: + break; + case XED_REG_R11: + case XED_REG_R11D: + case XED_REG_R11W: + break; + case XED_REG_R12: + case XED_REG_R12D: + case XED_REG_R12W: + break; + case XED_REG_R13: + case XED_REG_R13D: + case XED_REG_R13W: + break; + case XED_REG_R14: + case XED_REG_R14D: + case XED_REG_R14W: + break; + case XED_REG_R15: + case XED_REG_R15D: + case XED_REG_R15W: + break; + case XED_REG_RIP: + case XED_REG_EIP: + case XED_REG_IP: + break; + case XED_REG_CS: + case XED_REG_DS: + case XED_REG_ES: + case XED_REG_SS: + case XED_REG_FS: + case XED_REG_GS: + break; + default: + assert(0); + } + return 0; +} + +xed_uint64_t segment_callback(xed_reg_enum_t reg, void* context, xed_bool_t* error) { + /* for protected mode, this function returns the valid segment base values */ + + /* in reality, you'd have to return valid valies for each case */ + /* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + + (void) context; // pacify compiler + (void) error; + + switch(reg) { + case XED_REG_CS: + case XED_REG_DS: + case XED_REG_ES: + case XED_REG_SS: + return 0; + case XED_REG_FS: + return 0; + break; + case XED_REG_GS: + return 0; + break; + default: + assert(0); + break; + } + return 0; +} + + + + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + + xed_bool_t long_mode = 0; + xed_bool_t real_mode = 0; + xed_bool_t protected_16 = 0; + xed_state_t dstate; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + unsigned int memop_index = 0; + unsigned int memops = 0; + xed_uint64_t out_addr = 0; + + xed_tables_init(); + xed_agen_register_callback( register_callback, segment_callback); + + xed_state_zero(&dstate); + xed_set_verbosity( 99 ); + + if (argc > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + if (argc > 2 && strcmp(argv[1], "-r") == 0) + real_mode = 1; + if (argc > 2 && strcmp(argv[1], "-16") == 0) + protected_16 = 1; + + if (long_mode) { + first_argv = 2; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + } + else if (protected_16) { + first_argv = 2; + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_16, + XED_ADDRESS_WIDTH_16b, + XED_ADDRESS_WIDTH_16b); + } + else if (real_mode) { + first_argv = 2; + /* we say that real mode uses 16b addressing even though the + addresses returned are 20b long. */ + xed_state_init(&dstate, + XED_MACHINE_MODE_REAL_16, + XED_ADDRESS_WIDTH_16b, + XED_ADDRESS_WIDTH_16b); + } + else { + first_argv=1; + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, + XED_ADDRESS_WIDTH_32b); + } + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + for( i=first_argv ;i < argc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error = XED_ERROR_NONE; + unsigned int first_argv = 1; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t i=1; + xed_uint_t u=0; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode=XED_MACHINE_MODE_LEGACY_32; + xed_address_width_enum_t stack_addr_width=XED_ADDRESS_WIDTH_32b; + xed_chip_features_t features; + xed_chip_enum_t chip = XED_CHIP_HASWELL; + xed_uint_t uargc = (xed_uint_t)argc; + xed_bool_t already_set_mode = 0; + xed_bool_t bmi = 1; + + xed_tables_init(); + + for( i=1 ; i < uargc ; i++ ) + { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + first_argv++; + } + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < uargc); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + i++; + } + else if (strcmp(argv[i], "-nobmi") == 0) { + bmi = 0; + first_argv++; + i++; + } + else { // if not one of the thigns we're working on, break + break; + } + + } + + for( i=first_argv ;i < uargc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0 ; u < bytes ; u++ ) { + printf("%02x ", XED_STATIC_CAST(unsigned int,itext[u])); + } + printf("\n"); + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_decoded_inst_set_input_chip(&xedd, chip); + + // Start with a HSW (default) and (conditionally) turn off BMI1 so that + // TZCNT decodes as BSF + xed_get_chip_features(&features, chip); + if (bmi == 0) { + xed_modify_chip_features(&features, XED_ISA_SET_BMI1, 0); + } + + xed_error = xed_decode_with_features(&xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,itext), + bytes, + &features); + switch(xed_error) + { + case XED_ERROR_NONE: { +#define OBUFLEN 1024 + char outbuf[OBUFLEN]; + if (xed_format_context(XED_SYNTAX_INTEL, &xedd, outbuf, OBUFLEN, 0, 0, 0)) { + printf("DISASM %s\n", outbuf); + } + else { + fprintf(stderr,"DISASM printing error\n"); + exit(1); + } + + } + break; + case XED_ERROR_BUFFER_TOO_SHORT: + fprintf(stderr,"Not enough bytes provided\n"); + exit(1); + case XED_ERROR_GENERAL_ERROR: + fprintf(stderr,"Could not decode given input.\n"); + exit(1); + default: + fprintf(stderr,"Unhandled error code %s\n", + xed_error_enum_t2str(xed_error)); + exit(1); + } + + return 0; +} diff --git a/examples/xed-ex-ild.c b/examples/xed-ex-ild.c new file mode 100644 index 0000000..c34e5e0 --- /dev/null +++ b/examples/xed-ex-ild.c @@ -0,0 +1,47 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include "xed-interface.h" +#include + +int main(int argc, char** argv); + +int main(int argc, char** argv) +{ + xed_bool_t long_mode = 1; + xed_decoded_inst_t xedd; + xed_state_t dstate; + unsigned char itext[15] = { 0xf2, 0x2e, 0x4f, 0x0F, 0x85, 0x99, + 0x00, 0x00, 0x00 }; + + xed_tables_init(); // one time per process + + if (long_mode) + dstate.mmode=XED_MACHINE_MODE_LONG_64; + else + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + xed_ild_decode(&xedd, itext, XED_MAX_INSTRUCTION_BYTES); + printf("length = %u\n",xed_decoded_inst_get_length(&xedd)); + + return 0; + (void) argc; (void) argv; //pacify compiler + +} diff --git a/examples/xed-ex-ild2.c b/examples/xed-ex-ild2.c new file mode 100644 index 0000000..ec97160 --- /dev/null +++ b/examples/xed-ex-ild2.c @@ -0,0 +1,169 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include +#include +#include +#include +#include "xed-examples-util.h" + +int main(int argc, char** argv); + +#include "xed-interface.h" +#include "xed-get-time.h" + +#define BUFLEN 1024 +#define XDPRINT(x) printf("%23s = %d\n", #x , i-> x ); +#define XXPRINT(x) printf("%23s = 0x%x\n", #x ,i-> x ) +void print_ild(xed_decoded_inst_t* p) { + + char buf[BUFLEN]; + xed_chip_enum_t chip = xed_decoded_inst_get_input_chip(p); + xed_decoded_inst_dump(p, buf, BUFLEN); + printf("%23s = %s\n", "chip", + xed_chip_enum_t2str(chip)); +} + +#define MAX_INPUT_NIBBLES (XED_MAX_INSTRUCTION_BYTES*2) + +int main(int argc, char** argv) { + xed_decoded_inst_t ild; + xed_uint_t uargc = (xed_uint_t)argc; + xed_uint_t length = 0; + xed_uint_t dlen = 0; + xed_uint_t i,j,input_nibbles=0; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES]; + char src[MAX_INPUT_NIBBLES+1]; + xed_state_t dstate; + xed_decoded_inst_t xedd; + xed_uint_t first_argv; + xed_uint_t bytes; + xed_error_enum_t xed_error; + xed_chip_enum_t chip = XED_CHIP_INVALID; + int already_set_mode = 0; + + // initialize the XED tables -- one time. + xed_tables_init(); + + xed_state_zero(&dstate); + + first_argv = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_32b; + + for(i=1;i< uargc;i++) { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + first_argv++; + } + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_16; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-s16") == 0) { + already_set_mode = 1; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < uargc); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + } + + } + + assert(first_argv < uargc); + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + + if (first_argv >= uargc) { + printf("Need some hex instruction nibbles"); + exit(1); + } + + for(i=first_argv;i +#include +#include +#include + +int main(int argc, char** argv); +void print_misc(xed_decoded_inst_t* xedd) { + int i; + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(xedd); + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + xed_exception_enum_t e = xed_inst_exception(xi); + xed_uint_t np = xed_decoded_inst_get_nprefixes(xedd); + xed_uint_t vl_bits = xed_decoded_inst_vector_length_bits(xedd); + xed_isa_set_enum_t isaset = xed_decoded_inst_get_isa_set(xedd); + + if (xed_operand_values_has_real_rep(ov)) { + xed_iclass_enum_t norep = + xed_rep_remove(xed_decoded_inst_get_iclass(xedd)); + printf("REAL REP "); + printf("\tcorresponding no-rep iclass: %s\n" , + xed_iclass_enum_t2str(norep)); + + } + if (xed_operand_values_has_rep_prefix(ov)) { + printf("F3 PREFIX\n"); + } + if (xed_operand_values_has_repne_prefix(ov)) { + printf("F2 PREFIX\n"); + } + if (xed_operand_values_has_address_size_prefix(ov)) { + printf("67 PREFIX\n"); + } + if (xed_operand_values_has_operand_size_prefix(ov)) { + /* this 66 prefix is not part of the opcode */ + printf("66-OSZ PREFIX\n"); + } + if (xed_operand_values_has_66_prefix(ov)) { + /* this is any 66 prefix including the above */ + printf("ANY 66 PREFIX\n"); + } + + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)) { + printf("RING0 only\n"); + } + + if (e != XED_EXCEPTION_INVALID) { + printf("EXCEPTION TYPE: %s\n", xed_exception_enum_t2str(e)); + } + + // does not include instructions that have XED_ATTRIBUTE_MASK_AS_CONTROL. + // does not include vetor instructions that have k0 as a mask register. + if (xed_decoded_inst_masked_vector_operation(xedd)) + printf("WRITE-MASKING\n"); + + + if (np) + printf("Number of legacy prefixes: %u \n", np); + + + if (vl_bits) + printf("Vector length: %u \n", vl_bits); + + + printf("ISA SET: [%s]\n", xed_isa_set_enum_t2str(isaset)); + for(i=0; is.zf) { + printf("READS ZF\n"); + } + } +} + +void print_flags(xed_decoded_inst_t* xedd) { + unsigned int i, nflags; + if (xed_decoded_inst_uses_rflags(xedd)) { + const xed_simple_flag_t* rfi = xed_decoded_inst_get_rflags_info(xedd); + printf("FLAGS:\n"); + if (xed_simple_flag_reads_flags(rfi)) { + printf(" reads-rflags "); + } + else if (xed_simple_flag_writes_flags(rfi)) { + //XED provides may-write and must-write information + if (xed_simple_flag_get_may_write(rfi)) { + printf(" may-write-rflags "); + } + if (xed_simple_flag_get_must_write(rfi)) { + printf(" must-write-rflags "); + } + } + nflags = xed_simple_flag_get_nflags(rfi); + for( i=0;i> 3); + + printf(" %2u", xed_decoded_inst_operand_elements(xedd,i)); + printf(" %3u", xed_decoded_inst_operand_element_size_bits(xedd,i)); + + printf(" %10s", + xed_operand_element_type_enum_t2str( + xed_decoded_inst_operand_element_type(xedd,i))); + printf(" %10s\n", + xed_reg_class_enum_t2str( + xed_reg_class( + xed_decoded_inst_get_reg(xedd, op_name)))); + } +} + +int main(int argc, char** argv) { + xed_state_t dstate; + xed_decoded_inst_t xedd; + int i, bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int first_argv; + xed_bool_t already_set_mode = 0; + xed_chip_enum_t chip = XED_CHIP_INVALID; + char const* decode_text=0; + unsigned int len; + xed_error_enum_t xed_error; + +#if defined(XED_MPX) + unsigned int mpx_mode=0; +#endif + xed_tables_init(); + xed_state_zero(&dstate); + + first_argv = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_32b; + + for(i=1;i< argc;i++) { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + first_argv++; + } +#if defined(XED_MPX) + else if (strcmp(argv[i], "-mpx") == 0) { + mpx_mode = 1; + first_argv++; + } +#endif + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_16; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-s16") == 0) { + already_set_mode = 1; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < argc); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + } + } + + assert(first_argv < argc); + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + xed_decoded_inst_set_input_chip(&xedd, chip); +#if defined(XED_MPX) + xed3_operand_set_mpxmode(&xedd, mpx_mode); +#endif + + // convert ascii hex to hex bytes + for(i=first_argv; i< argc;i++) + decode_text = xedex_append_string(decode_text,argv[i]); + + len = (unsigned int) strlen(decode_text); + if ((len & 1) == 1) { + printf("Must supply even number of nibbles per substring\n"); + exit(1); + } + if (len >= XED_MAX_INSTRUCTION_BYTES*2) { + printf("Must supply at most 30 nibbles (15 bytes)\n"); + exit(1); + } + + bytes = xed_convert_ascii_to_hex(decode_text, + itext, + XED_MAX_INSTRUCTION_BYTES); + if (bytes == 0) { + printf("Must supply some hex bytes\n"); + exit(1); + } + + printf("Attempting to decode: "); + for(i=0;i +#include +#include + +int main(int argc, char** argv); + + +void +usage(char* progname) +{ + fprintf(stderr,"Usage: %s [-16|-32|-64] [-s16|-s32] encode-string\n", + progname); + exit(1); +} + +ascii_encode_request_t +parse_args(unsigned int argc, char** argv) +{ + char const* c = 0; + unsigned int i = 1; + ascii_encode_request_t r; + if (argc == 1) + usage(argv[0]); + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + + for( ; i< argc; i++) + if (strcmp(argv[i],"-16")==0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + else if (strcmp(argv[i],"-32")==0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + else if (strcmp("-64", argv[i]) == 0) { + r.dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + else if (strcmp("-32", argv[i]) == 0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + else if (strcmp("-16", argv[i]) == 0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + else if (strcmp(argv[i],"-s32")==0) + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + else if (strcmp(argv[i],"-s16")==0) + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + else + break; + + if (i == argc) + usage(argv[0]); + + c = xed_strdup(argv[i++]); + for( ;i +#include +#include //strcmp, memset +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + + xed_bool_t long_mode = 0; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_format_options_t format_options; + + // one time initialization + xed_tables_init(); + xed_set_verbosity( 99 ); + memset(&format_options,0, sizeof(format_options)); + format_options.hex_address_before_symbolic_name=0; + format_options.xml_a=0; + format_options.omit_unit_scale=0; + format_options.no_sign_extend_signed_immediates=0; + + for(i=1;i +#include // malloc, etc. +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + xed_state_t dstate32, dstate64; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int ilen = XED_MAX_INSTRUCTION_BYTES; + unsigned int i, j, olen = 0, ninst=0; + xed_encoder_request_t enc_req; +#define NINST 50 + xed_encoder_instruction_t x[NINST]; + xed_bool_t convert_ok; +#if defined(XED_DECODER) + xed_bool_t ok; +# define DBUFLEN 1000 + char buffer[DBUFLEN]; + + xed_decoded_inst_t xedd; +#endif + + xed_tables_init(); + xed_state_zero(&dstate32); + xed_state_zero(&dstate64); + + dstate32.stack_addr_width=XED_ADDRESS_WIDTH_32b; + dstate32.mmode=XED_MACHINE_MODE_LEGACY_32; + + dstate64.stack_addr_width=XED_ADDRESS_WIDTH_64b; + dstate64.mmode=XED_MACHINE_MODE_LONG_64; + + xed_inst1(x+ninst, dstate64, XED_ICLASS_JMP, 64, + xed_relbr(0x11223344, 32)); + ninst++; + + /* using 0 for instructions that have the default effective operand + * width for their mode. The default effective operand width for 16b + * mode is 16b. The default effective operand width for 32b and 64b + * modes is 32b. */ + + // add an lock and xacquire + xed_inst2(x+ninst, dstate32, XED_ICLASS_XOR_LOCK, 0, + xed_mem_bd(XED_REG_EDX, xed_disp(0x11, 8), 32), + xed_reg(XED_REG_ECX) ); + xed_repne(x+ninst); // xacquire + ninst++; + + xed_inst2(x+ninst, + dstate32, XED_ICLASS_ADD, 0, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_EDX, xed_disp(0x11223344, 32), 32)); + ninst++; + + xed_inst2(x+ninst, + dstate32, XED_ICLASS_ADD, 0, + xed_reg(XED_REG_EAX), + xed_mem_gbisd(XED_REG_FS, + XED_REG_EAX, + XED_REG_ESI,4, xed_disp(0x11223344, 32), 32)); + ninst++; + + // displacment-only LEA + xed_inst2(x+ninst, + dstate32, XED_ICLASS_LEA, 32, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_INVALID, xed_disp(0x11223344, 32), 32)); + ninst++; + + + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSB, 0); + ninst++; + + /* nondefault effective operand width for 32b mode so we must specify + it. XED could figure it out from the opcode, but currently does + not. */ + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSW, 16); + ninst++; + + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSD, 0); + ninst++; + + xed_inst1(x+ninst, dstate32, XED_ICLASS_PUSH, 0, xed_reg(XED_REG_ECX)); + ninst++; + + xed_inst2(x+ninst, dstate32, XED_ICLASS_XOR, 0, + xed_reg(XED_REG_ECX), + xed_reg(XED_REG_EDX)); + ninst++; + + + /* this one has a nondefault effective operand width for 64b mode so we + must specify it. XED could figure this output from the operands, + but currently it does not. */ + + xed_inst2(x+ninst, dstate64, XED_ICLASS_XOR, 64, + xed_reg(XED_REG_RCX), + xed_reg(XED_REG_RDX)); + ninst++; + + /* nondefault effective operand width for 64b mode so we must specify + it. XED could figure it out from the opcode, but currently does + not. */ + xed_inst0(x+ninst, dstate64, XED_ICLASS_REPE_CMPSQ, 64); + ninst++; + + /* here it is ambiguous from the opcode what the effective operand + * width is. I could use the operand, but do not do that yet. */ + xed_inst1(x+ninst, dstate64, XED_ICLASS_PUSH, 64, xed_reg(XED_REG_RCX)); + ninst++; + + /* again, here's one where I could infer that the operation is 64b from + * the memory operand, but not yet. */ + xed_inst1(x+ninst, dstate64, XED_ICLASS_PUSH, 64, + xed_mem_bd(XED_REG_RDX, xed_disp(0x11223344, 32), 64)); + ninst++; + + // move a 64b quantity in to RAX using only a 64b displacment + xed_inst2(x+ninst, dstate64, XED_ICLASS_MOV, 64, + xed_reg(XED_REG_RAX), + xed_mem_bd(XED_REG_INVALID, xed_disp(0x1122334455667788, 64), 64)); + ninst++; + + + + xed_inst1(x+ninst, dstate64, XED_ICLASS_JMP_FAR, 64, + xed_mem_bd(XED_REG_RAX, xed_disp(0x20, 8), 80)); + + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_ADD, 64, + xed_reg(XED_REG_RAX), + xed_imm0(0x77,8)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_ADD, 64, + xed_reg(XED_REG_RAX), + xed_imm0(0x44332211,32)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_MOV_CR, 64, + xed_reg(XED_REG_CR3), + xed_reg(XED_REG_RDI)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_MOV, 32, + xed_mem_bisd(XED_REG_R8, XED_REG_RBP, 1, xed_disp(0xf8, 8), 32), + xed_simm0(0x0,32)); + ninst++; + + + // example showing how to set the effective address size to 32b in 64b + // mode. Normally XED deduces that from the memory operand base + // register, but in this case the memops are implicit. + xed_inst0(x+ninst, + dstate64, XED_ICLASS_STOSQ, 64); + xed_addr(x+ninst, 32); + ninst++; + + + xed_inst1(x+ninst, + dstate32, + XED_ICLASS_JECXZ, + 4, + xed_relbr(5, 8)); + ninst++; + + xed_inst1(x+ninst, + dstate64, + XED_ICLASS_JECXZ, + 4, + xed_relbr(5, 8)); + xed_addr(x+ninst,32); + ninst++; + + xed_inst1(x+ninst, + dstate64, + XED_ICLASS_JRCXZ, + 4, + xed_relbr(5, 8)); + ninst++; + + +#if defined(XED_AVX) + xed_inst2(x+ninst, + dstate64, + XED_ICLASS_VBROADCASTSD, + 32, + xed_reg(XED_REG_YMM4), + xed_mem_gbisd(XED_REG_GS,XED_REG_INVALID,0,0, + xed_disp(0x808, 32), + 64)); + ninst++; +#endif + +#if defined(XED_SUPPORTS_AVX512) + // example showing how to set EVEX features. + // increase the number of operands and use xed_other(...) + xed_inst5(x+ninst, + dstate64, + XED_ICLASS_VADDPS, + 32, + xed_reg(XED_REG_XMM1), + xed_reg(XED_REG_K1), + xed_reg(XED_REG_XMM2), + xed_mem_b(XED_REG_RCX, 16), + xed_other(XED_OPERAND_ZEROING,1)); + ninst++; +#endif + + + for(i=0;iencoder example. + +#include "xed-interface.h" +#include "xed-examples-util.h" +#include +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_encoder_request_t* enc_req; + xed_uint8_t array[XED_MAX_INSTRUCTION_BYTES]; + unsigned int enc_olen, ilen = XED_MAX_INSTRUCTION_BYTES; + xed_error_enum_t encode_okay; + xed_bool_t change_to_long_mode = 0; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argc > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argc > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +void print_operands(xed_decoded_inst_t* xedd) { + unsigned int i = 0; + xed_inst_t const* const xi = xed_decoded_inst_inst(xedd); + const unsigned int noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + xed_operand_t const* op = xed_inst_operand(xi,i); + xed_operand_enum_t op_name = xed_operand_name(op); + if (xed_operand_is_register(op_name)) { + xed_reg_enum_t reg = xed_decoded_inst_get_reg(xedd,op_name); + xed_operand_action_enum_t rw = xed_decoded_inst_operand_action(xedd,i); + printf("%2d: %5s %5s\n", + (int)i, + xed_reg_enum_t2str(reg), + xed_operand_action_enum_t2str(rw)); + } + } +} + + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argc > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argc > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +void check_for_mov_to_cr3(xed_decoded_inst_t* xedd) +{ + if (xed_decoded_inst_get_iclass(xedd) == XED_ICLASS_MOV_CR) + { + // we know mov_cr has 2 operands so we do not check + // xed_inst_noperands. + + + // get the skeleton (static info) + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + + // get the dest operand (operand 0) + const xed_operand_t* op = xed_inst_operand(xi,0); + + xed_operand_enum_t op_name = xed_operand_name(op); + if (op_name == XED_OPERAND_REG0) + { + xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name); + if (r == XED_REG_CR3) + { + printf("Found a mov to CR3\n"); + } + } + } +} + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argc > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argc > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u //strlen, memcmp, memset +#if defined(XED_MAC) || defined(XED_LINUX) || defined(XED_BSD) +# include +# include +# include +# include +# include +#endif +#include +#include +#include +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-dot-prep.h" + + +#include "xed-ild.h" +#if defined(PTI_XED_TEST) +#include "pti-xed-test.h" +#endif + + +#define XED_TMP_BUF_LEN (1024*4) + + +#define XED_HISTO_MAX_CYCLES 10000 // must be divisible by cycles/bin +#define XED_HISTO_CYCLES_PER_BIN 50 +#define XED_HISTO_BINS (XED_HISTO_MAX_CYCLES/XED_HISTO_CYCLES_PER_BIN) + +typedef struct { + xed_uint64_t total_time ; + xed_uint64_t total_insts ; + xed_uint64_t total_ilen ; + xed_uint64_t total_olen ; + xed_uint64_t total_shorter ; + xed_uint64_t total_longer ; + xed_uint64_t bad_times ; + xed_uint64_t reset_counter; + + xed_uint64_t total_insts_tail; + xed_uint64_t total_time_tail; + xed_uint64_t perf_tail; + + xed_uint64_t histo[XED_HISTO_BINS]; +} xed_stats_t; + +#if defined(XED_DECODER) +static void +update_histogram(xed_stats_t* p, + xed_uint64_t delta) +{ + xed_uint32_t bin; + if (delta < XED_HISTO_MAX_CYCLES) + bin = delta / XED_HISTO_CYCLES_PER_BIN; + else + bin = XED_HISTO_BINS-1; + p->histo[bin]++; +} + +static void +init_histogram(xed_stats_t* p) +{ + memset(p->histo, 0, + sizeof(xed_uint64_t)*XED_HISTO_BINS); +} + + +static void +xed_stats_update(xed_stats_t* p, + xed_uint64_t t1, + xed_uint64_t t2) +{ + if (t2 > t1) + { + xed_uint64_t delta = t2-t1; + p->total_time += delta; + update_histogram(p,delta); + } + else + p->bad_times++; + p->total_insts++; + p->reset_counter++; + if (p->reset_counter == 50) { + if (CLIENT_VERBOSE1) + printf("\n\nRESETTING STATS\n\n"); + // to ignore startup transients paging everything in. + init_histogram(p); + p->total_insts=0; + p->total_time=0; + } + //these guys count average on tail instructions - + //when all cpu caches and tables are full + if (p->total_insts >= p->perf_tail) { + p->total_insts_tail++; + p->total_time_tail += (t2-t1); + } +} + +static void +xed_stats_zero(xed_stats_t* p, + xed_disas_info_t* di) +{ + p->total_time = 0; + p->total_insts = 0; + p->total_ilen = 0; + p->total_olen = 0; + p->total_shorter = 0; + p->total_longer = 0; + p->bad_times = 0; + p->reset_counter = 0; + + p->total_time_tail = 0; + p->total_insts_tail = 0; + p->perf_tail = di->perf_tail_start; + + init_histogram(p); +} +#endif + +static xed_stats_t xed_dec_stats; +static xed_stats_t xed_enc_stats; + +void xed_disas_info_init(xed_disas_info_t* p) +{ + memset(p,0,sizeof(xed_disas_info_t)); +} + +xed_syntax_enum_t global_syntax = XED_SYNTAX_INTEL; +int client_verbose=0; + +//////////////////////////////////////////////////////////////////////////// + +static char xed_toupper(char c) { + if (c >= 'a' && c <= 'z') + return c-'a'+'A'; + return c; +} + +char* xed_upcase_buf(char* s) { + xed_uint_t len = XED_STATIC_CAST(xed_uint_t,strlen(s)); + xed_uint_t i; + for(i=0 ; i < len ; i++ ) + s[i] = XED_STATIC_CAST(char,xed_toupper(s[i])); + return s; +} + +static xed_uint8_t convert_nibble(xed_uint8_t x) { + // convert ascii nibble to hex + xed_uint8_t rv = 0; + if (x >= '0' && x <= '9') + rv = x - '0'; + else if (x >= 'A' && x <= 'F') + rv = x - 'A' + 10; + else if (x >= 'a' && x <= 'f') + rv = x - 'a' + 10; + else { + printf("Error converting hex digit. Nibble value 0x%x\n", x); + exit(1); + } + return rv; +} + + +xed_int64_t xed_atoi_hex(char* buf) { + xed_int64_t o=0; + xed_uint_t i; + xed_uint_t len = XED_STATIC_CAST(xed_uint_t,strlen(buf)); + for(i=0; i= (2*n+1)); /* including null */ + for( i=0 ; i< n; i++) { + buf[2*i+0] = nibble_to_ascii_hex(array[i]>>4); + buf[2*i+1] = nibble_to_ascii_hex(array[i]&0xF); + } + buf[2*i]=0; +} + + + +void XED_NORETURN xedex_derror(const char* s) { + printf("[XED CLIENT ERROR] %s\n",s); + exit(1); +} + +void xedex_dwarn(const char* s) { + printf("[XED CLIENT WARNING] %s\n",s); +} + + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_DECODER) +//#define BINARY_DUMP + +#if defined (BINARY_DUMP) +int fd = 0; +void open_binary_output_file(void); +void open_binary_output_file(void) +{ + fd = open("output", O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU); + if (fd == -1) { + fprintf(stderr,"Could not open binary output file\n"); + exit(1); + } +} +#endif + +static XED_INLINE xed_error_enum_t +decode_internal(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + xed_uint_t max_bytes) +{ + xed_error_enum_t err = xed_decode(xedd,itext,max_bytes); + +#if defined (BINARY_DUMP) + if (err == XED_ERROR_NONE) + write(fd, itext, xed_decoded_inst_get_length(xedd)); +#endif + + return err; +} +#endif + +void init_xedd(xed_decoded_inst_t* xedd, + xed_state_t const* const dstate, + xed_chip_enum_t chip, + int mpx_mode) +{ +#if defined(XED_DECODER) + xed_decoded_inst_zero_set_mode(xedd, dstate); +#endif + xed_decoded_inst_set_input_chip(xedd, chip); +#if defined(XED_MPX) + xed3_operand_set_mpxmode(xedd,mpx_mode); +#else + (void)mpx_mode; +#endif + (void)dstate; +} + +//////////////////////////////////////////////////////////////////////////// + +#if defined(_MSC_VER) +# if _MSC_VER==1200 +# define XCAST(x) XED_STATIC_CAST(xed_int64_t,x) +# else +# define XCAST(x) (x) +# endif +#else +# define XCAST(x) (x) +#endif + +static void +dump_histo(xed_uint64_t* histo, + xed_uint32_t bins, + xed_uint32_t cycles_per_bin) +{ + xed_uint32_t i=0; + xed_uint64_t total=0; + double cdf = 0; + for(i=0;itotal_time); + printf("#Total instructions %s: " XED_FMT_LU "\n", dec_enc, + p->total_insts); + printf("#Total tail %s cycles: " XED_FMT_LU "\n", dec_enc, + p->total_time_tail); + printf("#Total tail instructions %s: " XED_FMT_LU "\n", dec_enc, + p->total_insts_tail); + + cpi = 1.0 * XCAST(p->total_time) / XCAST(p->total_insts); + printf("#Total cycles/instruction %s: %.2f\n" , dec_enc, cpi); + + cpi_tail = 1.0 * XCAST(p->total_time_tail) / + XCAST(p->total_insts_tail); + printf("#Total tail cycles/instruction %s: %.2f\n" , dec_enc, cpi_tail); + + if (p->bad_times) + printf("#Bad times: " XED_FMT_LU "\n", p->bad_times); + + if (di->histo) + dump_histo(p->histo, XED_HISTO_BINS, XED_HISTO_CYCLES_PER_BIN); +} + +void xed_print_decode_stats(xed_disas_info_t* di) +{ + print_decode_stats_internal(di, &xed_dec_stats, "XED3", "DECODE"); +} + +void xed_print_encode_stats(xed_disas_info_t* di) +{ + print_decode_stats_internal(di, &xed_enc_stats, "XED3", "ENCODE"); +} + + + +void +xed_map_region(const char* path, + void** start, + unsigned int* length) +{ +#if defined(_WIN32) + FILE* f; + size_t t,ilen; + xed_uint8_t* p; +#if defined(XED_MSVC8_OR_LATER) && !defined(PIN_CRT) + errno_t err; + fprintf(stderr,"#Opening %s\n", path); + err = fopen_s(&f,path,"rb"); +#else + int err=0; + fprintf(stderr,"#Opening %s\n", path); + f = fopen(path,"rb"); + err = (f==0); +#endif + if (err != 0) { + fprintf(stderr,"ERROR: Could not open %s\n", path); + exit(1); + } + err = fseek(f, 0, SEEK_END); + if (err != 0) { + fprintf(stderr,"ERROR: Could not fseek %s\n", path); + exit(1); + } + ilen = ftell(f); + fprintf(stderr,"#Trying to read " XED_FMT_SIZET "\n", ilen); + p = (xed_uint8_t*)malloc(ilen); + t=0; + err = fseek(f,0, SEEK_SET); + if (err != 0) { + fprintf(stderr,"ERROR: Could not fseek to start of file %s\n", path); + exit(1); + } + + while(t < ilen) { + size_t n; + if (feof(f)) { + fprintf(stderr, "#Read EOF. Stopping.\n"); + break; + } + n = fread(p+t, 1, ilen-t,f); + t = t+n; + fprintf(stderr,"#Read " XED_FMT_SIZET " of " XED_FMT_SIZET " bytes\n", + t, ilen); + if (ferror(f)) { + fprintf(stderr, "Error in file read. Stopping.\n"); + break; + } + } + fclose(f); + *start = p; + *length = (unsigned int)ilen; + +#else + int ilen,fd; + fd = open(path, O_RDONLY); + if (fd == -1) { + printf("Could not open file: %s\n" , path); + exit(1); + } + ilen = lseek(fd, 0, SEEK_END); // find the size. + if (ilen == -1) + xedex_derror("lseek failed"); + else + *length = (unsigned int) ilen; + + lseek(fd, 0, SEEK_SET); // go to the beginning + *start = mmap(0, + *length, + PROT_READ|PROT_WRITE, + MAP_PRIVATE, + fd, + 0); + if (*start == (void*) -1) + xedex_derror("could not map region"); +#endif + if (CLIENT_VERBOSE1) + printf("Mapped " XED_FMT_U " bytes!\n", *length); +} + + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_DECODER) + +static xed_disassembly_callback_fn_t registered_disasm_callback=0; + +void +xed_register_disassembly_callback(xed_disassembly_callback_fn_t f) +{ + registered_disasm_callback = f; +} + + +void disassemble(xed_disas_info_t* di, + char* buf, + int buflen, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + void* caller_data) +{ + int ok; + xed_print_info_t pi; + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = buflen; + pi.buf = buf; + + // passed back to symbolic disassembly function + pi.context = caller_data; + + // 0=use the default symbolic disassembly function registered via + // xed_register_disassembly_callback(). If nonzero, it would be a + // function pointer to a disassembly callback routine. See xed-disas.h + pi.disassembly_callback = registered_disasm_callback; + + pi.runtime_address = runtime_instruction_address; + pi.syntax = global_syntax; + pi.format_options_valid = 1; + pi.format_options = di->format_options; + pi.buf[0]=0; //allow use of strcat + + ok = xed_format_generic(&pi); + if (!ok) + { + pi.blen = xed_strncpy(pi.buf,"Error disassembling ",pi.blen); + pi.blen = xed_strncat(pi.buf, + xed_syntax_enum_t2str(pi.syntax), + pi.blen); + pi.blen = xed_strncat(pi.buf," syntax.",pi.blen); + } +} + +void xed_decode_error( xed_uint64_t runtime_instruction_address, + xed_uint64_t offset, + const xed_uint8_t* ptr, + xed_error_enum_t xed_error, + xed_uint_t length) +{ + char buf[XED_HEX_BUFLEN]; + printf("ERROR: %s Could not decode at offset: 0x" + XED_FMT_LX " PC: 0x" XED_FMT_LX ": [", + xed_error_enum_t2str(xed_error), + offset, + runtime_instruction_address); + + xed_print_hex_line(buf, ptr, length, XED_HEX_BUFLEN); + printf("%s]\n",buf); +} + +static void +print_hex_line(const xed_uint8_t* p, + unsigned int length) +{ + char buf[XED_HEX_BUFLEN]; + unsigned int lim = XED_HEX_BUFLEN/2; + if (length < lim) + lim = length; + xed_print_hex_line(buf,p, lim, XED_HEX_BUFLEN); + printf("%s\n", buf); +} + + + +xed_uint_t +disas_decode_binary(xed_disas_info_t* di, + const xed_uint8_t* hex_decode_text, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + // decode one instruction + xed_uint64_t t1,t2; + xed_error_enum_t xed_error; + xed_bool_t okay; + + if (CLIENT_VERBOSE) { + print_hex_line(hex_decode_text, bytes); + } + + t1 = xed_get_time(); + xed_error = decode_internal(xedd, hex_decode_text, bytes); + t2 = xed_get_time(); + okay = (xed_error == XED_ERROR_NONE); + +#if defined(PTI_XED_TEST) + if (okay) + pti_xed_test(xedd,hex_decode_text, bytes, runtime_address); +#endif + + if (CLIENT_VERBOSE3) { + xed_uint64_t delta = t2-t1; + printf("Decode time = " XED_FMT_LU "\n", delta); + } + + if (okay) { + + if (CLIENT_VERBOSE1) { + char tbuf[XED_TMP_BUF_LEN]; + xed_decoded_inst_dump(xedd,tbuf,XED_TMP_BUF_LEN); + printf("%s\n",tbuf); + } + if (CLIENT_VERBOSE) { + char buf[XED_TMP_BUF_LEN]; + if (xed_decoded_inst_valid(xedd)) + { + printf( "ICLASS: %s CATEGORY: %s EXTENSION: %s IFORM: %s" + " ISA_SET: %s\n", + xed_iclass_enum_t2str(xed_decoded_inst_get_iclass(xedd)), + xed_category_enum_t2str(xed_decoded_inst_get_category(xedd)), + xed_extension_enum_t2str(xed_decoded_inst_get_extension(xedd)), + xed_iform_enum_t2str(xed_decoded_inst_get_iform_enum(xedd)), + xed_isa_set_enum_t2str(xed_decoded_inst_get_isa_set(xedd))); + } + disassemble(di, buf,XED_TMP_BUF_LEN, xedd, runtime_address,0); + printf("SHORT: %s\n", buf); + } + return 1; + } + else { + xed_decode_error(0, 0, hex_decode_text, xed_error, 15); + return 0; + } +} +#endif // XED_DECODER + +#if defined(XED_ENCODER) && defined(XED_DECODER) +xed_uint_t +disas_decode_encode_binary(xed_disas_info_t* di, + const xed_uint8_t* decode_text_binary, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + // decode then encode one instruction + unsigned int retval_olen = 0; + xed_uint64_t dt1, dt2; + xed_bool_t decode_okay; + + // decode it... + dt1 = xed_get_time(); + decode_okay = disas_decode_binary(di, + decode_text_binary, + bytes, + xedd, + runtime_address); + dt2=xed_get_time(); + xed_stats_update(&xed_dec_stats, dt1, dt2); + + if (decode_okay) { + xed_error_enum_t encode_okay; + xed_uint64_t et1,et2; + unsigned int enc_olen, ilen = XED_MAX_INSTRUCTION_BYTES; + xed_uint8_t array[XED_MAX_INSTRUCTION_BYTES]; + // they are basically the same now + xed_encoder_request_t* enc_req = xedd; + // convert decode structure to proper encode structure + xed_encoder_request_init_from_decode(xedd); + + // encode it again... + et1 = xed_get_time(); + encode_okay = xed_encode(enc_req, array, ilen, &enc_olen); + et2 = xed_get_time(); + xed_stats_update(&xed_enc_stats, et1, et2); + if (encode_okay != XED_ERROR_NONE) { + if (CLIENT_VERBOSE) { + char buf[XED_TMP_BUF_LEN]; + char buf2[XED_TMP_BUF_LEN]; + int blen=XED_TMP_BUF_LEN; + xed_encode_request_print(enc_req, buf, XED_TMP_BUF_LEN); + blen = xed_strncpy(buf2,"Could not re-encode: ", blen); + blen = xed_strncat(buf2, buf, blen); + blen = xed_strncat(buf2,"\nError code was: ",blen); + blen = xed_strncat(buf2, + xed_error_enum_t2str(encode_okay),blen); + blen = xed_strncat(buf2, "\n",blen); + xedex_dwarn(buf2); + } + } + else { + retval_olen = enc_olen; + // See if it matched the original... + if (CLIENT_VERBOSE) { + char buf[XED_HEX_BUFLEN]; + xed_uint_t dec_length; + xed_print_hex_line(buf,array, enc_olen, XED_HEX_BUFLEN); + printf("Encodable! %s\n",buf); + dec_length = xed_decoded_inst_get_length(xedd); + if ((enc_olen != dec_length || + memcmp(decode_text_binary, array, enc_olen) )) { + char buf2[XED_TMP_BUF_LEN]; + char buf3[XED_TMP_BUF_LEN]; + printf("Discrepenacy after re-encoding. dec_len= " + XED_FMT_U " ", dec_length); + xed_print_hex_line(buf, decode_text_binary, + dec_length,XED_HEX_BUFLEN); + printf("[%s] ", buf); + printf("enc_olen= " XED_FMT_U "", enc_olen); + xed_print_hex_line(buf, array, enc_olen, XED_HEX_BUFLEN); + printf(" [%s] ", buf); + printf("for instruction: "); + xed_decoded_inst_dump(xedd, buf3,XED_TMP_BUF_LEN); + printf("%s\n", buf3); + printf("vs Encode request: "); + xed_encode_request_print(enc_req, buf2, XED_TMP_BUF_LEN); + printf("%s\n", buf2); + } + else + printf("Identical re-encoding\n"); + } + } + } + return retval_olen; +} +#endif +/////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) && defined(XED_AVX) +typedef enum { XED_AST_INPUT_NOTHING, + XED_AST_INPUT_SSE, + XED_AST_INPUT_AVX_SCALAR, + XED_AST_INPUT_AVX128, + XED_AST_INPUT_AVX256, + XED_AST_INPUT_VZEROALL, + XED_AST_INPUT_VZEROUPPER, + XED_AST_INPUT_XRSTOR, + XED_AST_INPUT_EVEX_SCALAR, + XED_AST_INPUT_EVEX128, + XED_AST_INPUT_EVEX256, + XED_AST_INPUT_EVEX512, + XED_AST_INPUT_LAST } xed_ast_input_enum_t; + +static char const* const xed_ast_input_enum_t_strings[] = { + "n/a", + "sse", + "avx.scalar", + "avx.128", + "avx.256", + "vzeroall", + "vzeroupper", + "xrstor", + "evex.scalar", + "evex.128", + "evex.256", + "evex.512" +}; + +static xed_uint8_t avx_extensions[XED_EXTENSION_LAST]; +static void init_interesting_avx(void) { + memset(avx_extensions,0,sizeof(xed_uint8_t)*XED_EXTENSION_LAST); + avx_extensions[XED_EXTENSION_AVX]=1; + avx_extensions[XED_EXTENSION_FMA]=1; + avx_extensions[XED_EXTENSION_F16C]=1; + avx_extensions[XED_EXTENSION_AVX2]=1; + avx_extensions[XED_EXTENSION_AVX2GATHER]=1; +#if defined(XED_SUPPORTS_AVX512) + avx_extensions[XED_EXTENSION_AVX512EVEX]=1; +#endif +} +static XED_INLINE int is_interesting_avx(xed_extension_enum_t extension) { + return avx_extensions[extension]; +} +static XED_INLINE xed_ast_input_enum_t avx_type(xed_decoded_inst_t* xedd) { + xed_uint32_t vl; +#if defined(XED_SUPPORTS_AVX512) + xed_uint32_t avx512 = (xed_decoded_inst_get_extension(xedd) == XED_EXTENSION_AVX512EVEX); +#else + xed_uint32_t avx512 = 0; +#endif + + // scalar ops are implicitly 128b + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_SIMD_SCALAR)) + return avx512 ? XED_AST_INPUT_EVEX_SCALAR : XED_AST_INPUT_AVX_SCALAR; + + // look at the VEX.VL field + vl = xed3_operand_get_vl(xedd); + switch(vl) { + case 0: return avx512 ? XED_AST_INPUT_EVEX128 : XED_AST_INPUT_AVX128; + case 1: return avx512 ? XED_AST_INPUT_EVEX256 : XED_AST_INPUT_AVX256; + case 2: return XED_AST_INPUT_EVEX512; + default: return XED_AST_INPUT_NOTHING; + } +} +static int is_sse(xed_decoded_inst_t* xedd) { + const xed_extension_enum_t extension = xed_decoded_inst_get_extension(xedd); + const xed_category_enum_t category = xed_decoded_inst_get_category(xedd); + + if (extension == XED_EXTENSION_SSE) + { + if (category != XED_CATEGORY_MMX && + category != XED_CATEGORY_PREFETCH) /* exclude PREFETCH* insts */ + return 1; + } + else if (extension == XED_EXTENSION_SSE2 || + extension == XED_EXTENSION_SSSE3 || + extension == XED_EXTENSION_SSE4) + { + if (category != XED_CATEGORY_MMX) + return 1; + } + else if (extension == XED_EXTENSION_AES || + extension == XED_EXTENSION_PCLMULQDQ +#if defined(XED_SUPPORTS_SHA) + || extension == XED_EXTENSION_SHA +#endif + ) + { + return 1; + } + return 0; +} + +static char const* xed_ast_input_enum_t2str(xed_ast_input_enum_t e) { + assert(e < XED_AST_INPUT_LAST); + return xed_ast_input_enum_t_strings[e]; +} +static xed_ast_input_enum_t classify_avx_sse(xed_decoded_inst_t* xedd) +{ + xed_extension_enum_t ext = xed_decoded_inst_get_extension(xedd); + xed_iclass_enum_t iclass = xed_decoded_inst_get_iclass(xedd); + if (iclass == XED_ICLASS_VZEROALL) { + return XED_AST_INPUT_VZEROALL; + } + else if (iclass == XED_ICLASS_VZEROUPPER) { + return XED_AST_INPUT_VZEROUPPER; + } + else if (is_interesting_avx(ext)) { + return avx_type(xedd); + } + else if (is_sse(xedd)) { + return XED_AST_INPUT_SSE; + } + else if (iclass == XED_ICLASS_XRSTOR) { + return XED_AST_INPUT_XRSTOR; + } + return XED_AST_INPUT_NOTHING; +} +#endif // XED_AVX + +/////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) + +static int +all_zeros(xed_uint8_t* p, unsigned int len) +{ + unsigned int i; + for( i=0;isymfn) { + char* name = (*di->symfn)(runtime_instruction_address, + di->caller_symbol_data); + if (name) { + if (di->xml_format) + printf("\n%s\n", name); + else + printf("\nSYM %s:\n", name); + } + } +} + +static void +emit_hex(xed_decoded_inst_t* xedd, unsigned char* z) +{ + unsigned int dec_len; + char buffer[XED_HEX_BUFLEN]; + dec_len = xed_decoded_inst_get_length(xedd); + xed_print_hex_line(buffer, (xed_uint8_t*) z, + dec_len, XED_HEX_BUFLEN); + printf("%s",buffer); + emit_pad(dec_len); +} + +static void +emit_cat_ext(xed_decoded_inst_t* xedd, + xed_disas_info_t* di) +{ + printf("%-9s ", + xed_category_enum_t2str( + xed_decoded_inst_get_category(xedd))); + printf("%-10s ", + xed_extension_enum_t2str( + xed_decoded_inst_get_extension(xedd))); + + if (di->emit_isa_set) + printf("%-10s ", + xed_isa_set_enum_t2str( + xed_decoded_inst_get_isa_set(xedd))); + +} +static void +emit_resync_msg(unsigned char* z, unsigned int x) +{ + char buf[XED_HEX_BUFLEN]; + printf("ERROR: found symbol in the middle of" + " an instruction. Resynchronizing...\n"); + printf("ERROR: Rejecting: ["); + xed_print_hex_line(buf, z, x, XED_HEX_BUFLEN); + printf("%s]\n",buf); +} + +static void +emit_dec_sep_msg(unsigned int i) { + printf("\n==============================================\n"); + printf("Decoding instruction " XED_FMT_U "\n", i); + printf("==============================================\n"); +} + +static void +emit_addr_hex(xed_uint64_t runtime_instruction_address, + unsigned char* z, + int ilim) +{ + char tbuf[XED_HEX_BUFLEN]; + printf("Runtime Address " XED_FMT_LX , + runtime_instruction_address); + xed_print_hex_line(tbuf, (xed_uint8_t*) z, ilim, XED_HEX_BUFLEN); + printf(" [%s]\n", tbuf); +} + +static void +emit_cat_ext_ast(xed_decoded_inst_t* xedd, + xed_disas_info_t* di) +{ +#if defined(XED_AVX) + if (di->ast) + { + printf("%-11s ", + xed_ast_input_enum_t2str( + classify_avx_sse(xedd))); + } + else +#endif + { + emit_cat_ext(xedd,di); + } + (void)di; //pacify compiler +} + +static void +emit_line_num(xed_disas_info_t* di, + xed_error_enum_t xed_error, + xed_uint64_t runtime_instruction_address) +{ + if (di->line_numbers || + xed_error == XED_ERROR_INVALID_FOR_CHIP) + { + if (di->line_number_info_fn) + (*di->line_number_info_fn)( + runtime_instruction_address); + } +} + + +static void +emit_xml(xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_disas_info_t* di) +{ + char buffer[XED_TMP_BUF_LEN]; + unsigned int dec_len; + + printf("\n"); + printf(" " XED_FMT_LX "\n", + runtime_instruction_address); + printf(" %s\n", + xed_category_enum_t2str( xed_decoded_inst_get_category(xedd))); + printf(" %s\n", + xed_extension_enum_t2str(xed_decoded_inst_get_extension(xedd))); + printf(" "); + dec_len = xed_decoded_inst_get_length(xedd); + xed_print_hex_line(buffer, (xed_uint8_t*) z, + dec_len, XED_TMP_BUF_LEN); + printf("%s\n",buffer); + disassemble(di, buffer,XED_TMP_BUF_LEN, + xedd, runtime_instruction_address, + di->caller_symbol_data); + printf( " %s\n",buffer); + printf("\n"); +} + + +static void +emit_disasm(xed_disas_info_t* di, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_dot_graph_supp_t* gs, + xed_error_enum_t xed_error) +{ + if (CLIENT_VERBOSE1) { + char tbuf[XED_TMP_BUF_LEN]; + xed_decoded_inst_dump(xedd,tbuf, XED_TMP_BUF_LEN); + printf("%s\n",tbuf); + } + if (CLIENT_VERBOSE) { + emit_sym(di, runtime_instruction_address); + if (di->xml_format) + emit_xml(xedd, runtime_instruction_address, z, di); + else + { + char buffer[XED_TMP_BUF_LEN]; + char const* fmt = "XDIS " XED_FMT_LX ": "; + if (di->format_options.lowercase_hex==0) + fmt = "XDIS " XED_FMT_LX_UPPER ": "; + + printf(fmt, runtime_instruction_address); + emit_cat_ext_ast(xedd,di); + emit_hex(xedd, z); + disassemble(di, + buffer,XED_TMP_BUF_LEN, + xedd, + runtime_instruction_address, + di->caller_symbol_data); + printf( "%s",buffer); + if (gs) { + xed_dot_graph_add_instruction( + gs, + xedd, + runtime_instruction_address, + di->caller_symbol_data, + registered_disasm_callback); + } + + if (xed_error == XED_ERROR_INVALID_FOR_CHIP) { + di->errors_chip_check++; + printf(" # INVALID-FOR-CHIP"); + } + emit_line_num(di, xed_error, + runtime_instruction_address); + + printf( "\n"); + } + } +} +static unsigned int +check_resync(xed_disas_info_t* di, + xed_uint64_t runtime_instruction_address, + unsigned int length, + unsigned char* z) +{ + if (di->resync && di->symfn) + { + unsigned int x; + for ( x=1 ; xsymfn)(runtime_instruction_address+x, + di->caller_symbol_data); + if (name) + { + /* bad news. We found a symbol in the middle of an + * instruction. That probably means decoding is messed up. + * This usually happens because of data-in the code/text + * section. We should reject the current instruction and + * pick up at the symbol address. */ + emit_resync_msg(z,x); + return x; + } + } + } + return 0; +} + +static void XED_NORETURN +die_zero_len( + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_disas_info_t* di, + xed_error_enum_t xed_error) +{ + printf("Zero length on decoded instruction!\n"); + xed_decode_error( runtime_instruction_address, + z-di->a, z, xed_error, 15); + xedex_derror("Dying"); +} + +void xed_disas_test(xed_disas_info_t* di) +{ + // this decodes are region defined by the input structure. + + static int first = 1; + xed_uint64_t errors = 0; + unsigned int m; + unsigned char* z; + unsigned char* zlimit; + unsigned int length; + int skipping; + int last_all_zeros; + unsigned int i; + int okay; + xed_decoded_inst_t xedd; + xed_uint64_t runtime_instruction_address; + xed_dot_graph_supp_t* gs = 0; + xed_bool_t graph_empty = 1; + unsigned int resync; + + if (di->dot_graph_output) { + xed_syntax_enum_t local_syntax = XED_SYNTAX_INTEL; + gs = xed_dot_graph_supp_create(local_syntax); + } + + if (first) { + xed_stats_zero(&xed_dec_stats, di); + first = 0; + } + + m = di->ninst; // number of things to decode + z = di->a; + + if (di->runtime_vaddr_disas_start) + if (di->runtime_vaddr_disas_start > di->runtime_vaddr) + z = (di->runtime_vaddr_disas_start - di->runtime_vaddr) + + di->a; + + zlimit = 0; + if (di->runtime_vaddr_disas_end) { + if (di->runtime_vaddr_disas_end > di->runtime_vaddr) + zlimit = (di->runtime_vaddr_disas_end - di->runtime_vaddr) + + di->a; + else /* end address is before start of this region -- skip it */ + goto finish; + } + + if (z >= di->q) /* start pointer is after end of section */ + goto finish; + + // for skipping long strings of zeros + skipping = 0; + last_all_zeros = 0; + for( i=0; i= zlimit) { + if (di->xml_format == 0) + printf("# end of range.\n"); + break; + } + if (z >= di->q) { + if (di->xml_format == 0) + printf("# end of text section.\n"); + break; + } + + /* if we get near the end of the section, clip the itext length */ + ilim = 15; + elim = di->q - z; + if (elim < ilim) + ilim = elim; + + if (CLIENT_VERBOSE3) + emit_dec_sep_msg(i); + + // if we get two full things of 0's in a row, start skipping. + if (all_zeros((xed_uint8_t*) z, ilim)) + { + if (skipping) { + z = z + ilim; + continue; + } + else if (last_all_zeros) { + printf("...\n"); + z = z + ilim; + skipping = 1; + continue; + } + else + last_all_zeros = 1; + } + else + { + skipping = 0; + last_all_zeros = 0; + } + + runtime_instruction_address = ((xed_uint64_t)(z-di->a)) + + di->runtime_vaddr; + + if (CLIENT_VERBOSE3) + emit_addr_hex(runtime_instruction_address, z, ilim); + + okay = 0; + length = 0; + + init_xedd(&xedd, &(di->dstate), di->chip, di->mpx_mode); + + if ( di->decode_only ) + { + xed_uint64_t t1,t2; + xed_error_enum_t xed_error = XED_ERROR_NONE; + + t1 = xed_get_time(); + + //do the decode + xed_error = decode_internal( + &xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim); + + t2 = xed_get_time(); + + okay = (xed_error == XED_ERROR_NONE); +#if defined(PTI_XED_TEST) + if (okay) + pti_xed_test(&xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim, + runtime_instruction_address); +#endif + + xed_stats_update(&xed_dec_stats, t1, t2); + length = xed_decoded_inst_get_length(&xedd); + + if (okay && length == 0) + die_zero_len(runtime_instruction_address, z, di, xed_error); + + resync = check_resync(di, runtime_instruction_address, length, z); + if (resync) { + z += resync; + continue; + } + + xed_dec_stats.total_ilen += length; + +//we don't want to print out disassembly with ILD perf +#if !defined(XED_ILD_ONLY) && !defined(XED2_PERF_MEASURE) + + if (okay || xed_error == XED_ERROR_INVALID_FOR_CHIP) + { + // we still print it out if it is invalid for the chip. + // so that people can see the problematic instruction + emit_disasm(di, &xedd, + runtime_instruction_address, + z, gs, xed_error); + if (CLIENT_VERBOSE && gs) + graph_empty = 0; + } + + if (okay == 0) + { + errors++; + length = xed_decoded_inst_get_length(&xedd); + if (length == 0) + length = 1; + + xed_decode_error( runtime_instruction_address, + z-di->a, + z, + xed_error, + length); + + } // okay == 0 + } // decode_only + +# if defined(XED_ENCODER) && defined(XED_DECODER) + else // decode->encode + { + unsigned int olen = 0; + olen = disas_decode_encode_binary(di, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim, + &xedd, + runtime_instruction_address); + okay = (olen != 0); + if (!okay) { + errors++; + printf("-- Could not decode/encode at offset: %d\n" , + (int)(z-di->a)); + // just give a length of 1B to see if we can restart decode... + length = 1; + } + else { + length = xed_decoded_inst_get_length(&xedd); + xed_dec_stats.total_ilen += length; + xed_dec_stats.total_olen += olen; + if (length > olen) + xed_dec_stats.total_shorter += (length - olen); + else + xed_dec_stats.total_longer += (olen - length); + } + } +# endif // XED_ENCODER & XED_DECODER +#endif //!defined(XED_ILD_ONLY) + + + z = z + length; + } + + if (di->xml_format == 0) { + printf( "# Errors: " XED_FMT_LU "\n", errors); + } +finish: + + if (gs) { + if (graph_empty ==0 ) + xed_dot_graph_dump(di->dot_graph_output, gs); + xed_dot_graph_supp_deallocate(gs); + } + + di->errors += errors; +} +#endif + +xed_uint8_t +convert_ascii_nibble(char c) +{ + if (c >= '0' && c <= '9') { + return c-'0'; + } + else if (c >= 'a' && c <= 'f') { + return c-'a' + 10; + } + else if (c >= 'A' && c <= 'F') { + return c-'A' + 10; + } + else { + char buffer[XED_HEX_BUFLEN]; + char* x; + xed_strncpy(buffer,"Invalid character in hex string: ", XED_HEX_BUFLEN); + x= buffer+strlen(buffer); + *x++ = c; + *x++ = 0; + xedex_derror(buffer); + return 0; + } +} + + + +xed_uint64_t convert_ascii_hex_to_int(const char* s) { + xed_uint64_t retval = 0; + const char* p = s; + while (*p) { + retval = (retval << 4) + convert_ascii_nibble(*p); + p++; + } + return retval; +} + + +xed_uint8_t convert_ascii_nibbles(char c1, char c2) { + xed_uint8_t a = convert_ascii_nibble(c1) * 16 + convert_ascii_nibble(c2); + return a; +} + +unsigned int +xed_convert_ascii_to_hex(const char* src, xed_uint8_t* dst, + unsigned int max_bytes) +{ + unsigned int j; + unsigned int p = 0; + unsigned int i = 0; + + const unsigned int len = XED_STATIC_CAST(unsigned int,strlen(src)); + if ((len & 1) != 0) + xedex_derror("test string was not an even number of nibbles"); + + if (len > (max_bytes * 2) ) + xedex_derror("test string was too long"); + + for( j=0;j= '0' && c <= '9') + { + unsigned int digit = c - '0'; + v = v*10 + digit; + } + else if (c == '_') /* skip underscores */ + continue; + else + { + break; + } + } + return v*sign; +} + +static xed_int64_t +convert_base16(const char* buf) +{ + xed_int64_t v = 0; + int len = XED_STATIC_CAST(int,strlen(buf)); + int start =0 ; + int i; + if (len > 2 && buf[0] == '0' && (buf[1] == 'x' || buf[1] == 'X')) + { + start = 2; + } + for(i=start;i= '0' && c <= '9') + { + unsigned int digit = c - '0'; + v = v*16 + digit; + } + else if (c >= 'A' && c <= 'F') + { + unsigned int digit = c - 'A' + 10; + v = v*16 + digit; + } + else if (c >= 'a' && c <= 'f') + { + unsigned int digit = c - 'a' + 10; + v = v*16 + digit; + } + else if (c == '_') /* skip underscores */ + continue; + else + { + break; + } + } + return v; +} + +static xed_int64_t +xed_internal_strtoll(const char* buf, int base) +{ + switch(base) + { + case 0: + if (strlen(buf) > 2 && buf[0] == '0' && + (buf[1] == 'x' || buf[1] == 'X')) + { + return convert_base16(buf); + } + return convert_base10(buf); + case 10: + return convert_base10(buf); + case 16: + return convert_base16(buf); + default: + assert(0); + } + return 0; +} + + +xed_int64_t xed_strtoll(const char* buf, int base) +{ + xed_int64_t t; + // strtoll is missing on some compilers and buggy on some platforms + t = xed_internal_strtoll(buf,base); + return t; +} + +char* xed_strdup(char const* const src) { + unsigned int n = (unsigned int)strlen(src)+1; /* plus one for null */ + char* dst = (char*)malloc(n*sizeof(char)); + assert(dst != 0); + dst[0]=0; /* start w/ a null */ + xed_strncat(dst, src, n); + return dst; +} + +void xed_example_utils_init(void) { +#if defined(XED_DECODER) && defined (BINARY_DUMP) + open_binary_output_file(); +#endif +#if defined(XED_DECODER) && defined(XED_AVX) + init_interesting_avx(); +#endif +} + + +char const* xedex_append_string(char const* p, // p is free()'d + char const* x) +{ + char* m = 0; //returned pointer + char* n = 0; //temp ptr for copying + char const* t = 0; //temp ptr for copying + size_t tl = (p?strlen(p):0) + strlen(x) + 1; + m = n = (char*) malloc(tl); + if (p) { + t = p; + while(*t) + *n++ = *t++; + } + + t = x; + while(*t) + *n++ = *t++; + *n++ = 0; // null terminate + if (p) + free((void*)p); + return m; +} + +//// +static xed_str_list_t* alloc_str_node(void) { + return (xed_str_list_t*) malloc(sizeof(xed_str_list_t)); +} + +// MS does not have strsep() +static char* +portable_strsep(char** input_string, char const* const sep) +{ + char* p = *input_string; + if (p) { + // find token in input string + char* t = strpbrk(*input_string, sep); + if (t) { + *t = 0; // write a null at sep + *input_string = t+1; // advance pointer + return p; + } + // no token, just return input string + *input_string=0; // clear pointer + return p; + } + *input_string = 0; + return 0; +} + +xed_str_list_t* xed_tokenize(char const* const p, char const* const sep) +{ + // return a list of strings with their own storage for the tokens. if + // one were to free the list, one would have to just free the first + // token. The strsep() puts nulls in to a copy of the input string p + // replacing the delimiters. + + xed_str_list_t* head=0; + xed_str_list_t* last=0; + xed_str_list_t* cur=0; + char* token=0; + char* tmp_string=0; + + tmp_string = xed_strdup(p); + // puts a null in string at token and returns pointer to first token, + // updates tmp_string to point after null. + while(1) + { + token = portable_strsep(&tmp_string, sep); + if (!token) + break; + if (token[0]) // we know token is non-null + { + cur = alloc_str_node(); + if (!head) + head = cur; + cur->next = 0; + cur->s = token; + if (last) + last->next = cur; + last = cur; + } + } + return head; +} + + +xed_uint_t xed_str_list_size(xed_str_list_t* p) { //count chunks + unsigned int c = 0; + while(p) { + c++; + p = p->next; + } + return c; +} + diff --git a/examples/xed-examples-util.h b/examples/xed-examples-util.h new file mode 100755 index 0000000..4373259 --- /dev/null +++ b/examples/xed-examples-util.h @@ -0,0 +1,170 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-examples-util.h + + +#ifndef _XED_EXAMPLES_UTIL_H_ +# define _XED_EXAMPLES_UTIL_H_ + +#include +#include "xed-interface.h" + +extern xed_syntax_enum_t global_syntax; +extern int client_verbose; + +#define CLIENT_VERBOSE (client_verbose > 1) +#define CLIENT_VERBOSE0 (client_verbose > 2) +#define CLIENT_VERBOSE1 (client_verbose > 3) +#define CLIENT_VERBOSE2 (client_verbose > 4) +#define CLIENT_VERBOSE3 (client_verbose > 5) + +char* xed_upcase_buf(char* s); + +/// Accepts K / M / G (or B) qualifiers ot multiply +xed_int64_t xed_atoi_general(char* buf, int mul); +xed_int64_t xed_atoi_hex(char* buf); + +/// Converts "112233" in to 0x112233 +xed_uint64_t convert_ascii_hex_to_int(const char* s); + + +unsigned int xed_convert_ascii_to_hex(const char* src, + xed_uint8_t* dst, + unsigned int max_bytes); + +#define XED_HEX_BUFLEN 200 +void xed_print_hex_line(char* buf, const xed_uint8_t* array, const int length, const int buflen); + +void XED_NORETURN xedex_derror(const char* s); +void xedex_dwarn(const char* s); + +////////////////////////////////////////////////////////////////////// + + +typedef struct { + xed_state_t dstate; + int ninst; + int decode_only; + int sixty_four_bit; + int mpx_mode; + char* input_file_name; + char* symbol_search_path; // for dbghelp symbol caches + char* target_section; + xed_bool_t use_binary_mode; + xed_int64_t addr_start; + xed_int64_t addr_end; + xed_bool_t xml_format; + xed_int64_t fake_base; + xed_bool_t resync; /* turn on/off symbol-based resynchronization */ + xed_bool_t line_numbers; /* control for printing file/line info */ + FILE* dot_graph_output; + unsigned int perf_tail_start; + xed_bool_t ast; + xed_bool_t histo; + xed_chip_enum_t chip; + xed_bool_t emit_isa_set; + xed_format_options_t format_options; + + xed_uint64_t errors; + xed_uint64_t errors_chip_check; + + unsigned char* s; // start of image + unsigned char* a; // start of instructions to decode region + unsigned char* q; // end of region + // where this region would live at runtime + xed_uint64_t runtime_vaddr; + // where to start in program space, if not zero + xed_uint64_t runtime_vaddr_disas_start; + + // where to stop in program space, if not zero + xed_uint64_t runtime_vaddr_disas_end; + + // a function to convert addresses to symbols + char* (*symfn)(xed_uint64_t, void*); + void* caller_symbol_data; + + void (*line_number_info_fn)(xed_uint64_t addr); + +} xed_disas_info_t; + +void xed_disas_info_init(xed_disas_info_t* p); + +void xed_map_region(const char* path, + void** start, + unsigned int* length); + + + +void xed_disas_test(xed_disas_info_t* di); + + + +// returns 1 on success, 0 on failure +xed_uint_t disas_decode_binary(xed_disas_info_t* di, + const xed_uint8_t* hex_decode_text, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address); + +// returns encode length on success, 0 on failure +xed_uint_t disas_decode_encode_binary(xed_disas_info_t* di, + const xed_uint8_t* decode_text_binary, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address); + + +void xed_print_decode_stats(xed_disas_info_t* di); +void xed_print_encode_stats(xed_disas_info_t* di); + +void xed_register_disassembly_callback( + xed_disassembly_callback_fn_t f); + + +void disassemble(xed_disas_info_t* di, + char* buf, + int buflen, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + void* caller_data); + +// 64b version missing on some MS compilers so I wrap it for portability. +// This function is rather limited and only handles base 10 and base 16. +xed_int64_t xed_strtoll(const char* buf, int base); + +char* xed_strdup(char const* const src); + +void xed_example_utils_init(void); + +void init_xedd(xed_decoded_inst_t* xedd, + xed_state_t const* const dstate, + xed_chip_enum_t chip, + int mpx_mode); + +char const* xedex_append_string(char const* p, // p is free()'d + char const* x); + +typedef struct xed_str_list_s { + char* s; + struct xed_str_list_s* next; +} xed_str_list_t; + +xed_str_list_t* xed_tokenize(char const* const p, char const* const sep); +xed_uint_t xed_str_list_size(xed_str_list_t* p); // counts chunks + +#endif // file diff --git a/examples/xed-min.c b/examples/xed-min.c new file mode 100644 index 0000000..f17f40d --- /dev/null +++ b/examples/xed-min.c @@ -0,0 +1,68 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-min.c +/// @brief a minimal toy example of using the decoder. + +#include "xed-interface.h" +#include + +int main(int argc, char** argv); + +int main(int argc, char** argv) { + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_bool_t long_mode = 0; + // create the decoded instruction, and fill in the machine mode (dstate) + // make up a simple 2Byte instruction to decode + unsigned int bytes = 0; + unsigned char itext[15] = { 0xf, 0x85, 0x99, 0x00, 0x00, 0x00 }; + + // initialize the XED tables -- one time. + xed_tables_init(); + + // The state of the machine -- required for decoding + if (long_mode) { + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width = XED_ADDRESS_WIDTH_64b; + } + else { + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width = XED_ADDRESS_WIDTH_32b; + } + + // This is a test of error handling. I vary the instuction length from + // 0 bytes to 15 bytes. Normally, you should send in 15 bytes of itext + // unless you are near the end of a page and don't want to take a page + // fault or tlb miss. Note, you have to reinitialize the xedd each time + // you try to decode in to it. + + // Try different instruction lengths to see when XED recognizes an + // instruction as valid. + for(bytes = 0;bytes<=15;bytes++) { + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_error = xed_decode(&xedd, + XED_STATIC_CAST(const xed_uint8_t*,itext), + bytes); + printf("%d %s\n",(int)bytes, xed_error_enum_t2str(xed_error)); + } + return 0; + (void) argc; (void) argv; //pacify compiler +} diff --git a/examples/xed-reps.c b/examples/xed-reps.c new file mode 100644 index 0000000..ec0d64a --- /dev/null +++ b/examples/xed-reps.c @@ -0,0 +1,107 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-min.c +/// @brief a minimal toy example of using the decoder. + +#include "xed-interface.h" +#include + +int main(int argc, char** argv); + +int xtest(xed_iclass_enum_t a, xed_iclass_enum_t b) +{ + if (a != b) { + printf("MISMATCH: %s %s\n", + xed_iclass_enum_t2str(a), + xed_iclass_enum_t2str(b)); + return 1; + } + printf("MATCH: %s %s\n", + xed_iclass_enum_t2str(a), + xed_iclass_enum_t2str(b)); + return 0; +} + +int main(int argc, char** argv) +{ + xed_uint_t i=0; + int r=0; + + const xed_iclass_enum_t repe[] = { + XED_ICLASS_REPE_CMPSB, + XED_ICLASS_REPE_CMPSD, + XED_ICLASS_REPE_CMPSQ, + XED_ICLASS_REPE_CMPSW, + XED_ICLASS_REPE_SCASB, + XED_ICLASS_REPE_SCASD, + XED_ICLASS_REPE_SCASQ, + XED_ICLASS_REPE_SCASW, + XED_ICLASS_INVALID }; + const xed_iclass_enum_t repne[] = { + XED_ICLASS_REPNE_CMPSB, + XED_ICLASS_REPNE_CMPSD, + XED_ICLASS_REPNE_CMPSQ, + XED_ICLASS_REPNE_CMPSW, + XED_ICLASS_REPNE_SCASB, + XED_ICLASS_REPNE_SCASD, + XED_ICLASS_REPNE_SCASQ, + XED_ICLASS_REPNE_SCASW, + XED_ICLASS_INVALID }; + const xed_iclass_enum_t rep[] = { + XED_ICLASS_REP_INSB, + XED_ICLASS_REP_INSD, + XED_ICLASS_REP_INSW, + XED_ICLASS_REP_LODSB, + XED_ICLASS_REP_LODSD, + XED_ICLASS_REP_LODSQ, + XED_ICLASS_REP_LODSW, + XED_ICLASS_REP_MOVSB, + XED_ICLASS_REP_MOVSD, + XED_ICLASS_REP_MOVSQ, + XED_ICLASS_REP_MOVSW, + XED_ICLASS_REP_OUTSB, + XED_ICLASS_REP_OUTSD, + XED_ICLASS_REP_OUTSW, + XED_ICLASS_REP_STOSB, + XED_ICLASS_REP_STOSD, + XED_ICLASS_REP_STOSQ, + XED_ICLASS_REP_STOSW, + XED_ICLASS_INVALID }; + + + xed_tables_init(); + + for (i=0; repe[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(repe[i]); + xed_iclass_enum_t xr = xed_repe_map(norep); + r |= xtest(repe[i],xr); + } + for (i=0; repne[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(repne[i]); + xed_iclass_enum_t xr = xed_repne_map(norep); + r |= xtest(repne[i],xr); + } + for (i=0; rep[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(rep[i]); + xed_iclass_enum_t xr = xed_rep_map(norep); + r |= xtest(rep[i],xr); + } + + return r; + (void) argc; (void) argv; //pacify compiler +} diff --git a/examples/xed-size.c b/examples/xed-size.c new file mode 100644 index 0000000..7477c3b --- /dev/null +++ b/examples/xed-size.c @@ -0,0 +1,34 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-interface.h" +#include + +int main(int argc, char** argv); +int main(int argc, char** argv) { + /* I use this to keep track of the size of my per-instruction data structures */ + xed_decoded_inst_t x; + /*xed_tables_init(); */ + printf("xed_decoded_inst_t %12d\n", (int)sizeof(xed_decoded_inst_t)); + printf("xed_inst_t %12d\n", (int)sizeof(xed_inst_t)); + printf("xed_operand_t %12d\n", (int)sizeof(xed_operand_t)); + printf("xed_iform_info_t %12d\n", (int)sizeof(xed_iform_info_t)); + return 0; + (void) argc; (void) argv; //pacify compiler + (void) x; +} diff --git a/examples/xed-symbol-table.c b/examples/xed-symbol-table.c new file mode 100644 index 0000000..8f22208 --- /dev/null +++ b/examples/xed-symbol-table.c @@ -0,0 +1,151 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include "xed-interface.h" +#include "xed-portability.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" + +////////////////////////////////////////////////////////////////////// +void xed_local_symbol_table_init(xed_local_symbol_table_t* p) +{ + avl_tree_init(&p->atree); +} + +void xed_symbol_table_init(xed_symbol_table_t* p) { + p->curtab = 0; + xed_local_symbol_table_init(&p->gtab); + avl_tree_init(&p->avl_lmap); +} + +xed_local_symbol_table_t* xst_get_local_map(xed_symbol_table_t* p, + xed_uint32_t section) +{ + xed_local_symbol_table_t* v = + (xed_local_symbol_table_t*) avl_find(&p->avl_lmap, section); + return v; +} + +xed_local_symbol_table_t* xst_make_local_map(xed_symbol_table_t* p, + xed_uint32_t section) +{ + xed_local_symbol_table_t* n = + (xed_local_symbol_table_t*) malloc(sizeof(xed_local_symbol_table_t)); + xed_local_symbol_table_init(n); + avl_insert(&p->avl_lmap, section, n, 0); + return n; +} + +void xst_set_current_table(xed_symbol_table_t* p, + xed_uint32_t section) +{ + p->curtab = xst_get_local_map(p,section); +} + +void xst_add_local_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name, + xed_uint32_t section) +{ + xed_local_symbol_table_t* ltab = xst_get_local_map(p,section); + if (ltab == 0) + ltab = xst_make_local_map(p,section); + avl_insert(<ab->atree,addr, name, 0); +} + +void xst_add_global_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name) { + avl_insert(&p->gtab.atree,addr, name, 0); +} + + + +////////////////////////////////////////////////////////////////////// +static xed_bool_t +find_symbol_address(xed_local_symbol_table_t* ltab, + xed_uint64_t tgt, + xed_uint64_t* sym_addr) +{ + uint64_t lbkey=0; + void* sym = avl_find_lower_bound(<ab->atree, tgt, &lbkey); + if (sym) { + *sym_addr = lbkey; + return 1; + } + return 0; +} + +static xed_bool_t +find_symbol_address_global(xed_uint64_t tgt, + xed_symbol_table_t* symbol_table, + xed_uint64_t* sym_addr) /* output*/ +{ + xed_bool_t r = 0; + if (symbol_table) { + /* look global and then local */ + r = find_symbol_address(&symbol_table->gtab, tgt, sym_addr); + if (r == 0 && symbol_table->curtab) { + r = find_symbol_address(symbol_table->curtab, tgt, sym_addr); + } + } + return r; +} + + +char* get_symbol(xed_uint64_t a, void* caller_data) { + xed_symbol_table_t* symbol_table = (xed_symbol_table_t*)caller_data; + /* look in the global symbol table first */ + char* name = (char*)avl_find(&symbol_table->gtab.atree, a); + if (name) + return name; + /* look in the local symbol table if present */ + if (symbol_table->curtab) { + name = (char*)avl_find(&symbol_table->curtab->atree, a); + return name; + } + return 0; +} + + +int xed_disassembly_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data) +{ + xed_uint64_t symbol_address; + xed_symbol_table_t* symbol_table = (xed_symbol_table_t*)caller_data; + xed_bool_t found = find_symbol_address_global(address, + symbol_table, + &symbol_address); + if (found) { + char* symbol = get_symbol(symbol_address, caller_data); + if (symbol) { + if (xed_strlen(symbol) < buffer_length) + xed_strncpy(symbol_buffer, symbol, buffer_length); + else { + xed_strncpy(symbol_buffer, symbol, buffer_length-1); + symbol_buffer[buffer_length-1]=0; + } + *offset = address - symbol_address; + return 1; + } + } + return 0; +} diff --git a/examples/xed-symbol-table.h b/examples/xed-symbol-table.h new file mode 100644 index 0000000..33b7050 --- /dev/null +++ b/examples/xed-symbol-table.h @@ -0,0 +1,70 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_SYMBOL_TABLE_H_) +#define _XED_SYMBOL_TABLE_H_ + +#include "xed-interface.h" +#include "xed-examples-util.h" +#include "avltree.h" +#include + +typedef struct { + avl_tree_t atree; +} xed_local_symbol_table_t; + +void xed_local_symbol_table_init(xed_local_symbol_table_t* p); + +typedef struct { + xed_local_symbol_table_t gtab; + /* section number maps to a local symbol table */ + avl_tree_t avl_lmap; + /* the symbol table for the current section */ + xed_local_symbol_table_t* curtab; + +} xed_symbol_table_t; + +void xed_symbol_table_init(xed_symbol_table_t* p); + +xed_local_symbol_table_t* xst_get_local_map(xed_symbol_table_t* p, + xed_uint32_t section); + +xed_local_symbol_table_t* xst_make_local_map(xed_symbol_table_t* p, + xed_uint32_t section); + +void xst_set_current_table(xed_symbol_table_t* p, + xed_uint32_t section); + +void xst_add_local_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name, + xed_uint32_t section); + +void xst_add_global_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name); + +//////////////////////////////////////////////////////////////// + +char* get_symbol(xed_uint64_t a, void* symbol_table); + +int xed_disassembly_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data); +#endif diff --git a/examples/xed-tables.c b/examples/xed-tables.c new file mode 100644 index 0000000..b7c9e02 --- /dev/null +++ b/examples/xed-tables.c @@ -0,0 +1,93 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-tables.c +/// @brief a minimal example of accessing the XED internal tables + +#include +#include "xed-interface.h" + + +void dump_operand(const xed_operand_t* op) { + printf("%s ", xed_operand_enum_t2str(xed_operand_name(op))); + printf("%s ", + xed_operand_visibility_enum_t2str(xed_operand_operand_visibility(op))); + printf("%s ", xed_operand_action_enum_t2str(xed_operand_rw(op))); + printf("%s ", xed_operand_type_enum_t2str(xed_operand_type(op))); + printf("%s ", xed_operand_element_xtype_enum_t2str(xed_operand_xtype(op))); + if (xed_operand_type(op) == XED_OPERAND_TYPE_NT_LOOKUP_FN) + printf("%s ", + xed_nonterminal_enum_t2str(xed_operand_nonterminal_name(op))); + if (xed_operand_type(op) == XED_OPERAND_TYPE_REG) + printf("%s ", xed_reg_enum_t2str(xed_operand_reg(op))); +} + + +void print_attributes(const xed_inst_t* xi) { + /* Walk the attributes. Generally, you'll know the one you want to + * query and just access that one directly. */ + + unsigned int i, nattributes = xed_attribute_max(); + + printf("ATTRIBUTES: "); + for(i=0;i + +int main(int argc, char** argv); + +typedef struct +{ + unsigned int len; + unsigned char itext[15]; +} xed_test_t; + +xed_test_t tests[] = { + { 2, { 0, 0 } }, + { 2, { 2, 0 } }, + { 2, { 0xF3, 0x90 } }, + { 0 } +}; + +int main(int argc, char** argv) { + unsigned int i,j; + xed_state_t dstate; + xed_tables_init(); + xed_state_zero(&dstate); + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, + XED_ADDRESS_WIDTH_32b); + for ( i=0; tests[i].len ; i++) { + xed_bool_t okay; + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + printf("Testing: "); + for( j=0; j< tests[i].len; j++) + printf("%02x ",XED_STATIC_CAST(unsigned int,tests[i].itext[j])); + printf("\n"); + + xed_error = xed_decode(&xedd, + XED_REINTERPRET_CAST(xed_uint8_t*,tests[i].itext), + tests[i].len); + + okay = (xed_error == XED_ERROR_NONE); + if (okay) { + printf("OK\n"); + } + } + (void) argc; (void) argv; //pacify compiler + return 0; +} diff --git a/examples/xed.c b/examples/xed.c new file mode 100644 index 0000000..0a16c4a --- /dev/null +++ b/examples/xed.c @@ -0,0 +1,829 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed.c + + +//////////////////////////////////////////////////////////////////////////// + +#include "xed-interface.h" +#include "xed-immdis.h" +#include "xed-portability.h" +#include "xed-examples-util.h" +#if defined(XED_ENCODER) +# include "xed-enc-lang.h" +#endif +#include "xed-disas-elf.h" +#include "xed-disas-macho.h" +#include "xed-disas-raw.h" +#include "xed-disas-hex.h" +#include "xed-disas-pecoff.h" + +#include +#include +#include + +int main(int argc, char** argv); +static int intel_asm_emit = 0; + +//////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) +static xed_uint_t disas_decode( xed_disas_info_t* di, + const char* decode_text, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + xed_uint8_t hex_decode_text[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t bytes = xed_convert_ascii_to_hex(decode_text, + hex_decode_text, + XED_MAX_INSTRUCTION_BYTES); + return disas_decode_binary(di, + hex_decode_text, + bytes, + xedd, + runtime_address); +} +#endif + +#if defined(XED_DECODER) && defined(XED_ENCODER) +static unsigned int disas_decode_encode(xed_disas_info_t* di, + const char* decode_text, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + xed_uint8_t hex_decode_text[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t bytes = xed_convert_ascii_to_hex( decode_text, + hex_decode_text, + XED_MAX_INSTRUCTION_BYTES); + return disas_decode_encode_binary(di, + hex_decode_text, + bytes, + xedd, + runtime_address); +} +#endif + +static FILE* +fopen_portable(char const* const file_name, + char const* const mode) +{ + FILE* f = 0; +#if defined(XED_WINDOWS) && !defined(PIN_CRT) + errno_t error = fopen_s(&f, file_name, mode); + if (error != 0) + return 0; +#else + f = fopen(file_name, mode); +#endif + return f; +} + + + +#if defined(XED_ENCODER) +static void print_bytes_pseudo_op(const xed_uint8_t* array, unsigned int olen) { + unsigned int i; + printf(".byte "); + for(i=0;i0) + printf(","); + printf("0x%02x",(xed_uint32_t)(array[i])); + } + printf("\n"); +} +static void print_intel_asm_emit(const xed_uint8_t* array, unsigned int olen) { + unsigned int i; + for(i=0;i 0) + printf(", "); + printf("0x%02x",array[i]); + } + printf("\n"); + } + fclose(f); +} +#endif +static void usage(char* prog) { + unsigned int i; + static const char* usage_msg[] = { + "One of the following is required:", +#if defined(__APPLE__) + "\t-i input_file (decode macho-format file)", +#elif defined(XED_ELF_READER) + "\t-i input_file (decode elf-format file)", +#elif defined(_WIN32) + "\t-i input_file (decode pecoff-format file)", +#endif + "\t-ir raw_input_file (decode a raw unformatted binary file)", + "\t-ih hex_input_file (decode a raw unformatted ASCII hex file)", + "\t-d hex-string (decode one instruction, must be last)", +#if defined(XED_ENCODER) + "\t-ide input_file (decode/encode file)", + "\t-e instruction (encode, must be last)", + "\t-ie file-to-assemble (assemble the contents of the file)", + "\t-de hex-string (decode-then-encode, must be last)", +#endif + "", + "Optional arguments:", + "", + "\t-v N (0=quiet, 1=errors, 2=useful-info, 3=trace,", + "\t 5=very verbose)", + "\t-xv N (XED engine verbosity, 0...99)", + "", + "\t-chip-check CHIP (count instructions that are not valid for CHIP)", + "\t-chip-check-list (list the valid chips)", + "", + "\t-s section (target section for file disassembly,", + "\t PECOFF and ELF formats only)", + "", + "\t-n N (number of instructions to decode. Default 100M,", + "\t accepts K/M/G qualifiers)", + " ", + "\t-b addr (Base address offset, for DLLs/shared libraries.", + "\t Use 0x for hex addresses)", + "\t-as addr (Address to start disassembling.", + "\t Use 0x for hex addresses)", + "\t-ae addr (Address to end disassembling.", + "\t Use 0x for hex addresses)", + "\t-no-resync (Disable symbol-based resynchronization algorithm", + "\t for disassembly)", + "\t-ast (Show the AVX/SSE transition classfication)", + "\t-histo (Histogram decode times)", + "", + "\t-I (Intel syntax for disassembly)", + "\t-A (ATT SYSV syntax for disassembly)", + "\t-isa-set (Emit the XED \"ISA set\" in dissasembly)", + "\t-xml (XML formatting)", + "\t-uc (upper case hex formatting)", + "\t-nwm (Format AVX512 without curly braces for writemasks, include k0)", + "\t-emit (Output __emit statements for the Intel compiler)", +#if defined(XED_DWARF) + "\t-line (Emit line number information, if present)", +#endif + "\t-dot FN (Emit a register dependence graph file in dot format.", + "\t Best used with -as ADDR -ae ADDR to limit graph size.)", + "", + "\t-r (for REAL_16 mode, 16b addressing (20b addresses),", + "\t 16b default data size)", + "\t-16 (for LEGACY_16 mode, 16b addressing,", + "\t 16b default data size)", + "\t-32 (for LEGACY_32 mode, 32b addressing,", + "\t 32b default data size -- default)", + "\t-64 (for LONG_64 mode w/64b addressing", + "\t Optional on windows/linux)", +#if defined(XED_MPX) + "\t-mpx (Turn on MPX mode for disassembly, default is off)", +#endif + "\t-s32 (32b stack addressing, default, not in LONG_64 mode)", + "\t-s16 (16b stack addressing, not in LONG_64 mode)", + +#if defined(XED_USING_DEBUG_HELP) + "", + "\t-sp (Search path for windows symbols)", +#endif + " ", + 0 + }; + + printf("%s\n", xed_get_copyright()); + printf("XED version: [%s]\n\n", xed_get_version()); + printf("Usage: %s [options]\n", prog); + for(i=0; usage_msg[i] ; i++) + printf("%s\n", usage_msg[i]); +} + + +static char const* remove_spaces(char const* s) { //frees original string + xed_uint32_t i=0,c=0; + char* p=0; + + if (s == 0) + return 0; + + while(s[i]) { + if (s[i] != ' ') + c++; + i++; + } + c++; // add the null + p = (char*)malloc(c); + i=0; + c=0; + while(s[i]) { + if (s[i] != ' ') + p[c++] = s[i]; + i++; + } + p[c]=0; + free((void*)s); + + return p; +} + + +static void +test_argc(int i, int argc) +{ + if (i+1 >= argc) + xedex_derror("Need more arguments. Use \"xed -help\" for usage."); +} + + + + +static void list_chips(void) +{ + xed_chip_enum_t c = XED_CHIP_INVALID; + int i=0; + for( ; c < XED_CHIP_LAST; i++ ) { + if (i > 0 && (i % 3) == 0) + printf("\n"); + printf("%-25s ", xed_chip_enum_t2str(c)); + c = (xed_chip_enum_t)(c + 1); + } + printf("\n"); +} + +int +main(int argc, char** argv) +{ + xed_bool_t sixty_four_bit = 0; + unsigned int mpx_mode = 0; + xed_bool_t decode_only = 1; + char* input_file_name = 0; + char* symbol_search_path = 0; + char const* decode_text=0; + char const* encode_text=0; + xed_state_t dstate; + xed_bool_t encode = 0; + unsigned int ninst = 100*1000*1000; // FIXME: should use maxint... + //perf_tail is for skipping first insts in performance measure mode + unsigned int perf_tail = 0; + xed_bool_t decode_encode = 0; + int i,j; + unsigned int loop_decode = 0; + xed_bool_t decode_raw = 0; + xed_bool_t decode_hex = 0; + xed_bool_t assemble = 0; + char* target_section = 0; + xed_bool_t use_binary_mode = 1; + xed_bool_t emit_isa_set = 0; + xed_int64_t addr_start = 0; + xed_int64_t addr_end = 0; + xed_int64_t fake_base = 0; + xed_bool_t xml_format =0; + xed_bool_t resync = 0; + xed_bool_t ast = 0; + xed_bool_t histo = 0; + int line_numbers = 0; + xed_chip_enum_t xed_chip = XED_CHIP_INVALID; + + char* dot_output_file_name = 0; + xed_bool_t dot = 0; + xed_decoded_inst_t xedd; + xed_uint_t retval_okay = 1; + unsigned int obytes=0; +#if defined(XED_DECODER) + xed_disas_info_t decode_info; +#endif + + /* I have this here to test the functionality, if you are happy with + * the XED formatting options, then you do not need to set this or call + * xed_format_set_options() */ + + xed_format_options_t format_options; + memset(&format_options,0,sizeof(xed_format_options_t)); +#if defined(XED_NO_HEX_BEFORE_SYMBOLIC_NAMES) + format_options.hex_address_before_symbolic_name=0; +#else + format_options.hex_address_before_symbolic_name=1; +#endif + format_options.write_mask_curly_k0 = 1; + format_options.lowercase_hex = 1; + + xed_example_utils_init(); + + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, /* 2nd parameter ignored */ + XED_ADDRESS_WIDTH_32b); + + resync = 1; + client_verbose = 3; + xed_set_verbosity( client_verbose ); + for( i=1; i < argc ; i++ ) { + if (strcmp(argv[i], "-no-resync") ==0) { + resync = 0; + continue; + } + if (strcmp(argv[i], "-ast") ==0) { + ast = 1; + continue; + } + if (strcmp(argv[i], "-histo") ==0) { + histo = 1; + continue; + } + else if (strcmp(argv[i],"-d")==0) { + test_argc(i,argc); + for(j=i+1; j< argc;j++) + decode_text = xedex_append_string(decode_text,argv[j]); + break; // leave the i=1...argc loop + } + else if (strcmp(argv[i],"-i")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + i++; + } +#if defined(XED_USING_DEBUG_HELP) + else if (strcmp(argv[i],"-sp")==0) { + test_argc(i,argc); + symbol_search_path = argv[i+1]; + i++; + } +#endif + else if (strcmp(argv[i],"-s")==0) { + test_argc(i,argc); + target_section = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-xml")==0) { + format_options.xml_a = 1; + format_options.xml_f = 1; + xml_format = 1; + } + else if (strcmp(argv[i],"-uc")==0) { + format_options.lowercase_hex = 0; // use uppercase hex + } + else if (strcmp(argv[i],"-nwm")==0) { + format_options.write_mask_curly_k0 = 0; + } +#if defined(XED_DWARF) + else if (strcmp(argv[i],"-line")==0) { + line_numbers = 1; + } +#endif + else if (strcmp(argv[i],"-dot")==0) { + test_argc(i,argc); + dot_output_file_name = argv[i+1]; + dot = 1; + i++; + } + else if (strcmp(argv[i],"-ir")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_raw = 1; + i++; + } + else if (strcmp(argv[i],"-ih")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_hex = 1; + i++; + } +#if defined(XED_ENCODER) + else if (strcmp(argv[i],"-e") ==0) { + encode = 1; + test_argc(i,argc); + // merge the rest of the args in to the encode_text string. + for( j = i+1; j< argc; j++ ) { + encode_text = xedex_append_string(encode_text, argv[j]); + encode_text = xedex_append_string(encode_text, " "); + } + break; // leave the loop + } + else if (strcmp(argv[i],"-de")==0) { + test_argc(i,argc); + decode_encode = 1; + for(j=i+1; j< argc;j++) + decode_text = xedex_append_string(decode_text,argv[j]); + break; // leave the i=1...argc loop + } + else if (strcmp(argv[i],"-ie")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + assemble = 1; + i++; + } + else if (strcmp(argv[i],"-ide")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_only = 0; + i++; + } +#endif + else if (strcmp(argv[i],"-n") ==0) { + test_argc(i,argc); + ninst = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-perftail") ==0) { + // undocumented. not an interesting knob for most users. + test_argc(i,argc); + perf_tail = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-b") ==0) { + test_argc(i,argc); + fake_base = xed_atoi_general(argv[i+1],1000); + printf("ASSUMED BASE = " XED_FMT_LX "\n",fake_base); + i++; + } + else if (strcmp(argv[i],"-as") == 0 || strcmp(argv[i],"-sa") == 0) { + test_argc(i,argc); + addr_start = XED_STATIC_CAST(xed_int64_t, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-ae") == 0 || strcmp(argv[i],"-ea") == 0) { + test_argc(i,argc); + addr_end = XED_STATIC_CAST(xed_int64_t,xed_atoi_general(argv[i+1],1000)); + i++; + } + + else if (strcmp(argv[i],"-loop") ==0) { + test_argc(i,argc); + loop_decode = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-v") ==0) { + test_argc(i,argc); + client_verbose = XED_STATIC_CAST(int,xed_atoi_general(argv[i+1],1000)); + xed_set_verbosity(client_verbose); + + i++; + } + else if (strcmp(argv[i],"-xv") ==0) { + unsigned int xed_engine_verbose; + test_argc(i,argc); + xed_engine_verbose = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + xed_set_verbosity(xed_engine_verbose); + i++; + } + else if (strcmp(argv[i],"-chip-check")==0) { + test_argc(i,argc); + xed_chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(xed_chip)); + if (xed_chip == XED_CHIP_INVALID) { + printf("Invalid chip name specified. Use -chip-check-list to " + "see the valid chip names.\n"); + exit(1); + } + i++; + } + else if (strcmp(argv[i],"-chip-check-list")==0) { + list_chips(); + exit(0); + } + else if (strcmp(argv[i],"-A")==0) { + global_syntax = XED_SYNTAX_ATT; + } + else if (strcmp(argv[i],"-I")==0) { + global_syntax = XED_SYNTAX_INTEL; + } + else if (strcmp(argv[i],"-X")==0) { // undocumented + global_syntax = XED_SYNTAX_XED; + } + else if (strcmp(argv[i],"-isa-set")==0) { + emit_isa_set = 1; + } + else if (strcmp(argv[i],"-r")==0) { + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_REAL_16; + dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-16")==0) { + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-32")==0) { // default + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-64")==0) { + sixty_four_bit = 1; + dstate.mmode = XED_MACHINE_MODE_LONG_64; + use_binary_mode = 0; + } +#if defined(XED_MPX) + else if (strcmp(argv[i],"-mpx")==0) { + mpx_mode = 1; + } +#endif + else if (strcmp(argv[i],"-s32")==0) { + dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-s16")==0) { + dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + use_binary_mode = 0; + } +#if 0 + else if (strcmp(argv[i],"-ti") ==0) { + client_verbose = 5; + xed_set_verbosity(5); + test_immdis(); + exit(1); + } +#endif + else if (strcmp(argv[i],"-emit") ==0) { + intel_asm_emit = 1; + } + else { + usage(argv[0]); + exit(1); + } + } + if (!encode) { + if (input_file_name == 0 && + (decode_text == 0 || + strlen(decode_text) == 0)) + { + printf("ERROR: required argument(s) were missing\n"); + usage(argv[0]); + exit(1); + } + } + if (CLIENT_VERBOSE2) + printf("Initializing XED tables...\n"); + + xed_tables_init(); + + if (CLIENT_VERBOSE2) + printf("Done initialing XED tables.\n"); + + decode_text = remove_spaces(decode_text); + +#if defined(XED_DECODER) + xed_format_set_options(format_options); +#endif + + if (CLIENT_VERBOSE1) + printf("#XED version: [%s]\n", xed_get_version()); + init_xedd(&xedd, &dstate, xed_chip, mpx_mode); + retval_okay = 1; + obytes=0; + +#if defined(XED_DECODER) + xed_disas_info_init(&decode_info); + decode_info.input_file_name = input_file_name; + decode_info.symbol_search_path = symbol_search_path; + decode_info.dstate = dstate; + decode_info.ninst = ninst; + decode_info.decode_only = decode_only; + decode_info.sixty_four_bit = sixty_four_bit; + decode_info.target_section = target_section; + decode_info.use_binary_mode = use_binary_mode; + decode_info.addr_start = addr_start; + decode_info.addr_end = addr_end; + decode_info.xml_format = xml_format; + decode_info.fake_base = fake_base; + decode_info.resync = resync; + decode_info.line_numbers = line_numbers; + decode_info.perf_tail_start = perf_tail; + decode_info.ast = ast; + decode_info.histo = histo; + decode_info.chip = xed_chip; + decode_info.mpx_mode = mpx_mode; + decode_info.emit_isa_set = emit_isa_set; + decode_info.format_options = format_options; + + if (dot) + { + decode_info.dot_graph_output = fopen_portable(dot_output_file_name,"w"); + if (!decode_info.dot_graph_output) { + printf("Could not open %s\n", dot_output_file_name); + xedex_derror("Dying"); + } + } +#endif + + if (assemble) + { +#if defined(XED_ENCODER) + xed_assemble(&dstate, input_file_name); +#endif + } + else if (decode_encode) + { +#if defined(XED_DECODER) && defined(XED_ENCODER) + obytes = disas_decode_encode(&decode_info, + decode_text, + &xedd, + fake_base); +#endif + retval_okay = (obytes != 0) ? 1 : 0; + } + else if (encode) + { +#if defined(XED_ENCODER) + obytes = disas_encode(&dstate, encode_text); +#endif + } + else if (decode_text && strlen(decode_text) != 0) + { +#if defined(XED_DECODER) + if (loop_decode) + { + unsigned int k; + for(k=0;k 0); + } +#endif + } + else + { +#if defined(XED_DECODER) + if (xml_format) { + printf("\n"); + printf("\n"); + printf("1\n"); + } + if (decode_raw) { + xed_disas_raw(&decode_info); + } + else if (decode_hex) { + xed_disas_hex(&decode_info); + } + else + { +#if defined(__APPLE__) + xed_disas_macho(&decode_info); +#elif defined(XED_ELF_READER) + xed_disas_elf(&decode_info); +#elif defined(_WIN32) + xed_disas_pecoff(&decode_info); +#else + xedex_derror("No PECOFF, ELF or MACHO support compiled in"); +#endif + printf("# Total Errors: " XED_FMT_LD "\n", decode_info.errors); + if (decode_info.chip) + printf("# Total Chip Check Errors: " XED_FMT_LD "\n", + decode_info.errors_chip_check); + } +#endif // XED_DECODER + } + + if (xml_format) + printf("\n"); + + + if (retval_okay==0) + exit(1); + return 0; + (void) obytes; + (void) encode_text; +#if !defined(XED_DECODER) + // pacify the compiler for encoder-only builds: + (void) sixty_four_bit; + (void) decode_only; + (void) symbol_search_path; + (void) ninst; + (void) perf_tail; + (void) loop_decode; + (void) decode_raw; + (void) decode_hex; + (void) target_section; + (void) addr_start; + (void) addr_end; + (void) resync; + (void) ast; + (void) histo; + (void) line_numbers; + (void) dot_output_file_name; + (void) dot; + (void) use_binary_mode; + (void) emit_isa_set; +#endif +} + + +//////////////////////////////////////////////////////////////////////////// diff --git a/examples/xed_examples_mbuild.py b/examples/xed_examples_mbuild.py new file mode 100644 index 0000000..391c506 --- /dev/null +++ b/examples/xed_examples_mbuild.py @@ -0,0 +1,463 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +#Copyright (c) 2004-2015, Intel Corporation. All rights reserved. +# +#Redistribution and use in source and binary forms, with or without +#modification, are permitted provided that the following conditions are +#met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +#"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +#LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +#A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +#OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +#SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +#LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +#DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +#THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +#OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#END_LEGAL + +import sys +import os +import re +import shutil +import copy +import time +import glob +import types +import optparse +# sys.path is set up by calling script (mfile.py ususally) +import mbuild +import xed_build_common as xbc + +def ex_compile_and_link(env, dag, src, objs): + """Return the exe name - used for the examples""" + basename = os.path.basename(src) + exe = env.build_dir_join(env.resuffix(basename, env['EXEEXT'])) + all_obj = [] + + # first_example_lib and last_example_lib are for supporting + # compilations using custom C runtimes. + if 'first_example_lib' in env: + all_obj.append(env['first_example_lib']) + all_obj.extend(env.compile(dag, [src])) + all_obj.extend(objs) + if 'last_example_lib' in env: + all_obj.append(env['last_example_lib']) + + lc = env.link(all_obj, exe) + cmd = dag.add(env,lc) + return cmd.targets[0] + +########################################################################### + +def mkenv(): + """External entry point: create the environment""" + if not mbuild.check_python_version(2,7): + xbc.cdie("Need python 2.7.x...") + # create an environment, parse args + env = mbuild.env_t() + standard_defaults = dict( doxygen_install='', + doxygen='', + clean=False, + die_on_errors=True, + xed_messages=False, + xed_asserts=False, + pedantic=True, + clr=False, + use_werror=True, + dbghelp=False, + install_dir='', + kit_kind='base', + win=False, + dev=False, + legal_header=None, + encoder=True, + decoder=True, + ld_library_path=[], + ld_library_path_for_tests=[], + use_elf_dwarf=False, + use_elf_dwarf_precompiled=False, + strip='strip', + verbose = 1, + example_linkflags='', + example_rpaths=[], + android=False, + xed_inc_dir='', + xed_lib_dir='', + xed_dir='', + build_cpp_examples=False, + pin_crt='') + + env['xed_defaults'] = standard_defaults + env.set_defaults(env['xed_defaults']) + return env + +def xed_args(env): + """For command line invocation: parse the arguments""" + env.parser.add_option("--no-encoder", + dest="encoder", + action="store_false", + help="No encoder") + env.parser.add_option("--no-decoder", + dest="decoder", + action="store_false", + help="No decoder") + env.parser.add_option("--android", + dest="android", + action="store_true", + help="Android build (avoid rpath for examples)") + env.parser.add_option("--example-linkflags", + dest="example_linkflags", + action="store", + help="Extra link flags for the examples") + env.parser.add_option("--example-rpath", + dest="example_rpaths", + action="append", + help="Extra rpath dirs for examples") + env.parser.add_option("-c","--clean", + dest="clean", + action="store_true", + help="Clean targets") + env.parser.add_option("--keep-going", '-k', + action="store_false", + dest="die_on_errors", + help="Keep going after errors occur when building") + env.parser.add_option("--messages", + action="store_true", + dest="xed_messages", + help="Enable use xed's debug messages") + env.parser.add_option("--no-pedantic", + action="store_false", + dest="pedantic", + help="Disable -pedantic (gnu/clang compilers).") + env.parser.add_option("--asserts", + action="store_true", + dest="xed_asserts", + help="Enable use xed's asserts") + env.parser.add_option("--clr", + action="store_true", + dest="clr", + help="Compile for Microsoft CLR") + env.parser.add_option("--no-werror", + action="store_false", + dest="use_werror", + help="Disable use of -Werror on GNU compiles") + env.parser.add_option("--dbghelp", + action="store_true", + dest="dbghelp", + help="Use dbghelp.dll on windows.") + env.parser.add_option("--install-dir", + dest="install_dir", + action="store", + help="XED Install directory. " + + "Default: kits/xed-install-date-os-cpu") + env.parser.add_option("--kit-kind", + dest="kit_kind", + action="store", + help="Kit version string. " + + "The default is 'base'") + env.parser.add_option("--win", + action="store_true", + dest="win", + help="Add -mno-cygwin to GCC-on-windows compilation") + env.parser.add_option("--ld-library-path", + action="append", + dest="ld_library_path", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running ldd and making kits") + env.parser.add_option("--ld-library-path-for-tests", + action="append", + dest="ld_library_path_for_tests", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running the tests") + + # elf.h is different than libelf.h. + env.parser.add_option("--elf-dwarf", "--dwarf", + action="store_true", + dest="use_elf_dwarf", + help="Use libelf/libdwarf. (Linux only)") + env.parser.add_option("--elf-dwarf-precompiled", + action="store_true", + dest="use_elf_dwarf_precompiled", + help="Use precompiled libelf/libdwarf from " + + " the XED source distribution." + + " This is the currently required" + + " if you are installing a kit." + + " Implies the --elf-dwarf knob." + " (Linux only)") + env.parser.add_option("--strip", + action="store", + dest="strip", + help="Path to strip binary. (Linux only)") + env.parser.add_option("--pin-crt", + action="store", + dest="pin_crt", + help="Compile for the Pin C-runtime. Specify" + + " path to pin kit") + env.parser.add_option("--lib-dir", + action="store", + dest="xed_lib_dir", + help="directory where libxed* is located.") + env.parser.add_option("--inc-dir", + action="store", + dest="xed_inc_dir", + help="directory where xed generated headers are located.") + env.parser.add_option("--xed-dir", + action="store", + dest="xed_dir", + help="directory where xed sources are located.") + env.parser.add_option("--build-cpp-examples", + action="store_true", + dest="build_cpp_examples", + help="Build the C++ examples default: False.") + + env.parse_args(env['xed_defaults']) + +def nchk(env,s): + #null string check or not set check + if s not in env or env[s] == '': + return True + return False + +def init(env): + xbc.init(env) + if nchk(env,'xed_lib_dir'): + env['xed_lib_dir'] = '../lib' + if nchk(env,'xed_inc_dir'): + env['xed_inc_dir'] = '../include' + if nchk(env,'xed_dir'): + env['xed_dir'] = '..' + + fx = mbuild.join(env['xed_dir'], "include","public") # static headers + if os.path.exists(fx): + env.add_include_dir(fx) + env.add_include_dir( env['src_dir'] ) # examples dir + env.add_include_dir( env['xed_inc_dir']) # generated headers + +def _wk_show_errors_only(): + #True means show errors only when building. + if mbuild.verbose(1): + return False # show output + return True # show errors only. + + + +def _add_libxed_rpath(env): + """Make example tools refer to the libxed.so from the lib directory + if doing an install""" + if not env['shared']: + return + if not env.on_linux(): + return + if env['android']: + return + if xbc.installing(env): + env['LINKFLAGS'] += " -Wl,-rpath,'$ORIGIN/../lib'" + else: + env['LINKFLAGS'] += " -Wl,-rpath,'$ORIGIN/..'" + + +def build_examples(env, work_queue): + """Build the examples""" + example_exes = [] + env['example_exes'] = [] # used by install + examples_dag = mbuild.dag_t('xedexamples', env=env) + + if not env.on_windows(): + for d in env['example_rpaths']: + env.add_to_var('example_linkflags', + '-Wl,-rpath,{}'.format(d)) + env.add_to_var('LINKFLAGS', env['example_linkflags']) + # put the examples in their own subdirectory + env['build_dir'] = mbuild.join(env['build_dir'],'examples') + mbuild.cmkdir(env['build_dir']) + + link_libxed = env['link_libxed'] + + if env['shared']: + _add_libxed_rpath(env) + + # C vs C++: env is for C++ and env_c is for C programs. + if env['compiler'] in ['gnu','clang', 'icc']: + env['LINK'] = env['CXX'] + env_c = copy.deepcopy(env) + if env_c['compiler'] in ['gnu','clang']: + env_c['LINK'] = '%(CC)s' + + if env['pin_crt']: + xbc.compile_with_pin_crt_lin_mac_common_cplusplus(env) + + # shared files + cc_shared_files = env.src_dir_join([ + 'xed-examples-util.c']) + if env['decoder']: + cc_shared_files.extend(env.src_dir_join([ + 'xed-dot.c', + 'xed-dot-prep.c'])) + + if env['encoder']: + cc_shared_files += env.src_dir_join([ 'xed-enc-lang.c']) + cc_shared_objs = env.compile( examples_dag, cc_shared_files) + # the XED command line tool + xed_cmdline_files = [ 'xed-disas-raw.c', + 'avltree.c', + 'xed-disas-hex.c', + 'xed-symbol-table.c'] + extra_libs = [] + if env['decoder']: + + if env.on_linux(): + xed_cmdline_files.append('xed-disas-elf.c') + + elif env.on_mac(): + xed_cmdline_files.append('xed-disas-macho.c') + + elif env.on_windows(): + xed_cmdline_files.append('xed-disas-pecoff.cpp') + if ( env['dbghelp'] and + env['msvs_version'] not in ['6','7'] ): + env.add_define("XED_DBGHELP") + xed_cmdline_files.append('udhelp.cpp') + extra_libs = ['dbghelp.lib', 'version.lib' ] + + xed_cmdline_files = env.src_dir_join(xed_cmdline_files) + xed_cmdline_obj = copy.deepcopy(cc_shared_objs) + + # Env for cmdline tool (with libelf/dwarf on linux.) + if env.on_windows(): # still C++ + cenv = copy.deepcopy(env) + else: # lin/mac are C code only. + cenv = copy.deepcopy(env_c) + + if env.on_linux(): + xbc.cond_add_elf_dwarf(cenv) + + xed_cmdline_obj += cenv.compile(examples_dag, xed_cmdline_files) + + xed_cmdline = ex_compile_and_link(cenv, examples_dag, + env.src_dir_join('xed.c'), + xed_cmdline_obj + [link_libxed] + + extra_libs) + mbuild.msgb("CMDLINE", xed_cmdline) + example_exes.append(xed_cmdline) + + ild_examples = [] + other_c_examples = [] + small_examples = ['xed-size.c'] + if env['encoder']: + small_examples += ['xed-ex5-enc.c'] + other_c_examples += ['xed-ex3.c'] + if env['decoder'] and env['encoder']: + other_c_examples += ['xed-ex6.c'] + if env['decoder']: + ild_examples += [ 'xed-ex-ild.c' ] + other_c_examples += ['xed-ex1.c', + 'xed-ex-ild2.c', + 'xed-min.c', + 'xed-reps.c', + 'xed-ex4.c', + 'xed-tester.c', + 'xed-dec-print.c', + 'xed-ex-agen.c', + 'xed-ex7.c', + 'xed-ex8.c', + 'xed-ex-cpuid.c', + 'xed-tables.c', + 'xed-dll-discovery.c'] + + # compile & link other_c_examples + for example in env.src_dir_join(other_c_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + cc_shared_objs + [ link_libxed ])) + # compile & link ild_examples + for example in env.src_dir_join(ild_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + [ env['link_libild'] ])) + + # compile & link small_examples + for example in env.src_dir_join(small_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + [ link_libxed ])) + if mbuild.verbose(3): + mbuild.msgb("ALL EXAMPLES", "\n\t".join(example_exes)) + + examples_to_build = example_exes + env['example_exes'] = example_exes + + mbuild.msgb("BUILDING EXAMPLES") + okay = work_queue.build(examples_dag, + targets=examples_to_build, + die_on_errors=env['die_on_errors'], + show_progress=True, + show_output=True, + show_errors_only=_wk_show_errors_only()) + if not okay: + xbc.cdie( "XED EXAMPLES build failed") + if mbuild.verbose(2): + mbuild.msgb("XED EXAMPLES", "build succeeded") + return 0 + +def verify_args(env): + if env['use_elf_dwarf_precompiled']: + env['use_elf_dwarf'] = True + +def examples_work(env): + """External entry point for non-command line invocations. + Initialize the environment, build libxed, the examples, the kit + and run the tests""" + xbc.prep(env) + verify_args(env) + start_time=mbuild.get_time() + xbc.init_once(env) + + init(env) + + if 'clean' in env['targets'] or env['clean']: + xbc.xed_remove_files_glob(env) + if len(env['targets'])<=1: + xbc.cexit(0) + + mbuild.cmkdir(env['build_dir']) + + work_queue = mbuild.work_queue_t(env['jobs']) + + xbc.get_libxed_names(env, work_queue) + retval = build_examples(env, work_queue) + end_time=mbuild.get_time() + mbuild.msgb("EXAMPLES BUILD ELAPSED TIME", + mbuild.get_elapsed_time(start_time, end_time)) + return retval + +def execute(): + """Main external entry point for command line invocations""" + + import mbuild + env = mkenv() + # xed_args() is skip-able for remote (import) invocation. The env + # from mkenv can be updated programmatically. One must call + # xbc.set_xed_defaults(env) if not calling xed_args(env) + xed_args(env) # parse command line knobs + retval = examples_work(env) + return retval diff --git a/include/private/xed-chip-features-private.h b/include/private/xed-chip-features-private.h new file mode 100644 index 0000000..09372c0 --- /dev/null +++ b/include/private/xed-chip-features-private.h @@ -0,0 +1,31 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_CHIP_FEATURES_PRIVATE_H_) +# define _XED_CHIP_FEATURES_PRIVATE_H_ + +#include "xed-types.h" +#include "xed-chip-features.h" +#include "xed-isa-set.h" + +xed_bool_t +xed_test_chip_features(xed_chip_features_t* p, + xed_isa_set_enum_t isa_set); + + +#endif diff --git a/include/private/xed-chip-modes.h b/include/private/xed-chip-modes.h new file mode 100644 index 0000000..3355c78 --- /dev/null +++ b/include/private/xed-chip-modes.h @@ -0,0 +1,29 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_CHIP_MODES) +# define XED_CHIP_MODES + +# include "xed-chip-enum.h" +# include "xed-decoded-inst.h" +# include "xed-chip-features.h" + +void set_chip_modes(xed_decoded_inst_t* xedd, + xed_chip_enum_t chip, + xed_chip_features_t* features); +#endif diff --git a/include/private/xed-decode-profile.h b/include/private/xed-decode-profile.h new file mode 100644 index 0000000..6e19ee4 --- /dev/null +++ b/include/private/xed-decode-profile.h @@ -0,0 +1,94 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +//#define XED_PROFILE_TRAVERSAL +//#define XED_PROFILE_NODE_FREQUENCY +//#define XED_PROFILE_ITERATION_TIME + + + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_PROFILE_TRAVERSAL) +# define XED_MAX_ITERATIONS_PROFILE 100 +xed_uint64_t xed_profile_iterations[XED_MAX_ITERATIONS_PROFILE]; + +# define BUMP_PROFILE() \ + do { \ + if (iterations < XED_MAX_ITERATIONS_PROFILE) \ + xed_profile_iterations[iterations]++;\ + else \ + xed_profile_iterations[XED_MAX_ITERATIONS_PROFILE-1]++; \ + } while(0) + +#else +# define BUMP_PROFILE() do {} while(0) +#endif + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_PROFILE_NODE_FREQUENCY) +xed_uint64_t xed_profile_node_frequency[XED_GRAPH_NODE_LAST]; +#endif + + + +#if defined(XED_PROFILE_ITERATION_TIME) +xed_uint64_t times[1000]; +xed_uint32_t xed_decode_traversals=0; +#endif + + +#if !defined(__GNUC__) +# pragma warning( default : 4706) +#endif + + +#if defined(XED_PROFILE_ITERATION_TIME) +void xed_decode_traverse_iteration_times(void) { + int i; + xed_uint64_t last=0; + printf("TRAVERSALS: " XED_FMT_D "\n", xed_decode_traversals); + + for(i=0;i_inst = inst; + xed3_operand_set_iclass(p,xed_inst_iclass(inst)); +} + +unsigned int +xed_decoded_inst_compute_memory_operand_length(const xed_decoded_inst_t* p, + unsigned int memop_idx); + +// sets MEM_WIDTH +static XED_INLINE void +xed_decoded_inst_cache_memory_operand_length(xed_decoded_inst_t* p) { + xed_uint16_t mem_width = + xed_decoded_inst_compute_memory_operand_length(p, 0); + xed3_operand_set_mem_width(p,mem_width); +} + + +static XED_INLINE xed_uint_t +xed_decoded_inst_set_length(xed_decoded_inst_t* p, + unsigned char length) { + return p->_decoded_length = length; +} + + +static XED_INLINE xed_uint_t +xed_decoded_inst_inc_length(xed_decoded_inst_t* p) { + return p->_decoded_length++; +} + +static XED_INLINE xed_uint32_t +xed_phash_invalid(const xed_decoded_inst_t* d) { + return 0; + (void) d; +} + + +#endif diff --git a/include/private/xed-disas-private.h b/include/private/xed-disas-private.h new file mode 100644 index 0000000..1713e50 --- /dev/null +++ b/include/private/xed-disas-private.h @@ -0,0 +1,34 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas.h +/// + +#if !defined(_XED_DISAS_PRIVATE_H_) +# define _XED_DISAS_PRIVATE_H_ + +#include "xed-disas.h" +#include "xed-print-info.h" + +int xed_get_symbolic_disassembly(xed_print_info_t* pi, + xed_uint64_t address, + char* buffer, + unsigned int buffer_length, + xed_uint64_t* offset); + + +#endif diff --git a/include/private/xed-encode-isa-functions.h b/include/private/xed-encode-isa-functions.h new file mode 100644 index 0000000..2ab1fba --- /dev/null +++ b/include/private/xed-encode-isa-functions.h @@ -0,0 +1,32 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode-isa-functions.h +/// + +#ifndef _XED_ENCODE_ISA_FUNCTIONS_H_ +# define _XED_ENCODE_ISA_FUNCTIONS_H_ + +#include "xed-encode.h" + + +xed_bool_t xed_encode_nonterminal_INSTRUCTIONS_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_INSTRUCTIONS_BIND(xed_encoder_request_t* xes); + + +#endif + diff --git a/include/private/xed-encode-private.h b/include/private/xed-encode-private.h new file mode 100644 index 0000000..bc1d5d7 --- /dev/null +++ b/include/private/xed-encode-private.h @@ -0,0 +1,185 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode-private.H +/// + + +#if !defined(_XED_ENCODE_PRIVATE_H_) +# define _XED_ENCODE_PRIVATE_H_ + +#include "xed-types.h" +#include "xed-encode-types.h" +#include "xed-portability.h" +#include "xed-error-enum.h" +#include "xed-operand-values-interface.h" +#include "xed-operand-width-enum.h" +#include "xed-ild-private.h" +#include "xed-encoder-iforms.h" //generated +#include "xed-encoder-gen-defs.h" //generated +#include // for memset + +#define XED_GLOBAL_EXTERN extern +#include "xed-encode-tables.h" +#undef XED_GLOBAL_EXTERN + +static XED_INLINE const xed_encoder_vars_t* +xed_encoder_request_ev_const(const xed_encoder_request_t* p) { + return p->u.ev; +} +static XED_INLINE xed_encoder_vars_t* xed_encoder_request_ev(xed_encoder_request_t* p) { + return p->u.ev; +} + +static XED_INLINE void xed_encoder_request_vars_remove(xed_encoder_request_t* p) { + p->u.ev = 0; // clear the internal data so no one sees it. +} + +static XED_INLINE void xed_encoder_request_vars_zero(xed_encoder_request_t* p) { + xed_encoder_vars_t* q = xed_encoder_request_ev(p); + if (q) { + q->_ilen = 0; + q->_olen = 0; + q->_bit_offset = 0; + memset(&(q->_iforms),0,sizeof(xed_encoder_iforms_t)); + } +} + +static XED_INLINE void xed_encoder_request_set_encoder_vars(xed_encoder_request_t* p, + xed_encoder_vars_t* xev) { + p->u.ev = xev; + xed_encoder_request_vars_zero(p); +} + +static XED_INLINE xed_uint16_t +xed_encoder_request_get_iform_index(const xed_encoder_request_t* p) { + return xed_encoder_request_ev_const(p)->_iform_index; +} + +static XED_INLINE void +xed_encoder_request_set_iform_index(xed_encoder_request_t* p, + xed_uint16_t iform_index) { + xed_encoder_request_ev(p)->_iform_index = iform_index; +} + + +static XED_INLINE xed_encoder_iforms_t* xed_encoder_request_iforms(xed_encoder_request_t* p) { + return &(xed_encoder_request_ev(p)->_iforms); +} + +static XED_INLINE xed_uint32_t xed_encoder_request_ilen(const xed_encoder_request_t* p) { + return xed_encoder_request_ev_const(p)->_ilen; +} + +static XED_INLINE xed_uint32_t xed_encoder_request_olen(const xed_encoder_request_t* p) { + return xed_encoder_request_ev_const(p)->_olen; +} +static XED_INLINE xed_uint32_t xed_encoder_request_bit_offset(const xed_encoder_request_t* p) { + return xed_encoder_request_ev_const(p)->_bit_offset; +} + + +static XED_INLINE void xed_encoder_request_set_ilen(xed_encoder_request_t* p, xed_uint32_t ilen) { + xed_encoder_request_ev(p)->_ilen= ilen; +} +static XED_INLINE void xed_encoder_request_set_olen(xed_encoder_request_t* p, xed_uint32_t olen) { + xed_encoder_request_ev(p)->_olen=olen; +} +static XED_INLINE void +xed_encoder_request_set_bit_offset( xed_encoder_request_t* p, xed_uint32_t bit_offset) { + xed_encoder_request_ev(p)->_bit_offset = bit_offset; +} +static XED_INLINE void +xed_encoder_request_update_bit_offset( xed_encoder_request_t* p, xed_uint32_t bit_offset_delta) { + xed_encoder_request_ev(p)->_bit_offset += bit_offset_delta; +} + +static XED_INLINE const xed_encoder_iform_t* +xed_encoder_get_encoder_iform(const xed_encoder_request_t* r){ + xed_uint16_t iform_index = xed_encoder_request_get_iform_index(r); + // KW false positive. Correct by construction. + return xed_encode_iform_db + iform_index; +} + +void +xed_encoder_request_emit_legacy_map(xed_encoder_request_t* q); + +void +xed_encoder_request_emit_bytes(xed_encoder_request_t* q, + const xed_uint8_t bits, + const xed_uint64_t value); +void +xed_encoder_request_encode_emit(xed_encoder_request_t* q, + const unsigned int bits, + const xed_uint64_t value); + +xed_bool_t +xed_encoder_request__memop_compatible(const xed_encoder_request_t* p, + xed_operand_width_enum_t operand_width); + + +static XED_INLINE xed_ptrn_func_ptr_t +xed_encoder_get_fb_ptrn(const xed_encoder_request_t* p){ + const xed_encoder_iform_t* enc_iform = xed_encoder_get_encoder_iform(p); + return xed_encode_fb_lu_table[enc_iform->_fb_ptrn_index]; +} + +static XED_INLINE xed_ptrn_func_ptr_t +xed_encoder_get_emit_ptrn(const xed_encoder_request_t* p){ + const xed_encoder_iform_t* enc_iform = xed_encoder_get_encoder_iform(p); + return xed_encode_emit_lu_table[enc_iform->_emit_ptrn_index]; +} + +static XED_INLINE xed_uint8_t +xed_encoder_get_nominal_opcode(const xed_encoder_request_t* p){ + const xed_encoder_iform_t* enc_iform = xed_encoder_get_encoder_iform(p); + return enc_iform->_nom_opcode; +} +static XED_INLINE xed_uint8_t +xed_encoder_get_map(const xed_encoder_request_t* p){ + const xed_encoder_iform_t* enc_iform = xed_encoder_get_encoder_iform(p); + return enc_iform->_legacy_map; +} + +static XED_INLINE xed_uint16_t +xed_encoder_get_fb_values_index(const xed_encoder_request_t* p){ + const xed_encoder_iform_t* enc_iform = xed_encoder_get_encoder_iform(p); + return enc_iform->_fb_values_index; +} + + +static XED_INLINE const xed_uint8_t* +xed_encoder_get_start_field_value(const xed_encoder_request_t* p){ + xed_uint16_t base_index = xed_encoder_get_fb_values_index(p); + return xed_encode_fb_values_table + base_index; +} + + +static XED_INLINE xed_encode_function_pointer_t +xed_encoder_get_group_encoding_function(xed_iclass_enum_t iclass){ + xed_uint16_t indx = xed_enc_iclass2group[iclass]; + return xed_encode_groups[indx]; +} + +static XED_INLINE xed_uint8_t +xed_encoder_get_iclasses_index_in_group(const xed_encoder_request_t* p){ + xed_iclass_enum_t iclass = xed_encoder_request_get_iclass(p); + return xed_enc_iclass2index_in_group[iclass]; +} + + +#endif diff --git a/include/private/xed-encode-tables.h b/include/private/xed-encode-tables.h new file mode 100644 index 0000000..ee99262 --- /dev/null +++ b/include/private/xed-encode-tables.h @@ -0,0 +1,57 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_ENCODE_TABLES_H_) +# define _XED_ENCODE_TABLES_H_ + +// Some things are "extern const" because they are filled in where they are +// declared in some generated *.c file. + +//Table of BIND function per each group +extern const +xed_encode_function_pointer_t xed_encode_groups[XED_ENC_GROUPS]; + +//mapping from xed iclass to the encoding group +XED_GLOBAL_EXTERN +xed_uint16_t xed_enc_iclass2group[XED_ICLASS_LAST]; + +//mapping from iclass to it's Id in the group +XED_GLOBAL_EXTERN +xed_uint8_t xed_enc_iclass2index_in_group[XED_ICLASS_LAST]; + +// The entries of this array are xed_operand_enum_t, but stored as +// xed_uint8_t to save space. Subverting the type system. +XED_GLOBAL_EXTERN +xed_uint8_t xed_encode_order[XED_ENCODE_ORDER_MAX_ENTRIES][XED_ENCODE_ORDER_MAX_OPERANDS]; +XED_GLOBAL_EXTERN +xed_uint_t xed_encode_order_limit[XED_ENCODE_ORDER_MAX_ENTRIES]; + + +extern const +xed_ptrn_func_ptr_t xed_encode_fb_lu_table[XED_ENCODE_MAX_FB_PATTERNS]; + +extern const +xed_ptrn_func_ptr_t xed_encode_emit_lu_table[XED_ENCODE_MAX_EMIT_PATTERNS]; + +extern const +xed_uint8_t xed_encode_fb_values_table[XED_ENCODE_FB_VALUES_TABLE_SIZE]; + +extern const +xed_encoder_iform_t xed_encode_iform_db[XED_ENCODE_MAX_IFORMS]; + +#endif diff --git a/include/private/xed-encode-types.h b/include/private/xed-encode-types.h new file mode 100644 index 0000000..9ecafe5 --- /dev/null +++ b/include/private/xed-encode-types.h @@ -0,0 +1,66 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode-types.H +/// + + +#if !defined(_XED_ENCODE_TYPES_H_) +# define _XED_ENCODE_TYPES_H_ + +#include "xed-types.h" +#include "xed-encode.h" + +// Type signature for an encode function +typedef xed_uint_t (*xed_encode_function_pointer_t)(xed_encoder_request_t* enc_req); +typedef xed_bool_t (*xed_nt_func_ptr_t)(xed_encoder_request_t*); +typedef xed_bool_t (*xed_ntluf_func_ptr_t)(xed_encoder_request_t*, xed_reg_enum_t); +typedef void (*xed_ptrn_func_ptr_t)(xed_encoder_request_t*); + +typedef struct xed_encoder_iform_s{ + //index of the field binding function in xed_encode_fb_lu_table + xed_uint8_t _fb_ptrn_index; + + //index of the emit function in xed_encode_emit_lu_table + xed_uint8_t _emit_ptrn_index; + + xed_uint8_t _nom_opcode; + xed_uint8_t _legacy_map; + + //start index of the field values in xed_encode_fb_values_table + xed_int16_t _fb_values_index; +} xed_encoder_iform_t; + +typedef struct xed_encoder_vars_s { + /// _iforms is a dynamically generated structure containing the values of + /// various encoding decisions + xed_encoder_iforms_t _iforms; + + // the index of the iform in the xed_encode_iform_db table + xed_uint16_t _iform_index; + + /// Encode output array size, specified by caller of xed_encode() + xed_uint32_t _ilen; + + /// Used portion of the encode output array + xed_uint32_t _olen; + + xed_uint32_t _bit_offset; +} xed_encoder_vars_t; + + +#endif diff --git a/include/private/xed-flags-private.h b/include/private/xed-flags-private.h new file mode 100644 index 0000000..67c1441 --- /dev/null +++ b/include/private/xed-flags-private.h @@ -0,0 +1,59 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flags-private.H +/// + +#ifndef _XED_FLAGS_PRIVATE_H_ +# define _XED_FLAGS_PRIVATE_H_ + +#include "xed-flags.h" + + +// during decode: store the pointer to the lowest level xed_simple_flag_t +// in the xedd based on an examination of the shift-operand. Need to know +// what operand discriminates the choices. Add that to the text table. + +// common the flags in the parser. + + +typedef enum +{ + XED_FLAG_CASE_IMMED_ZERO, + XED_FLAG_CASE_IMMED_ONE, + XED_FLAG_CASE_IMMED_OTHER, + XED_FLAG_CASE_HAS_REP, // implies may-dependence for writes + XED_FLAG_CASE_NO_REP, + XED_FLAG_CASE_LAST +} xed_flag_cases_enum_t; + + +typedef struct xed_complex_flag_s { + + // pointers to an array of dense flags. Only the cases that matter are + // non-null. We need to search for case of: register-counts, + // immediate-0, immediate-1, and other-immediate + + xed_bool_t check_rep :1; + xed_bool_t check_imm :1; + xed_uint16_t cases[XED_FLAG_CASE_LAST]; + +} xed_complex_flag_t; + +void xed_complex_flag_zero(xed_complex_flag_t* p); + +#endif diff --git a/include/private/xed-ild-private.h b/include/private/xed-ild-private.h new file mode 100644 index 0000000..82cbc19 --- /dev/null +++ b/include/private/xed-ild-private.h @@ -0,0 +1,163 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-ild-private.h +/// instruction length decoder private header + +#if !defined(_XED_ILD_PRIVATE_H_) +# define _XED_ILD_PRIVATE_H_ + + + + +#include "xed-ild.h" +#include "xed-machine-mode-enum.h" +static XED_INLINE xed_uint_t xed_modrm_mod(xed_uint8_t m) { return m>>6; } +static XED_INLINE xed_uint_t xed_modrm_reg(xed_uint8_t m) { return (m>>3)&7; } +static XED_INLINE xed_uint_t xed_modrm_rm(xed_uint8_t m) { return m&7; } +static XED_INLINE xed_uint_t xed_sib_scale(xed_uint8_t m) { return m>>6; } +static XED_INLINE xed_uint_t xed_sib_index(xed_uint8_t m) { return (m>>3)&7; } +static XED_INLINE xed_uint_t xed_sib_base(xed_uint8_t m) { return m&7; } +static XED_INLINE xed_uint_t bits2bytes(xed_uint_t bits) { return bits>>3; } +static XED_INLINE xed_uint_t bytes2bits(xed_uint_t bytes) { return bytes<<3; } + + +typedef void(*xed_ild_l1_func_t)(xed_decoded_inst_t*); +typedef xed_uint32_t(*xed3_find_func_t)(const xed_decoded_inst_t*); + +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu1_entry_t; +typedef struct {xed_uint32_t key; xed3_find_func_t l2_func;} lu2_entry_t; + + +typedef enum { + XED_ILD_MAP0, + XED_ILD_MAP1, /* 0F */ + XED_ILD_MAP2, /* 0F38 */ + XED_ILD_MAP3, /* 0F3A */ + XED_ILD_MAP4, /* required placeholders */ + XED_ILD_MAP5, + XED_ILD_MAP6, + XED_ILD_MAPAMD, /* fake map 7 - amd 3dnow */ + XED_ILD_MAP_XOP8, /* amd xop */ + XED_ILD_MAP_XOP9, /* amd xop */ + XED_ILD_MAP_XOPA, /* amd xop */ + XED_ILD_MAP_LAST, /* for array sizing */ + XED_ILD_MAP_INVALID /* for error handling */ +} xed_ild_map_enum_t; + + +#define XED_GRAMMAR_MODE_64 2 +#define XED_GRAMMAR_MODE_32 1 +#define XED_GRAMMAR_MODE_16 0 + +/* +Double immediate instructions are special. There are only 3 of them +and anyway they require a special care. It seems that the simplest way +is just to define L1 functions for both such map-opcode pairs: +(0x0F,0x78) and (0x0, 0xC8) +*/ + +/* (0x0f,0x78) map-opcode pair is even more special, because it has a conflict +on imm_bytes between AMD's INSERTQ,EXTRQ and Intel's VMREAD. +We already hardcode L1 functions for double immediate instructions, so we will +hardcode a conflict resolution here too. */ +static XED_INLINE void xed_ild_hasimm_map0x0F_op0x78_l1(xed_decoded_inst_t* x) { + /*FIXME: f3 prefix is not mentioned in INSERTQ or EXTRQ grammar + definitions, however is forbidden for VMREAD. It seems that it can + go with INSERTQ and EXTRQ. Right? */ + if (xed3_operand_get_osz(x) || + xed3_operand_get_ild_f2(x) + // || xed3_operand_get_ild_f3(x) + ) + { + /*for INSERTQ and EXTRQ*/ + /*straight in bytes*/ + xed3_operand_set_imm_width(x, bytes2bits(1)); + xed3_operand_set_imm1_bytes(x, 1); + return; + } + /* for VMREAD imm_bytes is 0*/ +} + +/*ENTER instruction has UIMM16 and UIMM8_1 NTs*/ +static XED_INLINE void xed_ild_hasimm_map0x0_op0xc8_l1(xed_decoded_inst_t* x) { + /* for ENTER */ + /*straight in bytes*/ + xed3_operand_set_imm_width(x, bytes2bits(2)); + xed3_operand_set_imm1_bytes(x, 1); +} + +/*FIXME: need to put getters in scanners headers to keep layering working*/ + +/// Convert xed_machine_mode_enum_t to a corresponding xed_bits_t value +/// for MODE operand +/// @param mmode - machine mode in xed_machine_mode_enum_t type +/// @return mode value for MODE operand in xed_bits_t type +/// +/// @ingroup ILD +xed_bits_t xed_ild_cvt_mode(xed_machine_mode_enum_t mmode); + +/// Initialize internal data structures of the ILD. +void xed_ild_init_decoder(void); + + + +/* Special getter for RM */ +static XED_INLINE xed_uint_t +xed_ild_get_rm(const xed_decoded_inst_t* ild) { + /* Sometimes we don't have modrm, but grammar still + * likes to use RM operand - in this case it is first + * 3 bits of the opcode. + */ + xed_uint8_t modrm; + if (xed3_operand_get_has_modrm(ild)) + return xed3_operand_get_rm(ild); + modrm = xed3_operand_get_nominal_opcode(ild); + return xed_modrm_rm(modrm); +} + +/* compressed operand getters */ +static XED_INLINE xed_uint_t +xed3_operand_get_mod3(const xed_decoded_inst_t* ild) { + return xed3_operand_get_mod(ild) == 3; +} + +static XED_INLINE xed_uint_t +xed3_operand_get_rm4(const xed_decoded_inst_t* ild) { + return xed3_operand_get_rm(ild) == 4; +} + +static XED_INLINE xed_uint_t +xed3_operand_get_uimm0_1(const xed_decoded_inst_t* ild) { + return xed3_operand_get_uimm0(ild) == 1; +} + + +#if defined(XED_AVX) +static XED_INLINE xed_uint_t +xed3_operand_get_vexdest210_7(const xed_decoded_inst_t* ild) { + return xed3_operand_get_vexdest210(ild) == 7; +} +#endif + +void +xed_instruction_length_decode(xed_decoded_inst_t* d); + + +#endif + diff --git a/include/private/xed-inst-defs.h b/include/private/xed-inst-defs.h new file mode 100644 index 0000000..4bea386 --- /dev/null +++ b/include/private/xed-inst-defs.h @@ -0,0 +1,27 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#define XED_BIT_PAIR(x,y,z,w) {{ x , y , z, w }} +/* ignoring iclass(ic), category(ca), and extension(ex) now that they are in the iform map. */ +#define XED_DEF_INST(ic, ca, ex, cpl, iforme, opnd_idx, opnd_cnt, flg_indx, flg_cmplx, attr, exceptions) \ + { opnd_cnt, cpl, flg_cmplx, (xed_uint8_t) exceptions, flg_indx, (xed_uint16_t) iforme, opnd_idx , attr } + +#define XED_DEF_DGRAPH(node_type, ok, decider_bits, skipped_bits, backup_pos, od, capfunc, nt_name, max_next, next_base) \ + { capfunc, max_next, next_base, node_type, ok, decider_bits, skipped_bits, backup_pos, od, nt_name } + +#define XED_DEF_OPND(name, vis, rw, oc2, type, xtype, cvt_idx, imm_nt_reg, nt) \ + { (xed_uint8_t)name, (xed_uint8_t)vis, (xed_uint8_t)rw, (xed_uint8_t)oc2, (xed_uint8_t)type, (xed_uint8_t)xtype, cvt_idx, nt, { imm_nt_reg } } diff --git a/include/private/xed-inst-private.h b/include/private/xed-inst-private.h new file mode 100644 index 0000000..8d88c59 --- /dev/null +++ b/include/private/xed-inst-private.h @@ -0,0 +1,37 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-inst-private.H +/// + + +#if !defined(_XED_INST_PRIVATE_H_) +# define _XED_INST_PRIVATE_H_ + +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-inst.h" + +xed_nonterminal_enum_t +xed_operand_nt_lookup_fn_enum(const xed_operand_t* p); + +//////////////////////////////////////////////////////////////////// + + +void xed_inst_init(xed_inst_t* p); + +#endif diff --git a/include/private/xed-internal-header-2.h b/include/private/xed-internal-header-2.h new file mode 100644 index 0000000..6704d38 --- /dev/null +++ b/include/private/xed-internal-header-2.h @@ -0,0 +1,57 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-internal-header-2.h +/// + + +#if !defined(_XED_INTERNAL_HEADER2_H_) +# define _XED_INTERNAL_HEADER2_H_ +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-types.h" +#include "xed-operand-ctype-enum.h" // a generated file +#include "xed-reg-enum.h" // a generated file +#include "xed-reg-class-enum.h" // a generated file +#include "xed-operand-enum.h" // a generated file +#include "xed-operand-storage.h" // a generated file +#include "xed-operand-visibility-enum.h" // a generated file +#include "xed-operand-action-enum.h" // a generated file +#include "xed-nonterminal-enum.h" // a generated file +#include "xed-operand-width-enum.h" // a generated file +#include "xed-iform-enum.h" // a generated file +#include "xed-operand-element-xtype-enum.h" // a generated file +#include "xed-inst.h" +#include "xed-inst-private.h" +#include "xed-ild-private.h" +#if defined(XED_ENCODER) +# include "xed-encode.h" +#endif +#include "xed-tables-extern.h" +#include "xed-error-enum.h" +#include "xed-flags.h" +#include "xed-operand-action.h" +#include "xed-cpuid-rec.h" +#include "xed-cpuid-bit-enum.h" + +struct xed_decoded_inst_s; //fwd-decl + +typedef void (*xed_lookup_function_pointer_t)(struct xed_decoded_inst_s* xds); + +#endif diff --git a/include/private/xed-internal-header.h b/include/private/xed-internal-header.h new file mode 100644 index 0000000..ad16db1 --- /dev/null +++ b/include/private/xed-internal-header.h @@ -0,0 +1,41 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-internal-header.h +/// + + + +#if !defined(_XED_INTERNAL_HEADER_H_) +# define _XED_INTERNAL_HEADER_H_ + + +#if defined(_WIN32) && defined(_MANAGED) +#pragma unmanaged +#endif + +#include "xed-internal-header-2.h" + +#include "xed-decoded-inst.h" +#include "xed-decoded-inst-api.h" +#include "xed-decoded-inst-private.h" +#include "xed-decode-supp.h" +#if defined(XED_ENCODER) +# include "xed-encode-isa-functions.h" +#endif + +#endif diff --git a/include/private/xed-operand-type-info.h b/include/private/xed-operand-type-info.h new file mode 100644 index 0000000..e36ce84 --- /dev/null +++ b/include/private/xed-operand-type-info.h @@ -0,0 +1,30 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_OPERAND_TYPE_INFO_H_) +# define _XED_OPERAND_TYPE_INFO_H_ + +#include "xed-operand-element-type-enum.h" // generated +#include "xed-types.h" + +typedef struct { + xed_operand_element_type_enum_t dtype; + xed_uint32_t bits_per_element; +} xed_operand_type_info_t; + +#endif diff --git a/include/private/xed-phash-invalid.h b/include/private/xed-phash-invalid.h new file mode 100644 index 0000000..499567a --- /dev/null +++ b/include/private/xed-phash-invalid.h @@ -0,0 +1,21 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +static xed_uint32_t xed_phash_invalid(xed_decoded_inst_t* d) { + return 0; + (void) d; +} diff --git a/include/private/xed-portability-private.h b/include/private/xed-portability-private.h new file mode 100644 index 0000000..f3d8cc2 --- /dev/null +++ b/include/private/xed-portability-private.h @@ -0,0 +1,26 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-portability-private.H +/// + +#if !defined(_XED_DECODE_PORTABILITY_PRIVATE_H_) +# define _XED_DECODE_PORTABILITY_PRIVATE_H_ + + + +#endif diff --git a/include/private/xed-tables-decl.h b/include/private/xed-tables-decl.h new file mode 100644 index 0000000..bdc372d --- /dev/null +++ b/include/private/xed-tables-decl.h @@ -0,0 +1,46 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-tables-decl.H +/// + +#if !defined(_XED_TABLES_DECL_H_) +# define _XED_TABLES_DECL_H_ + +#include "xed-gen-table-defs.h" // a generated file +#if defined(XED_ENCODER) +# include "xed-encoder-gen-defs.h" // a generated file +#endif +#include "xed-inst.h" +#include "xed-reg-class-enum.h" // a generated file +#include "xed-operand-width-enum.h" // a generated file +//#include "xed-flags.h" +#include "xed-operand-element-type-enum.h" // a generated file +#include "xed-operand-type-info.h" +#include "xed-flags-private.h" +#if defined(XED_ENCODER) +# include "xed-encode-types.h" +#endif +#define XED_GLOBAL_EXTERN +#include "xed-tables.h" +#undef XED_GLOBAL_EXTERN +#if defined(XED_ENCODER) +# include "xed-encode.h" +# include "xed-encode-private.h" +#endif + +#endif diff --git a/include/private/xed-tables-extern.h b/include/private/xed-tables-extern.h new file mode 100644 index 0000000..110aba2 --- /dev/null +++ b/include/private/xed-tables-extern.h @@ -0,0 +1,47 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-tables-extern.H +/// + +#if !defined(_XED_TABLES_EXTERN_H_) +# define _XED_TABLES_EXTERN_H_ + +#include "xed-gen-table-defs.h" // a generated file +#if defined(XED_ENCODER) +# include "xed-encoder-gen-defs.h" // a generated file +#endif +#include "xed-inst.h" +#include "xed-reg-class-enum.h" // a generated file +#include "xed-operand-width-enum.h" // a generated file +#include "xed-operand-element-xtype-enum.h" // a generated file +#include "xed-flags.h" +#include "xed-flags-private.h" +#include "xed-operand-element-type-enum.h" // a generated file +#include "xed-operand-type-info.h" +#if defined(XED_ENCODER) +# include "xed-encode-types.h" +#endif +#define XED_GLOBAL_EXTERN extern +#include "xed-tables.h" +#undef XED_GLOBAL_EXTERN +#if defined(XED_ENCODER) +# include "xed-encode.h" +# include "xed-encode-private.h" +#endif + +#endif diff --git a/include/private/xed-tables.h b/include/private/xed-tables.h new file mode 100644 index 0000000..6ddc381 --- /dev/null +++ b/include/private/xed-tables.h @@ -0,0 +1,124 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-tables.H +/// + +#if !defined(_XED_TABLES_H_) +# define _XED_TABLES_H_ + + +#if !defined(XED_MAX_INST_TABLE_NODES) +# error "Need to include the generated definition for XED_MAX_INST_TABLE_NODES" +#endif + + +#if !defined(XED_GLOBAL_EXTERN) +# error "Need to define XED_GLOBAL_EXTERN" +#endif + +// Some things are "extern const" because they are filled in where they are +// declared in some generated *.c file. + +/**************************************************************************/ +/* stuff needed for the decoder */ +#if defined(XED_DECODER) + +XED_DLL_EXPORT extern +const xed_inst_t xed_inst_table[XED_MAX_INST_TABLE_NODES]; +XED_DLL_EXPORT extern +const xed_operand_t xed_operand[XED_MAX_OPERAND_TABLE_NODES]; +XED_DLL_EXPORT extern +const xed_uint16_t xed_operand_sequences[XED_MAX_OPERAND_SEQUENCES]; +XED_DLL_EXPORT extern +const xed_iform_info_t xed_iform_db[XED_IFORM_LAST]; + +extern const xed_attribute_enum_t xed_attributes_table[XED_MAX_ATTRIBUTE_COUNT]; +extern const xed_operand_convert_enum_t + xed_operand_convert[XED_MAX_CONVERT_PATTERNS][XED_MAX_DECORATIONS_PER_OPERAND]; + +extern const xed_uint32_t xed_iform_first_per_iclass_table[XED_ICLASS_LAST]; +extern const xed_uint32_t xed_iform_max_per_iclass_table[XED_ICLASS_LAST]; + +#endif +/**************************************************************************/ + + + + + +/**************************************************************************/ +/* stuff needed for the encoder */ +#if defined(XED_ENCODER) +#include "xed-encode-tables.h" +#endif + +/**************************************************************************/ + + +/* more miscellaneous stuff */ + +/* names for each over-ridden iclass. Even entries are Intel. The subsquent odd + entry is the ATTY SYSV name. */ +XED_DLL_EXPORT extern +char const* const xed_iclass_string[XED_ICLASS_NAME_STR_MAX]; + +// the high level reg class for each register. +XED_GLOBAL_EXTERN xed_reg_class_enum_t xed_reg_class_array[XED_REG_LAST]; +// for just the GPR types: refines to REG8,16,32,64 +XED_GLOBAL_EXTERN xed_reg_class_enum_t xed_gpr_reg_class_array[XED_REG_LAST]; + +// the width in bits for each register. +// 2nd index 0=32b and 1=64b +XED_GLOBAL_EXTERN xed_uint_t xed_reg_width_bits[XED_REG_LAST][2]; + +// map each register to the largest enclosing register (for nested +// registers) or back to itself if there is no outer nesting. +XED_GLOBAL_EXTERN xed_reg_enum_t xed_largest_enclosing_register_array[XED_REG_LAST]; +XED_GLOBAL_EXTERN xed_reg_enum_t xed_largest_enclosing_register_array_32[XED_REG_LAST]; + +// OC2 width codes. The 2nd index is the effective operand size (1,2, or 3) +XED_GLOBAL_EXTERN xed_uint16_t xed_width_bits[XED_OPERAND_WIDTH_LAST][4]; + +// the default type of the operand elements +XED_GLOBAL_EXTERN +xed_operand_element_type_enum_t xed_operand_type_table[XED_OPERAND_WIDTH_LAST]; + +// the xtype -> dtype, # bits per element map +extern const xed_operand_type_info_t xed_operand_xtype_info[XED_OPERAND_XTYPE_LAST]; + + +// number of elements per operand +XED_GLOBAL_EXTERN +xed_uint32_t xed_operand_element_width[XED_OPERAND_WIDTH_LAST]; + +// Returns 1 if the corresponding value in xed_width_bits is a multiple of +// 8 bits +XED_GLOBAL_EXTERN xed_uint8_t xed_width_is_bytes[XED_OPERAND_WIDTH_LAST][4]; + +// FIXME: Could make the flags info decoder-only. +// Flags tables. The top table points to the flag-actions. The +// complex table points to the simple flags table entries. + +extern const xed_simple_flag_t +xed_flags_simple_table[XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES]; +extern const xed_complex_flag_t +xed_flags_complex_table[XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES]; +extern const xed_flag_action_t +xed_flag_action_table[XED_MAX_GLOBAL_FLAG_ACTIONS]; + +#endif diff --git a/include/private/xed-util-private.h b/include/private/xed-util-private.h new file mode 100644 index 0000000..9c6f99d --- /dev/null +++ b/include/private/xed-util-private.h @@ -0,0 +1,56 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-util.h +/// + + + +#ifndef _XED_UTIL_PRIVATE_H_ +# define _XED_UTIL_PRIVATE_H_ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-util.h" + +/* copy from src to dst, downcasing bytes as the copy proceeds. len is the + * available space in the buffer*/ +int xed_strncat_lower(char* dst, const char* src, int len); + +int xed_itoa_signed(char* buf, xed_int64_t f, int buflen); + +char xed_to_ascii_hex_nibble(xed_uint_t x, xed_bool_t lowercase); + +int xed_sprintf_uint8_hex(char* buf, xed_uint8_t x, int buflen); +int xed_sprintf_uint16_hex(char* buf, xed_uint16_t x, int buflen); +int xed_sprintf_uint32_hex(char* buf, xed_uint32_t x, int buflen); +int xed_sprintf_uint64_hex(char* buf, xed_uint64_t x, int buflen); +int xed_sprintf_uint8(char* buf, xed_uint8_t x, int buflen); +int xed_sprintf_uint16(char* buf, xed_uint16_t x, int buflen); +int xed_sprintf_uint32(char* buf, xed_uint32_t x, int buflen); +int xed_sprintf_uint64(char* buf, xed_uint64_t x, int buflen); +int xed_sprintf_int8(char* buf, xed_int8_t x, int buflen); +int xed_sprintf_int16(char* buf, xed_int16_t x, int buflen); +int xed_sprintf_int32(char* buf, xed_int32_t x, int buflen); +int xed_sprintf_int64(char* buf, xed_int64_t x, int buflen); + +void xed_derror(const char* s); +void xed_dwarn(const char* s); + + +#endif diff --git a/include/private/xed3-dynamic-decode.h b/include/private/xed3-dynamic-decode.h new file mode 100644 index 0000000..ecbf232 --- /dev/null +++ b/include/private/xed3-dynamic-decode.h @@ -0,0 +1,49 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed3-dynamic-decode.h +/// dynamic information decoder + +#if !defined(_XED3_DYNAMIC_DECODE_H_) +#define _XED3_DYNAMIC_DECODE_H_ + + +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-types.h" +#include "xed-decoded-inst.h" + +/// Set the operands information. +/// should be called after dynamic_decode_part2 +/// @ingroup XED3 +/* sets information about register operands with ntluf */ +xed_error_enum_t xed3_decode_operands(xed_decoded_inst_t* d); + + +/// decode instruction after xed_inst_t was set. +/// captures all NTs that appear in pattern. +/// xds should be initialized. +/// @ingroup XED3 +xed_error_enum_t +xed3_dynamic_decode_part2(xed_decoded_inst_t* d); + + + +#endif + diff --git a/include/private/xed3-static-decode.h b/include/private/xed3-static-decode.h new file mode 100644 index 0000000..2c19e9d --- /dev/null +++ b/include/private/xed3-static-decode.h @@ -0,0 +1,36 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed3-static-decode.h +/// instruction length decoder + +#if !defined(_XED3_STATIC_DECODE_H_) +#define _XED3_STATIC_DECODE_H_ + +#include "xed-ild.h" + + +/// Static decoder. +/// @param d xed_decoded_inst_t. +/// Sets the xed_inst_t +/// +/// @ingroup XED3 +void xed3_static_decode(xed_decoded_inst_t* d); + +#endif + diff --git a/include/public/xed-agen.h b/include/public/xed-agen.h new file mode 100644 index 0000000..bc1eef8 --- /dev/null +++ b/include/public/xed-agen.h @@ -0,0 +1,66 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-agen.h +/// + + +#ifndef _XED_AGEN_H_ +# define _XED_AGEN_H_ +#include "xed-decoded-inst.h" +#include "xed-error-enum.h" + + +/// A function for obtaining register values. 32b return values should be +/// zero extended to 64b. The error value is set to nonzero if the callback +/// experiences some sort of problem. @ingroup AGEN +typedef xed_uint64_t (*xed_register_callback_fn_t)(xed_reg_enum_t reg, + void* context, + xed_bool_t* error); + +/// A function for obtaining the segment base values. 32b return values +/// should be zero extended zero extended to 64b. The error value is set to +/// nonzero if the callback experiences some sort of problem. +/// @ingroup AGEN +typedef xed_uint64_t (*xed_segment_base_callback_fn_t)(xed_reg_enum_t reg, + void* context, + xed_bool_t* error); + + +/// Initialize the callback functions. Tell XED what to call when using +/// #xed_agen. +/// @ingroup AGEN +XED_DLL_EXPORT void xed_agen_register_callback(xed_register_callback_fn_t register_fn, + xed_segment_base_callback_fn_t segment_fn); + +/// Using the registered callbacks, compute the memory address for a +/// specified memop in a decoded instruction. memop_index can have the +/// value 0 for XED_OPERAND_MEM0, XED_OPERAND_AGEN, or 1 for +/// XED_OPERAND_MEM1. Any other value results in an error being +/// returned. The context parameter which is passed to the registered +/// callbacks can be used to identify which thread's state is being +/// referenced. The context parameter can also be used to specify which +/// element of a vector register should be returned for gather an scatter +/// operations. +/// @ingroup AGEN +XED_DLL_EXPORT xed_error_enum_t xed_agen(xed_decoded_inst_t* xedd, + unsigned int memop_index, + void* context, + xed_uint64_t* out_address); + + +#endif diff --git a/include/public/xed-attributes.h b/include/public/xed-attributes.h new file mode 100644 index 0000000..44432ce --- /dev/null +++ b/include/public/xed-attributes.h @@ -0,0 +1,28 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_ATTRIBUTES_H_) +# define _XED_ATTRIBUTES_H_ +#include "xed-types.h" + +typedef struct { + xed_uint64_t a1; + xed_uint64_t a2; +} xed_attributes_t; + +#endif diff --git a/include/public/xed-chip-features.h b/include/public/xed-chip-features.h new file mode 100644 index 0000000..0118220 --- /dev/null +++ b/include/public/xed-chip-features.h @@ -0,0 +1,46 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_CHIP_FEATURES_H_) +# define _XED_CHIP_FEATURES_H_ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-isa-set-enum.h" /* generated */ +#include "xed-chip-enum.h" /* generated */ + +#define XED_FEATURE_VECTOR_MAX 4 +/// @ingroup ISASET +typedef struct +{ + xed_uint64_t f[XED_FEATURE_VECTOR_MAX]; +} xed_chip_features_t; + + +/// fill in the contents of p with the vector of chip features. +XED_DLL_EXPORT void +xed_get_chip_features(xed_chip_features_t* p, xed_chip_enum_t chip); + +/// present = 1 to turn the feature on. present=0 to remove the feature. +XED_DLL_EXPORT void +xed_modify_chip_features(xed_chip_features_t* p, + xed_isa_set_enum_t isa_set, + xed_bool_t present); + + +#endif diff --git a/include/public/xed-common-defs.h b/include/public/xed-common-defs.h new file mode 100644 index 0000000..c97e5f6 --- /dev/null +++ b/include/public/xed-common-defs.h @@ -0,0 +1,47 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-common-defs.h +/// @brief some pervasive defines + + + +#ifndef _XED_COMMON_DEFS_H_ +# define _XED_COMMON_DEFS_H_ + + // for most things it is 4, but one 64b mov allows 8 +#define XED_MAX_DISPLACEMENT_BYTES 8 + + // for most things it is max 4, but one 64b mov allows 8. +#define XED_MAX_IMMEDIATE_BYTES 8 + +#define XED_MAX_INSTRUCTION_BYTES 15 + + +#define XED_BYTE_MASK(x) ((x) & 0xFF) +#define XED_BYTE_CAST(x) (XED_STATIC_CAST(xed_uint8_t,x)) + +#endif + + + + + + + + + diff --git a/include/public/xed-common-hdrs.h b/include/public/xed-common-hdrs.h new file mode 100644 index 0000000..c5f5d5d --- /dev/null +++ b/include/public/xed-common-hdrs.h @@ -0,0 +1,71 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-common-hdrs.h +/// + + + +#ifndef _XED_COMMON_HDRS_H_ +# define _XED_COMMON_HDRS_H_ + + + +#if defined(__FreeBSD__) +# define XED_BSD +#endif +#if defined(__linux__) +# define XED_LINUX +#endif +#if defined(_MSC_VER) +# define XED_WINDOWS +#endif +#if defined(__APPLE__) +# define XED_MAC +#endif + + +#if defined(XED_DLL) +// __declspec(dllexport) works with GNU GCC or MS compilers, but not ICC +// on linux + +# if defined(XED_WINDOWS) +# define XED_DLL_EXPORT __declspec(dllexport) +# define XED_DLL_IMPORT __declspec(dllimport) +# elif defined(XED_LINUX) || defined(XED_BSD) || defined(XED_MAC) +# define XED_DLL_EXPORT __attribute__((visibility("default"))) +# define XED_DLL_IMPORT +# else +# define XED_DLL_EXPORT +# define XED_DLL_IMPORT +# endif + +# if defined(XED_BUILD) + /* when building XED, we export symbols */ +# define XED_DLL_GLOBAL XED_DLL_EXPORT +# else + /* when building XED clients, we import symbols */ +# define XED_DLL_GLOBAL XED_DLL_IMPORT +# endif +#else +# define XED_DLL_EXPORT +# define XED_DLL_IMPORT +# define XED_DLL_GLOBAL +#endif + +#endif + diff --git a/include/public/xed-cpuid-rec.h b/include/public/xed-cpuid-rec.h new file mode 100644 index 0000000..da7b7fa --- /dev/null +++ b/include/public/xed-cpuid-rec.h @@ -0,0 +1,55 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#ifndef _XED_CPUID_REC_H_ +# define _XED_CPUID_REC_H_ +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-cpuid-bit-enum.h" +#include "xed-isa-set-enum.h" + + +typedef struct { + xed_uint32_t leaf; // cpuid leaf + xed_uint32_t subleaf; // cpuid subleaf + xed_uint32_t bit; // the bit number for the feature + xed_reg_enum_t reg; // the register containing the bit (EAX,EBX,ECX,EDX) +} xed_cpuid_rec_t; + +#define XED_MAX_CPUID_BITS_PER_ISA_SET (4) + +/// Returns the name of the i'th cpuid bit associated with this isa-set. +/// Call this repeatedly, with 0 <= i < +/// XED_MAX_CPUID_BITS_PER_ISA_SET. Give up when i == +/// XED_MAX_CPUID_BITS_PER_ISA_SET or the return value is +/// XED_CPUID_BIT_INVALID. +XED_DLL_EXPORT +xed_cpuid_bit_enum_t +xed_get_cpuid_bit_for_isa_set(xed_isa_set_enum_t isaset, + xed_uint_t i); + +/// This provides the details of the CPUID bit specification, if the +/// enumeration value is not sufficient. Returns 1 on success and fills in +/// the structure pointed to by p. Returns 0 on failure. +XED_DLL_EXPORT +xed_int_t +xed_get_cpuid_rec(xed_cpuid_bit_enum_t cpuid_bit, + xed_cpuid_rec_t* p); + +#endif + diff --git a/include/public/xed-decode.h b/include/public/xed-decode.h new file mode 100644 index 0000000..f84b2b0 --- /dev/null +++ b/include/public/xed-decode.h @@ -0,0 +1,69 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decode.h + + +#ifndef _XED_DECODE_H_ +# define _XED_DECODE_H_ + +#include "xed-decoded-inst.h" +#include "xed-error-enum.h" +#include "xed-chip-features.h" + +/// This is the main interface to the decoder. +/// @param xedd the decoded instruction of type #xed_decoded_inst_t . Mode/state sent in via xedd; See the #xed_state_t +/// @param itext the pointer to the array of instruction text bytes +/// @param bytes the length of the itext input array. 1 to 15 bytes, anything more is ignored. +/// @return #xed_error_enum_t indiciating success (#XED_ERROR_NONE) or failure. Note failure can be due to not +/// enough bytes in the input array. +/// +/// The maximum instruction is 15B and XED will tell you how long the +/// actual instruction is via an API function call +/// xed_decoded_inst_get_length(). However, it is not always safe or +/// advisable for XED to read 15 bytes if the decode location is at the +/// boundary of some sort of protection limit. For example, if one is +/// decoding near the end of a page and the XED user does not want to cause +/// extra page faults, one might send in the number of bytes that would +/// stop at the page boundary. In this case, XED might not be able to +/// decode the instruction and would return an error. The XED user would +/// then have to decide if it was safe to touch the next page and try again +/// to decode with more bytes. Also sometimes the user process does not +/// have read access to the next page and this allows the user to prevent +/// XED from causing process termination by limiting the memory range that +/// XED will access. +/// +/// @ingroup DEC +XED_DLL_EXPORT xed_error_enum_t +xed_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes); + +/// @ingroup DEC +/// See #xed_decode(). This version of the decode API adds a CPUID feature +/// vector to support restricting decode based on both a specified chip via +/// #xed_decoded_inst_set_input_chip() and a modify-able cpuid feature +/// vector obtained from #xed_get_chip_features(). +XED_DLL_EXPORT xed_error_enum_t +xed_decode_with_features(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes, + xed_chip_features_t* features); + + +#endif + diff --git a/include/public/xed-decoded-inst-api.h b/include/public/xed-decoded-inst-api.h new file mode 100644 index 0000000..dfc59ff --- /dev/null +++ b/include/public/xed-decoded-inst-api.h @@ -0,0 +1,653 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decoded-inst-api.h +/// + +#if !defined(_XED_DECODED_INST_API_H_) +# define _XED_DECODED_INST_API_H_ + +#include "xed-decoded-inst.h" +#include "xed-operand-accessors.h" +#include "xed-state.h" +#include "xed-operand-values-interface.h" +#include "xed-print-info.h" + +/////////////////////////////////////////////////////// +/// API +/////////////////////////////////////////////////////// + +/// @name xed_decoded_inst_t High-level accessors +//@{ +/// @ingroup DEC +/// Return true if the instruction is valid +static XED_INLINE xed_bool_t +xed_decoded_inst_valid(const xed_decoded_inst_t* p ) { + return XED_STATIC_CAST(xed_bool_t,(p->_inst != 0)); +} +/// @ingroup DEC +/// Return the #xed_inst_t structure for this instruction. This is the +/// route to the basic operands form information. +static XED_INLINE const xed_inst_t* +xed_decoded_inst_inst( const xed_decoded_inst_t* p) { + return p->_inst; +} + + +/// @ingroup DEC +/// Return the instruction #xed_category_enum_t enumeration +static XED_INLINE xed_category_enum_t +xed_decoded_inst_get_category(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_category(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_extension_enum_t enumeration +static XED_INLINE xed_extension_enum_t +xed_decoded_inst_get_extension( const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_extension(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_isa_set_enum_t enumeration +static XED_INLINE xed_isa_set_enum_t +xed_decoded_inst_get_isa_set(xed_decoded_inst_t const* const p) { + xed_assert(p->_inst != 0); + return xed_inst_isa_set(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_iclass_enum_t enumeration. +static XED_INLINE xed_iclass_enum_t +xed_decoded_inst_get_iclass( const xed_decoded_inst_t* p){ + xed_assert(p->_inst != 0); + return xed_inst_iclass(p->_inst); +} + +/// @name xed_decoded_inst_t Attirbutes and properties +//@{ +/// @ingroup DEC +/// Returns 1 if the attribute is defined for this instruction. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_get_attribute(const xed_decoded_inst_t* p, + xed_attribute_enum_t attr); + +/// @ingroup DEC +/// Returns the attribute bitvector +XED_DLL_EXPORT xed_attributes_t +xed_decoded_inst_get_attributes(const xed_decoded_inst_t* p); +//@} + +/// @ingroup DEC +/// Returns 1 if the instruction is xacquire. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_is_xacquire(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 if the instruction is xrelease. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_is_xrelease(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 if the instruction has mpx prefix. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_has_mpx_prefix(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns the modrm byte +XED_DLL_EXPORT xed_uint8_t +xed_decoded_inst_get_modrm(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 iff the instruction uses destination-masking. This is 0 for +/// blend operations that use their mask field as a control. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_masked_vector_operation(xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 128, 256 or 512 for operations in the VEX, EVEX (or XOP) +/// encoding space and returns 0 for (most) nonvector operations. +/// This usually the content of the VEX.L or EVEX.LL field, reinterpreted. +/// Some GPR instructions (like the BMI1/BMI2) are encoded in the VEX space +/// and return non-zero values from this API. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_vector_length_bits(xed_decoded_inst_t const* const p); + +/// @ingroup DEC +/// Returns the number of legacy prefixes. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_nprefixes(xed_decoded_inst_t* p); + +//@} + + +/// @name xed_decoded_inst_t Operands +//@{ +/// @ingroup DEC +/// Obtain a constant pointer to the operands +static XED_INLINE const xed_operand_values_t* +xed_decoded_inst_operands_const(const xed_decoded_inst_t* p) { + return p; +} +/// @ingroup DEC +/// Obtain a non-constant pointer to the operands +static XED_INLINE xed_operand_values_t* +xed_decoded_inst_operands(xed_decoded_inst_t* p) { + return p; +} + +/// Return the length in bits of the operand_index'th operand. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_length_bits(const xed_decoded_inst_t* p, + unsigned int operand_index); + + +/// Deprecated -- returns the length in bytes of the operand_index'th +/// operand. Use #xed_decoded_inst_operand_length_bits() instead. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_length(const xed_decoded_inst_t* p, + unsigned int operand_index); + + +/// Return the number of operands +/// @ingroup DEC +static XED_INLINE unsigned int +xed_decoded_inst_noperands(const xed_decoded_inst_t* p) { + unsigned int noperands = xed_inst_noperands(xed_decoded_inst_inst(p)); + return noperands; +} + + +/// Return the number of element in the operand (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_elements(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Return the size of an element in bits (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_element_size_bits(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Return the type of an element of type #xed_operand_element_type_enum_t +/// (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT xed_operand_element_type_enum_t +xed_decoded_inst_operand_element_type(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Interpret the operand action in light of AVX512 masking and +/// zeroing/merging. If masking and merging are used together, the dest +/// operand may also be read. If masking and merging are used together, +/// the elemnents of dest operand register may be conditionally written (so +/// that input values live on in the output register). +/// @ingroup DEC +XED_DLL_EXPORT xed_operand_action_enum_t +xed_decoded_inst_operand_action(const xed_decoded_inst_t* p, + unsigned int operand_index); + +//@} + +/// @name xed_decoded_inst_t AVX512 Masking +//@{ +/// Returns true if the instruction uses write-masking +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_masking(const xed_decoded_inst_t* p); + +/// Returns true if the instruction uses write-masking with merging +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_merging(const xed_decoded_inst_t* p); + +/// Returns true if the instruction uses write-masking with zeroing +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_zeroing(const xed_decoded_inst_t* p); +//@} + +/// @name xed_decoded_inst_t Initialization +//@{ +/// @ingroup DEC +/// Zero the decode structure, but set the machine state/mode +/// information. Re-initializes all operands. +XED_DLL_EXPORT void +xed_decoded_inst_zero_set_mode(xed_decoded_inst_t* p, + const xed_state_t* dstate); + +/// @ingroup DEC +/// Zero the decode structure, but preserve the existing machine state/mode +/// information. Re-initializes all operands. +XED_DLL_EXPORT void xed_decoded_inst_zero_keep_mode(xed_decoded_inst_t* p); + + +/// @ingroup DEC +/// Zero the decode structure completely. Re-initializes all operands. +XED_DLL_EXPORT void xed_decoded_inst_zero(xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Set the machine mode and stack addressing width directly. This is NOT a +/// full initialization; Call #xed_decoded_inst_zero() before using this if +/// you want a clean slate. +static XED_INLINE void +xed_decoded_inst_set_mode(xed_decoded_inst_t* p, + xed_machine_mode_enum_t mmode, + xed_address_width_enum_t stack_addr_width) +{ + xed_state_t dstate; + dstate.mmode = mmode; + dstate.stack_addr_width = stack_addr_width; + xed_operand_values_set_mode(p, &dstate); +} + + + +/// @ingroup DEC +/// Zero the decode structure, but copy the existing machine state/mode +/// information from the supplied operands pointer. Same as +/// #xed_decoded_inst_zero_keep_mode. +XED_DLL_EXPORT void +xed_decoded_inst_zero_keep_mode_from_operands( + xed_decoded_inst_t* p, + const xed_operand_values_t* operands); + +/// @name xed_decoded_inst_t Length +//@{ +/// @ingroup DEC +/// Return the length of the decoded instruction in bytes. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_length(const xed_decoded_inst_t* p) { + return p->_decoded_length; +} + +//@} + + +/// @name xed_decoded_inst_t get Byte +//@{ +/// @ingroup DEC +/// Read itext byte. +static XED_INLINE xed_uint8_t +xed_decoded_inst_get_byte(const xed_decoded_inst_t* p, xed_uint_t byte_index) +{ + /// Read a whole byte from the normal input bytes. + xed_uint8_t out = p->_byte_array._dec[byte_index]; + return out; +} + +//@} + +/// @name Modes +//@{ +/// @ingroup DEC +/// Returns 16/32/64 indicating the machine mode with in bits. This is +/// derived from the input mode information. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_machine_mode_bits(const xed_decoded_inst_t* p) { + xed_uint8_t mode = xed3_operand_get_mode(p); + if (mode == 2) return 64; + if (mode == 1) return 32; + return 16; +} +/// @ingroup DEC +/// Returns 16/32/64 indicating the stack addressing mode with in +/// bits. This is derived from the input mode information. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_stack_address_mode_bits(const xed_decoded_inst_t* p) { + xed_uint8_t smode = xed3_operand_get_smode(p); + if (smode == 2) return 64; + if (smode == 1) return 32; + return 16; +} + +/// Returns the operand width in bits: 8/16/32/64. This is different than +/// the #xed_operand_values_get_effective_operand_width() which only +/// returns 16/32/64. This factors in the BYTEOP attribute when computing +/// its return value. This is a convenience function. +/// @ingroup DEC +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_get_operand_width(const xed_decoded_inst_t* p); + +/// Return the user-specified #xed_chip_enum_t chip name, or +/// XED_CHIP_INVALID if not set. +/// @ingroup DEC +static XED_INLINE xed_chip_enum_t +xed_decoded_inst_get_input_chip(const xed_decoded_inst_t* p) { + return xed3_operand_get_chip(p); +} + +/// Set a user-specified #xed_chip_enum_t chip name for restricting decode +/// @ingroup DEC +static XED_INLINE void +xed_decoded_inst_set_input_chip(xed_decoded_inst_t* p, + xed_chip_enum_t chip) { + xed3_operand_set_chip(p,chip); +} + + +/// Indicate if this decoded instruction is valid for the specified +/// #xed_chip_enum_t chip +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_valid_for_chip(xed_decoded_inst_t const* const p, + xed_chip_enum_t chip); + +//@} + + + + +/// @name IFORM handling +//@{ + +/// @ingroup DEC +/// Return the instruction iform enum of type #xed_iform_enum_t . +static XED_INLINE xed_iform_enum_t +xed_decoded_inst_get_iform_enum(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_iform_enum(p->_inst); +} + +/// @ingroup DEC +/// Return the instruction zero-based iform number based on masking the +/// corresponding #xed_iform_enum_t. This value is suitable for +/// dispatching. The maximum value for a particular iclass is provided by +/// #xed_iform_max_per_iclass() . +static XED_INLINE unsigned int +xed_decoded_inst_get_iform_enum_dispatch(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_iform_enum(p->_inst) - + xed_iform_first_per_iclass(xed_inst_iclass(p->_inst)); +} +//@} + + + + +/// @name xed_decoded_inst_t Printers +//@{ +/// @ingroup PRINT +/// Print out all the information about the decoded instruction to the +/// buffer buf whose length is maximally buflen. This is for debugging. +XED_DLL_EXPORT void +xed_decoded_inst_dump(const xed_decoded_inst_t* p, char* buf, int buflen); + + + +/// @ingroup PRINT +/// Print the instruction information in a verbose format. +/// This is for debugging. +/// @param p a #xed_decoded_inst_t for a decoded instruction +/// @param buf a buffer to write the disassembly in to. +/// @param buflen maximum length of the disassembly buffer +/// @param runtime_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. +/// @return Returns 0 if the disassembly fails, 1 otherwise. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_dump_xed_format(const xed_decoded_inst_t* p, + char* buf, + int buflen, + xed_uint64_t runtime_address) ; + + +/// Disassemble the decoded instruction using the specified syntax. +/// The output buffer must be at least 25 bytes long. Returns true if +/// disassembly proceeded without errors. +/// @param syntax a #xed_syntax_enum_t the specifies the disassembly format +/// @param xedd a #xed_decoded_inst_t for a decoded instruction +/// @param out_buffer a buffer to write the disassembly in to. +/// @param buffer_len maximum length of the disassembly buffer +/// @param runtime_instruction_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. +/// @param context A void* used only for the call back routine for symbolic disassembly if one is provided. Can be zero. +/// @param symbolic_callback A function pointer for obtaining symbolic disassembly. Can be zero. +/// @return Returns 0 if the disassembly fails, 1 otherwise. +///@ingroup PRINT +XED_DLL_EXPORT xed_bool_t +xed_format_context(xed_syntax_enum_t syntax, + const xed_decoded_inst_t* xedd, + char* out_buffer, + int buffer_len, + xed_uint64_t runtime_instruction_address, + void* context, + xed_disassembly_callback_fn_t symbolic_callback); + + +/// @ingroup PRINT +/// Disassemble the instruction information to a buffer. See the +/// #xed_print_info_t for the required public fields of the argument. +/// This is the preferred method of doing disassembly. +/// The output buffer must be at least 25 bytes long. +/// @param pi a #xed_print_info_t +/// @return Returns 0 if the disassembly fails, 1 otherwise. +XED_DLL_EXPORT xed_bool_t +xed_format_generic(xed_print_info_t* pi); + +//@} + +/// @name xed_decoded_inst_t Operand Field Details +//@{ +/// @ingroup DEC +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_seg_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_base_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_index_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_scale(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_int64_t +xed_decoded_inst_get_memory_displacement(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +/// Result in BYTES +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_memory_displacement_width(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +/// Result in BITS +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_memory_displacement_width_bits(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_int32_t +xed_decoded_inst_get_branch_displacement(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Result in BYTES +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_branch_displacement_width(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Result in BITS +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_branch_displacement_width_bits( + const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_uint64_t +xed_decoded_inst_get_unsigned_immediate(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return true if the first immediate (IMM0) is signed +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_is_signed(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the immediate width in BYTES. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_width(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the immediate width in BITS. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_width_bits(const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_int32_t +xed_decoded_inst_get_signed_immediate(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the second immediate. +static XED_INLINE xed_uint8_t +xed_decoded_inst_get_second_immediate(const xed_decoded_inst_t* p) { + return xed3_operand_get_uimm1(p); +} + +/// @ingroup DEC +/// Return the specified register operand. The specifier is of type +/// #xed_operand_enum_t . +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_reg(const xed_decoded_inst_t* p, + xed_operand_enum_t reg_operand); + + +/// See the comment on xed_decoded_inst_uses_rflags(). This can return +/// 0 if the flags are really not used by this instruction. +/// @ingroup DEC +XED_DLL_EXPORT const xed_simple_flag_t* +xed_decoded_inst_get_rflags_info( const xed_decoded_inst_t* p ); + +/// This returns 1 if the flags are read or written. This will return 0 +/// otherwise. This will return 0 if the flags are really not used by this +/// instruction. For some shifts/rotates, XED puts a flags operand in the +/// operand array before it knows if the flags are used because of +/// mode-dependent masking effects on the immediate. +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_uses_rflags(const xed_decoded_inst_t* p); + +/// @ingroup DEC +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_number_of_memory_operands(const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_read(const xed_decoded_inst_t* p, unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_written(const xed_decoded_inst_t* p, unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_written_only(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_conditionally_writes_registers(const xed_decoded_inst_t* p); +/// returns bytes +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_get_memory_operand_length(const xed_decoded_inst_t* p, + unsigned int memop_idx); + +/// Returns the addressing width in bits (16,32,64) for MEM0 (memop_idx==0) +/// or MEM1 (memop_idx==1). This factors in things like whether or not the +/// reference is an implicit stack push/pop reference, the machine mode and +// 67 prefixes if present. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_get_memop_address_width(const xed_decoded_inst_t* p, + xed_uint_t memop_idx); + + + +/// @ingroup DEC +/// Returns true if the instruction is a prefetch +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_is_prefetch(const xed_decoded_inst_t* p); +//@} + + +/// @name xed_decoded_inst_t Modification +//@{ +// Modifying decoded instructions before re-encoding +/// @ingroup DEC +XED_DLL_EXPORT void +xed_decoded_inst_set_scale(xed_decoded_inst_t* p, xed_uint_t scale); +/// @ingroup DEC +/// Set the memory displacement using a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_memory_displacement(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the branch displacement using a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_branch_displacement(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the signed immediate a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_signed(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the unsigned immediate a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_unsigned(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bytes); + + +/// @ingroup DEC +/// Set the memory displacement a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_memory_displacement_bits(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the branch displacement a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_branch_displacement_bits(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the signed immediate a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_signed_bits(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the unsigned immediate a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_unsigned_bits(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bits); + +//@} + +/// @name xed_decoded_inst_t User Data Field +//@{ +/// @ingroup DEC +/// Return a user data field for arbitrary use by the user after decoding. +static XED_INLINE xed_uint64_t +xed_decoded_inst_get_user_data(xed_decoded_inst_t* p) { + return p->u.user_data; +} +/// @ingroup DEC +/// Modify the user data field. +static XED_INLINE void +xed_decoded_inst_set_user_data(xed_decoded_inst_t* p, + xed_uint64_t new_value) { + p->u.user_data = new_value; +} + + + + +//@} +#endif + diff --git a/include/public/xed-decoded-inst.h b/include/public/xed-decoded-inst.h new file mode 100644 index 0000000..691045e --- /dev/null +++ b/include/public/xed-decoded-inst.h @@ -0,0 +1,90 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decoded-inst.h +/// + +#if !defined(_XED_DECODER_STATE_H_) +# define _XED_DECODER_STATE_H_ +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-types.h" +#include "xed-inst.h" +#include "xed-flags.h" +#if defined(XED_ENCODER) +# include "xed-encoder-gen-defs.h" //generated +#endif +#include "xed-chip-enum.h" //generated +#include "xed-operand-element-type-enum.h" // a generated file +#include "xed-operand-storage.h" // a generated file + + +struct xed_encoder_vars_s; +struct xed_decoder_vars_s; +/// @ingroup DEC +/// The main container for instructions. After decode, it holds an array of +/// operands with derived information from decode and also valid +/// #xed_inst_t pointer which describes the operand templates and the +/// operand order. See @ref DEC for API documentation. +typedef struct xed_decoded_inst_s { + /// The _operands are storage for information discovered during + /// decoding. They are also used by encode. The accessors for these + /// operands all have the form xed3_operand_{get,set}_*(). They should + /// be considered internal and subject to change over time. It is + /// preferred that you use xed_decoded_inst_*() or the + /// xed_operand_values_*() functions when available. + xed_operand_storage_t _operands; + +#if defined(XED_ENCODER) + /// Used for encode operand ordering. Not set by decode. + xed_uint8_t _operand_order[XED_ENCODE_ORDER_MAX_OPERANDS]; + /// Length of the _operand_order[] array. + xed_uint8_t _n_operand_order; +#endif + xed_uint8_t _decoded_length; + + /// when we decode an instruction, we set the _inst and get the + /// properites of that instruction here. This also points to the + /// operands template array. + const xed_inst_t* _inst; + + // decoder does not change it, encoder does + union { + xed_uint8_t* _enc; + const xed_uint8_t* _dec; + } _byte_array; + + // The ev field is stack allocated by xed_encode(). It is per-encode + // transitory data. + union { + /* user_data is available as a user data storage field after + * decoding. It does not live across re-encodes or re-decodes. */ + xed_uint64_t user_data; +#if defined(XED_ENCODER) + struct xed_encoder_vars_s* ev; +#endif + } u; + +} xed_decoded_inst_t; + +typedef xed_decoded_inst_t xed_operand_values_t; + + +#endif + diff --git a/include/public/xed-disas.h b/include/public/xed-disas.h new file mode 100644 index 0000000..778cea4 --- /dev/null +++ b/include/public/xed-disas.h @@ -0,0 +1,52 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas.h +/// + +#if !defined(_XED_DISAS_H_) +# define _XED_DISAS_H_ + +#include "xed-types.h" + +/// @ingroup PRINT +/// A #xed_disassembly_callback_fn_t takes an address, a pointer to a +/// symbol buffer of buffer_length bytes, and a pointer to an offset. The +/// function fills in the symbol_buffer and sets the offset to the desired +/// offset for that symbol. If the function succeeds, it returns 1. +// The call back should return 0 if the buffer is not long enough to +// include the null termination.If no symbolic information is +// located, the function returns zero. +/// @param address The input address for which we want symbolic name and offset +/// @param symbol_buffer A buffer to hold the symbol name. The callback function should fill this in and terminate +/// with a null byte. +/// @param buffer_length The maximum length of the symbol_buffer including then null +/// @param offset A pointer to a xed_uint64_t to hold the offset from the provided symbol. +/// @param context This void* pointer passed to the disassembler's new interface so that the caller can identify +/// the proper context against which to resolve the symbols. +/// The disassembler passes this value to +/// the callback. The legacy formatters +/// that do not have context will pass zero for this parameter. +/// @return 0 on failure, 1 on success. +typedef int (*xed_disassembly_callback_fn_t)( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* context); + +#endif diff --git a/include/public/xed-encode.h b/include/public/xed-encode.h new file mode 100644 index 0000000..31b5d10 --- /dev/null +++ b/include/public/xed-encode.h @@ -0,0 +1,287 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode.h + + +#ifndef _XED_ENCODE_H_ +# define _XED_ENCODE_H_ +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-error-enum.h" +#include "xed-operand-values-interface.h" +#include "xed-operand-width-enum.h" +#include "xed-encoder-iforms.h" //generated +#include "xed-encoder-gen-defs.h" //generated + +// we now (mostly) share the decode data structure +#include "xed-decoded-inst.h" + + +// establish a type equivalence for the xed_encoder_request_t and the +// corresponding xed_decoded_inst_t. + +/// @ingroup ENC +typedef struct xed_decoded_inst_s xed_encoder_request_s; +/// @ingroup ENC +typedef xed_decoded_inst_t xed_encoder_request_t; + + + +/// @ingroup ENC +XED_DLL_EXPORT xed_iclass_enum_t +xed_encoder_request_get_iclass( const xed_encoder_request_t* p); + +///////////////////////////////////////////////////////// +// set functions + +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_iclass( xed_encoder_request_t* p, + xed_iclass_enum_t iclass); + +/// @name Prefixes +//@{ +/// @ingroup ENC +/// for REPNE(F2) prefix on string ops +XED_DLL_EXPORT void xed_encoder_request_set_repne(xed_encoder_request_t* p); +/// @ingroup ENC +/// for REP(F3) prefix on string ops +XED_DLL_EXPORT void xed_encoder_request_set_rep(xed_encoder_request_t* p); +/// @ingroup ENC +/// clear the REP prefix indicator +XED_DLL_EXPORT void xed_encoder_request_clear_rep(xed_encoder_request_t* p); +//@} + +/// @name Primary Encode Functions +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_effective_operand_width( xed_encoder_request_t* p, + xed_uint_t width_bits); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_effective_address_size( xed_encoder_request_t* p, + xed_uint_t width_bits); +/*! @ingroup ENC + * + * Set the operands array element indexed by operand to the actual register + * name reg. + * + * @param[in] p xed_encoder_request_t + * @param[in] operand indicates which register operand storage field to use + * @param[in] reg the actual register represented (EAX, etc.) to store. + */ +XED_DLL_EXPORT void xed_encoder_request_set_reg(xed_encoder_request_t* p, + xed_operand_enum_t operand, + xed_reg_enum_t reg); +//@} + +/// @name Operand Order +//@{ +/*! @ingroup ENC + * Specify the name as the n'th operand in the operand order. + * + * The complication of this function is that the register operand names are + * specific to the position of the operand (REG0, REG1, REG2...). One can + * use this function for registers or one can use the + * xed_encoder_request_set_operand_name_reg() which takes integers instead + * of operand names. + * + * @param[in] p #xed_encoder_request_t + * @param[in] operand_index xed_uint_t representing n'th operand position + * @param[in] name #xed_operand_enum_t operand name. + */ +XED_DLL_EXPORT void +xed_encoder_request_set_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index, + xed_operand_enum_t name); + +/*! @ingroup ENC + * Retreive the name of the n'th operand in the operand order. + * + * @param[in] p #xed_encoder_request_t + * @param[in] operand_index xed_uint_t representing n'th operand position + * @return The #xed_operand_enum_t operand name. + */ +XED_DLL_EXPORT xed_operand_enum_t +xed_encoder_request_get_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index); + + +/// @ingroup ENC +/// Retreive the number of entries in the encoder operand order array +/// @return The number of entries in the encoder operand order array +static XED_INLINE xed_uint_t +xed_encoder_request_operand_order_entries(xed_encoder_request_t* p) +{ + return p->_n_operand_order; +} + +//@} + + +/// @name branches and far pointers +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_relbr(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_branch_displacement(xed_encoder_request_t* p, + xed_int32_t brdisp, + xed_uint_t nbytes); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_ptr(xed_encoder_request_t* p); +//@} + + +/// @name Immediates +//@{ +/// @ingroup ENC +/// Set the uimm0 using a BYTE width. +XED_DLL_EXPORT void xed_encoder_request_set_uimm0(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbytes); +/// @ingroup ENC +/// Set the uimm0 using a BIT width. +XED_DLL_EXPORT void xed_encoder_request_set_uimm0_bits(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbits); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_uimm1(xed_encoder_request_t* p, + xed_uint8_t uimm); +/// @ingroup ENC +/// same storage as uimm0 +XED_DLL_EXPORT void xed_encoder_request_set_simm(xed_encoder_request_t* p, + xed_int32_t simm, + xed_uint_t nbytes); + +/// @name Memory +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_memory_displacement(xed_encoder_request_t* p, + xed_int64_t memdisp, + xed_uint_t nbytes); + +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_agen(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_mem0(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_mem1(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_memory_operand_length(xed_encoder_request_t* p, + xed_uint_t nbytes); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_seg0(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_seg1(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_base0(xed_encoder_request_t* p, + xed_reg_enum_t base_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_base1(xed_encoder_request_t* p, + xed_reg_enum_t base_reg) ; +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_index(xed_encoder_request_t* p, + xed_reg_enum_t index_reg); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_scale(xed_encoder_request_t* p, + xed_uint_t scale); +//@} + +////////////////////////////////////////////// +/// @ingroup ENC +XED_DLL_EXPORT const xed_operand_values_t* +xed_encoder_request_operands_const(const xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT xed_operand_values_t* +xed_encoder_request_operands(xed_encoder_request_t* p); + +/// @name Initialization +//@{ +/*! @ingroup ENC + * clear the operand order array + * @param[in] p xed_encoder_request_t + */ +XED_DLL_EXPORT void +xed_encoder_request_zero_operand_order(xed_encoder_request_t* p); + +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_zero_set_mode(xed_encoder_request_t* p, + const xed_state_t* dstate); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_zero(xed_encoder_request_t* p) ; +//@} + +struct xed_decoded_inst_s; //fwd decl +/// @ingroup ENC +/// Converts an decoder request to a valid encoder request. +XED_DLL_EXPORT void +xed_encoder_request_init_from_decode(struct xed_decoded_inst_s* d); + +/// @name String Printing +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void xed_encode_request_print(const xed_encoder_request_t* p, + char* buf, xed_uint_t buflen); +//@} + + + + +/// @name Encoding +//@{ +/// This is the main interface to the encoder. The array should be +/// at most 15 bytes long. The ilen parameter should indiciate +/// this length. If the array is too short, the encoder may fail to +/// encode the request. Failure is indicated by a return value of +/// type #xed_error_enum_t that is not equal to +/// #XED_ERROR_NONE. Otherwise, #XED_ERROR_NONE is returned and the +/// length of the encoded instruction is returned in olen. +/// +/// @param r encoder request description (#xed_encoder_request_t), includes mode info +/// @param array the encoded instruction bytes are stored here +/// @param ilen the input length of array. +/// @param olen the actual length of array used for encoding +/// @return success/failure as a #xed_error_enum_t +/// @ingroup ENC +XED_DLL_EXPORT xed_error_enum_t +xed_encode(xed_encoder_request_t* r, + xed_uint8_t* array, + const unsigned int ilen, + unsigned int* olen); + +/// This function will attempt to encode a NOP of exactly ilen +/// bytes. If such a NOP is not encodeable, then false will be returned. +/// +/// @param array the encoded instruction bytes are stored here +/// @param ilen the input length array. +/// @return success/failure as a #xed_error_enum_t +/// @ingroup ENC +XED_DLL_EXPORT xed_error_enum_t +xed_encode_nop(xed_uint8_t* array, + const unsigned int ilen); +//@} + +#endif diff --git a/include/public/xed-encoder-hl.h b/include/public/xed-encoder-hl.h new file mode 100644 index 0000000..6553832 --- /dev/null +++ b/include/public/xed-encoder-hl.h @@ -0,0 +1,668 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#ifndef _XED_ENCODER_HL_H_ +# define _XED_ENCODER_HL_H_ +#include "xed-types.h" +#include "xed-reg-enum.h" +#include "xed-state.h" +#include "xed-iclass-enum.h" +#include "xed-portability.h" +#include "xed-encode.h" + + +typedef struct { + xed_uint64_t displacement; + xed_uint32_t displacement_bits; +} xed_enc_displacement_t; /* fixme bad name */ + +/// @name Memory Displacement +//@{ +/// @ingroup ENCHL +/// a memory displacement (not for branches) +/// @param displacement The value of the displacement +/// @param displacement_bits The width of the displacement in bits. Typically 8 or 32. +/// @returns #xed_enc_displacement_t +static XED_INLINE +xed_enc_displacement_t xed_disp(xed_uint64_t displacement, + xed_uint32_t displacement_bits ) { + xed_enc_displacement_t x; + x.displacement = displacement; + x.displacement_bits = displacement_bits; + return x; +} +//@} + +typedef struct { + xed_reg_enum_t seg; + xed_reg_enum_t base; + xed_reg_enum_t index; + xed_uint32_t scale; + xed_enc_displacement_t disp; +} xed_memop_t; + + +typedef enum { + XED_ENCODER_OPERAND_TYPE_INVALID, + XED_ENCODER_OPERAND_TYPE_BRDISP, + XED_ENCODER_OPERAND_TYPE_REG, + XED_ENCODER_OPERAND_TYPE_IMM0, + XED_ENCODER_OPERAND_TYPE_SIMM0, + XED_ENCODER_OPERAND_TYPE_IMM1, + XED_ENCODER_OPERAND_TYPE_MEM, + XED_ENCODER_OPERAND_TYPE_PTR, + + /* special for things with suppressed implicit memops */ + XED_ENCODER_OPERAND_TYPE_SEG0, + + /* special for things with suppressed implicit memops */ + XED_ENCODER_OPERAND_TYPE_SEG1, + + /* specific operand storage fields -- must supply a name */ + XED_ENCODER_OPERAND_TYPE_OTHER +} xed_encoder_operand_type_t; + +typedef struct { + xed_encoder_operand_type_t type; + union { + xed_reg_enum_t reg; + xed_int32_t brdisp; + xed_uint64_t imm0; + xed_uint8_t imm1; + struct { + xed_operand_enum_t operand_name; + xed_uint32_t value; + } s; + xed_memop_t mem; + } u; + xed_uint32_t width_bits; +} xed_encoder_operand_t; + +/// @name Branch Displacement +//@{ +/// @ingroup ENCHL +/// a relative branch displacement operand +/// @param brdisp The branch displacement +/// @param width_bits The width of the displacement in bits. Typically 8 or 32. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_relbr(xed_int32_t brdisp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_BRDISP; + o.u.brdisp = brdisp; + o.width_bits = width_bits; + return o; +} +//@} + +/// @name Pointer Displacement +//@{ +/// @ingroup ENCHL +/// a relative displacement for a PTR operand -- the subsequent imm0 holds +///the 16b selector +/// @param brdisp The displacement for a far pointer operand +/// @param width_bits The width of the far pointr displacement in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_ptr(xed_int32_t brdisp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_PTR; + o.u.brdisp = brdisp; + o.width_bits = width_bits; + return o; +} +//@} + +/// @name Register and Immmediate Operands +//@{ +/// @ingroup ENCHL +/// a register operand +/// @param reg A #xed_reg_enum_t register operand +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_reg(xed_reg_enum_t reg) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_REG; + o.u.reg = reg; + o.width_bits = 0; + return o; +} + +/// @ingroup ENCHL +/// a first immediate operand (known as IMM0) +/// @param v An immdediate operand. +/// @param width_bits The immediate width in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_imm0(xed_uint64_t v, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_IMM0; + o.u.imm0 = v; + o.width_bits = width_bits; + return o; +} +/// @ingroup ENCHL +/// an 32b signed immediate operand +/// @param v An signed immdediate operand. +/// @param width_bits The immediate width in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_simm0(xed_int32_t v, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_SIMM0; + /* sign conversion: we store the int32 in an uint64. It gets sign + extended. Later we convert it to the right width_bits for the + instruction. The maximum width_bits of a signed immediate is currently + 32b. */ + o.u.imm0 = v; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// The 2nd immediate operand (known as IMM1) for rare instructions that require it. +/// @param v The 2nd immdediate (byte-width) operand +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_imm1(xed_uint8_t v) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_IMM1; + o.u.imm1 = v; + o.width_bits = 8; + return o; +} + + +/// @ingroup ENCHL +/// an operand storage field name and value +static XED_INLINE xed_encoder_operand_t xed_other( + xed_operand_enum_t operand_name, + xed_int32_t value) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_OTHER; + o.u.s.operand_name = operand_name; + o.u.s.value = value; + o.width_bits = 0; + return o; +} +//@} + + +//@} + +/// @name Memory and Segment-releated Operands +//@{ + +/// @ingroup ENCHL +/// seg reg override for implicit suppressed memory ops +static XED_INLINE xed_encoder_operand_t xed_seg0(xed_reg_enum_t seg0) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_SEG0; + o.u.reg = seg0; + return o; +} + +/// @ingroup ENCHL +/// seg reg override for implicit suppressed memory ops +static XED_INLINE xed_encoder_operand_t xed_seg1(xed_reg_enum_t seg1) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_SEG1; + o.u.reg = seg1; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base only +/// @param base The base register +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_b(xed_reg_enum_t base, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp.displacement = 0; + o.u.mem.disp.displacement_bits = 0; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base and displacement only +/// @param base The base register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_bd(xed_reg_enum_t base, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp =disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base, index, scale, displacement +/// @param base The base register +/// @param index The index register +/// @param scale The scale for the index register value +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_bisd(xed_reg_enum_t base, + xed_reg_enum_t index, + xed_uint_t scale, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= index; + o.u.mem.scale = scale; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + + +/// @ingroup ENCHL +/// memory operand - segment and base only +/// @param seg The segment override register +/// @param base The base register +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gb(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp.displacement = 0; + o.u.mem.disp.displacement_bits = 0; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment, base and displacement only +/// @param seg The segment override register +/// @param base The base register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gbd(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment and displacement only +/// @param seg The segment override register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gd(xed_reg_enum_t seg, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = XED_REG_INVALID; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment, base, index, scale, and displacement +/// @param seg The segment override register +/// @param base The base register +/// @param index The index register +/// @param scale The scale for the index register value +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gbisd(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_reg_enum_t index, + xed_uint_t scale, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= index; + o.u.mem.scale = scale; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} +//@} + +typedef union { + struct { + xed_uint32_t rep :1; + xed_uint32_t repne :1; + xed_uint32_t br_hint_taken :1; + xed_uint32_t br_hint_not_taken :1; + } s; + xed_uint32_t i; +} xed_encoder_prefixes_t; + +#define XED_ENCODER_OPERANDS_MAX 5 /* FIXME */ +typedef struct { + xed_state_t mode; + xed_iclass_enum_t iclass; /*FIXME: use iform instead? or allow either */ + xed_uint32_t effective_operand_width; + + /* the effective_address_width is only requires to be set for + * instructions * with implicit suppressed memops or memops with no + * base or index regs. When base or index regs are present, XED pick + * this up automatically from the register names. + + * FIXME: make effective_address_width required by all encodes for + * unifority. Add to xed_inst[0123]() APIs??? */ + xed_uint32_t effective_address_width; + + xed_encoder_prefixes_t prefixes; + xed_uint32_t noperands; + xed_encoder_operand_t operands[XED_ENCODER_OPERANDS_MAX]; +} xed_encoder_instruction_t; + +/// @name Instruction Properties and prefixes +//@{ +/// @ingroup ENCHL +/// This is to specify effective address size different than the +/// default. For things with base or index regs, XED picks it up from the +/// registers. But for things that have implicit memops, or no base or index +/// reg, we must allow the user to set the address width directly. +/// @param x The #xed_encoder_instruction_t being filled in. +/// @param width_bits The intended effective address size in bits. Values: 16, 32 or 64. +static XED_INLINE void xed_addr(xed_encoder_instruction_t* x, + xed_uint_t width_bits) { + x->effective_address_width = width_bits; +} + + +/// @ingroup ENCHL +/// To add a REP (0xF3) prefix. +/// @param x The #xed_encoder_instruction_t being filled in. +static XED_INLINE void xed_rep(xed_encoder_instruction_t* x) { + x->prefixes.s.rep=1; +} + +/// @ingroup ENCHL +/// To add a REPNE (0xF2) prefix. +/// @param x The #xed_encoder_instruction_t being filled in. +static XED_INLINE void xed_repne(xed_encoder_instruction_t* x) { + x->prefixes.s.repne=1; +} + + + + +/// @ingroup ENCHL +/// convert a #xed_encoder_instruction_t to a #xed_encoder_request_t for +/// encoding +XED_DLL_EXPORT xed_bool_t +xed_convert_to_encoder_request(xed_encoder_request_t* out, + xed_encoder_instruction_t* in); + +//@} + +/// @name Creating instructions from operands +//@{ + +/// @ingroup ENCHL +/// instruction with no operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +static XED_INLINE void xed_inst0( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->noperands = 0; +} + +/// @ingroup ENCHL +/// instruction with one operand +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the operand +static XED_INLINE void xed_inst1( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->noperands = 1; +} + +/// @ingroup ENCHL +/// instruction with two operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +static XED_INLINE void xed_inst2( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->noperands = 2; +} + +/// @ingroup ENCHL +/// instruction with three operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +static XED_INLINE void xed_inst3( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->noperands = 3; +} + + +/// @ingroup ENCHL +/// instruction with four operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +/// @param op3 the 4th operand +static XED_INLINE void xed_inst4( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2, + xed_encoder_operand_t op3) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->operands[3] = op3; + inst->noperands = 4; +} + +/// @ingroup ENCHL +/// instruction with five operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +/// @param op3 the 4th operand +/// @param op4 the 5th operand +static XED_INLINE void xed_inst5( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2, + xed_encoder_operand_t op3, + xed_encoder_operand_t op4) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->operands[3] = op3; + inst->operands[4] = op4; + inst->noperands = 5; +} + + +/// @ingroup ENCHL +/// instruction with an array of operands. The maximum number is +/// XED_ENCODER_OPERANDS_MAX. The array's contents are copied. +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param number_of_operands length of the subsequent array +/// @param operand_array An array of #xed_encoder_operand_t objects +static XED_INLINE void xed_inst( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_uint_t number_of_operands, + const xed_encoder_operand_t* operand_array) { + + xed_uint_t i; + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + xed_assert(number_of_operands < XED_ENCODER_OPERANDS_MAX); + for(i=0;ioperands[i] = operand_array[i]; + } + inst->noperands = number_of_operands; +} + +//@} + +/* + xed_encoder_instruction_t x,y; + + xed_inst2(&x, state, XED_ICLASS_ADD, 32, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_EDX, xed_disp(0x11223344, 32), 32)); + + xed_inst2(&y, state, XED_ICLASS_ADD, 32, + xed_reg(XED_REG_EAX), + xed_mem_gbisd(XED_REG_FS, XED_REG_EAX, XED_REG_ESI,4, + xed_disp(0x11223344, 32), 32)); + + */ + +#endif diff --git a/include/public/xed-flags.h b/include/public/xed-flags.h new file mode 100644 index 0000000..dcafe19 --- /dev/null +++ b/include/public/xed-flags.h @@ -0,0 +1,233 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flags.h +/// + +#ifndef _XED_FLAGS_H_ +# define _XED_FLAGS_H_ + +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-flag-enum.h" +#include "xed-flag-action-enum.h" +#include "xed-gen-table-defs.h" + + +//////////////////////////////////////////////////////////////////////////// +/// @ingroup FLAGS +/// a union of flags bits +union xed_flag_set_s { + xed_uint32_t flat; + struct { + xed_uint32_t cf:1; ///< bit 0 + xed_uint32_t must_be_1:1; + xed_uint32_t pf:1; + xed_uint32_t must_be_0a:1; + + xed_uint32_t af:1; ///< bit 4 + xed_uint32_t must_be_0b:1; + xed_uint32_t zf:1; + xed_uint32_t sf:1; + + xed_uint32_t tf:1; ///< bit 8 + xed_uint32_t _if:1; ///< underscore to avoid token clash + xed_uint32_t df:1; + xed_uint32_t of:1; + + xed_uint32_t iopl:2; ///< A 2-bit field, bits 12-13 + xed_uint32_t nt:1; + xed_uint32_t must_be_0c:1; + + xed_uint32_t rf:1; ///< bit 16 + xed_uint32_t vm:1; + xed_uint32_t ac:1; + xed_uint32_t vif:1; + + xed_uint32_t vip:1; ///< bit 20 + xed_uint32_t id:1; ///< bit 21 + xed_uint32_t must_be_0d:2; ///< bits 22-23 + + xed_uint32_t must_be_0e:4; ///< bits 24-27 + + // fc0,fc1,fc2,fc3 are not really part of rflags but I put them + // here to save space. These bits are only used for x87 + // instructions. + xed_uint32_t fc0:1; ///< x87 flag FC0 (not really part of rflags) + xed_uint32_t fc1:1; ///< x87 flag FC1 (not really part of rflags) + xed_uint32_t fc2:1; ///< x87 flag FC2 (not really part of rflags) + xed_uint32_t fc3:1; ///< x87 flag FC3 (not really part of rflags) + } s; + +}; + +typedef union xed_flag_set_s xed_flag_set_t; +/// @ingroup FLAGS +/// @name Flag-set accessors +//@{ +/// @ingroup FLAGS +/// print the flag set in the supplied buffer +XED_DLL_EXPORT int xed_flag_set_print(const xed_flag_set_t* p, char* buf, int buflen); +/// @ingroup FLAGS +/// returns true if this object has a subset of the flags of the +/// "other" object. +XED_DLL_EXPORT xed_bool_t xed_flag_set_is_subset_of(const xed_flag_set_t* p, + const xed_flag_set_t* other); +//@} + + +//////////////////////////////////////////////////////////////////////////// + +/// @ingroup FLAGS +/// Associated with each flag field there can be one action. +typedef struct xed_flag_enum_s { + xed_flag_enum_t flag; + // there are at most two actions per flag. The 2nd may be invalid. + xed_flag_action_enum_t action; +} xed_flag_action_t; + + + + +/// @ingroup FLAGS +/// @name Lowest-level flag-action accessors +//@{ +/// @ingroup FLAGS +/// get the name of the flag +XED_DLL_EXPORT xed_flag_enum_t +xed_flag_action_get_flag_name(const xed_flag_action_t* p); +/// @ingroup FLAGS +/// return the action +XED_DLL_EXPORT xed_flag_action_enum_t +xed_flag_action_get_action(const xed_flag_action_t* p, unsigned int i); +/// @ingroup FLAGS +/// returns true if the specified action is invalid. Only the 2nd flag might be invalid. +XED_DLL_EXPORT xed_bool_t +xed_flag_action_action_invalid(const xed_flag_action_enum_t a); +/// @ingroup FLAGS +/// print the flag & actions +XED_DLL_EXPORT int xed_flag_action_print(const xed_flag_action_t* p, char* buf, int buflen); +/// @ingroup FLAGS +/// returns true if either action is a read +XED_DLL_EXPORT xed_bool_t +xed_flag_action_read_flag(const xed_flag_action_t* p ); +/// @ingroup FLAGS +/// returns true if either action is a write +XED_DLL_EXPORT xed_bool_t +xed_flag_action_writes_flag(const xed_flag_action_t* p); + +/// @ingroup FLAGS +/// test to see if the specific action is a read +XED_DLL_EXPORT xed_bool_t +xed_flag_action_read_action( xed_flag_action_enum_t a); +/// @ingroup FLAGS +/// test to see if a specific action is a write +XED_DLL_EXPORT xed_bool_t +xed_flag_action_write_action( xed_flag_action_enum_t a); +//@} + +//////////////////////////////////////////////////////////////////////////// + +/// @ingroup FLAGS +/// A collection of #xed_flag_action_t's and unions of read and written flags +typedef struct xed_simple_flag_s +{ + ///number of flag actions associated with this record + xed_uint8_t nflags; + + xed_uint8_t may_write; /* 1/0, only using one bit */ + xed_uint8_t must_write; /* 1/0, only using one bit */ + + ///union of read flags + xed_flag_set_t read; + + /// union of written flags (includes undefined flags); + xed_flag_set_t written; + + /// union of undefined flags; + xed_flag_set_t undefined; + + // index in to the xed_flag_action_table. nflags limits the # of entries. + xed_uint16_t fa_index; + +} xed_simple_flag_t; + +/// @ingroup FLAGS +/// @name Accessing the simple flags (Mid-level access) +//@{ +/// @ingroup FLAGS +/// returns the number of flag-actions +XED_DLL_EXPORT unsigned int +xed_simple_flag_get_nflags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return union of bits for read flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_read_flag_set(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return union of bits for written flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_written_flag_set(const xed_simple_flag_t* p); + + +/// @ingroup FLAGS +/// return union of bits for undefined flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_undefined_flag_set(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// Indicates the flags are only conditionally written. Usally MAY-writes +/// of the flags instructions that are dependent on a REP count. +XED_DLL_EXPORT xed_bool_t xed_simple_flag_get_may_write(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// the flags always written +XED_DLL_EXPORT xed_bool_t xed_simple_flag_get_must_write(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return the specific flag-action. Very detailed low level information +XED_DLL_EXPORT const xed_flag_action_t* +xed_simple_flag_get_flag_action(const xed_simple_flag_t* p, unsigned int i); + +/// @ingroup FLAGS +/// boolean test to see if flags are read, scans the flags +XED_DLL_EXPORT xed_bool_t +xed_simple_flag_reads_flags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// boolean test to see if flags are written, scans the flags +XED_DLL_EXPORT xed_bool_t xed_simple_flag_writes_flags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// print the flags +XED_DLL_EXPORT int xed_simple_flag_print(const xed_simple_flag_t* p, char* buf, int buflen); + +/// @ingroup FLAGS +/// Return the flags as a mask +static XED_INLINE int xed_flag_set_mask(const xed_flag_set_t* p) { + return p->flat; // FIXME: could mask out the X87 flags +} + +//@} + +//////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/include/public/xed-format-options.h b/include/public/xed-format-options.h new file mode 100644 index 0000000..fd7fdd1 --- /dev/null +++ b/include/public/xed-format-options.h @@ -0,0 +1,64 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-format-options.h + + +#ifndef _XED_FORMAT_OPTIONS_H_ +# define _XED_FORMAT_OPTIONS_H_ +#include "xed-types.h" + + +/// @name Formatting options +//@{ + +/// Options for the disasembly formatting functions. Set once during +/// initialization by a calling #xed_format_set_options +/// @ingroup PRINT +typedef struct { + /// by default, XED prints the hex address before any symbolic name for + /// branch targets. If set to zero, then XED will not print the hex + /// address before a valid symbolic name. + unsigned int hex_address_before_symbolic_name; + + /// Simple XML output format for the Intel syntax disassembly. + unsigned int xml_a; + /// Include flags in the XML formatting (must also supply xml_a) + unsigned int xml_f; + + /// omit unit scale "*1" + unsigned int omit_unit_scale; + + /// do not sign extend signed immediates + unsigned int no_sign_extend_signed_immediates; + + /// write-mask-with-curly-brackets, omit k0 + unsigned int write_mask_curly_k0; + + /// lowercase hexidecimal + xed_bool_t lowercase_hex; + +} xed_format_options_t; + +/// Optionally, customize the disassembly formatting options by passing +/// in a #xed_format_options_t structure. +/// @ingroup PRINT +XED_DLL_EXPORT void +xed_format_set_options(xed_format_options_t format_options); +//@} + +#endif diff --git a/include/public/xed-get-time.h b/include/public/xed-get-time.h new file mode 100644 index 0000000..46bf7b9 --- /dev/null +++ b/include/public/xed-get-time.h @@ -0,0 +1,72 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_GET_TIME_H_) +# define _XED_GET_TIME_H_ + +# include "xed-portability.h" +# include "xed-types.h" + +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER > 810 && !defined(_M_IA64) +# include +# endif +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 810 && !defined(_M_IA64) +# if __INTEL_COMPILER < 1000 +# pragma intrinsic(__rdtsc) +# endif +# endif +# if !defined(__INTEL_COMPILER) + /* MSVS8 and later */ +# if defined(_MSC_VER) && _MSC_VER >= 1400 && !defined(_M_IA64) +# include +# pragma intrinsic(__rdtsc) +# endif +# endif + + +///xed_get_time() must be compiled with gnu99 on linux to enable the asm() +///statements. If not gnu99, then xed_get_time() returns zero with gcc. GCC +///has no intrinsic for rdtsc. (The default for XED is to compile with +///-std=c99.) GCC allows __asm__ even under c99! +static XED_INLINE xed_uint64_t xed_get_time(void) { + xed_union64_t ticks; + // __STRICT_ANSI__ comes from the -std=c99 +# if defined(__GNUC__) //&& !defined(__STRICT_ANSI__) +# if defined(__i386__) || defined(i386) || defined(i686) || defined(__x86_64__) + __asm__ volatile ("rdtsc":"=a" (ticks.s.lo32), "=d"(ticks.s.hi32)); +# define FOUND_RDTSC +# endif +# endif +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER>=810 && !defined(_M_IA64) + ticks.u64 = __rdtsc(); +# define FOUND_RDTSC +# endif +# if !defined(__INTEL_COMPILER) +# if !defined(FOUND_RDTSC) && defined(_MSC_VER) && _MSC_VER >= 1400 && \ + !defined(_M_IA64) && !defined(_MANAGED) /* MSVS7, 8 */ + ticks.u64 = __rdtsc(); +# define FOUND_RDTSC +# endif +# endif +# if !defined(FOUND_RDTSC) + ticks.u64 = 0; +# endif + return ticks.u64; +} + +#endif diff --git a/include/public/xed-iform-map.h b/include/public/xed-iform-map.h new file mode 100644 index 0000000..2b94225 --- /dev/null +++ b/include/public/xed-iform-map.h @@ -0,0 +1,117 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iform-map.h +/// + +#if !defined(_XED_IFORM_MAP_H_) +# define _XED_IFORM_MAP_H_ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-iform-enum.h" /* generated */ +#include "xed-iclass-enum.h" /* generated */ +#include "xed-category-enum.h" /* generated */ +#include "xed-extension-enum.h" /* generated */ +#include "xed-isa-set-enum.h" /* generated */ + +/// @ingroup IFORM +/// Statically available information about iforms. +/// Values are returned by #xed_iform_map(). +typedef struct xed_iform_info_s { + xed_uint32_t iclass :16; // xed_iclass_enum_t + xed_uint32_t category :8; //xed_category_enum_t + xed_uint32_t extension :8; //xed_extension_enum_t + + xed_uint32_t isa_set :8;//xed_isa_set_enum_t + /* if nonzero, index in to the disassembly string table */ + xed_uint32_t string_table_idx:16; +} xed_iform_info_t; + + +/// @ingroup IFORM +/// Map the #xed_iform_enum_t to a pointer to a #xed_iform_info_t which +/// indicates the #xed_iclass_enum_t, the #xed_category_enum_t and the +/// #xed_extension_enum_t for the iform. Returns 0 if the iform is not a +/// valid iform. +XED_DLL_EXPORT +const xed_iform_info_t* xed_iform_map(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the maximum number of iforms for a particular iclass. This +/// function returns valid data as soon as global data is +/// initialized. (This function does not require a decoded instruction as +/// input). +XED_DLL_EXPORT +xed_uint32_t xed_iform_max_per_iclass(xed_iclass_enum_t iclass); + +/// @ingroup IFORM +/// Return the first of the iforms for a particular iclass. This function +/// returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +XED_DLL_EXPORT +xed_uint32_t xed_iform_first_per_iclass(xed_iclass_enum_t iclass); + +/// @ingroup IFORM +/// Return the iclass for a given iform. This +/// function returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +static +xed_iclass_enum_t XED_INLINE xed_iform_to_iclass(xed_iform_enum_t iform) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) + return (xed_iclass_enum_t) ii->iclass; + return XED_ICLASS_INVALID; +} + +/// @ingroup IFORM +/// Return the category for a given iform. This +/// function returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +XED_DLL_EXPORT +xed_category_enum_t xed_iform_to_category(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the extension for a given iform. This function returns valid +/// data as soon as global data is initialized. (This function does not +/// require a decoded instruction as input). +XED_DLL_EXPORT +xed_extension_enum_t xed_iform_to_extension(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the isa_set for a given iform. This function returns valid data +/// as soon as global data is initialized. (This function does not require +/// a decoded instruction as input). +XED_DLL_EXPORT +xed_isa_set_enum_t xed_iform_to_isa_set(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return a pointer to a character string of the iclass. This +/// translates the internal disambiguated names to the more ambiguous +/// names that people like to see. This returns the ATT SYSV-syntax name. +XED_DLL_EXPORT +char const* xed_iform_to_iclass_string_att(xed_iform_enum_t iform); + + +/// @ingroup IFORM +/// Return a pointer to a character string of the iclass. This +/// translates the internal disambiguated names to the more ambiguous +/// names that people like to see. This returns the Intel-syntax name. +XED_DLL_EXPORT +char const* xed_iform_to_iclass_string_intel(xed_iform_enum_t iform); + +#endif diff --git a/include/public/xed-ild.h b/include/public/xed-ild.h new file mode 100644 index 0000000..f86511d --- /dev/null +++ b/include/public/xed-ild.h @@ -0,0 +1,61 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-ild.h +/// instruction length decoder + +#if !defined(_XED_ILD_H_) +# define _XED_ILD_H_ +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-types.h" +#include "xed-decoded-inst.h" + +#include "xed-operand-accessors.h" + + +/// This function just does instruction length decoding. +/// It does not return a fully decoded instruction. +/// @param xedd the decoded instruction of type #xed_decoded_inst_t . +/// Mode/state sent in via xedd; See the #xed_state_t . +/// @param itext the pointer to the array of instruction text bytes +/// @param bytes the length of the itext input array. +/// 1 to 15 bytes, anything more is ignored. +/// @return #xed_error_enum_t indiciating success (#XED_ERROR_NONE) or +/// failure. +/// Only two failure codes are valid for this function: +/// #XED_ERROR_BUFFER_TOO_SHORT and #XED_ERROR_GENERAL_ERROR. +/// In general this function cannot tell if the instruction is valid or +/// not. For valid instructions, XED can figure out if enough bytes were +/// provided to decode the instruction. If not enough were provided, +/// XED returns #XED_ERROR_BUFFER_TOO_SHORT. +/// From this function, the #XED_ERROR_GENERAL_ERROR is an indication +/// that XED could not decode the instruction's length because the +/// instruction was so invalid that even its length +/// may across implmentations. +/// +/// @ingroup DEC +XED_DLL_EXPORT xed_error_enum_t +xed_ild_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes); + + +#endif + diff --git a/include/public/xed-immdis.h b/include/public/xed-immdis.h new file mode 100644 index 0000000..c1dc91d --- /dev/null +++ b/include/public/xed-immdis.h @@ -0,0 +1,199 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immdis.h +/// + + + +#ifndef _XED_IMMDIS_H_ +# define _XED_IMMDIS_H_ + +#include "xed-types.h" +#include "xed-common-defs.h" +#include "xed-util.h" + + +//////////////////////////////////////////////////////////////////////////// +// DEFINES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// TYPES +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +// PROTOTYPES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// GLOBALS +//////////////////////////////////////////////////////////////////////////// + +#define XED_MAX_IMMDIS_BYTES 8 + +// A union for speed of zeroing +union xed_immdis_values_t +{ + xed_uint8_t x[XED_MAX_IMMDIS_BYTES];// STORED LITTLE ENDIAN. BYTE 0 is LSB + xed_uint64_t q; +}; + +/// Stores immediates and displacements for the encoder & decoder. +typedef struct xed_immdis_s { + union xed_immdis_values_t value; + unsigned int currently_used_space :4; // current number of assigned bytes + unsigned int max_allocated_space :4; // max allocation, 4 or 8 + xed_bool_t present : 1; + xed_bool_t immediate_is_unsigned : 1; +} xed_immdis_t; + + + + +XED_DLL_EXPORT void xed_immdis_init(xed_immdis_t* p, int max_bytes); + +/// @name Sizes and lengths +//@{ +/// return the number of bytes added +XED_DLL_EXPORT unsigned int xed_immdis_get_bytes(const xed_immdis_t* p) ; + +//@} + +/// @name Accessors for the value of the immediate or displacement +//@{ +XED_DLL_EXPORT xed_int64_t +xed_immdis_get_signed64(const xed_immdis_t* p); + +XED_DLL_EXPORT xed_uint64_t +xed_immdis_get_unsigned64(const xed_immdis_t* p); + +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_zero(const xed_immdis_t* p) ; + +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_one(const xed_immdis_t* p) ; + +/// Access the i'th byte of the immediate +XED_DLL_EXPORT xed_uint8_t xed_immdis_get_byte(const xed_immdis_t* p, unsigned int i) ; +//@} + +/// @name Presence / absence of an immediate or displacement +//@{ +XED_DLL_EXPORT void xed_immdis_set_present(xed_immdis_t* p) ; + +/// True if the object has had a value or individual bytes added to it. +XED_DLL_EXPORT xed_bool_t xed_immdis_is_present(const xed_immdis_t* p) ; +//@} + + +/// @name Initialization and setup +//@{ +XED_DLL_EXPORT void xed_immdis_set_max_len(xed_immdis_t* p, unsigned int mx) ; +XED_DLL_EXPORT void +xed_immdis_zero(xed_immdis_t* p); + +XED_DLL_EXPORT unsigned int xed_immdis_get_max_length(const xed_immdis_t* p) ; + +//@} + +/// @name Signed vs Unsigned +//@{ +/// Return true if signed. +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_unsigned(const xed_immdis_t* p) ; +/// Return true if signed. +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_signed(const xed_immdis_t* p) ; + +/// Set the immediate to be signed; For decoder use only. +XED_DLL_EXPORT void +xed_immdis_set_signed(xed_immdis_t* p) ; +/// Set the immediate to be unsigned; For decoder use only. +XED_DLL_EXPORT void +xed_immdis_set_unsigned( xed_immdis_t* p) ; +//@} + + +/// @name Adding / setting values +//@{ +XED_DLL_EXPORT void +xed_immdis_add_byte(xed_immdis_t* p, xed_uint8_t b); + + +XED_DLL_EXPORT void +xed_immdis_add_byte_array(xed_immdis_t* p, int nb, xed_uint8_t* ba); + +/// Add 1, 2, 4 or 8 bytes depending on the value x and the mask of +/// legal_widths. The default value of legal_widths = 0x5 only stops +/// adding bytes only on 1 or 4 byte quantities - depending on which +/// bytes of x are zero -- as is used for most memory addressing. You +/// can set legal_widths to 0x7 for branches (1, 2 or 4 byte branch +/// displacements). Or if you have an 8B displacement, you can set +/// legal_widths to 0x8. NOTE: add_shortest_width will add up to +/// XED_MAX_IMMDIS_BYTES if the x value requires it. NOTE: 16b memory +/// addressing can have 16b immediates. +XED_DLL_EXPORT void +xed_immdis_add_shortest_width_signed(xed_immdis_t* p, xed_int64_t x, xed_uint8_t legal_widths); + +/// See add_shortest_width_signed() +XED_DLL_EXPORT void +xed_immdis_add_shortest_width_unsigned(xed_immdis_t* p, xed_uint64_t x, xed_uint8_t legal_widths ); + + +/// add an 8 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add8(xed_immdis_t* p, xed_int8_t d); + +/// add a 16 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add16(xed_immdis_t* p, xed_int16_t d); + +/// add a 32 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add32(xed_immdis_t* p, xed_int32_t d); + +/// add a 64 bit value to the byte array. +XED_DLL_EXPORT void +xed_immdis_add64(xed_immdis_t* p, xed_int64_t d); + +//@} + + +/// @name printing / debugging +//@{ + +/// just print the raw bytes in hex with a leading 0x +XED_DLL_EXPORT int xed_immdis_print(const xed_immdis_t* p, char* buf, int buflen); + +/// Print the value as a signed or unsigned number depending on the +/// value of the immediate_is_unsigned variable. +XED_DLL_EXPORT int +xed_immdis_print_signed_or_unsigned(const xed_immdis_t* p, char* buf, int buflen); + +/// print the signed value, appropriate width, with a leading 0x +XED_DLL_EXPORT int +xed_immdis_print_value_signed(const xed_immdis_t* p, char* buf, int buflen); + +/// print the unsigned value, appropriate width, with a leading 0x +XED_DLL_EXPORT int +xed_immdis_print_value_unsigned(const xed_immdis_t* p, char* buf, int buflen); + +#endif + +//@} + + diff --git a/include/public/xed-immed.h b/include/public/xed-immed.h new file mode 100644 index 0000000..d9effc8 --- /dev/null +++ b/include/public/xed-immed.h @@ -0,0 +1,48 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immed.h +/// + +#ifndef _XED_IMMED_H_ +# define _XED_IMMED_H_ + +#include "xed-types.h" +#include "xed-common-defs.h" +#include "xed-util.h" + +XED_DLL_EXPORT xed_int64_t xed_immed_from_bytes(xed_int8_t* bytes, xed_uint_t n); + /* + Convert an array of bytes representing a Little Endian byte ordering + of a number (11 22 33 44 55.. 88), in to a a 64b SIGNED number. That gets + stored in memory in little endian format of course. + + Input 11 22 33 44 55 66 77 88, 8 + Ouptut 0x8877665544332211 (stored in memory as (lsb) 11 22 33 44 55 66 77 88 (msb)) + + Input f0, 1 + Output 0xffff_ffff_ffff_fff0 (stored in memory as f0 ff ff ff ff ff ff ff) + + Input f0 00, 2 + Output 0x0000_0000_0000_00F0 (stored in memory a f0 00 00 00 00 00 00 00) + + Input 03, 1 + Output 0x0000_0000_0000_0030 (stored in memory a 30 00 00 00 00 00 00 00) + */ + + +#endif diff --git a/include/public/xed-init.h b/include/public/xed-init.h new file mode 100644 index 0000000..1ab815c --- /dev/null +++ b/include/public/xed-init.h @@ -0,0 +1,35 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-init.h +/// + + + + +#if !defined(_XED_INIT_H_) +# define _XED_INIT_H_ + + +/// @ingroup INIT +/// This is the call to initialize the XED encode and decode tables. It +/// must be called once before using XED. +void XED_DLL_EXPORT xed_tables_init(void); + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/include/public/xed-inst.h b/include/public/xed-inst.h new file mode 100644 index 0000000..4033e95 --- /dev/null +++ b/include/public/xed-inst.h @@ -0,0 +1,368 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-inst.h + + +#if !defined(_XED_INST_H_) +# define _XED_INST_H_ + +#include "xed-util.h" +#include "xed-portability.h" +#include "xed-category-enum.h" // generated +#include "xed-extension-enum.h" //generated +#include "xed-iclass-enum.h" //generated +#include "xed-operand-enum.h" // generated +#include "xed-operand-visibility-enum.h" //generated +#include "xed-operand-action-enum.h" // generated +#include "xed-operand-convert-enum.h" // generated +#include "xed-operand-type-enum.h" // generated +#include "xed-nonterminal-enum.h" // a generated file +#include "xed-operand-width-enum.h" // a generated file +#include "xed-operand-element-xtype-enum.h" // a generated file +#include "xed-reg-enum.h" // a generated file +#include "xed-attribute-enum.h" // a generated file +#include "xed-exception-enum.h" // a generated file +#include "xed-iform-enum.h" // a generated file +#include "xed-iform-map.h" +#include "xed-attributes.h" + +struct xed_decoded_inst_s; //fwd-decl + +typedef void (*xed_operand_extractor_fn_t)(struct xed_decoded_inst_s* xds); + + +/// @ingroup DEC +/// Constant information about an individual generic operand, like an +///operand template, describing the operand properties. See @ref DEC for +///API information. +typedef struct xed_operand_s +{ + xed_uint8_t _name; // xed_operand_enum_t + + // implicit, explicit, suppressed + xed_uint8_t _operand_visibility; // xed_operand_visibility_enum_t + xed_uint8_t _rw; // read or written // xed_operand_action_enum_t + + // width code, could be invalid (then use register name) + xed_uint8_t _oc2; // xed_operand_width_enum_t + + // IMM, IMM_CONST, NT_LOOKUP_FN, REG, ERROR + xed_uint8_t _type; //xed_operand_type_enum_t + xed_uint8_t _xtype; // xed data type: u32, f32, etc. //xed_operand_element_xtype_enum_t + xed_uint8_t _cvt_idx; // decoration index + xed_uint8_t _nt; + union { + xed_uint32_t _imm; // value for some constant immmed + xed_nonterminal_enum_t _nt; // for nt_lookup_fn's + xed_reg_enum_t _reg; // register name + } _u; +} xed_operand_t; + +/// @name xed_inst_t Template Operands Access +//@{ +/// @ingroup DEC +static XED_INLINE xed_operand_enum_t +xed_operand_name(const xed_operand_t* p) { + return (xed_operand_enum_t)p->_name; +} + + +/// @ingroup DEC +static XED_INLINE xed_operand_visibility_enum_t +xed_operand_operand_visibility( const xed_operand_t* p) { + return (xed_operand_visibility_enum_t)(p->_operand_visibility); +} + + +/// @ingroup DEC +/// @return The #xed_operand_type_enum_t of the operand template. +/// This is probably not what you want. +static XED_INLINE xed_operand_type_enum_t +xed_operand_type(const xed_operand_t* p) { + return (xed_operand_type_enum_t)p->_type; +} + +/// @ingroup DEC +/// @return The #xed_operand_element_xtype_enum_t of the operand template. +/// This is probably not what you want. +static XED_INLINE xed_operand_element_xtype_enum_t +xed_operand_xtype(const xed_operand_t* p) { + return (xed_operand_element_xtype_enum_t)p->_xtype; +} + + +/// @ingroup DEC +static XED_INLINE xed_operand_width_enum_t +xed_operand_width(const xed_operand_t* p) { + return (xed_operand_width_enum_t)p->_oc2; +} + +/// @ingroup DEC +/// @param p an operand template, #xed_operand_t. +/// @param eosz effective operand size of the instruction, 1 | 2 | 3 for +/// 16 | 32 | 64 bits respectively. 0 is invalid. +/// @return the actual width of operand in bits. +/// See xed_decoded_inst_operand_length_bits() for a more general solution. +XED_DLL_EXPORT xed_uint32_t +xed_operand_width_bits(const xed_operand_t* p, + const xed_uint32_t eosz); + +/// @ingroup DEC +static XED_INLINE xed_nonterminal_enum_t +xed_operand_nonterminal_name(const xed_operand_t* p) { + if (p->_nt) + return p->_u._nt; + return XED_NONTERMINAL_INVALID; +} + +/// @ingroup DEC +/// Careful with this one -- use #xed_decoded_inst_get_reg()! This one is +/// probably not what you think it is. It is only used for hard-coded +/// registers implicit in the instruction encoding. Most likely you want to +/// get the #xed_operand_enum_t and then look up the instruction using +/// #xed_decoded_inst_get_reg(). The hard-coded registers are also available +/// that way. +/// @param p an operand template, #xed_operand_t. +/// @return the implicit or suppressed registers, type #xed_reg_enum_t +static XED_INLINE xed_reg_enum_t xed_operand_reg(const xed_operand_t* p) { + if (xed_operand_type(p) == XED_OPERAND_TYPE_REG) + return p->_u._reg; + return XED_REG_INVALID; +} + + + +/// @ingroup DEC +/// Careful with this one; See #xed_operand_is_register(). +/// @param p an operand template, #xed_operand_t. +/// @return 1 if the operand template represents are register-type +/// operand. +/// +/// Related functions: +/// Use #xed_decoded_inst_get_reg() to get the decoded name of /// the +/// register, #xed_reg_enum_t. Use #xed_operand_is_register() to test +/// #xed_operand_enum_t names. +static XED_INLINE xed_uint_t +xed_operand_template_is_register(const xed_operand_t* p) { + return p->_nt || p->_type == XED_OPERAND_TYPE_REG; +} + +/// @ingroup DEC +/// @param p an operand template, #xed_operand_t. +/// These operands represent branch displacements, memory displacements and +/// various immediates +static XED_INLINE xed_uint32_t xed_operand_imm(const xed_operand_t* p) { + if (xed_operand_type(p) == XED_OPERAND_TYPE_IMM_CONST) + return p->_u._imm; + return 0; +} + +/// @ingroup DEC +/// Print the operand p into the buffer buf, of length buflen. +/// @param p an operand template, #xed_operand_t. +/// @param buf buffer that gets filled in +/// @param buflen maximum buffer length +XED_DLL_EXPORT void +xed_operand_print(const xed_operand_t* p, char* buf, int buflen); +//@} + +/// @name xed_inst_t Template Operand Enum Name Classification +//@{ +/// @ingroup DEC +/// Tests the enum for inclusion in XED_OPERAND_REG0 through XED_OPERAND_REG15. +/// @param name the operand name, type #xed_operand_enum_t +/// @return 1 if the operand name is REG0...REG15, 0 otherwise. +/// +///Note there are other registers for memory addressing; See +/// #xed_operand_is_memory_addressing_register . +static XED_INLINE xed_uint_t xed_operand_is_register(xed_operand_enum_t name) { + return name >= XED_OPERAND_REG0 && name <= XED_OPERAND_REG8; +} +/// @ingroup DEC +/// Tests the enum for inclusion in XED_OPERAND_{BASE0,BASE1,INDEX,SEG0,SEG1} +/// @param name the operand name, type #xed_operand_enum_t +/// @return 1 if the operand name is for a memory addressing register operand, 0 +/// otherwise. See also #xed_operand_is_register . +static XED_INLINE xed_uint_t +xed_operand_is_memory_addressing_register(xed_operand_enum_t name) { + return ( name == XED_OPERAND_BASE0 || + name == XED_OPERAND_INDEX || + name == XED_OPERAND_SEG0 || + name == XED_OPERAND_BASE1 || + name == XED_OPERAND_SEG1 ); +} + +//@} + +/// @name xed_inst_t Template Operand Read/Written +//@{ +/// @ingroup DEC +/// DEPRECATED: Returns the raw R/W action. There are many cases for conditional reads +/// and writes. See #xed_decoded_inst_operand_action(). +static XED_INLINE xed_operand_action_enum_t +xed_operand_rw(const xed_operand_t* p) { + return (xed_operand_action_enum_t)p->_rw; +} + +/// @ingroup DEC +/// If the operand is read, including conditional reads +XED_DLL_EXPORT xed_uint_t xed_operand_read(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is read-only, including conditional reads +XED_DLL_EXPORT xed_uint_t xed_operand_read_only(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is written, including conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_written(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is written-only, including conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_written_only(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is read-and-written, conditional reads and conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_read_and_written(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand has a conditional read (may also write) +XED_DLL_EXPORT xed_uint_t xed_operand_conditional_read(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand has a conditional write (may also read) +XED_DLL_EXPORT xed_uint_t xed_operand_conditional_write(const xed_operand_t* p); +//@} + + +/// @ingroup DEC +/// constant information about a decoded instruction form, including +/// the pointer to the constant operand properties #xed_operand_t for this +/// instruction form. +typedef struct xed_inst_s { + + + // rflags info -- index in to the 2 tables of flags information. + // If _flag_complex is true, then the data are in the + // xed_flags_complex_table[]. Otherwise, the data are in the + // xed_flags_simple_table[]. + + //xed_instruction_fixed_bit_confirmer_fn_t _confirmer; + + // number of operands in the operands array + xed_uint8_t _noperands; + xed_uint8_t _cpl; // the nominal CPL for the instruction. + xed_uint8_t _flag_complex; /* 1/0 valued, bool type */ + xed_uint8_t _exceptions; //xed_exception_enum_t + + xed_uint16_t _flag_info_index; + + xed_uint16_t _iform_enum; //xed_iform_enum_t + // index into the xed_operand[] array of xed_operand_t structures + xed_uint16_t _operand_base; + // index to table of xed_attributes_t structures + xed_uint16_t _attributes; + +} xed_inst_t; + +/// @name xed_inst_t Template Instruction Information +//@{ +/// @ingroup DEC +/// xed_inst_cpl() is DEPRECATED. Please use +/// "xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)" +/// instead. +///Return the current privilege level (CPL) required for execution, 0 or +///3. If the value is zero, then the instruction can only execute in ring 0. +XED_DLL_EXPORT unsigned int xed_inst_cpl(const xed_inst_t* p) ; + + +//These next few are not doxygen commented because I want people to use the +//higher level interface in xed-decoded-inst.h. +static XED_INLINE xed_iform_enum_t xed_inst_iform_enum(const xed_inst_t* p) { + return (xed_iform_enum_t)p->_iform_enum; +} + +static XED_INLINE xed_iclass_enum_t xed_inst_iclass(const xed_inst_t* p) { + return xed_iform_to_iclass(xed_inst_iform_enum(p)); +} + +static XED_INLINE xed_category_enum_t xed_inst_category(const xed_inst_t* p) { + return xed_iform_to_category(xed_inst_iform_enum(p)); +} + +static XED_INLINE xed_extension_enum_t xed_inst_extension(const xed_inst_t* p) { + return xed_iform_to_extension(xed_inst_iform_enum(p)); +} +static XED_INLINE xed_isa_set_enum_t xed_inst_isa_set(const xed_inst_t* p) { + return xed_iform_to_isa_set(xed_inst_iform_enum(p)); +} + + + +///@ingroup DEC +/// Number of instruction operands +static XED_INLINE unsigned int xed_inst_noperands(const xed_inst_t* p) { + return p->_noperands; +} + +///@ingroup DEC +/// Obtain a pointer to an individual operand +XED_DLL_EXPORT const xed_operand_t* +xed_inst_operand(const xed_inst_t* p, unsigned int i); + + + +XED_DLL_EXPORT xed_uint32_t xed_inst_flag_info_index(const xed_inst_t* p); + +//@} + +/// @name xed_inst_t Attribute access +//@{ +/// @ingroup DEC +/// Scan for the attribute attr and return 1 if it is found, 0 otherwise. +XED_DLL_EXPORT xed_uint32_t +xed_inst_get_attribute(const xed_inst_t* p, + xed_attribute_enum_t attr); + +/// @ingroup DEC +/// Return the attributes bit vector +XED_DLL_EXPORT xed_attributes_t +xed_inst_get_attributes(const xed_inst_t* p); + + +/// @ingroup DEC +/// Return the maximum number of defined attributes, independent of any +/// instruction. +XED_DLL_EXPORT unsigned int xed_attribute_max(void); + +/// @ingroup DEC +/// Return the i'th global attribute in a linear sequence, independent of +/// any instruction. This is used for scanning and printing all attributes. +XED_DLL_EXPORT xed_attribute_enum_t xed_attribute(unsigned int i); + +//@} + +/// @name Exceptions +//@{ +/// @ingroup DEC +/// Return #xed_exception_enum_t if present for the specified instruction. +/// This is currently only used for SSE and AVX instructions. +static XED_INLINE +xed_exception_enum_t xed_inst_exception(const xed_inst_t* p) { + return (xed_exception_enum_t)p->_exceptions; +} + +//@} +/// @ingroup DEC +/// Return the base of instruction table. +XED_DLL_EXPORT const xed_inst_t* xed_inst_table_base(void); + +#endif diff --git a/include/public/xed-interface.h b/include/public/xed-interface.h new file mode 100644 index 0000000..4efdc5b --- /dev/null +++ b/include/public/xed-interface.h @@ -0,0 +1,81 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/* +/// @file xed-interface.h +/// +*/ + + + +#if !defined(_XED_INTERFACE_H_) +# define _XED_INTERFACE_H_ + +#if defined(_WIN32) && defined(_MANAGED) +#pragma unmanaged +#endif + +#include "xed-build-defines.h" /* generated */ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-operand-enum.h" + +#include "xed-init.h" +#include "xed-decode.h" +#include "xed-ild.h" + +#include "xed-state.h" /* dstate, legacy */ +#include "xed-syntax-enum.h" +#include "xed-reg-class-enum.h" /* generated */ +#include "xed-reg-class.h" + +#if defined(XED_ENCODER) +# include "xed-encode.h" +# include "xed-encoder-hl.h" +#endif +#include "xed-util.h" +#include "xed-operand-action.h" + +#include "xed-version.h" +#include "xed-decoded-inst.h" +#include "xed-decoded-inst-api.h" +#include "xed-inst.h" +#include "xed-iclass-enum.h" /* generated */ +#include "xed-category-enum.h" /* generated */ +#include "xed-extension-enum.h" /* generated */ +#include "xed-attribute-enum.h" /* generated */ +#include "xed-exception-enum.h" /* generated */ +#include "xed-operand-element-type-enum.h" /* generated */ +#include "xed-operand-element-xtype-enum.h" /* generated */ + +#include "xed-disas.h" // callbacks for disassembly +#include "xed-format-options.h" /* options for disassembly */ + +#include "xed-iform-enum.h" /* generated */ +/* indicates the first and last index of each iform, for building tables */ +#include "xed-iformfl-enum.h" /* generated */ +/* mapping iforms to iclass/category/extension */ +#include "xed-iform-map.h" +#include "xed-rep-prefix.h" + + +#include "xed-agen.h" +#include "xed-cpuid-rec.h" + + +#endif diff --git a/include/public/xed-isa-set.h b/include/public/xed-isa-set.h new file mode 100644 index 0000000..1357312 --- /dev/null +++ b/include/public/xed-isa-set.h @@ -0,0 +1,37 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-isa-set.h + + +#if !defined(_XED_ISA_SET_H_) +# define _XED_ISA_SET_H_ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-isa-set-enum.h" /* generated */ +#include "xed-chip-enum.h" /* generated */ + +/// @ingroup ISASET +/// return 1 if the isa_set is part included in the specified chip, 0 +/// otherwise. +XED_DLL_EXPORT xed_bool_t +xed_isa_set_is_valid_for_chip(xed_isa_set_enum_t isa_set, + xed_chip_enum_t chip); + + +#endif diff --git a/include/public/xed-operand-action.h b/include/public/xed-operand-action.h new file mode 100644 index 0000000..d04e856 --- /dev/null +++ b/include/public/xed-operand-action.h @@ -0,0 +1,36 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-action.h +/// + +#if !defined(_XED_OPERAND_ACTION_H_) +# define _XED_OPERAND_ACTION_H_ + +#include "xed-types.h" +#include "xed-operand-action-enum.h" + +XED_DLL_EXPORT xed_uint_t xed_operand_action_read(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_read_only(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_written(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_written_only(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_read_and_written(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_conditional_read(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_conditional_write(const xed_operand_action_enum_t rw); + +#endif + diff --git a/include/public/xed-operand-values-interface.h b/include/public/xed-operand-values-interface.h new file mode 100644 index 0000000..3c21268 --- /dev/null +++ b/include/public/xed-operand-values-interface.h @@ -0,0 +1,513 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-values-interface.h +/// + +#if !defined(_XED_OPERAND_VALUES_INTERFACE_H_) +# define _XED_OPERAND_VALUES_INTERFACE_H_ + +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-types.h" +#include "xed-state.h" // a generated file +#include "xed-operand-enum.h" // a generated file +#include "xed-decoded-inst.h" +#include "xed-reg-enum.h" // generated +#include "xed-iclass-enum.h" // generated +/// @name Initialization +//@{ +/// @ingroup OPERANDS +/// Initializes operand structure +XED_DLL_EXPORT void xed_operand_values_init(xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Initializes the operand storage and sets mode values. +XED_DLL_EXPORT void xed_operand_values_init_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate); + +/// @ingroup OPERANDS +/// Set the mode values +XED_DLL_EXPORT void +xed_operand_values_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate); + +/// @ingroup OPERANDS +/// Initializes dst operand structure but preserves the existing +/// MODE/SMODE values from the src operand structure. +XED_DLL_EXPORT void +xed_operand_values_init_keep_mode( xed_operand_values_t* dst, + const xed_operand_values_t* src ); +//@} + +/////////////////////////////////////////////////////////// +/// @name String output +//@{ +/// @ingroup OPERANDS +/// Dump all the information about the operands to buf. +XED_DLL_EXPORT void +xed_operand_values_dump(const xed_operand_values_t* ov, + char* buf, + int buflen); +/// @ingroup OPERANDS +/// More tersely dump all the information about the operands to buf. +XED_DLL_EXPORT void +xed_operand_values_print_short(const xed_operand_values_t* ov, + char* buf, + int buflen); +//@} + +/// @name REP/REPNE Prefixes +//@{ +/// @ingroup OPERANDS +/// True if the instruction has a real REP prefix. This returns false if +/// there is no F2/F3 prefix or the F2/F3 prefix is used to refine the +/// opcode as in some SSE operations. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_real_rep(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if the instruction as a F3 REP prefix (used for opcode refining, +/// for rep for string operations, or ignored). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_rep_prefix(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if the instruction as a F2 REP prefix (used for opcode refining, +/// for rep for string operations, or ignored). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_repne_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// DO NOT USE - DEPRECATED. The correct way to do remove a rep prefix is by changing the iclass +XED_DLL_EXPORT void xed_operand_values_clear_rep(xed_operand_values_t* p); + +//@} + +/// @name Atomic / Locked operations +//@{ +/// @ingroup OPERANDS +/// Returns true if the memory operation has atomic read-modify-write +/// semantics. An XCHG accessing memory is atomic with or without a +/// LOCK prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_atomic(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the memory operation has a valid lock prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_lock_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction could be re-encoded to have a lock +/// prefix but does not have one currently. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_lockable(const xed_operand_values_t* p); +//@} + + +/// @ingroup OPERANDS +/// Indicates if the default segment is being used. +/// @param[in] p the pointer to the #xed_operand_values_t structure. +/// @param[in] i 0 or 1, indicating which memory operation. +/// @return true if the memory operation is using the default segment for +/// the associated addressing mode base register. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_using_default_segment(const xed_operand_values_t* p, + unsigned int i); + + + +/// @ingroup OPERANDS +/// Returns The effective operand width in bits: 16/32/64. Note this is not +/// the same as the width of the operand which can vary! For 8 bit +/// operations, the effective operand width is the machine mode's default +/// width. If you also want to identify byte operations use the higher +/// level function #xed_decoded_inst_get_operand_width() . +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_effective_operand_width(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns The effective address width in bits: 16/32/64. +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_effective_address_width(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns The stack address width in bits: 16/32/64. +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_stack_address_width(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// True if there is a memory displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_memory_displacement(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if there is a branch displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_branch_displacement(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if there is a memory or branch displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_displacement(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// Deprecated. Compatibility function for XED0. See has_memory_displacement(). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_displacement_for_memop(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return true if there is an immediate operand +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_immediate(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// ALIAS for has_displacement(). +/// Deprecated. See has_memory_displacement() and +/// has_branch_displacement(). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_disp(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This indicates the presence of a 67 prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_address_size_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This does not include the cases when the 66 prefix is used an +/// opcode-refining prefix for multibyte opcodes. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_operand_size_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This includes any 66 prefix that shows up even if it is ignored. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_66_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This instruction has a REX prefix with the W bit set. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_rexw_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_segment_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return the segment prefix, if any, as a #xed_reg_enum_t value. +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_segment_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_is_prefetch(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_long_mode(const xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_real_mode(const xed_operand_values_t* p); + +/// @name Memory Addressing +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_accesses_memory(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_number_of_memory_operands(const xed_operand_values_t* p); + +/// return bytes +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_get_memory_operand_length(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_base_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_index_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_seg_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_get_scale(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction access memory but without using a MODRM +/// byte limiting its addressing modes. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_memop_without_modrm(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns true if the instruction has a MODRM byte. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_modrm_byte(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction has a SIB byte. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_sib_byte(const xed_operand_values_t* p); +//@} + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_branch_not_taken_hint(const xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_branch_taken_hint(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_is_nop(const xed_operand_values_t* p); + + +/// @name Immediates +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_immediate_int64(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint64_t +xed_operand_values_get_immediate_uint64(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return true if the first immediate (IMM0) is signed +XED_DLL_EXPORT xed_uint_t +xed_operand_values_get_immediate_is_signed(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// Return the i'th byte of the immediate +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_immediate_byte(const xed_operand_values_t* p, + unsigned int i); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_second_immediate(const xed_operand_values_t* p); +//@} + +/// @name Memory Displacements +//@{ +/// @ingroup OPERANDS +/// Return the memory displacement width in BYTES +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Return the memory displacement width in BITS +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits( + const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return the raw memory displacement width in BITS(ignores scaling) +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits_raw( + const xed_operand_values_t* p); + +/// Returns the potentially scaled value of the memory +/// displacement. Certain AVX512 memory displacements are scaled before +/// they are used. @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_memory_displacement_int64(const xed_operand_values_t* p); + +/// Returns the unscaled (raw) memory displacement. Certain AVX512 memory +/// displacements are scaled before they are used. @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_memory_displacement_int64_raw(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_memory_displacement_byte(const xed_operand_values_t* p, + unsigned int i); +//@} + +/// @name Branch Displacements +//@{ +/// @ingroup OPERANDS +/// Return the branch displacement width in bytes +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_branch_displacement_length(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Return the branch displacement width in bits +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_branch_displacement_length_bits( + const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_int32_t +xed_operand_values_get_branch_displacement_int32(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_branch_displacement_byte(const xed_operand_values_t* p, + unsigned int i); +//@} + + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_iclass_enum_t +xed_operand_values_get_iclass(const xed_operand_values_t* p); + +//////////////////////////////////////////////////// +// ENCODE API +//////////////////////////////////////////////////// +/// @name Encoding +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_immediate(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_branch_displacement(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_memory_displacement(xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_lock(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_segment_override(xed_operand_values_t* p); + + +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_set_iclass(xed_operand_values_t* p, + xed_iclass_enum_t iclass); + +/// @ingroup OPERANDS +/// width is bits 8, 16, 32, 64 +XED_DLL_EXPORT void +xed_operand_values_set_effective_operand_width(xed_operand_values_t* p, + unsigned int width); + +/// @ingroup OPERANDS +/// width is bits 16, 32, 64 +XED_DLL_EXPORT void +xed_operand_values_set_effective_address_width(xed_operand_values_t* p, + unsigned int width); +/// takes bytes, not bits, as an argument +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_set_memory_operand_length(xed_operand_values_t* p, + unsigned int memop_length); + + +/// @ingroup OPERANDS +/// Set the memory displacement using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_memory_displacement(xed_operand_values_t* p, + xed_int64_t x, unsigned int len); +/// @ingroup OPERANDS +/// Set the memory displacement using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_memory_displacement_bits(xed_operand_values_t* p, + xed_int64_t x, + unsigned int len_bits); + +/// @ingroup OPERANDS +/// Indicate that we have a relative branch. +XED_DLL_EXPORT void xed_operand_values_set_relbr(xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Set the branch displacement using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_branch_displacement(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len); +/// @ingroup OPERANDS +/// Set the branch displacement using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_branch_displacement_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len_bits); + +/// @ingroup OPERANDS +/// Set the signed immediate using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_immediate_signed(xed_operand_values_t* p, + xed_int32_t x, + unsigned int bytes); +/// @ingroup OPERANDS +/// Set the signed immediate using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_immediate_signed_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int bits); + + +/// @ingroup OPERANDS +/// Set the unsigned immediate using a BYTE length. +XED_DLL_EXPORT void +xed_operand_values_set_immediate_unsigned(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bytes); +/// @ingroup OPERANDS +/// Set the unsigned immediate using a BIT length. +XED_DLL_EXPORT void +xed_operand_values_set_immediate_unsigned_bits(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bits); + + + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_base_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_base); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_seg_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_seg); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_index_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_index); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_scale(xed_operand_values_t* p, + xed_uint_t memop_idx, + xed_uint_t new_scale); + + +/// @ingroup OPERANDS +/// Set the operand storage field entry named 'operand_name' to the +/// register value specified by 'reg_name'. +XED_DLL_EXPORT void +xed_operand_values_set_operand_reg(xed_operand_values_t* p, + xed_operand_enum_t operand_name, + xed_reg_enum_t reg_name); + +//@} +#endif + diff --git a/include/public/xed-portability.h b/include/public/xed-portability.h new file mode 100644 index 0000000..e13b121 --- /dev/null +++ b/include/public/xed-portability.h @@ -0,0 +1,186 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-portability.h +/// + +#ifndef _XED_PORTABILITY_H_ +# define _XED_PORTABILITY_H_ +# include "xed-common-hdrs.h" +# include "xed-types.h" + + +#define XED_STATIC_CAST(x,y) ((x) (y)) +#define XED_REINTERPRET_CAST(x,y) ((x) (y)) +#define XED_CAST(x,y) ((x) (y)) + + + +XED_DLL_EXPORT xed_uint_t xed_strlen(const char* s); +XED_DLL_EXPORT void xed_strcat(char* dst, const char* src); +XED_DLL_EXPORT void xed_strcpy(char* dst, const char* src); + +/// returns the number of bytes remaining for the next use of +/// #xed_strncpy() or #xed_strncat() . +XED_DLL_EXPORT int xed_strncpy(char* dst, const char* src, int len); + +/// returns the number of bytes remaining for the next use of +/// #xed_strncpy() or #xed_strncat() . +XED_DLL_EXPORT int xed_strncat(char* dst, const char* src, int len); + +#if defined(__INTEL_COMPILER) +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER >= 1400 +# define XED_MSVC8_OR_LATER 1 +# endif +# endif +#endif + +/* recognize VC98 */ +#if !defined(__INTEL_COMPILER) +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER == 1200 +# define XED_MSVC6 1 +# endif +# endif +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER == 1310 +# define XED_MSVC7 1 +# endif +# endif +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER >= 1400 +# define XED_MSVC8_OR_LATER 1 +# endif +# if _MSC_VER == 1400 +# define XED_MSVC8 1 +# endif +# if _MSC_VER == 1500 +# define XED_MSVC9 1 +# endif +# if _MSC_VER >= 1500 +# define XED_MSVC9_OR_LATER 1 +# endif +# if _MSC_VER == 1600 +# define XED_MSVC10 1 +# endif +# if _MSC_VER >= 1600 +# define XED_MSVC10_OR_LATER 1 +# endif +# endif +#endif + +/* I've had compatibilty problems here so I'm using a trivial indirection */ +#if defined(__GNUC__) +# if defined(__CYGWIN__) + /* cygwin's gcc 3.4.4 on windows complains */ +# define XED_FMT_X "%lx" +# define XED_FMT_08X "%08lx" +# define XED_FMT_D "%ld" +# define XED_FMT_U "%lu" +# define XED_FMT_9U "%9lu" +# else +# define XED_FMT_X "%x" +# define XED_FMT_08X "%08x" +# define XED_FMT_D "%d" +# define XED_FMT_U "%u" +# define XED_FMT_9U "%9u" +# endif +#else +# define XED_FMT_X "%x" +# define XED_FMT_08X "%08x" +# define XED_FMT_D "%d" +# define XED_FMT_U "%u" +# define XED_FMT_9U "%9u" +#endif + +// Go write portable code... Sigh +#if defined(__APPLE__) // clang *32b* and 64b +# define XED_FMT_SIZET "%lu" +#elif defined(__LP64__) // 64b gcc, icc +# define XED_FMT_SIZET "%lu" +#elif defined (_M_X64) // 64b msvs, ICL + // MSVS/x64 accepts %llu or %lu, icl/x64 does not) +# define XED_FMT_SIZET "%llu" +#else // 32b everything else +# define XED_FMT_SIZET "%u" +#endif + +#if defined(__GNUC__) && defined(__LP64__) && !defined(__APPLE__) +# define XED_FMT_LX "%lx" +# define XED_FMT_LX_UPPER "%lX" +# define XED_FMT_LU "%lu" +# define XED_FMT_LU12 "%12lu" +# define XED_FMT_LD "%ld" +# define XED_FMT_LX16 "%016lx" +# define XED_FMT_LX16_UPPER "%016lX" +#else +# define XED_FMT_LX "%llx" +# define XED_FMT_LX_UPPER "%llX" +# define XED_FMT_LU "%llu" +# define XED_FMT_LU12 "%12llu" +# define XED_FMT_LD "%lld" +# define XED_FMT_LX16 "%016llx" +# define XED_FMT_LX16_UPPER "%016llX" +#endif + +#if defined(__LP64__) || defined (_M_X64) +# define XED_64B 1 +#endif + +#if defined(_M_IA64) +# define XED_IPF +# define XED_FMT_SIZET "%lu" +#endif + +#if defined(__GNUC__) + /* gcc4.2.x has a bug with c99/gnu99 inlining */ +# if __GNUC__ == 4 && __GNUC_MINOR__ == 2 +# define XED_INLINE inline +# else +# if __GNUC__ == 2 +# define XED_INLINE +# else +# define XED_INLINE inline +# endif +# endif +# define XED_NORETURN __attribute__ ((noreturn)) +# if __GNUC__ == 2 +# define XED_NOINLINE +# else +# define XED_NOINLINE __attribute__ ((noinline)) +# endif +#else +# define XED_INLINE __inline +# if defined(XED_MSVC6) +# define XED_NOINLINE +# else +# define XED_NOINLINE __declspec(noinline) +# endif +# define XED_NORETURN __declspec(noreturn) +#endif + + + +#define XED_MAX(a, b) (((a) > (b)) ? (a):(b)) +#define XED_MIN(a, b) (((a) < (b)) ? (a):(b)) + + + + +#endif // _XED_PORTABILITY_H_ + diff --git a/include/public/xed-print-info.h b/include/public/xed-print-info.h new file mode 100644 index 0000000..5dbf0b6 --- /dev/null +++ b/include/public/xed-print-info.h @@ -0,0 +1,98 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_PRINT_INFO_H_) +# define _XED_PRINT_INFO_H_ + +#include "xed-types.h" +#include "xed-decoded-inst.h" +#include "xed-disas.h" // callback function type +#include "xed-syntax-enum.h" +#include "xed-format-options.h" + +/// @ingroup PRINT +/// This contains the information used by the various disassembly printers. +/// Call xed_init_print_info to initialize the fields. Then change the +/// required and optional fields when required. +typedef struct { + + ///////////////////////////////////////// + // REQUIRED FIELDS - users should set these + ///////////////////////////////////////// + + /// the decoded instruction to print + const xed_decoded_inst_t* p; + + /// pointer to the output buffer + char* buf; + + /// length of the output buffer. (bytes) Must be > 25 to start. + int blen; + + ///////////////////////////////////////// + // OPTIONAL FIELDS - user can set these + ///////////////////////////////////////// + + /// program counter location. Must be zero if not used. (Sometimes + /// instructions are disassembled in a temporary buffer at a different + /// location than where they may or will exist in memory). + xed_uint64_t runtime_address; + + /// disassembly_callback MUST be set to zero if not used! If zero, the + /// default disassembly callback is used (if one has been registered). + xed_disassembly_callback_fn_t disassembly_callback; + + /// passed to disassembly callback. Can be zero if not used. + void* context; + + /// default is Intel-syntax (dest on left) + xed_syntax_enum_t syntax; + + /// 1=indicated the format_options field is valid, 0=use default + /// formating options from xed_format_set_options(). + int format_options_valid; + xed_format_options_t format_options; + + + ///////////////////////////////////////// + // NONPUBLIC FIELDS - Users should not use these! + ///////////////////////////////////////// + + /// internal, do not use + xed_bool_t emitted; + + /// internal, do not use + unsigned int operand_indx; + + /// internal, do not use + unsigned int skip_operand; + + /// internal, do not use + xed_reg_enum_t extra_index_operand; // for MPX + + /// internal, do not use + xed_bool_t implicit; + +} xed_print_info_t; + +// This function initializes the #xed_print_info_t structure. +// You must still set the required fields of that structure. +/// @ingroup PRINT +XED_DLL_EXPORT void xed_init_print_info(xed_print_info_t* pi); + +#endif diff --git a/include/public/xed-reg-class.h b/include/public/xed-reg-class.h new file mode 100644 index 0000000..aa37ec2 --- /dev/null +++ b/include/public/xed-reg-class.h @@ -0,0 +1,62 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-reg-class.h +/// + +#ifndef _XED_REG_CLASS_H_ +# define _XED_REG_CLASS_H_ + +#include "xed-types.h" +#include "xed-reg-enum.h" // a generated file +#include "xed-reg-class-enum.h" // a generated file + +/// Returns the register class of the given input register. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_class_enum_t xed_reg_class(xed_reg_enum_t r); + +/// Returns the specific width GPR reg class (like XED_REG_CLASS_GPR32 or +/// XED_REG_CLASS_GPR64) +/// for a given GPR register. Or XED_REG_INVALID if not a GPR. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_class_enum_t xed_gpr_reg_class(xed_reg_enum_t r); + +/// Returns the largest enclosing register for any kind of register; This +/// is mostly useful for GPRs. (64b mode assumed) +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_enum_t +xed_get_largest_enclosing_register(xed_reg_enum_t r); + +/// Returns the largest enclosing register for any kind of register; This +/// is mostly useful for GPRs in 32b mode. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_enum_t +xed_get_largest_enclosing_register32(xed_reg_enum_t r); + +/// Returns the width, in bits, of the named register. 32b mode +///@ingroup REGINTFC +XED_DLL_EXPORT xed_uint32_t +xed_get_register_width_bits(xed_reg_enum_t r); + +/// Returns the width, in bits, of the named register. 64b mode. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_uint32_t +xed_get_register_width_bits64(xed_reg_enum_t r); + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/include/public/xed-rep-prefix.h b/include/public/xed-rep-prefix.h new file mode 100644 index 0000000..089bfb2 --- /dev/null +++ b/include/public/xed-rep-prefix.h @@ -0,0 +1,61 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immed.h +/// + +#ifndef _XED_REP_PREFIX_H_ +# define _XED_REP_PREFIX_H_ + +#include "xed-types.h" +#include "xed-common-defs.h" +#include "xed-iclass-enum.h" +/// @name REP-like prefix removal and addition +//@{ + +/// @ingroup DEC Take an instruction with a REP/REPE/REPNE prefix and +/// return the corresponding xed_iclass_enum_t without that prefix. The +/// return value differs from the other functions in this group: If the +/// input iclass does not have REP/REPNE/REPE prefix, the function returns +/// the original instruction. +XED_DLL_EXPORT xed_iclass_enum_t xed_rep_remove(xed_iclass_enum_t x); + +/// @ingroup DEC Take an #xed_iclass_enum_t value without a REPE prefix and +/// return the corresponding #xed_iclass_enum_t with a REPE prefix. If the +/// input instruction cannot have have a REPE prefix, this function returns +/// XED_ICLASS_INVALID. +XED_DLL_EXPORT xed_iclass_enum_t xed_repe_map(xed_iclass_enum_t iclass); + +/// @ingroup DEC Take an #xed_iclass_enum_t value without a REPNE prefix +/// and return the corresponding #xed_iclass_enum_t with a REPNE prefix. If +/// the input instruction cannot have a REPNE prefix, this function returns +/// XED_ICLASS_INVALID. +XED_DLL_EXPORT xed_iclass_enum_t xed_repne_map(xed_iclass_enum_t iclass); + +/// @ingroup DEC Take an #xed_iclass_enum_t value without a REP prefix and +/// return the corresponding #xed_iclass_enum_t with a REP prefix. If the +/// input instruction cannot have a REP prefix, this function returns +/// XED_ICLASS_INVALID. +XED_DLL_EXPORT xed_iclass_enum_t xed_rep_map(xed_iclass_enum_t iclass); + +/// @ingroup DEC Take an #xed_iclass_enum_t value for an instruction with a +/// REP/REPNE/REPE prefix and return the corresponding #xed_iclass_enum_t +/// without that prefix. If the input instruction does not have a +/// REP/REPNE/REPE prefix, this function returns XED_ICLASS_INVALID. +XED_DLL_EXPORT xed_iclass_enum_t xed_norep_map(xed_iclass_enum_t iclass); +//@} +#endif diff --git a/include/public/xed-state.h b/include/public/xed-state.h new file mode 100644 index 0000000..0cab025 --- /dev/null +++ b/include/public/xed-state.h @@ -0,0 +1,190 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-state.h +/// + + + +#ifndef _XED_STATE_H_ +# define _XED_STATE_H_ +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-address-width-enum.h" // generated +#include "xed-machine-mode-enum.h" // generated + + +/// Encapsulates machine modes for decoder/encoder requests. +/// It specifies the machine operating mode as a +/// #xed_machine_mode_enum_t +/// for decoding and encoding. The machine mode corresponds to the default +/// data operand width for that mode. For all modes other than the 64b long +/// mode (XED_MACHINE_MODE_LONG_64), a default addressing width, and a +/// stack addressing width must be supplied of type +/// #xed_address_width_enum_t . @ingroup INIT +typedef struct xed_state_s { + /// real architected machine modes + xed_machine_mode_enum_t mmode; + /// for 16b/32b modes + xed_address_width_enum_t stack_addr_width; +} xed_state_t; + +/// @name Initialization +//@{ +/// Constructor. +/// DEPRECATED: use #xed_state_init2(). +/// The mode, and addresses widths are enumerations that specify the number +/// of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and +/// stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine +/// modes, you must specify valid addressing widths. +/// +/// @param p the pointer to the #xed_state_t type +/// @param arg_mmode the machine mode of type #xed_machine_mode_enum_t +/// @param arg_ignored Ignored. The addressing width is now implied by the machine mode implied by arg_mmmode. +/// @param arg_stack_addr_width the stack address width of type #xed_address_width_enum_t (only required if not the mode is not #XED_MACHINE_MODE_LONG_64) +/// @ingroup INIT +static XED_INLINE void xed_state_init(xed_state_t* p, + xed_machine_mode_enum_t arg_mmode, + xed_address_width_enum_t arg_ignored, + xed_address_width_enum_t arg_stack_addr_width) { + p->mmode=arg_mmode; + p->stack_addr_width=arg_stack_addr_width; + (void) arg_ignored; //pacify compiler unused arg warning +} + +/// Constructor. +/// The mode, and addresses widths are enumerations that specify the number +/// of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and +/// stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine +/// modes, you must specify valid addressing widths. +/// +/// @param p the pointer to the #xed_state_t type +/// @param arg_mmode the machine mode of type #xed_machine_mode_enum_t +/// @param arg_stack_addr_width the stack address width of type #xed_address_width_enum_t (only required if not the mode is not #XED_MACHINE_MODE_LONG_64) +/// @ingroup INIT +static XED_INLINE void xed_state_init2(xed_state_t* p, + xed_machine_mode_enum_t arg_mmode, + xed_address_width_enum_t arg_stack_addr_width) { + p->mmode=arg_mmode; + p->stack_addr_width=arg_stack_addr_width; +} + +/// clear the xed_state_t +/// @ingroup INIT +static XED_INLINE void xed_state_zero(xed_state_t* p) { + p->mmode= XED_MACHINE_MODE_INVALID; + p->stack_addr_width=XED_ADDRESS_WIDTH_INVALID; +} + +//@} + +/// @name Machine mode +//@{ +/// return the machine mode +/// @ingroup INIT +static XED_INLINE xed_machine_mode_enum_t xed_state_get_machine_mode(const xed_state_t* p) { + return p->mmode; +} + + +/// true iff the machine is in LONG_64 mode +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_long64_mode(const xed_state_t* p) { + return xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_64; +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_real_mode(const xed_state_t* p) { + return (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_REAL_16); +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_mode_width_16(const xed_state_t* p) { + return (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LEGACY_16) || + (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_COMPAT_16); +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_mode_width_32(const xed_state_t* p) { + return (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LEGACY_32) || + (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_COMPAT_32); +} + + +/// Set the machine mode which corresponds to the default data operand size +/// @ingroup INIT +static XED_INLINE void xed_state_set_machine_mode( xed_state_t* p, + xed_machine_mode_enum_t arg_mode) { + p->mmode = arg_mode; +} +//@} + +/// @name Address width +//@{ + +/// return the address width +/// @ingroup INIT +static XED_INLINE xed_address_width_enum_t +xed_state_get_address_width(const xed_state_t* p) +{ + switch(xed_state_get_machine_mode(p)) { + case XED_MACHINE_MODE_LONG_64: + return XED_ADDRESS_WIDTH_64b; + + case XED_MACHINE_MODE_REAL_16: + /* should be 20b... but if you are working w/real mode then you're + going to have to deal with somehow. Could easily make this be + 20b if anyone cares. */ + return XED_ADDRESS_WIDTH_32b; + + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LONG_COMPAT_32: + return XED_ADDRESS_WIDTH_32b; + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_LONG_COMPAT_16: + return XED_ADDRESS_WIDTH_16b; + default: + return XED_ADDRESS_WIDTH_INVALID; + } +} + +//@} + +/// @name Stack address width +//@{ +/// set the STACK address width +/// @ingroup INIT +static XED_INLINE void +xed_state_set_stack_address_width(xed_state_t* p, + xed_address_width_enum_t arg_addr_width) +{ + p->stack_addr_width = arg_addr_width; +} + + +/// Return the STACK address width +/// @ingroup INIT +static XED_INLINE xed_address_width_enum_t xed_state_get_stack_address_width(const xed_state_t* p) { + return p->stack_addr_width; +} +//@} + +/// @ingroup INIT +XED_DLL_EXPORT int xed_state_print(const xed_state_t* p, char* buf, int buflen); + +#endif + diff --git a/include/public/xed-types.h b/include/public/xed-types.h new file mode 100644 index 0000000..c66564b --- /dev/null +++ b/include/public/xed-types.h @@ -0,0 +1,131 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-types.h +/// + + +#ifndef _XED_TYPES_H_ +# define _XED_TYPES_H_ + +//////////////////////////////////////////////////////////////////////////// + +#include "xed-common-hdrs.h" + +#if defined(__GNUC__) || defined(__ICC) +# include +# define xed_uint8_t uint8_t +# define xed_uint16_t uint16_t +# define xed_uint32_t uint32_t +# define xed_uint64_t uint64_t +# define xed_int8_t int8_t +# define xed_int16_t int16_t +# define xed_int32_t int32_t +# define xed_int64_t int64_t +#elif defined(_WIN32) +# define xed_uint8_t unsigned __int8 +# define xed_uint16_t unsigned __int16 +# define xed_uint32_t unsigned __int32 +# define xed_uint64_t unsigned __int64 +# define xed_int8_t __int8 +# define xed_int16_t __int16 +# define xed_int32_t __int32 +# define xed_int64_t __int64 +#else +# error "XED types unsupported platform? Need windows, gcc, or icc." +#endif + +typedef unsigned int xed_uint_t; +typedef int xed_int_t; +typedef unsigned int xed_bits_t; +typedef unsigned int xed_bool_t; + +#if defined(__LP64__) || defined (_M_X64) +typedef xed_uint64_t xed_addr_t; +#else +typedef xed_uint32_t xed_addr_t; +#endif + + +typedef union { + xed_uint8_t byte[2]; + xed_int8_t s_byte[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; /*high 8 bits*/ + } b; + xed_int16_t i16; + xed_uint16_t u16; +} xed_union16_t ; + +typedef union { + xed_uint8_t byte[4]; + xed_uint16_t word[2]; + xed_int8_t s_byte[4]; + xed_int16_t s_word[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; + xed_uint8_t b2; + xed_uint8_t b3; /*high 8 bits*/ + } b; + + struct { + xed_uint16_t w0; /*low 16 bits*/ + xed_uint16_t w1; /*high 16 bits*/ + } w; + xed_int32_t i32; + xed_uint32_t u32; +} xed_union32_t ; + +typedef union { + xed_uint8_t byte[8]; + xed_uint16_t word[4]; + xed_uint32_t dword[2]; + xed_int8_t s_byte[8]; + xed_int16_t s_word[4]; + xed_int32_t s_dword[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; + xed_uint8_t b2; + xed_uint8_t b3; + xed_uint8_t b4; + xed_uint8_t b5; + xed_uint8_t b6; + xed_uint8_t b7; /*high 8 bits*/ + } b; + + struct { + xed_uint16_t w0; /*low 16 bits*/ + xed_uint16_t w1; + xed_uint16_t w2; + xed_uint16_t w3; /*high 16 bits*/ + } w; + struct { + xed_uint32_t lo32; + xed_uint32_t hi32; + } s; + xed_uint64_t u64; + xed_int64_t i64; +} xed_union64_t ; + +//////////////////////////////////////////////////////////////////////////// +#endif diff --git a/include/public/xed-util.h b/include/public/xed-util.h new file mode 100644 index 0000000..a66a80a --- /dev/null +++ b/include/public/xed-util.h @@ -0,0 +1,251 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-util.h +/// + + + +#ifndef _XED_UTIL_H_ +# define _XED_UTIL_H_ + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-portability.h" + + + +extern int xed_verbose; +#if defined(XED_MESSAGES) +# include +extern FILE* xed_log_file; +# define XED_EMIT_MESSAGES (xed_verbose >= 1) +# define XED_INFO_VERBOSE (xed_verbose >= 2) +# define XED_INFO2_VERBOSE (xed_verbose >= 3) +# define XED_VERBOSE (xed_verbose >= 4) +# define XED_MORE_VERBOSE (xed_verbose >= 5) +# define XED_VERY_VERBOSE (xed_verbose >= 6) +#else +# define XED_EMIT_MESSAGES (0) +# define XED_INFO_VERBOSE (0) +# define XED_INFO2_VERBOSE (0) +# define XED_VERBOSE (0) +# define XED_MORE_VERBOSE (0) +# define XED_VERY_VERBOSE (0) +#endif + +#if defined(__GNUC__) +# define XED_FUNCNAME __func__ +#else +# define XED_FUNCNAME "" +#endif + +#if defined(XED_MESSAGES) +#define XED2IMSG(x) \ + do { \ + if (XED_EMIT_MESSAGES) { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + } \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +#define XED2TMSG(x) \ + do { \ + if (XED_VERBOSE) { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + } \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +#define XED2VMSG(x) \ + do { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +#define XED2DIE(x) \ + do { \ + if (XED_EMIT_MESSAGES) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + xed_assert(0); \ + } while(0) + + + +#else +# define XED2IMSG(x) +# define XED2TMSG(x) +# define XED2VMSG(x) +# define XED2DIE(x) do { xed_assert(0); } while(0) +#endif + +#if defined(XED_ASSERTS) +# define xed_assert(x) do { if (( x )== 0) xed_internal_assert( #x, __FILE__, __LINE__); } while(0) +#else +# define xed_assert(x) do { } while(0) +#endif +XED_NORETURN XED_NOINLINE XED_DLL_EXPORT void xed_internal_assert(const char* s, const char* file, int line); + +typedef void (*xed_user_abort_function_t)(const char* msg, + const char* file, + int line, + void* other); + +/// @ingroup INIT +/// This is for registering a function to be called during XED's assert +/// processing. If you do not register an abort function, then the system's +/// abort function will be called. If your supplied function returns, then +/// abort() will still be called. +/// +/// @param fn This is a function pointer for a function that should handle the +/// assertion reporting. The function pointer points to a function that +/// takes 4 arguments: +/// (1) msg, the assertion message, +/// (2) file, the file name, +/// (3) line, the line number (as an integer), and +/// (4) other, a void pointer that is supplied as thei +/// 2nd argument to this registration. +/// @param other This is a void* that is passed back to your supplied function fn +/// as its 4th argument. It can be zero if you don't need this +/// feature. You can used this to convey whatever additional context +/// to your assertion handler (like FILE* pointers etc.). +/// +XED_DLL_EXPORT void xed_register_abort_function(xed_user_abort_function_t fn, + void* other); + + +XED_DLL_EXPORT int xed_itoa(char* buf, + xed_uint64_t f, + int buflen); + +/// defaults to lowercase +XED_DLL_EXPORT int xed_itoa_hex_zeros(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen); + +/// defaults to lowercase +XED_DLL_EXPORT int xed_itoa_hex(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + int buflen); + +XED_DLL_EXPORT int xed_itoa_hex_ul(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen, + xed_bool_t lowercase); + + +/// Set the FILE* for XED's log msgs. This takes a FILE* as a void* because +/// some software defines their own FILE* types creating conflicts. +XED_DLL_EXPORT void xed_set_log_file(void* o); + + +/// Set the verbosity level for XED +XED_DLL_EXPORT void xed_set_verbosity(int v); + +XED_DLL_EXPORT xed_int64_t xed_sign_extend32_64(xed_int32_t x); +XED_DLL_EXPORT xed_int64_t xed_sign_extend16_64(xed_int16_t x); +XED_DLL_EXPORT xed_int64_t xed_sign_extend8_64(xed_int8_t x); + +XED_DLL_EXPORT xed_int32_t xed_sign_extend16_32(xed_int16_t x); +XED_DLL_EXPORT xed_int32_t xed_sign_extend8_32(xed_int8_t x); + +XED_DLL_EXPORT xed_int16_t xed_sign_extend8_16(xed_int8_t x); + +///arbitrary sign extension from a qty of "bits" length to 32b +XED_DLL_EXPORT xed_int32_t xed_sign_extend_arbitrary_to_32(xed_uint32_t x, unsigned int bits); + +///arbitrary sign extension from a qty of "bits" length to 64b +XED_DLL_EXPORT xed_int64_t xed_sign_extend_arbitrary_to_64(xed_uint64_t x, unsigned int bits); + + +XED_DLL_EXPORT xed_uint64_t xed_zero_extend32_64(xed_uint32_t x); +XED_DLL_EXPORT xed_uint64_t xed_zero_extend16_64(xed_uint16_t x); +XED_DLL_EXPORT xed_uint64_t xed_zero_extend8_64(xed_uint8_t x); + +XED_DLL_EXPORT xed_uint32_t xed_zero_extend16_32(xed_uint16_t x); +XED_DLL_EXPORT xed_uint32_t xed_zero_extend8_32(xed_uint8_t x); + +XED_DLL_EXPORT xed_uint16_t xed_zero_extend8_16(xed_uint8_t x); + +#if defined(XED_LITTLE_ENDIAN_SWAPPING) +XED_DLL_EXPORT xed_int32_t +xed_little_endian_to_int32(xed_uint64_t x, unsigned int len); + +XED_DLL_EXPORT xed_int64_t +xed_little_endian_to_int64(xed_uint64_t x, unsigned int len); +XED_DLL_EXPORT xed_uint64_t +xed_little_endian_to_uint64(xed_uint64_t x, unsigned int len); + +XED_DLL_EXPORT xed_int64_t +xed_little_endian_hilo_to_int64(xed_uint32_t hi_le, xed_uint32_t lo_le, unsigned int len); +XED_DLL_EXPORT xed_uint64_t +xed_little_endian_hilo_to_uint64(xed_uint32_t hi_le, xed_uint32_t lo_le, unsigned int len); +#endif + +XED_DLL_EXPORT xed_uint8_t +xed_get_byte(xed_uint64_t x, unsigned int i, unsigned int len); + +static XED_INLINE xed_uint64_t xed_make_uint64(xed_uint32_t hi, xed_uint32_t lo) { + xed_union64_t y; + y.s.lo32= lo; + y.s.hi32= hi; + return y.u64; +} +static XED_INLINE xed_int64_t xed_make_int64(xed_uint32_t hi, xed_uint32_t lo) { + xed_union64_t y; + y.s.lo32= lo; + y.s.hi32= hi; + return y.i64; +} + +/// returns the number of bytes required to store the UNSIGNED number x +/// given a mask of legal lengths. For the legal_widths argument, bit 0 +/// implies 1 byte is a legal return width, bit 1 implies that 2 bytes is a +/// legal return width, bit 2 implies that 4 bytes is a legal return width. +/// This returns 8 (indicating 8B) if none of the provided legal widths +/// applies. +XED_DLL_EXPORT xed_uint_t xed_shortest_width_unsigned(xed_uint64_t x, xed_uint8_t legal_widths); + +/// returns the number of bytes required to store the SIGNED number x +/// given a mask of legal lengths. For the legal_widths argument, bit 0 implies 1 +/// byte is a legal return width, bit 1 implies that 2 bytes is a legal +/// return width, bit 2 implies that 4 bytes is a legal return width. This +/// returns 8 (indicating 8B) if none of the provided legal widths applies. +XED_DLL_EXPORT xed_uint_t xed_shortest_width_signed(xed_int64_t x, xed_uint8_t legal_widths); + +#endif diff --git a/include/public/xed-version.h b/include/public/xed-version.h new file mode 100644 index 0000000..d51aaec --- /dev/null +++ b/include/public/xed-version.h @@ -0,0 +1,29 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(_XED_VERSION_H_) +# define _XED_VERSION_H_ +#include "xed-common-hdrs.h" + +///@ingroup INIT +/// Returns a string representing XED svn commit revision and time stamp. +XED_DLL_EXPORT char const* xed_get_version(void); +///@ingroup INIT +/// Returns a copyright string. +XED_DLL_EXPORT char const* xed_get_copyright(void); +#endif diff --git a/mfile.py b/mfile.py new file mode 100755 index 0000000..dedcd61 --- /dev/null +++ b/mfile.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +import sys +import os + +# Assume mbuild is next to the current source directory +# put mbuild on the import path +# from "path-to-xed/xed2/mfile.py" obtain: "path-to-xed/xed2". + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +def fatal(m): + sys.stderr.write("\n\nXED build error: %s\n\n" % (m) ) + sys.exit(1) + +def try_mbuild_import(): + try: + import mbuild + return True + except: + return False + +def find_mbuild_import(): + if try_mbuild_import(): + # mbuild is already findable by PYTHONPATH. Nothing required from + # this function. + return + + script_name = sys.argv[0] + mbuild_install_path_derived = \ + os.path.join(os.path.dirname(script_name), '..', 'mbuild') + + mbuild_install_path_relative = find_dir('mbuild') + mbuild_install_path = mbuild_install_path_derived + if not os.path.exists(mbuild_install_path): + if not mbuild_install_path_relative: + # If find_dir() fails, it returns None. That messes + # up os.path.exists() so we fix it with '' + mbuild_install_path_relative='' + mbuild_install_path = mbuild_install_path_relative + if not os.path.exists(mbuild_install_path): + s = "mfile.py cannot find the mbuild directory: [%s] or [%s]" + fatal(s % (mbuild_install_path_derived, + mbuild_install_path_relative)) + + # modify the environment python path so that the imported modules + # (enumer,codegen) can find mbuild. + + if 'PYTHONPATH' in os.environ: + sep = ':' + os.environ['PYTHONPATH'] = mbuild_install_path + sep + \ + os.environ['PYTHONPATH'] + else: + os.environ['PYTHONPATH'] = mbuild_install_path + + sys.path.insert(0,mbuild_install_path) + +def work(): + if sys.version_info[0] >= 3: + fatal("Python version 3.x not supported.") + if sys.version_info[0] == 2 and sys.version_info[1] < 7: + fatal("Need python version 2.7 or later.") + try: + find_mbuild_import() + except: + fatal("mbuild import failed") + import xed_mbuild + import xed_build_common + try: + retval = xed_mbuild.execute() + except Exception, e: + xed_build_common.handle_exception_and_die(e) + return retval + +if __name__ == "__main__": + retval = work() + sys.exit(retval) + diff --git a/misc/API.NAMES.txt b/misc/API.NAMES.txt new file mode 100644 index 0000000..66ad90e --- /dev/null +++ b/misc/API.NAMES.txt @@ -0,0 +1,410 @@ +str2xed_address_width_enum_t +str2xed_attribute_enum_t +str2xed_category_enum_t +str2xed_chip_enum_t +str2xed_cpuid_bit_enum_t +str2xed_error_enum_t +str2xed_exception_enum_t +str2xed_extension_enum_t +str2xed_flag_action_enum_t +str2xed_flag_enum_t +str2xed_iclass_enum_t +str2xed_iform_enum_t +str2xed_isa_set_enum_t +str2xed_machine_mode_enum_t +str2xed_nonterminal_enum_t +str2xed_operand_action_enum_t +str2xed_operand_convert_enum_t +str2xed_operand_ctype_enum_t +str2xed_operand_element_type_enum_t +str2xed_operand_element_xtype_enum_t +str2xed_operand_enum_t +str2xed_operand_type_enum_t +str2xed_operand_visibility_enum_t +str2xed_operand_width_enum_t +str2xed_reg_class_enum_t +str2xed_reg_enum_t +str2xed_reg_role_enum_t +str2xed_syntax_enum_t +xed3_decode_operands +xed3_dynamic_decode_part2 +xed3_static_decode +xed_address_width_enum_t2str +xed_address_width_enum_t_last +xed_agen +xed_agen_register_callback +xed_attribute +xed_attribute_enum_t2str +xed_attribute_enum_t_last +xed_attribute_max +xed_category_enum_t2str +xed_category_enum_t_last +xed_chip_enum_t2str +xed_chip_enum_t_last +xed_convert_to_encoder_request +xed_cpuid_bit_enum_t2str +xed_cpuid_bit_enum_t_last +xed_decode +xed_decoded_inst_conditionally_writes_registers +xed_decoded_inst_dump +xed_decoded_inst_dump_xed_format +xed_decoded_inst_get_attribute +xed_decoded_inst_get_attributes +xed_decoded_inst_get_base_reg +xed_decoded_inst_get_branch_displacement +xed_decoded_inst_get_branch_displacement_width +xed_decoded_inst_get_branch_displacement_width_bits +xed_decoded_inst_get_immediate_is_signed +xed_decoded_inst_get_immediate_width +xed_decoded_inst_get_immediate_width_bits +xed_decoded_inst_get_index_reg +xed_decoded_inst_get_memop_address_width +xed_decoded_inst_get_memory_displacement +xed_decoded_inst_get_memory_displacement_width +xed_decoded_inst_get_memory_displacement_width_bits +xed_decoded_inst_get_memory_operand_length +xed_decoded_inst_get_modrm +xed_decoded_inst_get_nprefixes +xed_decoded_inst_get_operand_width +xed_decoded_inst_get_reg +xed_decoded_inst_get_rflags_info +xed_decoded_inst_get_scale +xed_decoded_inst_get_seg_reg +xed_decoded_inst_get_signed_immediate +xed_decoded_inst_get_unsigned_immediate +xed_decoded_inst_has_mpx_prefix +xed_decoded_inst_is_prefetch +xed_decoded_inst_is_xacquire +xed_decoded_inst_is_xrelease +xed_decoded_inst_masked_vector_operation +xed_decoded_inst_masking +xed_decoded_inst_mem_read +xed_decoded_inst_mem_written +xed_decoded_inst_mem_written_only +xed_decoded_inst_merging +xed_decoded_inst_number_of_memory_operands +xed_decoded_inst_operand_action +xed_decoded_inst_operand_element_size_bits +xed_decoded_inst_operand_element_type +xed_decoded_inst_operand_elements +xed_decoded_inst_operand_length +xed_decoded_inst_operand_length_bits +xed_decoded_inst_set_branch_displacement +xed_decoded_inst_set_branch_displacement_bits +xed_decoded_inst_set_immediate_signed +xed_decoded_inst_set_immediate_signed_bits +xed_decoded_inst_set_immediate_unsigned +xed_decoded_inst_set_immediate_unsigned_bits +xed_decoded_inst_set_memory_displacement +xed_decoded_inst_set_memory_displacement_bits +xed_decoded_inst_set_scale +xed_decoded_inst_uses_rflags +xed_decoded_inst_valid_for_chip +xed_decoded_inst_vector_length_bits +xed_decoded_inst_zero +xed_decoded_inst_zero_keep_mode +xed_decoded_inst_zero_keep_mode_from_operands +xed_decoded_inst_zero_set_mode +xed_decoded_inst_zeroing +xed_decode_with_features +xed_encode +xed_encode_nop +xed_encode_request_print +xed_encoder_request_clear_rep +xed_encoder_request_get_iclass +xed_encoder_request_get_operand_order +xed_encoder_request_init_from_decode +xed_encoder_request_operands +xed_encoder_request_operands_const +xed_encoder_request_set_agen +xed_encoder_request_set_base0 +xed_encoder_request_set_base1 +xed_encoder_request_set_branch_displacement +xed_encoder_request_set_effective_address_size +xed_encoder_request_set_effective_operand_width +xed_encoder_request_set_iclass +xed_encoder_request_set_index +xed_encoder_request_set_mem0 +xed_encoder_request_set_mem1 +xed_encoder_request_set_memory_displacement +xed_encoder_request_set_memory_operand_length +xed_encoder_request_set_operand_order +xed_encoder_request_set_ptr +xed_encoder_request_set_reg +xed_encoder_request_set_relbr +xed_encoder_request_set_rep +xed_encoder_request_set_repne +xed_encoder_request_set_scale +xed_encoder_request_set_seg0 +xed_encoder_request_set_seg1 +xed_encoder_request_set_simm +xed_encoder_request_set_uimm0 +xed_encoder_request_set_uimm0_bits +xed_encoder_request_set_uimm1 +xed_encoder_request_zero +xed_encoder_request_zero_operand_order +xed_encoder_request_zero_set_mode +xed_error_enum_t2str +xed_error_enum_t_last +xed_exception_enum_t2str +xed_exception_enum_t_last +xed_extension_enum_t2str +xed_extension_enum_t_last +xed_flag_action_action_invalid +xed_flag_action_enum_t2str +xed_flag_action_enum_t_last +xed_flag_action_get_action +xed_flag_action_get_flag_name +xed_flag_action_print +xed_flag_action_read_action +xed_flag_action_read_flag +xed_flag_action_write_action +xed_flag_action_writes_flag +xed_flag_enum_t2str +xed_flag_enum_t_last +xed_flag_set_is_subset_of +xed_flag_set_print +xed_format_context +xed_format_generic +xed_format_set_options +xed_get_byte +xed_get_copyright +xed_get_cpuid_bit_for_isa_set +xed_get_cpuid_rec +xed_get_largest_enclosing_register +xed_get_largest_enclosing_register32 +xed_get_register_width_bits +xed_get_register_width_bits64 +xed_get_version +xed_gpr_reg_class +xed_iclass_enum_t2str +xed_iclass_enum_t_last +xed_iclass_string +xed_iform_db +xed_iform_enum_t2str +xed_iform_enum_t_last +xed_iform_first_per_iclass +xed_iform_map +xed_iform_max_per_iclass +xed_iform_to_category +xed_iform_to_extension +xed_iform_to_iclass_string_att +xed_iform_to_iclass_string_intel +xed_iform_to_isa_set +xed_iformfl_enum_t_last +xed_ild_decode +xed_immdis_add16 +xed_immdis_add32 +xed_immdis_add64 +xed_immdis_add8 +xed_immdis_add_byte +xed_immdis_add_byte_array +xed_immdis_add_shortest_width_signed +xed_immdis_add_shortest_width_unsigned +xed_immdis_get_byte +xed_immdis_get_bytes +xed_immdis_get_max_length +xed_immdis_get_signed64 +xed_immdis_get_unsigned64 +xed_immdis_init +xed_immdis_is_one +xed_immdis_is_present +xed_immdis_is_signed +xed_immdis_is_unsigned +xed_immdis_is_zero +xed_immdis_print +xed_immdis_print_signed_or_unsigned +xed_immdis_print_value_signed +xed_immdis_print_value_unsigned +xed_immdis_set_max_len +xed_immdis_set_present +xed_immdis_set_signed +xed_immdis_set_unsigned +xed_immdis_zero +xed_immed_from_bytes +xed_init_print_info +xed_inst_cpl +xed_inst_flag_info_index +xed_inst_get_attribute +xed_inst_get_attributes +xed_inst_operand +xed_inst_table +xed_inst_table_base +xed_internal_assert +xed_isa_set_enum_t2str +xed_isa_set_enum_t_last +xed_isa_set_is_valid_for_chip +xed_itoa +xed_itoa_hex +xed_itoa_hex_zeros +xed_machine_mode_enum_t2str +xed_machine_mode_enum_t_last +xed_nonterminal_enum_t2str +xed_nonterminal_enum_t_last +xed_norep_map +xed_operand +xed_operand_action_conditional_read +xed_operand_action_conditional_write +xed_operand_action_enum_t2str +xed_operand_action_enum_t_last +xed_operand_action_read +xed_operand_action_read_and_written +xed_operand_action_read_only +xed_operand_action_written +xed_operand_action_written_only +xed_operand_conditional_read +xed_operand_conditional_write +xed_operand_convert_enum_t2str +xed_operand_convert_enum_t_last +xed_operand_ctype_enum_t2str +xed_operand_ctype_enum_t_last +xed_operand_element_type_enum_t2str +xed_operand_element_type_enum_t_last +xed_operand_element_xtype_enum_t2str +xed_operand_element_xtype_enum_t_last +xed_operand_enum_t2str +xed_operand_enum_t_last +xed_operand_print +xed_operand_read +xed_operand_read_and_written +xed_operand_read_only +xed_operand_sequences +xed_operand_type_enum_t2str +xed_operand_type_enum_t_last +xed_operand_values_accesses_memory +xed_operand_values_branch_not_taken_hint +xed_operand_values_branch_taken_hint +xed_operand_values_clear_rep +xed_operand_values_dump +xed_operand_values_get_atomic +xed_operand_values_get_base_reg +xed_operand_values_get_branch_displacement_byte +xed_operand_values_get_branch_displacement_int32 +xed_operand_values_get_branch_displacement_length +xed_operand_values_get_branch_displacement_length_bits +xed_operand_values_get_displacement_for_memop +xed_operand_values_get_effective_address_width +xed_operand_values_get_effective_operand_width +xed_operand_values_get_iclass +xed_operand_values_get_immediate_byte +xed_operand_values_get_immediate_int64 +xed_operand_values_get_immediate_is_signed +xed_operand_values_get_immediate_uint64 +xed_operand_values_get_index_reg +xed_operand_values_get_long_mode +xed_operand_values_get_memory_displacement_byte +xed_operand_values_get_memory_displacement_int64 +xed_operand_values_get_memory_displacement_int64_raw +xed_operand_values_get_memory_displacement_length +xed_operand_values_get_memory_displacement_length_bits +xed_operand_values_get_memory_displacement_length_bits_raw +xed_operand_values_get_memory_operand_length +xed_operand_values_get_real_mode +xed_operand_values_get_scale +xed_operand_values_get_second_immediate +xed_operand_values_get_seg_reg +xed_operand_values_get_stack_address_width +xed_operand_values_has_66_prefix +xed_operand_values_has_address_size_prefix +xed_operand_values_has_branch_displacement +xed_operand_values_has_displacement +xed_operand_values_has_immediate +xed_operand_values_has_lock_prefix +xed_operand_values_has_memory_displacement +xed_operand_values_has_modrm_byte +xed_operand_values_has_operand_size_prefix +xed_operand_values_has_real_rep +xed_operand_values_has_rep_prefix +xed_operand_values_has_repne_prefix +xed_operand_values_has_rexw_prefix +xed_operand_values_has_segment_prefix +xed_operand_values_has_sib_byte +xed_operand_values_init +xed_operand_values_init_keep_mode +xed_operand_values_init_set_mode +xed_operand_values_is_nop +xed_operand_values_lockable +xed_operand_values_memop_without_modrm +xed_operand_values_number_of_memory_operands +xed_operand_values_print_short +xed_operand_values_segment_prefix +xed_operand_values_set_base_reg +xed_operand_values_set_branch_displacement +xed_operand_values_set_branch_displacement_bits +xed_operand_values_set_effective_address_width +xed_operand_values_set_effective_operand_width +xed_operand_values_set_iclass +xed_operand_values_set_immediate_signed +xed_operand_values_set_immediate_signed_bits +xed_operand_values_set_immediate_unsigned +xed_operand_values_set_immediate_unsigned_bits +xed_operand_values_set_index_reg +xed_operand_values_set_lock +xed_operand_values_set_memory_displacement +xed_operand_values_set_memory_displacement_bits +xed_operand_values_set_memory_operand_length +xed_operand_values_set_mode +xed_operand_values_set_operand_reg +xed_operand_values_set_relbr +xed_operand_values_set_scale +xed_operand_values_set_seg_reg +xed_operand_values_using_default_segment +xed_operand_values_zero_branch_displacement +xed_operand_values_zero_immediate +xed_operand_values_zero_memory_displacement +xed_operand_values_zero_segment_override +xed_operand_visibility_enum_t2str +xed_operand_visibility_enum_t_last +xed_operand_width_bits +xed_operand_width_enum_t2str +xed_operand_width_enum_t_last +xed_operand_written +xed_operand_written_only +xed_reg_class +xed_reg_class_enum_t2str +xed_reg_class_enum_t_last +xed_reg_enum_t2str +xed_reg_enum_t_last +xed_reg_role_enum_t2str +xed_reg_role_enum_t_last +xed_register_abort_function +xed_rep_map +xed_rep_remove +xed_repe_map +xed_repne_map +xed_set_log_file +xed_set_verbosity +xed_shortest_width_signed +xed_shortest_width_unsigned +xed_sign_extend16_32 +xed_sign_extend16_64 +xed_sign_extend32_64 +xed_sign_extend8_16 +xed_sign_extend8_32 +xed_sign_extend8_64 +xed_sign_extend_arbitrary_to_32 +xed_sign_extend_arbitrary_to_64 +xed_simple_flag_get_flag_action +xed_simple_flag_get_may_write +xed_simple_flag_get_must_write +xed_simple_flag_get_nflags +xed_simple_flag_get_read_flag_set +xed_simple_flag_get_undefined_flag_set +xed_simple_flag_get_written_flag_set +xed_simple_flag_print +xed_simple_flag_reads_flags +xed_simple_flag_writes_flags +xed_state_print +xed_strcpy +xed_strlen +xed_strncat +xed_strncpy +xed_syntax_enum_t2str +xed_syntax_enum_t_last +xed_tables_init +xed_zero_extend16_32 +xed_zero_extend16_64 +xed_zero_extend32_64 +xed_zero_extend8_16 +xed_zero_extend8_32 +xed_zero_extend8_64 diff --git a/misc/apache-header.txt b/misc/apache-header.txt new file mode 100644 index 0000000..b0e522a --- /dev/null +++ b/misc/apache-header.txt @@ -0,0 +1,15 @@ + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + diff --git a/pysrc/actions.py b/pysrc/actions.py new file mode 100755 index 0000000..96404d9 --- /dev/null +++ b/pysrc/actions.py @@ -0,0 +1,352 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +from verbosity import * +import re +import patterns +import genutil +import encutil +import mbuild +import copy + +def msgb(s,b=''): + mbuild.msgb(s,b) + +def gen_return_action(ret_val): + ''' create new action with type return ''' + + #temporary creating it as dummy + action = action_t("nothing") + action.type = 'return' + action.value = str(ret_val) + return action + +def dummy_emit(act_in,name): + ''' creating new action based on the input action with + dummy emit type and name as the field name''' + + action = copy.deepcopy(act_in) + action.emit_type = 'dummy' + action.field_name = name + return action + +def gen_dummy_fb(fb): + ''' create new fb action that sets the value to -1 ''' + str = "%s=-1" % fb + action = action_t(str) + return action + +def gen_null_fb(): + ''' create new fb with fake fb name:"null" and value 0 + using this to represent null pointers''' + str = "null=0" + action = action_t(str) + return action + +def gen_nt_action(nt): + ''' create new action with type nt ''' + str = "%s()" % nt + action = action_t(str) + return action + +class action_t(object): + """This is the right hand side of the rule_t. It can be a (1) + field binding (2) a byte encoding, (3) 'error' or (4) 'nothing'.""" + + + def __init__(self, arg_action): + self.type = None # 'FB', 'emit', 'nt', 'error', 'nothing', return + self.field_name = None + self.value = None + self.nt = None + self.ntluf = None + self.int_value = None + self.emit_type = None # 'numeric', 'letters', 'reg' + self.nbits = 0 + if vaction(): + msgb("ARGACTION", arg_action) + if arg_action == 'nothing' or arg_action == "NOTHING": + self.type = 'nothing' + return + # in the inputs, "error" gets expanded to "ERROR=1" via the statebits. + if arg_action == 'error' or arg_action == "ERROR" or arg_action == 'ERROR=1': + self.type = 'error' + return + + b = patterns.bit_expand_pattern.search(arg_action) + if b: + expanded = b.group('bitname') * int(b.group('count')) + action = patterns.bit_expand_pattern.sub(expanded,arg_action) + else: + action = arg_action + + #msgerr("CHECKING: %s" % action) + + a = patterns.equals_pattern.search(action) + if a: + # field binding + #msgerr("FIELD BINDING: %s" % action) + self.field_name = a.group('lhs') + rhs = a.group('rhs') + if patterns.decimal_pattern.match(rhs) or \ + patterns.binary_pattern.match(rhs) or \ + patterns.hex_pattern.match(rhs): + self.int_value = genutil.make_numeric(rhs) + self.value = str(self.int_value) + #msgb("SET RHS", "%s -> %s" % (rhs,self.value)) + else: + self.value = rhs + + self.type = 'FB' + return + + nt = patterns.nt_name_pattern.match(action) + if nt: + # NTLUF or NT. Only shows up on decode-oriented rules + self.nt = nt.group('ntname') + self.type = 'nt' + return + ntluf = patterns.ntluf_name_pattern.match(action) + if ntluf: + # NTLUF or NT. Only shows up on decode-oriented rules + self.ntluf = ntluf.group('ntname') + self.type = 'ntluf' + return + + cp = patterns.lhs_capture_pattern_end.match(action) + if cp: + self.type = 'emit' + self.value = cp.group('bits') + self.field_name = cp.group('name').lower() + #msgerr("EMIT ACTION %s" % action) + self.classify() + return + + # simple byte encoding + self.type = 'emit' + self.field_name = None + #msgerr("EMIT ACTION %s" % action) + self.value = action + self.classify() + + + def classify(self): + if patterns.decimal_pattern.match(self.value): + self.emit_type = 'numeric' + self.int_value = int(self.value) + t = hex(self.int_value) + self.nbits = 4*len(t[2:]) + if vclassify(): + msgb("CLASSIFY", "%s as decimal values" % (self.value)) + return + + if patterns.hex_pattern.match(self.value): + self.emit_type = 'numeric' + self.int_value = int(self.value,16) + self.nbits = 4*(len(self.value)-2) # drop the 0x, convert nibbles to bits + if vclassify(): + msgb("CLASSIFY", "%s as hex" % (self.value)) + return + if patterns.letter_and_underscore_pattern.match(self.value): + self.emit_type = 'letters' + t = self.value + t = genutil.no_underscores(t) + self.nbits = len(t) + if vclassify(): + msgb("CLASSIFY", "%s as letters" % (self.value)) + return + b = patterns.binary_pattern.match(self.value) # leading "0b" + if b: + self.emit_type = 'numeric' + t = '0b' + b.group('bits') # pattern match strips out 0b + self.int_value = genutil.make_numeric(t) + bits_str = genutil.make_binary(t) + self.nbits = len(bits_str) + if vclassify(): + msgb("CLASSIFY", "%s as explicit-binary -> int = %d nbits=%d [%s,%s]" % (self.value,self.int_value,self.nbits,t,bits_str)) + return + if patterns.bits_and_letters_underscore_pattern.match(self.value): + self.emit_type = 'letters' + v = genutil.no_underscores(self.value) + self.nbits = len(v) + if vclassify(): + msgb("CLASSIFY", "%s as mixed-letters" % (self.value)) + return + + + if patterns.simple_number_pattern.match(self.value): + self.emit_type = 'numeric' + self.int_value = genutil.make_numeric(self.value) + t = hex(self.int_value) + self.nbits = 4*len(t[2:]) + if vclassify(): + msgb("CLASSIFY", "%s as simple-number" % (self.value)) + return + + genutil.die("unknown pattern") + + def naked_bits(self): + ''' returns True if the type is emit but there is no field name. ''' + if self.type == 'emit' and self.field_name == None: + return True + return False + + def is_nothing(self): + return self.type == 'nothing' + def is_error(self): + return self.type == 'error' + def is_return(self): + return self.type == 'return' + + def is_nonterminal(self): + if self.nt: + return True + return False + def is_ntluf(self): + if self.ntluf: + return True + return False + + def is_field_binding(self): + """Return True if this action is a field binding.""" + if self.type == 'FB': + return True + return False + + def is_emit_action(self): + """Return True if this action is an emit action.""" + if self.type == 'emit': + return True + return False + + def __str__(self): + s = [] + s.append(str(self.type)) + if self.nt: + s.append(" NT[%s]" % (self.nt)) + if self.field_name: + s.append(" ") + s.extend([self.field_name,'=',self.value]) + elif self.value != None: + s.append(" ") + s.append(self.value) + if self.emit_type: + s.append(" emit_type=%s" % self.emit_type) + if self.int_value != None: + s.append(" value=0x%x" % self.int_value) + if self.nbits != 0: + s.append(" nbits=%d" % self.nbits) + return ''.join(s) + + def get_str_value(self): + if self.is_field_binding() or self.is_return(): + return self.value + if self.is_nonterminal(): + return self.nt + if self.is_ntluf(): + return self.ntluf + + err = "unsupported type: %s for function get_str_value" % self.type + genutil.die(err) + + + def emit_code(self, bind_or_emit): + if self.is_error(): + #return [ ' return 0; /* error */' ] + # FIXME? bind ERROR=1? + return [ ' okay=0; /* error */' ] + elif self.is_nothing(): + return [ ' return 1; /* nothing */' ] + + elif self.is_field_binding(): + return self._generate_code_for_field_binding(bind_or_emit) + + elif self.is_emit_action(): + return self._generate_code_for_emit_action(bind_or_emit) + + elif self.is_nonterminal(): + return self._emit_nonterminal_code(bind_or_emit) + + else: + return [ '/* FIXME action code not done yet for ' + self.__str__() + '*/' ] + + def _generate_code_for_field_binding(self, bind_or_emit): + if bind_or_emit == 'EMIT': + return [] + # we are in BIND + if self.field_name == 'NO_RETURN': + return [ '/* no code required for NO_RETURN binding */'] + operand_setter = "%s_set_%s" % (encutil.enc_strings['op_accessor'], + self.field_name.lower()) + obj_name = encutil.enc_strings['obj_str'] + s = ' %s(%s,%s);' % (operand_setter, + obj_name, self.value) + if self.field_name == 'ERROR': + return [ s, " return 0; /* error */" ] + else: + return [ s ] + def _generate_code_for_emit_action(self,bind_or_emit): + """Emit code for emit action """ + if bind_or_emit == 'BIND': + if self.emit_type == 'letters' or self.field_name == None: + return '' + elif self.emit_type == 'numeric': + op_accessor = encutil.enc_strings['op_accessor'] + operand_setter = "%s_set_%s" % (op_accessor, + self.field_name.lower()) + obj_name = encutil.enc_strings['obj_str'] + hex_val = hex(self.int_value) + code = "%s(%s, %s);" % (operand_setter, obj_name, hex_val) + return [' ' + code] + else: + genutil.die("Unknown emit_type %s" % self.emit_type) + else: + emit_util_function = encutil.enc_strings['emit_util_function'] + obj_name = encutil.enc_strings['obj_str'] + nbits = self.nbits + code = '' + if self.field_name == None: + if self.emit_type == 'numeric': + hex_val = hex(self.int_value) + code = "%s(%s, %d, %s);" % (emit_util_function,obj_name, + nbits,hex_val) + else: + genutil.die("must have field name for letter action") + else: + op_accessor = encutil.enc_strings['op_accessor'] + operand_getter = "%s_get_%s(%s)" % (op_accessor, + self.field_name.lower(), + obj_name) + code = "%s(%s, %d, %s);" % (emit_util_function, + obj_name,nbits,operand_getter) + return [' ' + code] + + def _emit_nonterminal_code(self,bind_or_emit): + """Emit code for calling a nonterminal in bind or emit modes""" + + nt_prefix = "%s" % encutil.enc_strings['nt_prefix'] + obj_name = encutil.enc_strings['obj_str'] + if bind_or_emit =='BIND': + s = [] + s.append(' if (okay)') + s.append(' okay = %s_%s_%s(%s);' %(nt_prefix,self.nt, + bind_or_emit,obj_name)) + return s + + else: #'EMIT' + code = '%s_%s_%s(%s);' %(nt_prefix, self.nt, bind_or_emit, obj_name) + return [' ' + code] diff --git a/pysrc/actions_codegen.py b/pysrc/actions_codegen.py new file mode 100755 index 0000000..0f5b607 --- /dev/null +++ b/pysrc/actions_codegen.py @@ -0,0 +1,354 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import collections +import actions +import types +import sys + +class actions_codegen_t(object): + ''' This file is about: + (a) examining the actions that we'll do after hashing. + Some actions may be conditional and this creates valid indicators for the + conditional bindings. + (b) printing the values of the actions for the hash table initialization. + (c) printing the conditional initialization of the xed fields after + successful hashing. Including calling other functions and returning values. + ''' + def __init__(self, tuple2rule, default_actions, strings_dict): + ''' params: tuple2rule: is a mapping from tuple to a rule + default_actions is a list action when we do not hit + a valid hash entry + strings_dict a is mapping of string to string''' + self.all_fbs = None + self.common_fbs = None + self.max_nt_number = 0 + self.tuple2rule = tuple2rule + self.default_actions = default_actions + self.strings_dict = strings_dict + + #this is a mapping from a tuple to a lost of action_t objects + self.tuple2actions = self._preprocess(tuple2rule) + + def _gather_all_fb(self, rules): + ''' returns a tuple of: + (1) the super set of all the field binding + (2) the intersection of all the fb + ''' + if len(rules) == 0: + return ([], []) + + #create a bin of fbs, one entry per rule + fbs_bin = [] + for rule in rules: + rule_fbs = set() + for action in rule.actions: + if action.is_field_binding(): + rule_fbs.add(action.field_name.lower()) + fbs_bin.append(rule_fbs) + + + all_fbs = set() + common_fbs = fbs_bin[0] + for bin in fbs_bin: + all_fbs.update(bin) + common_fbs.intersection_update(bin) + + return sorted(all_fbs), common_fbs + + def _get_max_nt_number(self, rules): + ''' find the maximal number of nt and ntlus among all the rules''' + nts_per_rule = [] + ntlufs_per_rule = [] + for rule in rules: + nts = 0 + ntlufs = 0 + for action in rule.actions: + if action.is_nonterminal(): + nts += 1 + if action.is_ntluf(): + ntlufs += 1 + nts_per_rule.append(nts) + ntlufs_per_rule.append(ntlufs) + + if nts_per_rule: + return max(nts_per_rule), max(ntlufs_per_rule) + return 0,0 + + def _create_ntluf_actions(self, action_list): + ''' return a list of all the ntluf actions ''' + i = 0 + ntluf_list = [] + for action in action_list: + if action.is_ntluf(): + if i < self.max_ntluf_number: + ntluf_list.append(action) + else: + genutil.die('currently do not support unequal \ + number of ntluf among all the rules') + i += 1 + #adding null pointer values to the actions list so all the rules will + #have the same number of actions + while i < self.max_ntluf_number: + nt_list.append(actions.gen_null_fb()) + i += 1 + + return ntluf_list + def _create_nt_actions(self, action_list): + ''' return a list of all the nt actions ''' + i = 0 + nt_list = [] + for action in action_list: + if action.is_nonterminal(): + if i < self.max_nt_number: + nt_list.append(action) + else: + genutil.die('currently do not support unequal number of \ + nt among all the rules') + i += 1 + #adding null pointer values to the actions list so all the rules will + #have the same number of actions + while i < self.max_nt_number: + nt_list.append(actions.gen_null_fb()) + i += 1 + + return nt_list + + + def _create_fb_actions(self, all_fbs, common_fbs, rule): + ''' creates a list fb actions for the given rule. + in case the given rule does not have an action for some fb in the + all_fbs list, we add a dummy action node ''' + + fbs = all_fbs + fb_list = [] + for fb_name in fbs: + fb_found = False + for action in rule.actions: + if action.is_field_binding() and \ + action.field_name.lower() == fb_name: + fb_found = True + fb_list.append(action) + + if not fb_found: + #the rule does not have action for this fb, creating a dummy + #node for it + fb_list.append(actions.gen_dummy_fb(fb_name)) + + return fb_list + + def _get_return_action(self, actions): + ''' find a return action and return it ''' + for action in actions: + if action.is_return(): + return [action] + return [] + + def _has_emit(self, rules): + ''' returns True if one of the rules has emit action''' + + for rule in rules: + if rule.has_emit_action(): + return True + return False + + def _preprocess(self, tuple2rule): + ''' generates the following information: + (1) the super set of all the field bindings among the rules + (2) the intersection of the fb. + (3) the max number of nonterminal functions + (4) if we have a 'return' action + (5) a mapping from tuple to a list of all the actions that were + captured ''' + tuple2actions = {} + + rules = tuple2rule.values() + self.rules = rules + self.all_fbs, self.common_fbs = self._gather_all_fb(rules) + self.max_nt_number, self.max_ntluf_number = self._get_max_nt_number(rules) + self.ret_action = False + self.has_emit = self._has_emit(rules) + + for tuple, rule in tuple2rule.iteritems(): + actions = self._create_fb_actions(self.all_fbs, self.common_fbs, rule) + nts = self._create_nt_actions(rule.actions) + ntlufs = self._create_ntluf_actions(rule.actions) + ret_action = self._get_return_action(rule.actions) + if ret_action: + self.ret_action = True + tuple2actions[tuple] = actions + nts + ntlufs + ret_action + + + return tuple2actions + + def get_actions_desc(self): + ''' returns the description of the action types ''' + desc = [] + for fb in self.all_fbs: + desc.append("%s %s" % (self.strings_dict['fb_type'], fb)) + for i in range(self.max_nt_number): + desc.append("%s ntptr%d" % (self.strings_dict['nt_fptr'], i)) + for i in range(self.max_ntluf_number): + desc.append("%s ntlufptr%d" % (self.strings_dict['ntluf_fptr'], i)) + if self.ret_action: + desc.append("%s value" % self.strings_dict['return_type']) + if self.has_emit: + desc.append("%s emit" % self.strings_dict['return_type']) + + if desc: + return " ;".join(desc) + ";" + return "" + + def no_actions(self): + ''' returns True if there is no actions, of any kind. + returns False if there is at least one action ''' + if self.all_fbs or self.common_fbs or self.max_nt_number or \ + self.max_ntluf_number or self.ret_action or self.has_emit: + return False + return True + + def get_values(self, tuple): + ''' return the values of the actions for the specific given tuple''' + action_vals = [] + + actions_list = self.tuple2actions[tuple] + for action in actions_list: + val = action.get_str_value() + if action.is_nonterminal(): + val = "%s_%s_BIND" % (self.strings_dict['nt_prefix'],val) + if action.is_ntluf(): + val = "%s_%s" % (self.strings_dict['ntluf_prefix'],val) + action_vals.append(val) + + if self.has_emit: + if self.tuple2rule[tuple].has_emit_action(): + hash_index = self.tuple2rule[tuple].index + action_vals.append(str(hash_index)) + else: + action_vals.append('0') + values = ",".join(action_vals) + return values + + def emit_actions(self): + ''' dump the code that executes the actions ''' + + actions_list = [] + fb_template = "%s_set_%s(%s,%s)" + hash_entry = "%s[%s].%s" + + #dump the code for the fb + for fb in self.all_fbs: + hash_val = hash_entry % (self.strings_dict['table_name'], + self.strings_dict['hidx_str'], fb) + action = fb_template % (self.strings_dict['op_accessor'], + fb, self.strings_dict['obj_str'], hash_val) + + if fb not in self.common_fbs: + #we need to add fb validation + validation = "if(%s >= 0) " % hash_val + action = validation + action + actions_list.append(action) + + #dump the code for the nonterminal + for i in range(self.max_nt_number): + fptri = "ntptr%d" % i + hash_val = hash_entry % (self.strings_dict['table_name'], + self.strings_dict['hidx_str'], fptri) + validation = "if(%s != 0) " % hash_val + f_call = "res=(*%s)(%s)" % (hash_val, self.strings_dict['obj_str']) + actions_list.append(validation + f_call) + + nt = self.tuple2rule.values()[0].nt + obj_str = self.strings_dict['obj_str'] + emit_call = "xed_encoder_request_iforms(%s)->x_%s=hidx+1" + actions_list.append(emit_call % (obj_str,nt)) + + #dump the code for the ntluf + for i in range(self.max_ntluf_number): + fptri = "ntlufptr%d" % i + hash_val = hash_entry % (self.strings_dict['table_name'], + self.strings_dict['hidx_str'], fptri) + validation = "if(%s != 0) " % hash_val + f_call = "res=(*%s)(%s,%s)" % (hash_val, self.strings_dict['obj_str'], 'arg_reg') + actions_list.append(validation + f_call) + #dump the return code + if self.ret_action: + ret_str = "return %s[%s].value" % (self.strings_dict['table_name'], + self.strings_dict['hidx_str']) + actions_list.append(ret_str) + + #dump the emit action + if self.has_emit: + nt = self.tuple2rule.values()[0].nt + obj_str = self.strings_dict['obj_str'] + emit_call = "xed_encoder_request_iforms(%s)->x_%s=%s" + hash_entry = "%s[%s].emit" % (self.strings_dict['table_name'], + self.strings_dict['hidx_str']) + actions_list.append(emit_call % (obj_str,nt,hash_entry)) + return actions_list + + def _has_return_stmt(self): + ''' we assume it is enough to check only the first rule, since if + on rule has return stmt than all the rules will have one ''' + for action in self.rules[0].actions: + if action.is_return(): + return True + return False + + def get_return_type(self): + ''' get the c type of the return action ''' + if self._has_return_stmt(): + return self.strings_dict['return_type'] + else: + return 'void' + + def emit_default(self): + ''' emit the action taken when we did not hit a valid hash table entry + ''' + actions = [] + for action in self.default_actions: + if action.is_return(): + s = "return %s" % action.get_str_value() + actions.append(s) + if action.is_field_binding(): + val = action.get_str_value() + fb = action.field_name.lower() + s = "%s_set_%s(%s,%s)" % (self.strings_dict['op_accessor'], fb, + self.strings_dict['obj_str'], val) + actions.append(s) + + return actions + + def get_empty_slots(self): + ''' return a list of the empty slots that will be used in the lu table + whenever we do not have a valid hash entry ''' + slots_num = 0 + slots_num += len(self.all_fbs) + slots_num += self.max_nt_number + slots_num += self.max_ntluf_number + # FIXME: the ret_action seems like the only thing that matters + # for the decoder + if self.ret_action: + slots_num += 1 + return ['0'] * slots_num + + def has_fcall(self): + return self.max_nt_number > 0 or self.max_ntluf_number > 0 + + + diff --git a/pysrc/chipmodel.py b/pysrc/chipmodel.py new file mode 100755 index 0000000..19e5a7e --- /dev/null +++ b/pysrc/chipmodel.py @@ -0,0 +1,251 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os +import re +import enum_txt_writer +import codegen +import genutil + +def _die(s): + genutil.die(s) + +def filter_comments(lines): + n = [] + for line in lines: + t = re.sub('#.*','',line) + t = t.strip() + if t: + n.append(t) + return n + +all_of_pattern = re.compile(r'ALL_OF[(](?P[A-Z0-9a-z_]+)[)]') +not_pattern = re.compile(r'NOT[(](?P[A-Z0-9a-z_]+)[)]') + +def uniquify_list(l): + d = {} + for a in l: + d[a]=True + return d.keys() + +def expand_all_of_once(d): + found = False + for chip,ext_list in d.iteritems(): + newexts = [] + for ext in ext_list: + m = all_of_pattern.match(ext) + if m: + found = True + other_chip = m.group('chip') + newexts.extend(d[other_chip]) + + else: + newexts.append(ext) + d[chip] = uniquify_list(newexts) + return found + +def expand_macro(d,expander): + found = True + while found: + found = expander(d) + +def expand_macro_not(d): + for chip,ext_list in d.iteritems(): + to_remove = [] + positive_exts = [] + for ext in ext_list: + m = not_pattern.match(ext) + if m: + to_remove.append( m.group('ext')) + else: + positive_exts.append(ext) + + for r in to_remove: + try: + positive_exts.remove(r) + except: + _die("Could not remove %s from %s for chip %s" % + ( r, " ".join(positive_exts), chip)) + + d[chip] = uniquify_list(positive_exts) + +def parse_lines(input_file_name, lines): # returns a dictionary + d = {} + chips = [] + for line in lines: + if line.find(':') == -1: + _die("reading file %s. " + + "Missing colon in line: %s" % + (input_file_name, line)) + (chip, extensions) = line.split(':') + chip = chip.strip() + chips.append(chip) + extensions = extensions.split() + if chip in d: + _die("Duplicate definition of %s in %s" % + (chip, input_file_name)) + if chip == 'ALL': + _die("Cannot define a chip named 'ALL'." + + " That name is reserved.") + d[chip] = extensions + return (chips,d) + + +def _feature_index(all_features, f): + try: + return all_features.index(f) + except: + _die("Did not find isa set %s in list\n" % (f)) + + + +def read_database(filename): + lines = file(filename).readlines() + lines = filter_comments(lines) + lines = genutil.process_continuations(lines) + # returns a list and a dictionary + (chips,chip_features_dict) = parse_lines(filename,lines) + + expand_macro(chip_features_dict,expand_all_of_once) + expand_macro_not(chip_features_dict) + + return (chips,chip_features_dict) + +def work(arg): + (chips,chip_features_dict) = read_database(arg.input_file_name) + + # the XED_CHIP_ enum + chips.append("ALL") + chip_enum = enum_txt_writer.enum_info_t(['INVALID'] + chips, + arg.xeddir, + arg.gendir, + 'xed-chip', + 'xed_chip_enum_t', + 'XED_CHIP_', + cplusplus=False) + chip_enum.print_enum() + chip_enum.run_enumer() + + # Add the "ALL" chip + + # the XED_ISA_SET_ enum + isa_set = set() + for vl in chip_features_dict.values(): + for v in vl: + isa_set.add(v.upper()) + isa_set = list(isa_set) + isa_set.sort() + + chip_features_dict['ALL'] = isa_set + + isa_set = ['INVALID'] + isa_set + isa_set_enum = enum_txt_writer.enum_info_t(isa_set, + arg.xeddir, + arg.gendir, + 'xed-isa-set', + 'xed_isa_set_enum_t', + 'XED_ISA_SET_', + cplusplus=False) + isa_set_enum.print_enum() + isa_set_enum.run_enumer() + + # the initialization file and header + chip_features_cfn = 'xed-chip-features-table.c' + chip_features_hfn = 'xed-chip-features-table.h' + cfe = codegen.xed_file_emitter_t(arg.xeddir, + arg.gendir, + chip_features_cfn, + shell_file=False) + private_gendir = os.path.join(arg.gendir,'include-private') + hfe = codegen.xed_file_emitter_t(arg.xeddir, + private_gendir, + chip_features_hfn, + shell_file=False) + for header in [ 'xed-isa-set-enum.h', 'xed-chip-enum.h' ]: + cfe.add_header(header) + hfe.add_header(header) + cfe.start() + hfe.start() + + + cfe.write("xed_uint64_t xed_chip_features[XED_CHIP_LAST][4];\n") + hfe.write("extern xed_uint64_t xed_chip_features[XED_CHIP_LAST][4];\n") + + fo = codegen.function_object_t('xed_init_chip_model_info', 'void') + fo.add_code_eol("const xed_uint64_t one=1") + # make a set for each machine name + spacing = "\n |" + for c in chips: + s0 = ['0'] + s1 = ['0'] + s2 = ['0'] + s3 = ['0'] + # loop over the features + for f in chip_features_dict[c]: + feature_index = _feature_index(isa_set,f) + + if feature_index < 64: + s0.append('(one< 256. Need anotehr features array") + + s0s = spacing.join(s0) + s1s = spacing.join(s1) + s2s = spacing.join(s2) + s3s = spacing.join(s3) + + for i,x in enumerate([s0s, s1s, s2s,s3s]): + fo.add_code_eol("xed_chip_features[XED_CHIP_{}][{}] = {}".format(c,i,x) ) + + cfe.write(fo.emit()) + cfe.close() + hfe.write(fo.emit_header()) + hfe.close() + + return ( [chip_enum.hdr_full_file_name, + chip_enum.src_full_file_name, + isa_set_enum.hdr_full_file_name, + isa_set_enum.src_full_file_name, + hfe.full_file_name, + cfe.full_file_name], chips, isa_set) + + +class args_t(object): + def __init__(self): + self.input_file_name = None + self.xeddir = None + self.gendir = None + +if __name__ == '__main__': + arg = args_t() + arg.input_file_name = 'datafiles/xed-chips.txt' + arg.xeddir = '.' + arg.gendir = 'obj' + files_created,chips,isa_set = work(arg) + print "Created files: %s" % (" ".join(files_created)) + sys.exit(0) + diff --git a/pysrc/classify_keys.py b/pysrc/classify_keys.py new file mode 100755 index 0000000..69ee18e --- /dev/null +++ b/pysrc/classify_keys.py @@ -0,0 +1,161 @@ +#!/usr/bin/env python +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import re +import optparse +import collections + +def read_keys(env): + kys_lst = [] + for line in file(env.fn): + line = line.strip() + line = map(int,line.split()) + kys_lst.append(line) + return kys_lst + +def sequential_nonzero_base(kys): + ln = len(kys) + minimum = kys[0] + lst = kys[-1] + if (ln-1) == (lst-minimum): + return True + return False + +def mildly_sparse(kys): + ln = len(kys) + minimum = kys[0] + lst = kys[-1] + nrange = kys[-1] - minimum + # tolerate 10% sparsity + if nrange <= ln * 1.20: + return True + return False +def sparse_and_small(kys): + ln = len(kys) + minimum = kys[0] + lst = kys[-1] + nrange = kys[-1] - minimum + limit = 32 + if nrange <= limit and ln <= limit: + return True + return False + +def two_values(kys): + if len(kys) == 2: + return True + return False + +def three_values(kys): + if len(kys) == 3: + return True + return False + + + +def classify(kys,env): + ln = len(kys) + + env.lengths[ln] += 1 + env.unique_sequences[str(kys)] += 1 + + if (ln-1) == kys[-1]: + env.sequential_zero_base += 1 + elif sequential_nonzero_base(kys): + env.sequential_nonzero_base += 1 + elif two_values(kys): + env.twofer += 1 + elif three_values(kys): + env.threefer += 1 + elif mildly_sparse(kys): + env.mildly_sparse += 1 + elif sparse_and_small(kys): + env.sparse_and_small += 1 + else: + env.funky.append(kys) + +def dump_classifications(env): + for k in env.lengths.keys(): + v = env.lengths[k] + print "LENGTH {} COUNT {}".format(k,v) + + for lst in env.funky: + print str(lst) + + u = len(env.unique_sequences.keys()) + print "TOTAL KEY SEQUENCES {}".format(env.all_keys) + print "UNIQUE KEY SEQUENCES {}".format(u) + print "" + print "SEQUENTIAL (Zero Based) {}".format(env.sequential_zero_base) + print "SEQUENTIAL (NonZero Based) {}".format(env.sequential_nonzero_base) + print "MILDLY SPARSE 20% {}".format(env.mildly_sparse) + print "SPARSE and SMALL (<=32 values and values <= 32) {}".format(env.sparse_and_small) + print "TWO VALUES {}".format(env.twofer) + print "THREE VALUES {}".format(env.threefer) + r = (u - env.sequential_nonzero_base - env.sequential_zero_base - + env.mildly_sparse - env.twofer - env.threefer - env.sparse_and_small) + print "OTHER {}".format(r) + + +def main(env): + env.funky = [] + env.mildly_sparse = 0 + env.sparse_and_small = 0 + env.twofer = 0 + env.threefer = 0 + env.sequential_zero_base = 0 + env.sequential_nonzero_base = 0 + env.lengths = collections.defaultdict(int) + env.unique_sequences = collections.defaultdict(int) + + kys_lst = read_keys(env) + env.all_keys = len(kys_lst) + u = {} + for k in kys_lst: + u[str(k)]=k + unique_keys = u.values() + + for k in unique_keys: + classify(k,env) + dump_classifications(env) + return 0 + +class obj_t(object): + def __init__(self): + pass + +def setup(): + env = obj_t() + + parser = optparse.OptionParser() + parser.add_option('-i', + action='store', + dest='input', + default='keys.dec', + help='Input file name') + + (options,args) = parser.parse_args() + env.fn = options.input + return env + +if __name__ == "__main__": + env = setup() + r = main(env) + sys.exit(r) diff --git a/pysrc/codegen.py b/pysrc/codegen.py new file mode 100644 index 0000000..02435bb --- /dev/null +++ b/pysrc/codegen.py @@ -0,0 +1,1037 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# Code generation support: emitting files, emitting functions, etc. +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os +import re +import types +import glob + +from genutil import * +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + #print "Trying %s" % (target_dir) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None +sys.path.append(find_dir('mbuild')) +try: + import mbuild +except: + sys.stderr.write("\nERROR(file: codegen.py): Could not find mbuild. Might try setting PYTHONPATH env var.\n\n") + sys.exit(1) + +class ip_header_t(object): + """Intellectual property headers""" + def __init__(self): + self.lines = None + def read_header(self,fn): + ##msge("Attempting to open: " + fn) + fp = base_open_file(fn,"r") + self.lines = fp.readlines() + + def emit_header(self, shell_type = False): + eol = '\n' + out = [] + if shell_type: + out.append("#BEGIN_LEGAL" + eol) + for line in self.lines: + out.append("#" + line) + out.append("#END_LEGAL" + eol) + + else: + out.append("/*BEGIN_LEGAL" + eol) + out.extend(self.lines) + out.append("END_LEGAL */" + eol) + return out + + +class file_emitter_t(object): + """Attach IP headers, standard includes, and namespace decorations + to generated files. This replaces the file objects I was using for + emitting files.""" + header_file_name_pattern = re.compile(r'.[hH]$') + + + # note: in the following the '-' must be last or it will (try to) act like a range! + header_guard_pattern = re.compile(r'[./-]') + + def __init__(self,gendir, file_name, shell_file=False, namespace=None): + """gendir is the output dir. If shell_file is True, we delimit + the header differently.""" + self.file_name = file_name + + self.gendir = gendir + self.namespace = namespace + # True for shell-like files, False for C++ files. Determines the comment syntax + self.shell_file = shell_file + + self.lines = [] + self.full_file_name = mbuild.join(self.gendir, self.file_name) + self.eol = '\n' + self.closed = False + self.header = False + if file_emitter_t.header_file_name_pattern.search(self.file_name): + self.header = True + self.headers = [] + self.system_headers = [] + self.misc_header = [] + + + def add_header(self,h): + """Add h to the list of headers""" + if type(h) == types.ListType: + self.headers.extend(h) + else: + self.headers.append(h) + + def add_system_header(self,h): + """Add h to the list of system headers""" + if type(h) == types.ListType: + self.system_headers.extend(h) + else: + self.system_headers.append(h) + + def add_misc_header(self,h): + if type(h) == types.ListType: + self.misc_header.extend(h) + else: + self.misc_header.append(h) + + def replace_headers(self,h): + """Replace the existing headers with the header h""" + if type(h) == types.ListType: + self.headers = h + else: + self.headers = [h] + + def start(self): + """Call this this after creating the objectd""" + self.emit_header() + if not self.shell_file: + self.system_headers_emit() + self.user_headers_emit() + self.misc_headers_emit() + self.namespace_start() + + def count_lines(self): + return len(self.lines) + + def write(self,str): + """Replaces the file pointer write() function call""" + self.lines.append(str) + def writelines(self,list_of_str): + """Replaces the file pointer writelines() function call""" + self.lines.extend(list_of_str) + def add_code(self,str): + """Add a line and newline""" + self.write(str+'\n') + def add_code_eol(self,str): + """Add a line with semicolon, newline""" + self.add_code(str+';') + + def close(self): + if not self.closed: + self.closed = True + if not self.shell_file: + self.namespace_end() + if self.header: + self.emit_header_guard_end() + self.emit_file() + del self.lines + else: + msge("FE: Closing an already-closed file: " + self.full_file_name) + + def emit_file(self): + msge("FE:EMIT_FILE " + self.full_file_name) + fp = self.open_file(self.full_file_name,"w") + fp.writelines(self.lines) + fp.close() + + # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # + + def open_file(self,fn,rw): + fp = base_open_file(fn,rw) + return fp + + def emit_ip_header(self, ip_header_file_name): + iph = ip_header_t() + iph.read_header(ip_header_file_name) + s = iph.emit_header(self.shell_file) + return s + + def emit_header(self): + self.dox('@file ' + self.file_name) + self.emit() + self.cmt('This file was automatically generated.') + self.cmt('Do not edit this file.') + self.emit() + if self.header: + self.emit_header_guard_start() + + def emit_header_guard_start(self): + s = file_emitter_t.header_guard_pattern.sub('_',self.file_name) + defname = '_%s_' % s.upper() + self.emit_eol('#if !defined(' + defname + ')') + self.emit_eol('# define ' + defname ) + def emit_header_guard_end(self): + self.emit_eol("#endif") + + def dox(self,s): + if self.shell_file: + self.emit_eol('# '+ s) + else: + self.emit_eol('/// '+ s) + def cmt(self,s): + if self.shell_file: + self.emit_eol('# '+ s) + else: + self.emit_eol('// '+ s) + def emit(self,s='\n'): + self.lines.append(s) + def emit_eol(self,s=''): + self.emit(s + '\n') + + def user_headers_emit(self): + for h in self.headers: + self.emit_eol('#include \"%s\"' % h ) + + def system_headers_emit(self): + for h in self.system_headers: + self.emit_eol('#include <%s>' % h ) + + def misc_headers_emit(self): + for h in self.misc_header: + self.emit_eol(h) + + + def namespace_start(self): + if self.namespace: + self.emit_eol( ''.join(['namespace ' , self.namespace , ' {'])) + def namespace_end(self): + if self.namespace: + msge("FE:NAMESPACE " + self.full_file_name) + self.emit_eol( '} // namespace') + + + + +class xed_file_emitter_t(file_emitter_t): + """Attach IP headers, standard includes, and namespace decorations + to generated files. This replaces the file objects I was using for + emitting files.""" + + def __init__(self, xeddir, gendir, file_name, shell_file=False, + namespace=None, is_private=True): + file_emitter_t.__init__( self,gendir, file_name, shell_file, namespace) + self.xeddir = xeddir + if is_private: + self.headers.append('xed-internal-header.h') + + def start(self): + """override the parent's start() function to apply the IP + header.""" + self.emit_header() + ip_header_file_name = mbuild.join(self.xeddir, + 'misc', + 'apache-header.txt') + for line in self.emit_ip_header(ip_header_file_name): + self.emit(line) + if not self.shell_file: + self.system_headers_emit() + self.user_headers_emit() + self.misc_headers_emit() + self.namespace_start() + +#inline_string = "inline" +inline_sring = "XED_INLINE" + + +class function_object_t(object): + inline_string = "XED_INLINE" + + def __init__(self,name, return_type='xed_bool_t', static=False, inline=False, + doxgroup=None, force_no_inline=False, dll_export=False): + self.function_name = name + self.doxgroup=doxgroup + self.return_type = return_type + self.static=static + self.inline=inline + self.dll_export = dll_export + self.body = [] + self.args = [] + self.const_member = False + self.ref_return = False + self.force_no_inline = force_no_inline + + def set_function_name(self,fname): + self.function_name = fname + + def lines(self): + return len(self.body) + + def add_arg(self, arg): + self.args.append(arg) + + def get_arg_num(self): + return len(self.args) + + def add_comment(self,s): + self.body.append(''.join(['/* ' , s , ' */'])) + + def set_const_member(self): + self.const_member = True + def set_ref_return(self): + self.ref_return = True + + def add_code(self, line): + self.body.append(line) + def add_code_eol(self, line): + self.body.append(line + ';') + + def add_lines(self, lines): + self.body.extend(lines) + + def emit_header_internal(self, class_qualfier='', emit_group=False): + """private function that emits the function name and args, but + no newline or semicolon""" + s = [] + if emit_group and self.doxgroup: + s.append("/// @ingroup %s\n" % (self.doxgroup)) + if self.static: + s.append("static ") + if self.inline: + s.append( function_object_t.inline_string + " ") + if self.force_no_inline: + s.append('XED_NOINLINE ') + if self.dll_export: + s.append('XED_DLL_EXPORT ') + s.append(self.return_type) + if self.ref_return: + s.append('&') + s.append(' ') + + s.append(class_qualfier) + + s.append(self.function_name) + s.append('(') + first_arg = True + for arg in self.args: + if first_arg: + first_arg = False + else: + s.append(', ') + s.append(arg) + if first_arg: + s.append('void') + s.append(')') + if self.const_member: + s.append(' const') + return ''.join(s) + + def emit_header(self): + 'emit the header with the semicolon and newline' + s = [ self.emit_header_internal(emit_group=True), ";\n" ] + return ''.join(s) + + def emit(self, class_qualfier=''): + 'emit the function body' + eol = '\n' + s = [ self.emit_header_internal(class_qualfier) , eol ] + s.append('{') + s.append(eol) + for bline in self.body: + s.extend([ ' ' , bline , eol]) + s.append('}') + s.append(eol) + return ''.join(s) + + def emit_file_emitter(self, fe, class_qualfier=''): + 'emit the function body' + fe.add_code(self.emit_header_internal(class_qualfier)) + fe.add_code('{') + for bline in self.body: + fe.add_code(bline) + fe.add_code('}') + + def emit_body(self): + 'emit function body as string' + return '\n'.join([bline + ';' for bline in self.body]) + +############################################################ + +def dump_flist_2_header(h_file, functions, headers, + emit_headers=True, + emit_bodies=True): + ''' emits the list of functions objects to a header file + @type: functions: list of function_object_t + @param functions: the function to emit + @type: h_file: xed_file_emitter_t + @param h_file: emmiting the function to this headr file + @type: headers: list of strings + @param headers: include headers to emit + ''' + for header in headers: + h_file.add_header(header) + h_file.start() + + if emit_headers: + for fo in functions: + decl = fo.emit_header() + h_file.add_code(decl) + + if emit_bodies: + for fo in functions: + fo.emit_file_emitter(h_file) + + h_file.close() + +def emit_function_list(func_list, fn_prefix, xeddir, gendir, hgendir, namespace=None, other_headers=[]): + """Emit a list of functions to a numbered sequence of + files. Breaking them up when the files get too big. + + @type func_list: list of function_object_t objects + @param func_list: functions to emit + @type fn_prefix: string + @param fn_prefix: basis for the output file names. + @type xeddir: string + @param xeddir: location of the source directory so that we can find the legal header + @type gendir: string + @param gendir: directory where the output files go. + @type hgendir: string + @param hgendir: directory where the output hdr files go. + @type namespace: string + @param namespace: defaults to XED + """ + file_number = 0; + max_lines_per_file = 3000 + fe = None + fn_header = "%s.h" % (fn_prefix) + fe_list = [] + fe_header = xed_file_emitter_t(xeddir,hgendir,fn_header,shell_file=False,namespace=namespace) + fe_header.start() + fe_list.append(fe_header) + + # remove any numbered files that we previously emitted. We won't + # necessarily overwrite them all each build and do not want + # stale files remaining from previous builds + for fn in glob.glob(mbuild.join(gendir, fn_prefix + '-[0-9]*.c')): + mbuild.remove_file(fn) + + for func in func_list: + fe_header.write(func.emit_header()) + if not fe or fe.count_lines() + func.lines() >= max_lines_per_file: + if fe: + fe.close() + fn = "%s-%d.c" % (fn_prefix, file_number) + fe = xed_file_emitter_t(xeddir,gendir, fn, shell_file=False, namespace=namespace) + fe.add_header(fn_header) + for header in other_headers: + fe.add_header(header) + fe.start() + fe_list.append(fe) + file_number += 1 + + func.emit_file_emitter(fe) + + + fe.close() + fe_header.close() + return fe_list + + +############################################################ + + +def function_call_sequence(fname, lst): + """Return a function object (returning nothing) for a function + named fname that calls all the functions in lst. + + @type fname: string + @param fname: function name + @type lst: list + @param lst: list of function names without parens + @rtype: function_object_t + @return: function that calls each function in lst + """ + fo = function_object_t(fname, "void") + for fn in lst: + fo.add_code_eol(fn + "()") + return fo + +def function_call_sequence_conditional(fname, lst, subroutine_arg=''): + """Return a function object (that returns xed_bool_t) for a function named fname that calls + all the functions in lst. Check each function call for an okay + return value and have this function return false if any of the + subroutines return false. + + @type fname: string + @param fname: function name + @type lst: list + @param lst: list of function names without parens + @type subroutine_arg: string + @param subroutine_arg: optional parameter for the called functions + + @rtype: function_object_t + @return: function that calls each function in lst + """ + fo = function_object_t(fname, "xed_bool_t") + fo.add_code_eol("xed_bool_t okay") + args = "(%s)" % subroutine_arg + for fn in lst: + fo.add_code_eol("okay = " + fn + args) + fo.add_code_eol("if (!okay) return 0") + fo.add_code_eol("return 1") + return fo + +class class_generator_t(object): + """Generate code for a c++ class (or union) declaration and + implementation. + + If you want initialization or a printer, you can add your create + your own functions and add them with add_function(). + """ + inline_string = "XED_INLINE" + inline_pattern = re.compile(inline_string) + + def __init__(self,name, class_or_union='class', var_prefix = "_"): + self.name = name + self.var_type = [] # list of (variable,type,bit_width) tuples + self.functions = [] # member functions + self.class_or_union = class_or_union + self.var_prefix = var_prefix + + def add_var(self, var, type, bit_width = None, accessors='set-get'): + """Add a variable var of type. If accessors is set, generate + set/get functions for it. The potential values are the following + strings: + + set + get + set-get + get-ref + set-get-array + none + """ + pvar = self.var_prefix + var + self.var_type.append((pvar,type,bit_width)) + if accessors == 'set-get-array': + self.add_function(self.add_get_array_fn(var,pvar,type)) + self.add_function(self.add_set_array_fn(var,pvar,type)) + if accessors == 'set-get': + self.add_function(self.add_get_fn(var,pvar,type)) + self.add_function(self.add_set_fn(var,pvar,type)) + elif accessors == 'set': + self.add_function(self.add_set_fn(var,pvar,type)) + elif accessors == 'get': + self.add_function(self.add_get_fn(var,pvar,type)) + elif accessors == 'get-ref': + self.add_function(self.add_get_ref_fn(var,pvar,type)) + elif accessors == 'none': + pass + else: + die("Unhandled accessor keyword: " + accessors) + + def add_get_ref_fn(self,var,pvar,type): + 'A get-accessor function for class varable pvar, returns a reference' + fname = 'get_' + var + fo = function_object_t(fname, inline_string + ' ' + type) + fo.set_ref_return() + fo.add_code_eol( 'return %s' %( pvar )) + return fo + + def add_get_fn(self,var,pvar,type): + 'A get-accessor function for class varable pvar' + fname = 'get_' + var + fo = function_object_t(fname, inline_string + ' ' + type) + fo.set_const_member() + fo.add_code_eol( 'return %s' % ( pvar )) + return fo + + def add_set_fn(self, var,pvar,type): + 'A set-accessor function for class varable pvar' + fname = 'set_' + var + fo = function_object_t(fname, inline_string + ' void') + fo.add_arg(type + ' arg_' + var) + fo.add_code_eol( '%s=arg_%s' % (pvar,var)) + return fo + + def add_get_array_fn(self,var,pvar,type): + 'A get-accessor function for class varable pvar' + fname = 'get_' + var + fo = function_object_t(fname, inline_string + ' ' + type) + fo.add_arg("unsigned int idx") #FIXME: parameterize unsigned int + fo.set_const_member() + # FIXME: add bound checking for array index + fo.add_code_eol( 'return %s[idx]' % (pvar)) + return fo + + def add_set_array_fn(self, var,pvar,type): + 'A set-accessor function for class varable pvar' + fname = 'set_' + var + fo = function_object_t(fname, inline_string +' void') + fo.add_arg("unsigned int idx") #FIXME: parameterize unsigned int + fo.add_arg(type + ' arg_' + var) + # FIXME add bounds checking for array index + fo.add_code_eol( '%s[idx]=arg_%s' % (pvar, var)) + return fo + + def add_function(self, function): + self.functions.append(function) + + def emit_decl(self): + 'emit the class declaration' + eol = '\n' + pad = ' ' + + s = [] + s.append(self.class_or_union + ' ' + self.name + eol) + s.append('{' + eol) + s.append(' public:' + eol) + for (var,type,bit_width) in self.var_type: + t = pad + type + ' ' + var + if bit_width: + t += ' : ' + str(bit_width) + s.append(t+ ';' + eol) + for fo in self.functions: + s.append( pad + fo.emit_header()) + s.append('};' + eol) + + # emit the inline functions in the header + for fo in self.functions: + if class_generator_t.inline_pattern.search(fo.return_type): + s.append(fo.emit(self.name + '::') ) + + return ''.join(s) + + def emit_impl(self): + 'emit the class implementation' + s = [] + # only emit the noninline functions + for fo in self.functions: + if not class_generator_t.inline_pattern.search(fo.return_type): + s.append(fo.emit(self.name + '::') ) + return ''.join(s) + +############################################################################ +class c_switch_generator_t(object): + def __init__(self, var_name, func_obj, pad=' '): + self.func_obj = func_obj + self.var_name = var_name + self.pad = pad + self._add('switch(%s) {' % (self.var_name)) + + def _add(self,s): + self.func_obj.add_code(self.pad + s) + + def add_case(self,case_name,clines, do_break=True): + """Add a case with a bunch of lines of code -- no semicolons + required""" + self._add('case %s:' % (case_name)) + for line in clines: + self._add(' ' + line) + if do_break: + self._add(' break;') + + def add_default(self,clines, do_break=True): + """Add a default case with a bunch of lines of code -- no + semicolons required""" + self._add('default:') + for line in clines: + self._add(' ' + line) + if do_break: + self._add(' break;') + + def finish(self): + self._add('}') + + +############################################################################ + +class c_class_generator_t(object): + """Generate code for a C struct (or union) declaration and + implementation. + + If you want initialization or a printer, you can add your create + your own functions and add them with add_function(). + """ + + type_ending_pattern = re.compile(r'_t$') + def remove_suffix(self,x): + return c_class_generator_t.type_ending_pattern.sub('',x) + + inline_string = "XED_INLINE" + inline_pattern = re.compile(inline_string) + + def __init__(self,name, class_or_union='struct', var_prefix = "_"): + self.name = name + self.var_type = [] # list of (variable,type,bit_width) tuples + self.array_type = [] # list of (variable,type,limit) tuples + self.functions = [] # member functions + self.class_or_union = class_or_union + self.var_prefix = var_prefix + + def add_array(self, var, type, limit): + """Add an array variable var of type. + """ + pvar = self.var_prefix + var + self.array_type.append((pvar,type,limit)) + self.add_function(self.add_get_array_fn(var,pvar,type)) + self.add_function(self.add_set_array_fn(var,pvar,type)) + + def add_var(self, var, type, bit_width = None, accessors='set-get'): + """Add a variable var of type. If accessors is set, generate + set/get functions for it. The potential values are the following + strings: + + set + get + set-get + get-ref + set-get-array + none + """ + pvar = self.var_prefix + var + self.var_type.append((pvar,type,bit_width)) + if accessors == 'set-get-array': + self.add_function(self.add_get_array_fn(var,pvar,type)) + self.add_function(self.add_set_array_fn(var,pvar,type)) + if accessors == 'set-get': + self.add_function(self.add_get_fn(var,pvar,type)) + self.add_function(self.add_set_fn(var,pvar,type)) + elif accessors == 'set': + self.add_function(self.add_set_fn(var,pvar,type)) + elif accessors == 'get': + self.add_function(self.add_get_fn(var,pvar,type)) + elif accessors == 'get-ref': + self.add_function(self.add_get_ref_fn(var,pvar,type)) + elif accessors == 'none': + pass + else: + die("Unhandled accessor keyword: " + accessors) + + def add_get_ref_fn(self,var,pvar,type): + """A get-accessor function for class varable pvar, returns a POINTER""" + fname = self.remove_suffix(self.name) + '_get_' + var + fo = function_object_t(fname, type + "*") + fo.add_arg("%s* ppp" % self.name) + fo.add_code_eol( 'return &(ppp->%s)' %( pvar )) + return fo + + def add_get_fn(self,var,pvar,type): + 'A get-accessor function for class varable pvar' + fname = self.remove_suffix(self.name) + '_get_' + var + fo = function_object_t(fname, type) + fo.add_arg("%s* ppp" % self.name) + fo.add_code_eol( 'return ppp->%s' % ( pvar )) + return fo + + def add_set_fn(self, var,pvar,type): + 'A set-accessor function for class varable pvar' + fname = self.remove_suffix(self.name) + '_set_' + var + fo = function_object_t(fname, 'void') + fo.add_arg("%s* ppp" % self.name) + fo.add_arg(type + ' arg_' + var) + fo.add_code_eol( 'ppp->%s=arg_%s' % (pvar,var)) + return fo + + def add_get_array_fn(self,var,pvar,type): + 'A get-accessor function for class varable pvar' + fname = self.remove_suffix(self.name) + '_get_' + var + fo = function_object_t(fname, type) + fo.add_arg("%s* ppp" % self.name) + fo.add_arg("unsigned int idx") #FIXME: parameterize unsigned int + # FIXME: add bound checking for array index + fo.add_code_eol( 'return ppp->%s[idx]' % (pvar)) + return fo + + def add_set_array_fn(self, var,pvar,type): + 'A set-accessor function for class varable pvar' + fname = self.remove_suffix(self.name) + '_set_' + var + fo = function_object_t(fname, 'void') + fo.add_arg("%s* ppp" % self.name) + fo.add_arg("unsigned int idx") #FIXME: parameterize unsigned int + fo.add_arg(type + ' arg_' + var) + # FIXME add bounds checking for array index + fo.add_code_eol( 'ppp->%s[idx]=arg_%s' % (pvar, var)) + return fo + + def add_function(self, function): + self.functions.append(function) + + def emit_decl(self): + 'emit the class declaration' + eol = '\n' + pad = ' ' + + s = [] + # I replace the suffix _t$ first then append a _s or _u. This way it + # adds a _s/_u even if no _t is present. + + struct_name = re.sub(r'_t$', '',self.name ) + if self.class_or_union == 'union': + struct_name += '_u' + else: + struct_name += '_s' + + s.append('typedef %s %s {\n' % (self.class_or_union, struct_name)) + + for (var,type,limit) in self.array_type: + t = "%s %s %s[%s];\n" % ( pad, type, var, str(limit)) + s.append(t) + + for (var,type,bit_width) in self.var_type: + t = '%s %s %s' % ( pad, type, var) + if bit_width: + t += ' : ' + str(bit_width) + s.append(t+ ';' + eol) + s.append('} %s;\n' % self.name ) + + # accessor function prototypes + for fo in self.functions: + s.append( pad + fo.emit_header()) + return ''.join(s) + + def emit_impl(self): + """emit the class implementation""" + s = [] + # only emit the noninline functions + for fo in self.functions: + s.append(fo.emit() ) + return ''.join(s) + + +############################################################################ + +class array_gen_t(object): + """A simple C++ multidimensional array generator. The ranges are + typed. New values are added by specifying a list of indices, one + per dimension and a value""" + def __init__(self, name, type, target_op=None): + """Set the name and storage type for the array""" + self.name = name + self.type = type + self.target_op = target_op + + self.ranges = [] # list of tuples (range_type, minval, maxval+1, argname ) + # including the max + # value for dimensioning the array + + self.values = [] # list of tuples of tuples (dict(names->indices), value) + + self.lookup_fn = None + self.init_fn = None + + def add_dimension(self, range_type, range_min, range_max, argname): + """For one dimension, add the type of the range index and the + min/max range values.""" + self.ranges.append((range_type,range_min, range_max, argname)) + + def get_arg_names(self): + return [range_tuple[3] for range_tuple in self.ranges] + + def get_target_opname(self): + """Return the name of target operand of lookup function + (if it was supplied)""" + return self.target_op + + def get_dimension_num(self): + """Return the number of array dimensions. + In other words the number of the lookup function parameters.""" + return len(self.ranges) + + def get_values_space(self): + """Return a list of all possible return values of a lookup function""" + return [val for (_idx_dict, val) in self.values] + + def is_const_lookup_fun(self): + """Return true if a lookup function always returns same value. + Const lookup function and the array is just a variable.""" + return self.get_dimension_num() == 0 + + def add_value(self, indx_dict, value): + """set the scalar value for the dictionary of indices""" + self.values.append((indx_dict, value)) + + def validate(self): + """Make sure that all the index arrays have the expected + number of elements.""" + expected_len = len(self.ranges) + for idict,value in self.values: + if len(idict.keys()) != expected_len: + return False + return True + + def gen_lookup_function(self, fn_name, check_bounds=True, static=False, + inline=False, check_const=False): + """Create a lookup function that will look up the value and + return the appropriate type. Typed args will be added for each + dimension + + check_const argument is for checking if lookup function is of a form + return var; - constant function. Then we can optimize it to a form + return const; where const is a compile-time constant (a number). + """ + + fo = function_object_t(fn_name, self.type, static=static, inline=inline) + + #optimization for const functions + if check_const: + if self.is_const_lookup_fun() and len(self.values) == 1: + fo.add_code('/*Constant function*/') + value = self.values[0][1] + fo.add_code_eol('return %s' % str(value)) + self.lookup_fn = fo + return + + + fo.add_code_eol(self.type + ' _v') + + index_expression = '' + for i,range_tuple in enumerate(self.ranges): + range_type, range_min, range_max, argname = range_tuple + fo.add_arg(range_type + ' arg_' + argname) + index_expression += '[arg_%s]' % (argname) + lower_bound = str(range_min) + upper_bound = str(range_max) + if check_bounds: + # FIXME: if the range type is unsigned, and the lower + # bound is zero, then we need not check it. But it is + # hard to tell from here with an arbitary type. ICL + # complains about this, warning/error #186. + fo.add_code_eol('xed_assert(arg_'+ argname + '>=' + lower_bound + + ' && arg_' + argname + '<' + upper_bound + ')') + + fo.add_code_eol('_v=' + self.name + index_expression) + + fo.add_code_eol('return _v') + self.lookup_fn = fo + + def emit_lookup_function(self): + """Emit the lookup function as a string""" + if self.lookup_fn == None: + die("Need to generate the lookup function first for " + self.name) + return self.lookup_fn.emit() + + def emit_lookup_function_header(self): + """Emit the lookup function header as a string""" + if self.lookup_fn == None: + die("Need to generate the lookup function first for " + self.name) + return self.lookup_fn.emit_header() + + def emit_initialization_function_header(self): + if self.init_fn == None: + die("Need to generate the init function first for " + self.name) + return self.init_fn.emit_header() + + def emit_declaration(self, extern=False, static=False): + """Emit the array declaration as a string.""" + s = [] + if static: + s.append( 'static ') + if extern: + s.append( 'extern ') + + s.append( self.type + ' ' + self.name) + for range_type, range_min, range_max, argname in self.ranges: + s.append('[%s]' % (str(range_max))) + s.append(';\n') + return ''.join(s) + + def compute_missing_values(self,key): + present_values = {} + for indices_dict,value in self.values: + if key in indices_dict: + present_values[indices_dict[key]] = True + return present_values.keys() + + + def make_initialization_function(self, init_function_name,verbose=False): + fo = function_object_t(init_function_name,'void') + lines = self.emit_initialization(verbose=verbose) + fo.add_lines(lines) + self.init_fn = fo + + + def emit_initialization(self,verbose=False): # private + """Return a list of strings containing array initialization lines""" + lines = [] + indices = map(lambda(x): x[3], self.ranges) # get the argnames + + missing_key = None + missed_one = True + # if we missed one then we process everything all over again to make sure we + # got everything. We only add one missing OD per pass + while missed_one: + missed_one = False + + new_values = [] + for indices_dict,value in self.values: + missing_key = None # 2007-06-16 bug fix. This line was missing + if verbose: + msge("AG: Processing value: %s indices: %s" % ( value, str(indices_dict))) + for key in indices: + if key not in indices_dict: + # we are missing values for this key. + if verbose: + msge("AG: Missing key %s" % (key)) + missing_key = key + missed_one = True + if missing_key == None: + # We have this key, so add the dictionary + new_values.append((indices_dict,value)) + else: + # We must replicate this entry for all values of the + # *all* missing keys! We can do this one missing field + # at a time. Eventually, we'll get them all. + all_present_values = self.compute_missing_values(missing_key) + if verbose: + msge('AG: Adding missing key %s to %s with values %s' % ( missing_key, + self.name, + str(all_present_values))) + for v in all_present_values: + new_dict = copy.copy(indices_dict) + new_dict[missing_key] = v + new_values.append((new_dict,value)) + del self.values + self.values = new_values + + + for indices_dict,value in self.values: + s = [self.name] + for key in indices: + indx = indices_dict[key] + if type(indx) == types.DictType: + die("A dictionary escaped during array init building for " + self.name) + s.append('[%s]' %(str(indx))) + s.append( '=%s;' % str(value) ) + t = ''.join(s) + if verbose: + msge("AG: %s" % t) + lines.append(t) + return lines + diff --git a/pysrc/constraint_vec_gen.py b/pysrc/constraint_vec_gen.py new file mode 100755 index 0000000..caa5b13 --- /dev/null +++ b/pysrc/constraint_vec_gen.py @@ -0,0 +1,185 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import copy +import math +import collections +import genutil +import encutil + +class constraint_vec_gen_t(object): + '''this class receives and list of rules and creates: + (a) tuples that represents each constraint. + (b) the int value of each tuple. + (c) log + ''' + def __init__(self,state_space,op_widths,rules,nt_name,default_action,log): + self.state_space = state_space + self.op_widths = op_widths + self.rules = rules + self.nt_name = nt_name + self.default_action = default_action + self.log = log + self.tuple2rule = {} + self.tuple2int = {} + self.tuple2conditions = {} + self.int2tuple = {} + + def work(self): + self.cnames = self._capture_cnames() + self._make_tuple2rule() + self._gen_tuple2int() + self.strings_dict = encutil.enc_strings + + def _capture_cnames(self): + ''' capture the superset of all constraint names ''' + + if not self.rules: + return [] + + cnames = set() + for rule in self.rules: + cnames.update(set(rule.cdict.keys())) + cnames = list(cnames) + cnames.sort() + if not cnames: + msg = "XED found rules without any constraints in nt %s" + genutil.die(msg % self.nt_name) + return cnames + def _make_tuple2rule(self): + ''' generate the tuple that represents the constraint + e.g.: for the constraint: MODE=0 EASZ=1 + the tuple is (0,1) + if a rule does not have constraint over certain operand then + we splatter all the possible values ''' + verbose=False + if verbose: print "_make_tuple2rule" + for rule in self.rules: + #print "\t RULE", str(rule) + # ctup is a list of tuples of all possible value + # combinations for the constraints. + ctup = [] + first = True + for cname in self.cnames: + if verbose: print "CNAME: {}".format(cname) + new_ctup = [] + if cname in rule.cdict: + vals = rule.cdict[cname] + if verbose: print "\tTHIS RULE VALS: {}".format(vals) + else: + vals = self.state_space[cname] + if verbose: print "\tSTATE SPACE VALS: {}".format(vals) + if first: + first = False + for val in vals: + ctup.append((val,)) + if verbose:print "\tFIRST CTUP: {}".format(ctup) + continue + else: + # cross product of constraints + for val in vals: + for c in ctup: + new_ctup.append(c+(val,)) + if verbose: print "\tNEW_CTUP: {}".format(new_ctup) + ctup = new_ctup + for tuple in ctup: + if tuple not in self.tuple2rule: + if verbose: print "TUPLE: {} RULE: {}".format(tuple, rule) + self.tuple2rule[tuple] = rule + self.tuple2conditions[tuple] = rule.conditions + else: + err = "in nt {}\n".format(self.nt_name) + err += "generated tuple for constraint {} already exists\n" + err = err.format(str(rule.cdict)) + if verbose: print err + genutil.die(err) + + def _gen_tuple2int(self): + ''' generate the int value of each tuple. + we shift each element by the number of bits that the previous + element took ''' + + for tuple in self.tuple2rule: + res = 0 + bit_shift = 0 + for i,byte in enumerate(tuple): + if self.cnames[i] == 'UIMM0': + pass + opwidth = self.op_widths[self.cnames[i]] + res += byte << bit_shift + bit_shift += opwidth + + if res not in self.int2tuple: + self.tuple2int[tuple] = res + self.int2tuple[res] = tuple + else: + conflict_tuple = self.int2tuple[res] + err = "conflict in nt: %s\n" % self.nt_name + err += "tuple %s = %s\n" + err =err % (str(tuple),self.tuple2conditions[tuple]) + err += "and tuple: %s = %s\n" + err =err % (str(conflict_tuple), + self.tuple2conditions[conflict_tuple]) + err += "generate the same int value: %d" % res + genutil.die(err) + + def filter_tuples(self,tuples): + ''' create new cvg that contains only the tuples in the input ''' + + new_cdict = copy.copy(self) + new_cdict.tuple2rule = {} + new_cdict.tuple2int = {} + new_cdict.tuple2conditions = {} + for t in tuples: + new_cdict.tuple2rule[t] = self.tuple2rule[t] + new_cdict.tuple2int[t] = self.tuple2int[t] + new_cdict.tuple2conditions[t] = self.tuple2conditions[t] + + + new_cdict.int2tuple = dict((i,t) for t,i in + new_cdict.tuple2int.iteritems()) + + return new_cdict + + def dump_log(self): + log = "nonterminal: %s\n" % self.nt_name + log += "cnames: %s\n" % str(self.cnames) + log += "{0:5} {1:15} {2}\n".format('int','tuple','conditions') + for val,tuple in sorted(self.int2tuple.items()): + log += "{0:<5} {1:<15} {2}\n".format(val, tuple, + self.tuple2conditions[tuple]) + log += "------------------------------------------------------------\n" + self.log.write(log) + + def no_constraints(self): + ''' return True if there are no constraints ''' + return len(self.tuple2conditions) == 0 + + def get_operand_accessor(self, cname): + ''' return the full function in order to access the operand given + in cname ''' + str = "%s_get_%s(%s)" % (self.strings_dict['op_accessor'],cname.lower(), + self.strings_dict['obj_str']) + return str, cname + + def get_ptrn(self, tuple): + ''' return the pattern for the give tuple ''' + return self.tuple2rule[tuple] + diff --git a/pysrc/ctables.py b/pysrc/ctables.py new file mode 100755 index 0000000..5f6082f --- /dev/null +++ b/pysrc/ctables.py @@ -0,0 +1,202 @@ +#!/usr/bin/env python +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import re,types,sys,os +import genutil +import codegen +import enum_txt_writer + +# emit XED_OPERAND_CONVERT_ enum +# emit mapping from XED_OPERAND_CONVERT_* enum to the arrays created here + + +def emit_convert_enum(converts,xeddir='.',gendir='obj'): + i = enum_txt_writer.enum_info_t(converts, xeddir, gendir, + 'xed-operand-convert', + 'xed_operand_convert_enum_t', + 'XED_OPERAND_CONVERT_', + cplusplus=False) + i.print_enum() + i.run_enumer() + return [i.src_full_file_name, i.hdr_full_file_name] + + +class constant_table_t(object): + """Create string constant lookup tables. Invalid error elements + are null strings. The inputs must be dense and ordered. FIXME: add + something that handles dont-cares, sorts, and fills in missing + entries. The input left hand column is ignored right now, and + assumed to be binary.""" + match_blank = re.compile(r'^$') + match_header = \ + re.compile(r'(?P[A-Za-z0-9_]+)[(](?P[A-Za-z0-9_]+)[)]::') + + match_pair = re.compile(r"""(?P[bxmA-F0-9_]+)[ \t]*[-][>][ \t]*['](?P[^']*)[']""") + + match_pair_error = \ + re.compile(r'(?P[bxmA-F0-9_]+)[ \t]*[-][>][ \t]*error') + + def __init__(self): + self.name=None + self.operand=None + self.value_string_pairs=[] + self.nlines = 0 + def valid(self): + if self.name != None: + return True + return False + def dump(self): + print "%s(%s)::" % (self.name, self.operand) + for (v,p) in self.value_string_pairs: + if isinstance(p, types.StringType): + print "%s '%s'" % (hex(v),p) + else: + print "%s error" %(hex(v)) + + def emit_init(self): + lines = [] + self.string_table_name = 'xed_convert_table_%s' % (self.name) + lines.append('static const char* %s[] = {' % (self.string_table_name)) + + for (v,p) in self.value_string_pairs: + if isinstance(p, types.StringType): + lines.append( '/*%s*/ "%s",' % (hex(v),p)) + else: + lines.append( '/*%s*/ 0, /* error */' % (hex(v))) + lines.append('};') + return lines + + + def read(self, lines): + """Read lines from lines until a new header or a blank line is reached""" + started = False + while 1: + if not lines: + break + self.nlines += 1 + line = lines[0] + line = line.strip() + line = re.sub(r'#.*','',line) + m= constant_table_t.match_blank.match(line) + if m: + del lines[0] + continue + + m= constant_table_t.match_header.match(line) + if m: + if started: + return + else: + started = True + del lines[0] + self.name = m.group('name') + self.operand = m.group('operand') + continue + m = constant_table_t.match_pair.match(line) + if m: + value = m.group('value') + symbol = m.group('symbol') + numeric_value = genutil.make_numeric(value) + #print "INPUT: [%s] [%s]" % (value,symbol) + self.value_string_pairs.append((numeric_value,symbol)) + del lines[0] + continue + m = constant_table_t.match_pair_error.match(line) + if m: + value = m.group('value') + numeric_value = genutil.make_numeric(value) + self.value_string_pairs.append((numeric_value,None)) + del lines[0] + continue + else: + genutil.die("Could not parse line %d: [%s]\n\n" % (self.nlines,line)) + + + + +def work(lines, xeddir = '.', gendir = 'obj'): + tables = [] + while lines: + y = constant_table_t() + y.read(lines) + #y.dump() + olines = y.emit_init() + #for l in olines: + # print l + tables.append(y) + + tables=filter(lambda(x): x.valid() , tables) + names=map(lambda(x): x.name , tables) + + srcs = emit_convert_enum(['INVALID'] + names, xeddir, gendir) + src_file_name = 'xed-convert-table-init.c' + hdr_file_name = 'xed-convert-table-init.h' + xfe = codegen.xed_file_emitter_t(xeddir, gendir, src_file_name) + xfe.add_header(hdr_file_name) + xfe.start() + + hfe = codegen.xed_file_emitter_t(xeddir, + gendir, + hdr_file_name) + hfe.start() + + xfe.add_code('xed_convert_table_t xed_convert_table[XED_OPERAND_CONVERT_LAST];') + + for t in tables: + l = t.emit_init() + l = map(lambda(x): x+'\n', l) + xfe.writelines(l) + fo = codegen.function_object_t('xed_init_convert_tables', 'void') + + s1 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].table_name = %s;' % ('INVALID', '0') + s2 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].limit = %s;' % ('INVALID', '0') + s3 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].opnd = %s;' % ('INVALID', 'XED_OPERAND_INVALID') + fo.add_code(s1) + fo.add_code(s2) + fo.add_code(s3) + + for t in tables: + s1 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].table_name = %s;' % (t.name, t.string_table_name) + s2 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].limit = %s;' % (t.name, len(t.value_string_pairs)) + s3 = 'xed_convert_table[XED_OPERAND_CONVERT_%s].opnd = %s;' % (t.name, t.operand) + fo.add_code(s1) + fo.add_code(s2) + fo.add_code(s3) + + fo.emit_file_emitter(xfe) + xfe.close() + + hdr = [] + hdr.append("typedef struct {\n") + hdr.append(" const char** table_name;\n") + hdr.append(" xed_operand_enum_t opnd;\n") # which operand indexes the table! + hdr.append(" unsigned int limit;\n") + hdr.append("} xed_convert_table_t;") + hdr.append("extern xed_convert_table_t xed_convert_table[XED_OPERAND_CONVERT_LAST];") + hfe.writelines(map(lambda(x): x+'\n', hdr)) + hfe.close() + + srcs.append(hfe.full_file_name) + srcs.append(xfe.full_file_name) + return srcs + +if __name__ == '__main__': + import sys + lines = file(sys.argv[1]).readlines() + srcs = work(lines,xeddir='.',gendir='obj') + print "WROTE: ", "\n\t".join(srcs) diff --git a/pysrc/encutil.py b/pysrc/encutil.py new file mode 100755 index 0000000..3a839ce --- /dev/null +++ b/pysrc/encutil.py @@ -0,0 +1,43 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import ildutil + +""" +dictionary of string to string. +used to provided a layer of abstraction +""" +enc_strings = {'key_str':'key', + 'hidx_str':'hidx', + 'key_type':'xed_uint64_t', + 'hidx_type':'xed_uint64_t', + 'obj_str':'xes', + 'obj_type':'xed_encoder_request_t', + 'nt_prefix':'xed_encode_nonterminal', + 'ntluf_prefix':'xed_encode_ntluf', + 'fb_type':'xed_int8_t', + 'nt_fptr':'xed_nt_func_ptr_t', + 'ntluf_fptr':'xed_ntluf_func_ptr_t', + 'obj_const': '', + 'lu_namespace':'enc', + 'emit_util_function':'xed_encoder_request_encode_emit', + 'static':False + } +enc_strings.update(ildutil.xed_strings) + + diff --git a/pysrc/enum_txt_writer.py b/pysrc/enum_txt_writer.py new file mode 100755 index 0000000..f21cffd --- /dev/null +++ b/pysrc/enum_txt_writer.py @@ -0,0 +1,170 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# Enumeration support +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# subprocess requires python 2.4 (replaces all os.popen() ) +import os +import sys +import re +import types + +import codegen +import enumer +import genutil + +################################################################################### + +class enum_info_t(object): + """This class can build enumeration txt files for offline + generation and it can also emit the enumeration by calling in to + the enumer.py module""" + + def __init__(self, + lines, + xeddir, + gendir, + base_name, + type_name, + prefix, + namespace='XED', + stream_ifdef='XED_PRINT', + cplusplus=True, + proto_prefix='XED_DLL_EXPORT', + extra_header="xed-common-hdrs.h", + upper_case=True, + density='automatic', + string_convert=True): + self.cplusplus = cplusplus + self.lines = lines + self.tuples = None # list [enumer.enumer_value_t] objects + self.gendir = gendir + self.xeddir = xeddir + self.base_name = base_name + self.type_name = type_name + self.prefix = prefix + self.proto_prefix = proto_prefix + self.extra_header = extra_header # could be a list + self.upper_case= upper_case + self.density = density + self.string_convert = string_convert + self.file_emitter = \ + codegen.xed_file_emitter_t(xeddir, + gendir, + self.base_name +'-enum.txt', + shell_file=True) + self.base_fn = self.base_name + '-enum' + if self.cplusplus: + self.cfn = self.base_fn + '.cpp' + self.hfn = self.base_fn + '.H' + else: + self.cfn = self.base_fn + '.c' + self.hfn = self.base_fn + '.h' + self.namespace = namespace + self.stream_ifdef = stream_ifdef + + def set_namespace(self,namespace): + self.namespace = namespace + + def print_enum_header(self,fp): # private + fp.write('namespace %s\n' % self.namespace) + fp.write('cfn %s\n' % self.cfn) + fp.write('hfn %s\n' % self.hfn) + fp.write('typename %s\n' % self.type_name) + fp.write('prefix %s\n' % self.prefix) + if self.stream_ifdef and self.stream_ifdef != '': + fp.write('stream_ifdef %s\n' % self.stream_ifdef) + if self.cplusplus: + fp.write("cplusplus\n") + if self.proto_prefix: + fp.write("proto_prefix %s\n" % self.proto_prefix) + if self.extra_header: + if isinstance(self.extra_header,types.ListType): + for f in self.extra_header: + fp.write("extra_header %s\n" % f) + else: + fp.write("extra_header %s\n" % self.extra_header) + + def prep_name(self,s): + if self.upper_case: + return s.upper() + return s + + def _print_lines(self, fp): # private + """print the lines""" + eol = '\n' + for line in self.lines: + if isinstance(line, enumer.enumer_value_t): + fp.write(self.prep_name(line.name) + eol) + elif type(line) == types.TupleType: + (token, val, comment) = line + fp.write(' '.join((self.prep_name(token), val, comment)) + eol) + else: + fp.write(self.prep_name(line) + eol) + def print_enum(self): # public + """emit the enumeration description file""" + self.file_emitter.start() + self.print_enum_header(self.file_emitter) + self._print_lines(self.file_emitter) + self.file_emitter.close() + + + def prepare_lines(self): + """Convert the lines to the appropriate type for emitting the + enumeration""" + self.tuples = [] + for line in self.lines: + if isinstance(line, enumer.enumer_value_t): + self.tuples.append(line) + elif type(line) == types.TupleType: + if len(line) == 3: + (token, value, comment) = line + else: + genutil.die("Cannot handle line: %s" % (str(line))) + token = self.prep_name(token) + self.tuples.append(enumer.enumer_value_t(token, value, comment)) + else: + token = self.prep_name(line) + self.tuples.append(enumer.enumer_value_t(token)) + + def run_enumer(self): # public + """Emit the enumeration""" + if self.tuples == None: + self.prepare_lines() + e = enumer.enumer_t(self.type_name, + self.prefix, + self.tuples, + self.cfn, + self.hfn, + self.gendir, + self.namespace, + self.stream_ifdef, + cplusplus = self.cplusplus, + proto_prefix=self.proto_prefix, + extra_header=self.extra_header, + density=self.density, + string_convert=self.string_convert) + e.emit() + self.hdr_full_file_name = e.hf.full_file_name + self.src_full_file_name = e.cf.full_file_name + + + + diff --git a/pysrc/enumer.py b/pysrc/enumer.py new file mode 100755 index 0000000..2fa88e1 --- /dev/null +++ b/pysrc/enumer.py @@ -0,0 +1,643 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import types +import re +import codegen + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + #print "Trying %s" % (target_dir) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None +sys.path.append(find_dir('mbuild')) +try: + import mbuild +except: + sys.stderr.write("\nERROR(enumer.py): Could not find mbuild. Might try setting PYTHONPATH env var.\n\n") + sys.exit(1) + +class enumer_value_t(object): + def __init__(self, name, value=None, doxygen=None, duplicate=False, display_str=None): + self.name = name + # display_str is a string to use for the parser. may contain + # values that are not valid enumeration characters (like + # parenthesis, etc.). display_str was added later and defaults + # to the value supplied for name. + if display_str: + self.display_str = display_str + else: + self.display_str = self.name + self.value=value + self.doxygen=doxygen + self.duplicate=duplicate + + def in_comment(self,s): + """is s substring in comment?""" + if self.doxygen: + if s in self.doxygen: + return True + return False + + + +def _make_str2foo(): + l = [ + "/// This converts strings to #%(type)s types.", + "/// @param s A C-string.", + "/// @return #%(type)s", + "/// @ingroup ENUM", + "%(prefix)s %(type)s str2%(type)s(const char* s)", + ] + s = "\n".join(l) + return s +def _make_foo2str(): + l = [ + "/// This converts strings to #%(type)s types.", + "/// @param p An enumeration element of type %(type)s.", + "/// @return string", + "/// @ingroup ENUM", + "%(prefix)s const char* %(type)s2str(const %(type)s p)" + ] + s = "\n".join(l) + return s + pass + + + + +class enumer_t(object): + def __init__(self, type_name, prefix, values, cfn, hfn, gendir, + namespace=None, stream_guard=None, + add_last_element=True, cplusplus=False, + proto_prefix='', extra_header=None, density='automatic', + string_convert=1 ): + """ + @type type_name: string + @param type_name: the name of the generated type + + @type prefix: string + @param prefix: prepended to all enumeration names + + @type values: list + @param values: list of L{enumer_value_t} objects + + @type cfn: string + @param cfn: output source file name + @type hfn: string + @param hfn: output header file name + + + @type gendir: string + @param gendir: output directory + + @type namespace: string + @param namespace: namespace wrapper + + @type stream_guard: string + + @param stream_guard: #ifdef test for ostream/istream functionality + + @type add_last_element: xed_bool_t + @param add_last_element: If True (defualt), add a _LAST element. + + @type cplusplus: xed_bool_t + @param cplusplus: True=>C++ or False=>C + + @type proto_prefix: string + @param proto_prefix: default is empty string. useful for DLL export decorations + + @type extra_header: string or list + @param extra_header: another header to include in the .H file. + + @type density: string + @param density: density of enumerated values. Can be sparse (default) or dense. Default is automatic which use the presense or absence of preset values to determine density + + @type string_convert: integer + @param string_convert: 1=default, generate convert routines, 0=empty stubs, -1=no-stubs or prototypes + """ + self.debug = False + self.proto_prefix = proto_prefix + + self.cplusplus = cplusplus + self.type_name = type_name + self.prefix = prefix + self.cfn = cfn + self.hfn = hfn + self.density = density + self.string_convert = string_convert + self.extra_header = extra_header + self.values= self._unique(values) # list of enumer_value_t's + + self.can_be_dense = True + self.preset_values = self._scan_for_preset_values(self.values) + if self.preset_values: + self.can_be_dense = \ + self._scan_for_dense_zero_based_preset_values(self.values) + + #sys.stderr.write("Can be dense %s\n" % (str(self.can_be_dense))) + #sys.stderr.write("Preset values %s\n" % (str(self.preset_values))) + + if self.density == 'automatic': + if self.can_be_dense: + self.density = 'dense' + else: + self.density = 'sparse' + + if self.preset_values and \ + self.can_be_dense == False and \ + self.density == 'dense': + sys.stderr.write("\nERROR(enumer.py): dense enum had some values specified preventing dense-enum generation\n\n") + sys.exit(1) + + self.add_last_element = add_last_element + if add_last_element: + self.values.append(enumer_value_t('LAST')) + + (unique, duplicates) = self._partition_duplicates(self.values) + # clobber the values with just the unique values + self.values = unique + self.duplicates = duplicates + + self.namespace=namespace + self.stream_guard=stream_guard + self.system_headers = [ "string.h" ] + if self.cplusplus: + self.system_headers.append("cassert") + self.system_headers.append("string") + else: + self.system_headers.append('assert.h') + + + self.convert_function_headers = [ _make_str2foo(), _make_foo2str() ] + + if self.cplusplus: + self.ostream_function_headers = ['std::ostream& operator<<(std::ostream& o, const %s& v)', + 'std::istream& operator>>(std::istream& o, %s& v)' ] + self.operator_function_headers = ['%s& operator++(%s& x, int)', + '%s& operator--(%s& x, int)' ] + else: + self.ostream_function_headers = [] + self.operator_function_headers = [] + + + if self.cplusplus: + namespace = self.namespace + else: + namespace = None + + full_header_file_name = mbuild.join(gendir,self.hfn) + self.hf = codegen.file_emitter_t(gendir, self.hfn, + namespace=namespace) + if type(self.extra_header) == types.ListType: + for hdr in self.extra_header: + self.hf.add_header(hdr) + elif self.extra_header: + self.hf.add_header(self.extra_header) + + full_source_file_name = mbuild.join(gendir,self.cfn) + self.cf = codegen.file_emitter_t(gendir, self.cfn, + namespace=namespace) + self.cf.add_header(self.hfn) + + for sh in self.system_headers: + self.cf.add_system_header(sh) + + if self.cplusplus: + if self.stream_guard and self.stream_guard != '': + self.hf.add_misc_header("#if %s==1" % self.stream_guard) + self.hf.add_misc_header("# include ") + self.hf.add_misc_header("#endif") + else: + self.hf.add_misc_header("#include ") + self.hf.start() + self.cf.start() + + def emit(self): + self._emit_header_file() + self._emit_source_file() + self._close() + ####################################################### + def _scan_for_preset_values(self, vals): + for v in vals: + if v.value != None: + return True + return False + def _make_number(self, s): + if re.match(r'^0x',s): + return (True,int(s,16)) + if re.match(r'^[0-9]*$',s): + return (True,int(s,10)) + return (False,s) + + def _partition_duplicates(self, vals): + duplicates = [] + unique = [] + for v in vals: + if v.duplicate: + duplicates.append(v) + else: + unique.append(v) + return (unique,duplicates) + def _scan_for_dense_zero_based_preset_values(self, vals): + """Scan the list of values, and check that each one has the + expected zero-based value, or no specified value (as often + happens with the LAST element). Return True if it dense and + zero based. """ + if self.debug: + print "SCAN FOR DENSE" + b = 0 + n = 0 + for v in vals: + if self.debug: + print "\tTESTING [%s]->[%s]" % (v.name, str(v.value)) + if v.value == None: + b = b + 1 + n = n + 1 + continue + (is_number,ov) = self._make_number(v.value) + if self.debug: + print "\t\t isnum=%s %s" % ( str(is_number), str(ov)) + if is_number and ov == b: + b = b + 1 + n = n + 1 + continue + # if it matches a previous value then it can still be dense, + # but we must not put this value in the value-2-string + # table. It must be in a separate string2value table. + #print "\t\t [%s]" % ( str(vals[0:n])) + previous_values = map(lambda(x): x.name, vals[0:n]) + if self.debug: + print "\t\t [%s]" % ( str(previous_values)) + if v.value in previous_values: + v.duplicate = True + n = n + 1 + continue + if self.debug: + print "\t\t Not in previous values" + return False + return True + def _unique(self, vals): + """Return a list of unique values, given a list of + enumer_value_t objects""" + uvals = {} + for v in vals: + if v.name in uvals: + if uvals[v.name].value != v.value: + sys.stderr.write("ENUMER ERROR: duplicate key name in enumeration with different values: %s\n" % v.name) + sys.exit(1) + uvals[ v.name ] = v + + # attempt to preserve the order of the values in the returned sequence. + # make sure INVALID is first though! + ovals = [] + if 'INVALID' in uvals: + ovals.append(uvals['INVALID']) + del uvals['INVALID'] + for v in vals: + if v.name in uvals: + ovals.append(uvals[v.name]) + del uvals[v.name] + return ovals + def _close(self): + self.cf.close() + self.hf.close() + + def _emit_header_file(self): + self._emit_typedef() + if self.string_convert >= 0: + self._emit_convert_protos() + if self.add_last_element: + self._emit_last_fn_proto() + if self.cplusplus: + self._emit_ostream_protos() + self._emit_operators_protos() + + def _emit_source_file(self): + if self.string_convert == 1: + self._emit_name_table_type() + self._emit_name_table() + self._emit_duplicate_name_table() + self._emit_converts() + elif self.string_convert == 0: + self._emit_convert_stubs() + if self.add_last_element: + self._emit_last_fn() + if self.cplusplus: + self._emit_ostream() + self._emit_operators() + self._emit_comment() + + def _emit_typedef(self): + max = len(self.values) + len(self.duplicates) + self.hf.emit_eol("typedef enum {") + for i,v in enumerate(self.values): + self.hf.emit(" %s%s" % (self.prefix,v.name)) + if v.value != None: + self.hf.emit("=%s" % v.value) + if i < max-1: + self.hf.emit(',') + if v.doxygen != None: + self.hf.emit(" %s" % v.doxygen) + self.hf.emit_eol() + + if len(self.duplicates) == 0: + self.hf.emit_eol("} %s;" % self.type_name) + self.hf.emit_eol() + return + + bias = len(self.values) + for i,v in enumerate(self.duplicates): + self.hf.emit(" %s%s" % (self.prefix,v.name)) + if v.value != None: + if v.duplicate: + self.hf.emit("=%s%s" % (self.prefix,v.value)) + else: + self.hf.emit("=%s" % v.value) + if i+bias < max-1: + self.hf.emit(',') + if v.doxygen != None: + self.hf.emit(" %s" % v.doxygen) + self.hf.emit_eol() + + self.hf.emit_eol("} %s;" % self.type_name) + self.hf.emit_eol() + + def _emit_convert_protos(self): + for x in self.convert_function_headers: + d = { 'type' : self.type_name, + 'prefix' : self.proto_prefix } + self.hf.add_code_eol(x % (d)) + self.hf.emit_eol() + + def _emit_ostream_protos(self): + if self.stream_guard and self.stream_guard != '': + self.hf.emit_eol("#if %s==1" % self.stream_guard) + for x in self.ostream_function_headers: + t = "%s " + x + self.hf.add_code_eol(t % (self.proto_prefix,self.type_name)) + if self.stream_guard and self.stream_guard != '': + self.hf.emit_eol("#endif") + self.hf.emit_eol() + def _emit_operators_protos(self): + for x in self.operator_function_headers: + t = "%s " + x + self.hf.add_code_eol(t % \ + (self.proto_prefix, self.type_name, self.type_name)) + self.hf.emit_eol() + + def _emit_name_table_type(self): + nt_string = """ +typedef struct { + const char* name; + %(type)s value; +} name_table_%(type)s;""" + self.cf.emit_eol(nt_string % {'type':self.type_name}) + + def _emit_name_table(self): + s = "static const name_table_%(type)s name_array_%(type)s[] = {" + self.cf.emit_eol(s % {'type':self.type_name}) + for v in self.values: + s = """{"%s", %s%s},""" % (v.display_str,self.prefix,v.name) + self.cf.emit_eol(s) + s = "{%s, %s%s}," % ('0',self.prefix,self.values[-1].name) + self.cf.emit_eol(s) + self.cf.emit_eol('};') + + def _emit_duplicate_name_table(self): + if len(self.duplicates) == 0: + return + + s = "static const name_table_%(type)s dup_name_array_%(type)s[] = {" + self.cf.emit_eol(s % {'type':self.type_name}) + for v in self.duplicates: + s = """{"%s", %s%s},""" % (v.display_str,self.prefix,v.name) + self.cf.emit_eol(s) + s = "{%s, %s%s}," % ('0',self.prefix,self.values[-1].name) + self.cf.emit_eol(s) + self.cf.emit_eol('};') + + def _invalid_or_last(self): + for v in self.values: + if v.name == 'INVALID': + return 'INVALID' + return self.values[-1].name + + def _emit_last_fn_proto(self): + """Emit a function that returns the LAST element""" + l = [ + "/// Returns the last element of the enumeration", + "/// @return %(type)s The last element of the enumeration.", + "/// @ingroup ENUM", + "%(proto_prefix)s %(type)s %(type)s_last(void);" + ] + s = "\n".join(l) + self.hf.emit_eol(s % {'type':self.type_name, + 'proto_prefix':self.proto_prefix} ) + + def _emit_last_fn(self): + """Emit a function that returns the LAST element""" + s = """ +%(type)s %(type)s_last(void) { + return %(prefix)sLAST; +} + """ + self.cf.emit_eol(s % {'type':self.type_name, 'prefix':self.prefix} ) + + def _emit_convert_stubs(self): + self._emit_str2enum_convert_stub() + self._emit_enum2str_convert_stub() + def _emit_str2enum_convert_stub(self): + """Emit a fake from-string converter that always returns invalid""" + top = """ +%(type)s str2%(type)s(const char* s) +{ + return %(prefix)s%(invalid)s; + (void)s; +}""" + invalid = self._invalid_or_last() + d = {'type':self.type_name, + 'prefix':self.prefix, + 'invalid':invalid} + self.cf.emit_eol(top % (d)) + + def _emit_enum2str_convert_stub(self): + """Emit a fake to-string converter that always returns invalid""" + s = """ +const char* %(type)s2str(const %(type)s p) +{ + return "INVALID"; + (void)p; +}""" + invalid = self._invalid_or_last() + self.cf.emit_eol(s % {'type':self.type_name, + 'prefix':self.prefix, + 'invalid':invalid}) + + def _emit_converts(self): + self._emit_str2enum_convert() + self._emit_enum2str_convert() + + def _emit_str2enum_convert(self): + top = """ + +%(type)s str2%(type)s(const char* s) +{ + const name_table_%(type)s* p = name_array_%(type)s; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + """ + dups = """ + { + const name_table_%(type)s* q = dup_name_array_%(type)s; + while( q->name ) { + if (strcmp(q->name,s) == 0) { + return q->value; + } + q++; + } + } + """ + end = """ + return %(prefix)s%(invalid)s; +}""" + + invalid = self._invalid_or_last() + d = {'type':self.type_name, + 'prefix':self.prefix, + 'invalid':invalid} + self.cf.emit_eol(top % (d)) + if self.duplicates: + self.cf.emit_eol(dups % (d)) + self.cf.emit_eol(end % (d)) + + def _emit_enum2str_convert(self): + if (self.density == 'sparse'): + self._emit_sparse_enum2str_convert() + else: + self._emit_dense_enum2str_convert() + + def _emit_sparse_enum2str_convert(self): + s = """ + +const char* %(type)s2str(const %(type)s p) +{ + const name_table_%(type)s* q = name_array_%(type)s; + while( q->name ) { + if (q->value == p) { + return q->name; + } + q++; + } + return "???"; +}""" + + invalid = self._invalid_or_last() + self.cf.emit_eol(s % {'type':self.type_name, + 'prefix':self.prefix, + 'invalid':invalid}) + + def _emit_dense_enum2str_convert(self): + + s = """ + +const char* %(type)s2str(const %(type)s p) +{ + %(type)s type_idx = p; + if ( p > %(prefix)sLAST) type_idx = %(prefix)sLAST; + return name_array_%(type)s[type_idx].name; +}""" + + invalid = self._invalid_or_last() + self.cf.emit_eol(s % {'type':self.type_name, + 'prefix':self.prefix, + 'invalid':invalid}) + + def _emit_ostream(self): + s = """ + +std::ostream& operator<<(std::ostream& o, const %(type)s& v) { + o << %(type)s2str(v); + return o; +} + +std::istream& operator>>(std::istream& i, %(type)s& v) { + std::string s; + i >> s; + v = str2%(type)s( s.c_str() ); + return i; +}""" + if self.stream_guard and self.stream_guard != '': + self.cf.emit_eol("#if %s==1" % self.stream_guard) + self.cf.emit_eol(s % {'type':self.type_name}) + if self.stream_guard and self.stream_guard != '': + self.cf.emit_eol("#endif") + + + def _emit_operators(self): + s = """ +%(type)s& operator++(%(type)s& x, int) +{ + return x = %(type)s(x+1); +} +%(type)s& operator--(%(type)s& x, int) +{ + return x = %(type)s(x-1); +}""" + self.cf.emit_eol(s % {'type':self.type_name}) + + def _emit_comment(self): + self.cf.emit_eol("/*") + self.cf.emit_eol() + self.cf.emit_eol("Here is a skeleton switch statement embedded in a comment") + self.cf.emit_eol() + self.cf.emit_eol() + self.cf.emit_eol(" switch(p) {") + for v in self.values: + self.cf.emit_eol(" case %s%s:" % (self.prefix, v.name)) + self.cf.emit_eol(" default:") + self.cf.emit_eol(" xed_assert(0);") + self.cf.emit_eol(" }") + self.cf.emit_eol("*/") + + +def _test_enumer(): + values = map(enumer_value_t, ['aaa','bbb','ccc']) + e = enumer_t("test_type_t", "TEST_TYPE_", values, + "enumer-test.cpp", "enumer-test.H", ".", + namespace = "XED", + stream_guard ="XEDPRINT") + e.emit() + +if __name__ == '__main__': + _test_enumer() diff --git a/pysrc/flag_gen.py b/pysrc/flag_gen.py new file mode 100755 index 0000000..fefee5e --- /dev/null +++ b/pysrc/flag_gen.py @@ -0,0 +1,577 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# FIXME: could cut table sizes by rusing identical entries in the +# simple flags table. 2007-05-02 + +import re +import os +import sys +from genutil import * + +def _convert_to_list_of_string(x): + return map(lambda a: str(a), x) +def _curly_list(x): + return ('{' + ','.join(x) + '},') +def _curly_string(x): + return ('{' + x + '}') + +class flag_set_t(object): + field_pairs = [('cf',1), ('must_be_1',1), + ('pf',1), ('must_be_0a',1), + ('af',1), ('must_be_0b',1), + ('zf',1), ('sf',1), + ('tf',1), ('_if',1), + ('df',1), ('of',1), + ('iopl',2), # 2b wide field + ('nt',1), ('must_be_0c',1), + ('rf',1), ('vm',1), + ('ac',1), ('vif',1), + ('vip',1), ('id',1), + ('must_be_0d',2), + ('must_be_0e',4), + + # not part of [er]flags, just stored that way for convenience. + ('fc0',1), + ('fc1',1), + ('fc2',1), + ('fc3',1) ] + field_names = map(lambda x: x[0], field_pairs) + + def __init__(self, very_technically_accurate=False): + for (f,w) in flag_set_t.field_pairs: + if very_technically_accurate and f.startswith('must_be_1'): + setattr(self,f,1) + else: + setattr(self,f,0) + + def set(self,fld,val=1): + if fld == 'if': + fld = '_if' # recode this one to avoid keyword clash + if fld == 'iopl': + val = 3 # turn on both bits for IOPL. Just a convention + + if fld in flag_set_t.field_names: + setattr(self,fld,val) + else: + die("Bad flags field name: {}".format(fld) ) + + def as_integer(self): + s = 0 + n = 0 + for (f,w) in flag_set_t.field_pairs: + mask = (1<.*)\s+[[](?P.*)[]]') + def __init__(self,input_chunk): + self.qualifier = None + self.may_must = None # Could be READONLY, MAY or MUST, REP_MAY + self.flag_actions = [] # [ flag_action_t ] + m = flags_rec_t._flag_pattern.search(input_chunk) + if m: + flags_input = m.group('flags').strip().split() + qualifiers = m.group('qualifiers').strip().split() + else: + die("Could not find flags in %s" % input_chunk) + + first = qualifiers[0] + if first in flags_rec_t.valid_flags_qualifiers: + self.qualifier = first + qualifiers.pop(0) + self.may_must = qualifiers[0] + if self.may_must not in flags_rec_t.valid_flags_semantics_specifiers: + die("Invalid flags specification: %s" % input_chunk) + + self.read_set = flag_set_t() + self.write_set = flag_set_t() + self.undefined_set = flag_set_t() + + self.flag_action_index = -1 + self.simple_id = -1 + + for flag_action_str in flags_input: + fa = flag_action_t(flag_action_str) + self.flag_actions.append(fa) + if fa.flag: + if fa.reads_flag(): + self.read_set.set(fa.flag) + if fa.writes_flag(): + self.write_set.set(fa.flag) + if fa.makes_flag_undefined(): + self.undefined_set.set(fa.flag) + else: + sys.stderr.write("Bogus flag: {}\n".format(flag_action_str)) + + def get_number_of_flag_actions(self): + return len(self.flag_actions) + + def get_flag_action_index(self): + return self.flag_action_index + def set_flag_action_index(self,n): + self.flag_action_index = n + def get_simple_id(self): + return self.simple_id + def set_simple_id(self,n): + self.simple_id = n + + def x86_flags(self): + """Return True if any of the flags are x86 flags. False otherwise""" + for flag_action in self.flag_actions: + s = flag_action.flag + if s != 'fc0' and s != 'fc1' and s != 'fc2' and s != 'fc3': + return True + return False + + def reads_flags(self): + for fa in self.flag_actions: + if fa.reads_flag(): + return True + return False + def writes_flags(self): + for fa in self.flag_actions: + if fa.writes_flag(): + return True + return False + def conditional_writes_flags(self): + if self.writes_flags() and (self.may_must == 'MAY' or self.may_must == 'REP_MAY'): + return True + return False + + def is_simple(self): + if self.qualifier == None: + return True + return False + def is_complex(self): + if self.qualifier != None: + return True + return False + def is_rep(self): + if self.qualifier == 'REP' or self.qualifier == 'NOREP': + return True + return False + def is_imm(self): + if self.qualifier == 'IMM0' or \ + self.qualifier == 'IMM1' or \ + self.qualifier == 'IMMx': + return True + return False + + def __str__(self): + s = [] + if self.qualifier != None: + s.append(self.qualifier) + s.append(self.may_must) + s.append('[') + s.extend(map(str,self.flag_actions)) + s.append(']') + return ' '.join(s) + + def is_nothing(self): + if len(self.flag_actions) == 1: + fa = self.flag_actions[0] + if fa.is_nothing(): + return True + return False + + def emit_code(self, prefix,fo): + for fa in self.flag_actions: + if fa.flag: + s = "xed_simple_flag_set_flag_action(%s,XED_FLAG_%s,XED_FLAG_ACTION_%s)" % \ + (prefix, fa.flag, fa.action) + fo.add_code_eol(s) + + def identifier(self,limit=99): + s = [] + for i,fa in enumerate(self.flag_actions): + if not fa.flag: + die("Bogus flag!") + s.append("{}-{}".format(fa.flag, fa.action)) + if i >= limit: + break + return ":".join(s) + + def emit_data_record(self, fo): + for i,fa in enumerate(self.flag_actions): + if not fa.flag: + die("Bogus flag!") + s = "/* {} */ {{ XED_FLAG_{},XED_FLAG_ACTION_{} }},".format( + self.get_flag_action_index() + i, fa.flag, fa.action) + fo.add_code(s) + +# Need to emit 3 tables: +# xed_flag_action_t array +# xed_simple_flag_t array +# xed_complex_flag_t array +# +# constraint: need hand out indices to the simple and complex table as +# instructions are encountered during code gen so that I can give the +# instruction record the index to the complex or simple flags table. +# +# most instructions are simple flags and have one simple record per +# instruction some are complex and have multiple simple flags records +# per instruction. +# + + + +class flags_info_t(object): + """Collection of flags_rec_t records""" + + _flag_simple_rec = 1 + _flag_complex_rec = 1 + _max_actions_per_simple_flag = 0 + _max_flag_actions = 0 + # for unique-ifying the flag-actions array. + _fa_table = {} + _fr_table = {} + + def __init__(self,input_line): + # flags_recs is a list of flag_rec_t's. Usually 0 or 1. Sometimes 3 + if input_line != '': + lst = input_line.split(',') + self.flags_recs = map(lambda(x): flags_rec_t(x.strip()), lst) + else: + self.flags_recs = [] + + self.complex_id = -1 + def set_complex_id(self,n): + self.complex_id = n + def get_complex_id(self,n): + return self.complex_id + + def __str__(self): + s = ', '.join(map(str,self.flags_recs)) + return s + + def x87_flags(self): + """Return True if all the flags are x87 flags. And False if any are x86 flags""" + for fr in self.flags_recs: + if fr.x86_flags(): + return False + return True + + def x86_flags(self): + """Return True if any flags are x86 flags""" + for fr in self.flags_recs: + if fr.x86_flags(): + return True + return False + + + def rw_action(self): + """Return one of: r, w, cw, rcw or rw. This is the r/w action + for a rFLAGS() NTLUF.""" + r = '' + w = '' + c= '' + has_nothing_record = False + for fr in self.flags_recs: + if fr.is_nothing(): + has_nothing_record=True + if fr.reads_flags(): + r = 'r' + if fr.writes_flags(): + w = 'w' + if fr.conditional_writes_flags(): + # things that are conditional writes are also writes + c = 'c' + + if has_nothing_record: + c = 'c' + retval = "%s%s%s" % (r,c,w) + return retval + + def make_case_name(self,qualifier): + if qualifier == 'IMMx': + return 'IMMED_OTHER' + elif qualifier == 'IMM0': + return 'IMMED_ZERO' + elif qualifier == 'IMM1': + return 'IMMED_ONE' + elif qualifier == 'REP': + return 'HAS_REP' + elif qualifier == 'NOREP': + return 'NO_REP' + else: + die("Unhandled flags qualifier: %s" % qualifier) + + def is_complex(self): + for x in self.flags_recs: + if x.is_complex(): + return True + return False + + def is_rep(self): + for x in self.flags_recs: + if x.is_rep(): + return True + return False + + def is_imm(self): + for x in self.flags_recs: + if x.is_imm(): + return True + return False + + + def _compute_assign_flag_action_id(self, fr, fo_flag_actions): + + # compute an identifying string as an identifer of the (flag, action)+ sequence + id = fr.identifier() + + try: + t = flags_info_t._fa_table[id] + is_new = False + except: + is_new = True + t = flags_info_t._max_flag_actions + # skip ahead by # of (flag,actions) entries + flags_info_t._max_flag_actions += fr.get_number_of_flag_actions() + + # install all the prefixes of the current flag-action group that + # share the same starting point for extra compression + + # FIXME: could do all possible singletons and subranges. + for i in range(0,fr.get_number_of_flag_actions()): + id = fr.identifier(i) + flags_info_t._fa_table[id] = t + + # set the flag_action index + fr.set_flag_action_index( t ) + + if is_new: + # emit the flag actions (using the indices assigned above) + fr.emit_data_record(fo_flag_actions) + + return t + + def emit_data_record(self, fo_simple, fo_complex, fo_flag_actions): + + # emit the simple flag records + # (a) remember and id/number for the flags records; complex flags need it later + # as do the instructions. + # (b) number the flag actions so that we can refer to them from the simple flag recs. + + flag_id = -1 + for fr in self.flags_recs: + + may = '1' if fr.may_must == 'MAY' else '0' + must = '1' if fr.may_must == 'MUST' else '0' + + s = [] + s.append( str( fr.get_number_of_flag_actions() )) + s.append(may) + s.append(must) + s.append(_curly_string(fr.read_set.as_hex())) + s.append(_curly_string(fr.write_set.as_hex())) + s.append(_curly_string(fr.undefined_set.as_hex())) + + flag_action_id = self._compute_assign_flag_action_id(fr, fo_flag_actions) + s.append(str(fr.get_flag_action_index())) + + t = _curly_list(s) + try: + # Attempt to reuse an identical flag record + flag_id = flags_info_t._fr_table[t] + is_new = False + except: + is_new = True + # Assign an id/number to the simple flag records. + # This gets used by the xed_inst_t to find the flags rec + # and by the complex flags to find the right simple flags. + flag_id = flags_info_t._flag_simple_rec + flags_info_t._flag_simple_rec += 1 + # remember pattern for later use + flags_info_t._fr_table[t] = flag_id + + fr.set_simple_id( flag_id ) + if is_new: + comment = '/* {} */ '.format(flag_id) + fo_simple.add_code( comment + t ) + + # emit the complex flag table + if self.is_complex(): + flag_id = flags_info_t._flag_complex_rec + self.set_complex_id( flag_id ) + flags_info_t._flag_complex_rec += 1 + + s = [] + s.append('1' if self.is_rep() else '0') + s.append('1' if self.is_imm() else '0') + + cases = [] + ordered_cases = ['IMMED_ZERO', # FIXME: IMMED_ZERO is unused + 'IMMED_ONE', + 'IMMED_OTHER', + 'HAS_REP', + 'NO_REP' ] + + # go through ordered cases, find a flag rec that matches + # and add it if found. + + for c in ordered_cases: + found = None + for fr in self.flags_recs: + cname = self.make_case_name(fr.qualifier) + if c == cname: + found = fr + break + if found: + cases.append( found.get_simple_id()) + else: + cases.append( 0 ) + if not cases: + die("Complex flag with no cases") + + cases = _convert_to_list_of_string(cases) + s.append(_curly_list(cases)) + comment = '/* {} */ '.format(flag_id) + fo_complex.add_code(comment + _curly_list(s)) + + + if flag_id == -1: + die("flag_id was not set") + if self.is_complex(): + return (flag_id, True) # True for complex + return (flag_id, False) # False for simple + + + def code_gen(self, itable_prefix_string, fo): # FIXME: DEAD: DELETE THIS + """ + - set xed_inst_t::_flag_info_index in to the index of one of the next 2 tables + - initialize the xed_flags_simple_table + - initialize the xed_flags_complex_table + + @type itable_prefix_string: string + @param itable_prefix_string: + @type fo: function_object_t + @param fo: the function object for the instruction we are initializing. + """ + + complex = self.is_complex() + if complex: + flags_info_t._flag_complex_rec += 1 + retval = (flags_info_t._flag_complex_rec, True) + + complex_prefix = "xed_flags_complex_table[%d]" % \ + (flags_info_t._flag_complex_rec) + if self.is_rep(): + fo.add_code_eol("%s.check_rep=1" % (complex_prefix)) + elif self.is_imm(): + fo.add_code_eol("%s.check_imm=1" % (complex_prefix)) + else: + die("Unhandled complex flags condition: %s" % str(self)) + else: # SIMPLE + retval = (flags_info_t._flag_simple_rec, False) + + for fr in self.flags_recs: + + if complex: + # emit the complex decider information for this record FIXME + case_name = self.make_case_name(fr.qualifier) + if fr.is_nothing(): + srec = 0 + else: + srec = flags_info_t._flag_simple_rec + + s="%s.cases[XED_FLAG_CASE_%s]=%d" % ( complex_prefix, + case_name, + srec) + fo.add_code_eol(s) + + + simple_prefix = "xed_flags_simple_table+%d" % \ + (flags_info_t._flag_simple_rec) + flags_info_t._flag_simple_rec += 1 + + may_must = None + if fr.may_must == 'MUST': + may_must = "xed_simple_flag_set_must_write" + elif fr.may_must == 'MAY': + may_must = "xed_simple_flag_set_may_write" + if may_must: + fo.add_code_eol("%s(%s)" % (may_must,simple_prefix)) + + # emit the individual bits + fr.emit_code(simple_prefix, fo) + + x = len(fr.flag_actions) + if x > flags_info_t._max_actions_per_simple_flag: + flags_info_t._max_actions_per_simple_flag = x + # track the max # of flag actions + flags_info_t._max_flag_actions += x + return retval + +def _testflags(): + """Test function for flag_set_t objects""" + a = flag_set_t() + a.set('cf') + a.set('zf') + a.set('of') + print a.as_integer() + print a.as_hex() + +if __name__ == '__main__': + _testflags() diff --git a/pysrc/func_gen.py b/pysrc/func_gen.py new file mode 100644 index 0000000..daa8598 --- /dev/null +++ b/pysrc/func_gen.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +import constraint_vec_gen # FIXME: not used, delete +import codegen +import actions +import ild_phash +import actions_codegen +import verbosity + + + +class func_gen_t(object): + def __init__(self,cvg, fname): + self.cvg = cvg # constraint vector generator + self.fname = fname + + def _gen_empty_function(self,fname): + ''' generate a function without constraints ''' + + return_type = 'xed_uint32_t' + fo = codegen.function_object_t(fname, + return_type=return_type, + static=False, + inline=False) + + obj_type = self.cvg.strings_dict['obj_type'] + obj_str = self.cvg.strings_dict['obj_str'] + arg = "%s* %s" % (obj_type, obj_str) + fo.add_arg(arg) + + lines = self.cvg.action_codegen.emit_default() + for line in lines: + if line == 'return ': + fo.add_code_eol('return 1') + else: + fo.add_code_eol(line) + fo.add_code_eol('(void)%s' % obj_str) + fo.add_code_eol('return 1') + return fo + + def gen_function(self): + ''' returns tuple of: + 1) list functions (we can have several functions in case we + need to levels of hashing) + 2) the operands lookup function (generates the key) + ''' + action_codegen = actions_codegen.actions_codegen_t(self.cvg.tuple2rule, + self.cvg.default_action, + self.cvg.strings_dict) + self.cvg.action_codegen = action_codegen + + if self.cvg.no_constraints(): + fo = self._gen_empty_function(self.fname) + return [fo], None + + phash = ild_phash.gen_hash(self.cvg) + if phash == None: + genutil.die("Failed to find perfect hash for %s" % self.fname) + if verbosity.vfuncgen(): + self.cvg.log.write("%s" % phash) + + fos, operand_lu_fo = phash.gen_find_fos(self.fname) + return fos, operand_lu_fo + + + + + + + + + + + + + + + + + + + + diff --git a/pysrc/gen-enum.py b/pysrc/gen-enum.py new file mode 100644 index 0000000..4548b57 --- /dev/null +++ b/pysrc/gen-enum.py @@ -0,0 +1,175 @@ +#!/usr/bin/env python +# -*- python -*- +######################################################## +# THIS IS NOT DONE YET... IGNORE FOR NOW +######################################################## +# Mark Charney +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# This is a front-end for the enumer program. It writes the config +# file used by the enumer. It currently generates operands, or +# iclasses enumerations, but could be generalized to do anything. + +# input: +# list of string s (iclasses, operands, field tokns) from the graph builder + +# output: +# file for use with the enumer + +import os +import sys +import re + + +############################################################################ +# Messages +def msge(s): + sys.stderr.write(s + '\n') +def msg(s): + sys.stdout.write(s + '\n') +def msgn(s): + sys.stdout.write(s) + +def cond_die(v, cmd, msg): + if v != 0: + s = msg + '\n [CMD] ' + cmd + die(s) + +def die(m): + msge('[ERROR] ' + m) + sys.exit(1) +def warn(m): + msg('[WARNING] ' + m) + +############################################################################ + +# Require python 2.4 (or later) for this script +def check_python_version(): + tuple = sys.version_info + major = tuple[0] + minor = tuple[1] + if (major > 2 ) or \ + (major == 2 and minor >= 4): + return + die('Need Python version 2.4 or later.') + +check_python_version() + +import glob +import re +#import time +#import tempfile +#import platform # requires python 2.3 +#import subprocess # requires python 2.4 (replaces all os.popen() ) +#from getpass import getuser +#from threading import Thread +from optparse import OptionParser # requires python 2.3 +import stat # for chmod +import pickle + +parser = OptionParser() + +# Most useful switches + +parser.add_option('--iclasses', + action='store_true', dest='iclasses', default=False, + help='Enum for iclasses') +parser.add_option('--operands', + action='store_true', dest='operands', default=False, + help='Enum for operands') +parser.add_option('--operand-types', + action='store_true', dest='operand_types', default=False, + help='Enum for operands') +parser.add_option('--extensions', + action='store_true', dest='extensions', default=False, + help='Enum for extensions') +parser.add_option('--categories', + action='store_true', dest='categories', default=False, + help='Enum for categories') +parser.add_option('--input', + action='store', dest='input', default='', + help='Input file') +parser.add_option('--output', + action='store', dest='output', default='', + help='Output file') +parser.add_option('--gendir', + action='store', dest='gendir', default='gen', + help='Output directory') +parser.add_option('--verbosity', '-v', + action='store', dest='verbosity', default=0, + help='Level of verbosity') + +############################################################################ + +def print_enum_header(f, type, prefix,cfn,hfn): + f.write('namespace ' + 'XED' + '\n') + f.write('cfn ' + cfn + '\n') + f.write('hfn ' + hfn + '\n') + f.write('typename ' + type + '\n') + f.write('prefix ' + prefix + '\n') + f.write('stream_ifdef ' + 'XED_PRINT' + '\n') + +def print_lines(lines, f): + 'print the lines, in upper case' + for line in lines: + f.write(line.upper()) + +def print_enum(lines,gendir, base_name, type_name, prefix,output): + #f = open(os.path.join(gendir,base_name +'-enum.txt'),'w') + f = open(output,'w') + base_fn = base_name + '-enum' + cfn = os.path.join(gendir,base_fn + '.cpp') + hfn = os.path.join(gendir,base_fn + '.H') + print_enum_header(f, type_name, prefix, cfn, hfn) + print_lines(lines,f) + + +def print_iclass_enum(lines,gendir, output): + print_enum(lines,gendir, 'xed-iclass', 'xed_iclass_enum_t', 'XED_ICLASS_',output) +def print_operand_enum(lines,gendir, output): + print_enum(lines,gendir, 'xed-operand', 'xed_operand_enum_t', 'XED_OPERAND_',output) +def print_operand_type_enum(lines,gendir, output): + print_enum(lines,gendir, 'xed-operand-type', 'xed_operand_type_enum_t', 'XED_OPERAND_TYPE_',output) +def print_category_enum(lines,gendir, output): + print_enum(lines,gendir, 'xed-category', 'xed_category_enum_t', 'XED_CATEGORY_',output) +def print_extension_enum(lines,gendir, output): + print_enum(lines,gendir, 'xed-extension', 'xed_extension_enum_t', 'XED_EXTENSION_',output) + +if __name__ == '__main__': + (options, args ) = parser.parse_args() + if options.input == '': + die('Need --input filename argument') + if options.output == '': + die('Need --output filename argument') + + lines = open(options.input,'r').readlines() + if options.operands: + print_operand_enum(lines,options.gendir, options.output) + elif options.iclasses: + print_iclass_enum(lines,options.gendir, options.output) + elif options.operand_types: + print_operand_type_enum(lines,options.gendir, options.output) + elif options.categories: + print_category_enum(lines,options.gendir, options.output) + elif options.extensions: + print_extension_enum(lines,options.gendir, options.output) + else: + die("Unrecognized option") + +############################################################################ diff --git a/pysrc/gen_chip_list.py b/pysrc/gen_chip_list.py new file mode 100755 index 0000000..d6ea46a --- /dev/null +++ b/pysrc/gen_chip_list.py @@ -0,0 +1,130 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import argparse +import re +import collections + +import read_xed_db +import chipmodel + +def die(s): + sys.stdout.write("ERROR: {0}\n".format(s)) + sys.exit(1) +def msgb(b,s=''): + sys.stdout.write("[{0}] {1}\n".format(b,s)) + + +def check(chip, xeddb, chipdb, classes): + icount = 0 + histo = collections.defaultdict(int) + for inst in xeddb.recs: + if inst.isa_set in chipdb[chip]: + icount = icount + 1 + clas = classes[inst.isa_set] + if inst.scalar: + clas = clas + '.sc' + histo[clas] = histo[clas] + 1 + return (chip, icount, histo) + + + +def work(args): # main function + msgb("READING XED DB") + (chips, chip_db) = chipmodel.read_database(args.chip_filename) + + xeddb = read_xed_db.xed_reader_t(args.state_bits_filename, + args.instructions_filename) + + isasets = set() + for r in xeddb.recs: + isasets.add(r.isa_set) + + classes = {} + for i in isasets: + c = 'general' + if 'XOP' in i: + c = 'xop' + elif 'SSE' in i: + c = 'sse' + elif 'AVX512' in i: + c = 'avx512' + elif 'ICL' in i: + c = 'avx512' + elif 'AVX' in i: + c = 'avx' + elif 'FMA' in i: + c = 'avx' + elif 'F16C' in i: + c = 'avx' + elif 'MMX' in i: + c = 'mmx' + classes[i]=c + + all = [] + for c in chips: + r = check(c, xeddb, chip_db, classes) + all.append(r) + + groups = [ 'general', 'mmx', 'sse', 'avx', 'avx512' ] + + for inst in xeddb.recs: + if classes[inst.isa_set] == 'general' and inst.scalar: + print "GPR SCALAR", inst.iclass + + tlist = [] + for s in all: + t = [] + (chip, icount, histo) = s + t.append("{0:20s} {1:4d}".format(chip,icount)) + for scalar in ['.sc', '']: + for x in groups: + k = x + scalar + t.append( "{0:7s}:{1:4d}".format( k, histo[k])) + tlist.append((icount, " ".join(t))) + def keyfn(x): + return x[0] + tlist.sort(key=keyfn) + + for x,y in tlist: + print y + + return 0 + + +def setup(): + parser = argparse.ArgumentParser( + description='Generate instruction counts per chip') + parser.add_argument('state_bits_filename', + help='Input state bits file') + parser.add_argument('instructions_filename', + help='Input instructions file') + parser.add_argument('chip_filename', + help='Input chip file') + args = parser.parse_args() + return args + +if __name__ == "__main__": + args = setup() + r = work(args) + sys.exit(r) + diff --git a/pysrc/gen_inst_list.py b/pysrc/gen_inst_list.py new file mode 100755 index 0000000..087c9d3 --- /dev/null +++ b/pysrc/gen_inst_list.py @@ -0,0 +1,88 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import argparse +import re +import collections + +import read_xed_db +import chipmodel + +def die(s): + sys.stdout.write("ERROR: {0}\n".format(s)) + sys.exit(1) +def msgb(b,s=''): + sys.stdout.write("[{0}] {1}\n".format(b,s)) + + +def check(chip, xeddb, chipdb): + all = [] + undoc = [] + for inst in xeddb.recs: + if inst.isa_set in chipdb[chip]: + if inst.undocumented: + undoc.append(inst) + else: + all.append(inst) + return (all, undoc) + + + +def work(args): # main function + msgb("READING XED DB") + (chips, chip_db) = chipmodel.read_database(args.chip_filename) + + xeddb = read_xed_db.xed_reader_t(args.state_bits_filename, + args.instructions_filename) + + + (insts,undoc) = check(args.chip, xeddb, chip_db) + ilist = list(set(map(lambda x: x.iclass, insts))) + ilist.sort() + ulist = list(set(map(lambda x: x.iclass, undoc))) + ulist.sort() + for i in ilist: + print i + for i in ulist: + print i, "UNDOC" + return 0 + + +def setup(): + parser = argparse.ArgumentParser( + description='Generate instruction counts per chip') + parser.add_argument('chip', + help='Chip name') + parser.add_argument('state_bits_filename', + help='Input state bits file') + parser.add_argument('instructions_filename', + help='Input instructions file') + parser.add_argument('chip_filename', + help='Input chip file') + args = parser.parse_args() + return args + +if __name__ == "__main__": + args = setup() + r = work(args) + sys.exit(r) + diff --git a/pysrc/gen_operands.py b/pysrc/gen_operands.py new file mode 100755 index 0000000..4c8c087 --- /dev/null +++ b/pysrc/gen_operands.py @@ -0,0 +1,80 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import argparse +import re +import collections + +import read_xed_db + +def die(s): + sys.stdout.write("ERROR: {0}\n".format(s)) + sys.exit(1) +def msgb(b,s=''): + sys.stdout.write("[{0}] {1}\n".format(b,s)) + + + +def work(args): # main function + msgb("READING XED DB") + + xeddb = read_xed_db.xed_reader_t(args.state_bits_filename, + args.instructions_filename) + + histo = collections.defaultdict(int) + for r in xeddb.recs: + if hasattr(r,'operands'): + s = re.sub(r'[ ]+',' ',r.operands) + if 0: + histo[s] = histo[s] + 1 + if 1: + for t in s.split(): + if t.startswith('REG'): + t = 'REG' + t[4:] + if t.startswith('MEM'): + t = 'MEM' + t[4:] + histo[t] = histo[t] + 1 + + + + for k,v in sorted( histo.items(), key=lambda t: t[1] ): + print "{0:4d} {1}".format(v,k) + print "TOTAL: ", len(histo) + + return 0 + + +def setup(): + parser = argparse.ArgumentParser( + description='Generate instruction counts per chip') + parser.add_argument('state_bits_filename', + help='Input state bits file') + parser.add_argument('instructions_filename', + help='Input instructions file') + args = parser.parse_args() + return args + +if __name__ == "__main__": + args = setup() + r = work(args) + sys.exit(r) + diff --git a/pysrc/generator.py b/pysrc/generator.py new file mode 100755 index 0000000..a7ffb02 --- /dev/null +++ b/pysrc/generator.py @@ -0,0 +1,6452 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +############################################################################ +## this is the main generator and the decoder generator. +## the main data structures are: +## +## class all_generator_info_t(object): +## the catch-all for all state -- at least it tries to be. +## +## class generator_common_t(object): +## class generator_info_t(generator_common_t): +## each generator has a parser +## +## class parser_t(object): +## +## which contains: +## +## class partitionable_info_t(object): +## class instruction_info_t(partitionable_info_t): +## +## class nonterminal_info_t(object): +## class nonterminal_dict_t(object): + +## class bits_list_t(object): +## +## contains a list of: +## +## class bit_info_t(object): + +## class state_info_t(object): +## class prebinding_t(object): +## class opnds.operand_info_t(object): +## class graph_node(object): + +## class code_gen_dec_args_t(object): +## class table_init_object_t(object): +## class bit_group_info_t(object): +## class reg_info_t(object): +## class width_info_t(object): +############################################################################ + +import os +import sys +import copy +import types +import glob +import re +import optparse + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +mbuild_install_path = os.path.join(os.path.dirname(sys.argv[0]), '..', 'mbuild') +if not os.path.exists(mbuild_install_path): + mbuild_install_path = find_dir('mbuild') +sys.path= [mbuild_install_path] + sys.path +try: + import mbuild +except: + sys.stderr.write("\nERROR(generator.py): Could not find mbuild. " + + "Should be a sibling of the xed2 directory.\n\n") + sys.exit(1) + +xed2_src_path = os.path.join(os.path.dirname(sys.argv[0])) +if not os.path.exists(xed2_src_path): + xed2_src_path = find_dir('xed2') +sys.path= [ xed2_src_path ] + sys.path +sys.path= [ os.path.join(xed2_src_path,'pysrc') ] + sys.path + +from genutil import * +import operand_storage +import slash_expand, flag_gen +from verbosity import * +import opnds +import opnd_types +import genutil + +send_stdout_message_to_file = False +if send_stdout_message_to_file: + fn = "out" + set_msgs(open(fn,"w")) + sys.stderr.write("Writing messages to file: [" + fn + "]\n") + +check_python_version(2,4) + +from codegen import * +import metaenum +import enum_txt_writer +import chipmodel +import ctables +import ild +import refine_regs + +##################################################################### +## OPTIONS +##################################################################### +def setup_arg_parser(): + arg_parser = optparse.OptionParser() + arg_parser.add_option('--limit-enum-strings', + action='store_true', + dest='limit_enum_strings', + default=False, + help='Save space by limiting the enum strings') + arg_parser.add_option('--gendir', + action='store', + dest='gendir', + default='gen', + help='Directory for generated files') + arg_parser.add_option('--xeddir', + action='store', + dest='xeddir', + default='', + help='Directory for generated files') + arg_parser.add_option('--input-regs', + action='store', + dest='input_regs', + default='', + help='Register input file') + arg_parser.add_option('--input-widths', + action='store', + dest='input_widths', + default='', + help='Widths input file') + arg_parser.add_option('--input-extra-widths', + action='store', + dest='input_extra_widths', + default='', + help='Extra widths input file') + arg_parser.add_option('--input-element-types', + action='store', + dest='input_element_types', + default='', + help='File with mappings from type names to' + + ' widths and base element types') + arg_parser.add_option('--input-element-type-base', + action='store', + dest='input_element_type_base', + default='', + help='new chunk for element type enum') + arg_parser.add_option('--input-pointer-names', + action='store', + dest='input_pointer_names', + default='', + help='Pointer names input file for disassembly') + arg_parser.add_option('--input-fields', + action='store', + dest='input_fields', + default='', + help='Operand storage description input file') + arg_parser.add_option('--input', + action='store', + dest='input', + default='', + help='Input file') + arg_parser.add_option('--input-state', + action='store', + dest='input_state', + default='xed-state-bits.txt', + help='state input file') + arg_parser.add_option('--inst', + action='store', + dest='inst_init_file', + default='xed-init-inst-table.c', + help='Instruction table init file') + arg_parser.add_option('--sout', + action='store', + dest='structured_output_fn', + default='xed-sout.txt', + help='Emit structured ouptut file') + arg_parser.add_option('--patterns', + action='store', + dest='structured_input_fn', + default='', + help='Read structured input file') + arg_parser.add_option('--chip-models', + action='store', + dest='chip_models_input_fn', + default='', + help='Chip models input file name') + arg_parser.add_option('--ctables', + action='store', + dest='ctables_input_fn', + default='', + help='Conversion tables input file name') + arg_parser.add_option('--isa', + action='store', + dest='isa_input_file', + default='', + help='Read structured input file containing' + + ' the ISA INSTRUCTIONS() nonterminal') + arg_parser.add_option('--spine', + action='store', + dest='spine', + default='', + help='Read the spine file containing the' + + ' top-most decoder nonterminal') + arg_parser.add_option('--print-graph', + action='store_true', + dest='print_graph', + default=False, + help='Print the graph for each nonterminal (big)') + + arg_parser.add_option('--verbosity', '--verbose', '-v', + action='append', + dest='verbosity', + default=[], + help='Level of verbosity, repeatable. ' + + ' Values=1..7, enc,merge') + arg_parser.add_option('--no-imm-suffix', + action='store_false', + dest='add_suffix_to_imm', + default=True, + help='Omit width suffixes from iforms') + arg_parser.add_option('--ild-scanners', + action='store', + dest='ild_scanners_input_fn', + default='', + help='ILD scanners input file') + arg_parser.add_option('--ild-getters', + action='store', + dest='ild_getters_input_fn', + default='', + help='ILD getters input file') + arg_parser.add_option('--cpuid', + action='store', + dest='cpuid_input_fn', + default='', + help='isa-set to cpuid map input file') + arg_parser.add_option('--gen-ild-storage', + action='store_true', + dest='gen_ild_storage', + default=False, + help='Dump the ILD storage file.') + arg_parser.add_option("--compress-operands", + action="store_true", + dest="compress_operands", + default=False, + help="use bit-fields to compress the "+ + "operand storage.") + return arg_parser + +##################################################################### + +header_pattern = re.compile(r'[.][Hh]$') +def is_header(fn): + global header_pattern + if header_pattern.search(fn): + return True + return False + + +############################################################################ +# Compiled patterns used in this program +############################################################################ +delete_iclass_pattern = re.compile('^DELETE') +delete_iclass_full_pattern = \ + re.compile(r'^DELETE[ ]*[:][ ]*(?P[A-Za-z_0-9]+)') + +udelete_pattern = re.compile('^UDELETE') +udelete_full_pattern = \ + re.compile(r'^UDELETE[ ]*[:][ ]*(?P[A-Za-z_0-9]+)') + +operand_token_pattern = re.compile('OPERAND') +underscore_pattern = re.compile(r'_') +invert_pattern = re.compile(r'[!]') + +instructions_pattern = re.compile(r'INSTRUCTIONS') +equals_pattern = re.compile(r'(?P[^!]+)=(?P.+)') +not_equals_pattern = re.compile(r'(?P[^!]+)!=(?P.+)') + +quick_equals_pattern= re.compile(r'=') +colon_pattern= re.compile(r'[:]') + +bits_and_letters_underscore_pattern = re.compile(r'^[10a-z_]+$') + +hex_pattern = re.compile(r'0[xX][0-9A-Fa-f]+') + +slash_macro_pattern = re.compile(r'([a-z][/][0-9]{1,2})') +nonterminal_string = r'([A-Z][a-zA-Z0-9_]*)[(][)]' + +parens_to_end_of_line = re.compile(r'[(][)].*::.*$') # with double colon +lookupfn_w_args_pattern = re.compile(r'[[][a-z]+]') +#nonterminal_start_pattern=re.compile(r'^' + nonterminal_string + r'\s*::') +nonterminal_start_pattern=re.compile(r'::') +nonterminal_pattern=re.compile(nonterminal_string) +nonterminal_parens_pattern = re.compile(r'[(][^)]*[)]') + +binary_pattern = re.compile(r'^[01_]+$') # only 1's and 0's +formal_binary_pattern = re.compile(r'^0b[01_]+$') # only 1's and 0's leading 0b +one_zero_pattern = re.compile(r'^[01]') # just a leading 0 or 1 +completely_numeric = re.compile(r'^[0-9]+$') # only numbers + +# things identified by the restriction_pattern are the operand deciders: +restriction_pattern = re.compile(r'([A-Z0-9_]+)(!=|=)([bx0-9A-Z_]+)') +all_caps_pattern = re.compile(r'^[A-Z_0-9]+$') + +not11_pattern = re.compile(r'NOT11[(]([a-z]{2})[)]') +letter_basis_pattern = re.compile(r'[a-z]') + +all_zeros_pattern = re.compile(r'^[0]+$') +type_ending_pattern = re.compile(r'_t$') +uniq_pattern = re.compile(r'_uniq(.*)$') +ntwidth_pattern = re.compile('NTWIDTH') +paren_underscore_pattern = re.compile(r'[(][)][_]+') + +all_lower_case_pattern = re.compile(r'^[a-z]+$') + + +pattern_binding_pattern = re.compile( + r'(?P[A-Za-z_0-9]+)[[](?P[A-Za-z01_]+)]') +uppercase_pattern = re.compile(r'[A-Z]') + + +reg_operand_name_pattern = re.compile("^REG(?P[0-9]+)$") +############################################################################ + +def comment(s): + return '/* ' + s + ' */' + +def all_the_same(lst): + "return True if all the elements of the list are the same" + first = lst[0] + for x in lst: + if x != first: + return False + return True + +def pad_to_multiple_of_8bits(x): + ilen = len(x) + frac = ilen & 7 + if frac == 0: + return x + t = [] + while frac < 8: + t.append('0') + frac = frac + 1 + t.extend(x) + return t + +############################################################################ +# $$ nonterminal_info_t +class nonterminal_info_t(object): + def __init__(self,name, type=None): + self.name = name + self.type = type + self.start_node = None + + def set_start_node(self,n): + self.start_node = n + + def is_lookup_function(self): + if self.type != None: + return True + return False + +# $$ nonterminal_dict_t +class nonterminal_dict_t(object): + """dictionary holding nonterminal information for code generation""" + + def __init__(self): + # dictionary of nonterminal_info_t's by short name. + # nonterminal_info_t has {name, type, start_node} + self.nonterminal_info = {} + + def keys(self): + return self.nonterminal_info.keys() + + def add_graph_node(self, nt_name, node_id): + """set the node id in the graph node""" + if nt_name not in self.nonterminal_info: + self.add_to_dict(nt_name) + n = self.nonterminal_info[nt_name] + n.start_node = node_id + + def get_node(self,nt_name): + if nt_name in self.nonterminal_info: + return self.nonterminal_info[nt_name] + die("Did not find " + nt_name + " in the nonterminal dictionary.") + + def add_to_dict(self,short_nt_name, nt_type): + msge("Adding " + short_nt_name + " to nonterminal dict") + #nonterminal_info_t has {name, type, start_node, encode, decoder} + new_nt = nonterminal_info_t(short_nt_name, nt_type) + self.nonterminal_info[short_nt_name] = new_nt + + def record_nonterminal(self,nt_name, nt_type): + if nt_name: + if nt_name not in self.nonterminal_info: + #msge("Adding NT: " + nt_name) + self.add_to_dict(nt_name, nt_type) + else: + die("Bad nonterminal name") + + +############################################################################ +# $$ bit_info_t +class bit_info_t(object): + """The patterns are built up of bits of various kinds. Normal 1/0 + bits are type bit. The other kinds of bits are dontcares which are + letter names, state bits, operand tests and nonterminals. + """ + + bit_types = [ 'bit', 'dontcare', 'operand', 'nonterminal' ] + def __init__(self, value, btype='bit', pbit=-1): + self.btype = btype # See bit_info_t.bit_types + self.value = value + + # Physical bits are bits that are real. They are offsets from + # the beginnning of this nonterminal or the last nonterminal. + + self.pbit = pbit + + self.token = None # operand decider + self.test = None # eq or ne + self.requirement = None # the value the od must have (or not have) + + if btype == 'operand': + # for operands, we split them in to a token name and a required value. + #search for FOO=233 or FOO!=233 + m = restriction_pattern.search(value) + if not m: + die("bad operand decider: "+ value) + (token,test,requirement) = m.groups([0,1,2]) + if vod(): + msge("OperandDecider Token= " + token + + " Test= " + test + " Requirement= " + requirement) + self.token = token + self.requirement = make_numeric(requirement, value) + if test == '=': + self.test='eq' + else: + self.test='ne' + + + def __eq__(self,other): + if other == None: + return False + if self.value == other.value: + if self.btype == other.btype: + return True + return False + + def __ne__(self,other): + if other == None: + return True + if self.value != other.value: + return True + if self.btype != other.btype: + return True + return False + + def __str__(self): + s = self.btype + '/' + str(self.value) + if self.pbit != -1: + s += '/PBIT' + str(self.pbit) + return s + + def just_bits(self): + return self.value + + def is_nonterminal(self): + if self.btype == 'nonterminal': + return True + return False + + def is_operand_decider(self): + if self.btype == 'operand': + return True + return False + + def is_dont_care(self): + if self.btype == 'dontcare': + return True + return False + + def is_real_bit(self): + if self.btype == 'dontcare' or self.btype == 'bit': + return True + return False + def is_one_or_zero(self): + if self.btype == 'bit': + return True + return False + + def nonterminal_name(self): + if self.is_nonterminal(): + g = nonterminal_pattern.search(self.value) + if g: + nt_name = g.group(1) + return nt_name + else: + die("Error finding NT name for " + self.value) + return None + +# $$ bits_list_t +class bits_list_t(object): + """ list of bit_info_t """ + def __init__(self): + self.bits = [] + def append(self,x): + self.bits.append(x) + + def __str__(self): + return self.just_bits() + + def just_bits(self): + """ return a string of just the bits""" + s = map(lambda(x): x.just_bits(), self.bits) + o = [] + i = 0 + for b in s: + o.append(b) + i = i + 1 + if i == 4: + i = 0 + o.append(' ') + return ' '.join(o) + +# $$ state_info_t +class state_info_t(object): + """This is really just a big dictionary for the state (operand + decider) macro expansion""" + def __init__(self, name, list_of_str): + """ takes a name and a string containing our bit strings""" + self.name = name + self.list_of_str = [] + # bust up bit strings that come in via the states file. + # make individual bits and add them to the list of strings. + for x in list_of_str: + if formal_binary_pattern.match(x): + t = re.sub('0b','',x) + t = re.sub('_','',t) + self.list_of_str.extend(list(t)) + else: + self.list_of_str.append(x) + + + def dump_str(self): + s = self.name + ' ' + for w in self.list_of_str: + s += w + ' ' + return s + +############################################################################ + +def blank_line(line): + if line == '': + return False + return True + +def pad_pattern(pattern): + "pad it to a multiple of 8 bits" + plen = len(pattern) + if (plen & 7) != 0: + rem = 8-(plen & 7) + pattern += '-' * rem + return pattern + +def read_dict_spec(fn): + """Read a file with expected format of a form + {KEY VALUE\n}, return a dict of dict[KEY] == VALUE """ + res_dict = {} + if not os.path.exists(fn): + die("Could not read file: " + fn) + lines = open(fn,'r').readlines() + lines = map(no_comments, lines) + lines = filter(blank_line, lines) + for line in lines: + wrds = line.split() + key = wrds[0] + value = wrds[1] + #convert straight to int + res_dict[key] = int(value) + return res_dict + +def read_ild_scanners_def(ild_scanners_fn): + scanners_dict = read_dict_spec(ild_scanners_fn) + return scanners_dict + +def read_ild_getters_def(ild_getters_fn): + getters_dict = read_dict_spec(ild_getters_fn) + return getters_dict + +def read_state_spec(fn): + "Return dictionary of state bits" + state_bits = {} + if not os.path.exists(fn): + die("Could not read file: " + fn) + lines = open(fn,'r').readlines() + lines = map(no_comments, lines) + lines = filter(blank_line, lines) + for line in lines: + ## remove comment lines + #line = no_comments(line) + #if line == '': + # continue + #msge("STATELINE: [" + line + ']') + + wrds = line.split() + tag = wrds[0] + spattern = wrds[1:] + + si = state_info_t(tag,spattern) + + state_bits[tag] = si + + return state_bits + +def compute_state_space(state_dict): + """Figure out all the values for each token, return a dictionary + indexed by token name""" + + # a dictionary of the values of a each operand_decider + state_values = {} + + for k in state_dict.keys(): + vals = state_dict[k] + for wrd in vals.list_of_str: + m = restriction_pattern.search(wrd) + if m: + (token,test,requirement) = m.groups([0,1,2]) + if requirement == 'XED_ERROR_GENERAL_ERROR': + continue + #if type(requirement) == types.IntType: + # die("Already an integer") + requirement_base10 = make_numeric(requirement,wrd) + #msge("STATE RESTRICTION PATTERN " + token + " : " + + # str(requirement) + " -> " + str(requirement_base10)) + if token in state_values: + if requirement_base10 not in state_values[token]: + state_values[token].append(requirement_base10) + else: + state_values[token] = [ requirement_base10 ] + elif formal_binary_pattern.match(wrd): + pass # ignore these + elif nonterminal_pattern.match(wrd): + pass # ignore these + elif hex_pattern.match(wrd): + pass # ignore these + else: + die("Unhandled state pattern: %s" % wrd) + + return state_values + + +############################################################################ + +def validate_field_width(agi, field_name, bits): + b=make_binary(bits) + n = len(b) + opnd = agi.operand_storage.get_operand(field_name) + if n > int(opnd.bitwidth): + s = ("length of captured field %s[%s] is %d and that exceeds " + + " operand storage field width %s\n") + die(s % (field_name, bits, n, opnd.bitwidth)) + +# $$ prebinding_t +class prebinding_t(object): + """This is for fields mentioned in the decode pattern. We want to + bind the bits to the operand storage fields before calling any + NT/NTLUFs that require these bindings. + """ + def __init__(self, name): + self.field_name = name + self.bit_info_list = [] # list of bit_info_t's + def add_bit(self, b): + self.bit_info_list.append(b) + + def is_constant(self): + for bi in self.bit_info_list: + if bi.is_dont_care(): + return False #dontcare in prebinding + return True + + def get_value(self): + value = '' + for bi in self.bit_info_list: + value += bi.just_bits() + return value + + def __str__(self): + s = [] + s.append(self.field_name) + s.extend(map(str,self.bit_info_list)) + return ', '.join(s) + +def get_btype(b): + if b == '1' or b == '0': + return 'bit' + return 'dontcare' + +def parse_opcode_spec(agi, line, state_dict): + """Given a string of bits, spaces and hex codes, canonicalize it + to useful binary, return a list of single char bits or letters, or + nonterminals. + + @rtype: tuple + @return: (list of bits, -- everything is raw bits at this level + list of operand binding tuples,-- same info as the prebindings + list bit_info_t, -- interpreted bits with types and positions + dict of prebinding_t, -- dictionary of the captured fields + pointing to bits + xed_bool_t otherwise_ok) + """ + # if there are any trailing underscores after a nonterminal paren, + # convert them to spaces. + b = paren_underscore_pattern.sub('() ', line) + # if there are any leading underscores before, convert them to spaces + + extra_bindings = [] # the inline captures become "extra" operands later + if vparse(): + msgb("PARSE OPCODE SPEC " + line) + # expand things from the state dictionary + wrds = [] + for w in b.split(): + if w in state_dict: + wrds.extend(copy.deepcopy(state_dict[w].list_of_str)) + else: + wrds.append(w) + + all_bits = [] + # + # 1. hex byte + # 2. immediate capture IMM(a-z,0-9) ??? IS THIS USED??? + # IMM(a,9) -- old form of slash + # 3. slash pattern (just more letter bits) + # 4. pattern binding eg: MOD[mm] or MOD[11_] + # 5. nonterminal + # Then EXPAND + all_bit_infos = [] + all_prebindings = {} + bcount = 0 # bit count + for w in wrds: + if w == 'otherwise': + return (None,None,None,None,True) + + if hex_pattern.match(w): + bits = pad_to_multiple_of_8bits(hex_to_binary(w)) + for b in bits: + all_bit_infos.append(bit_info_t(b,'bit',bcount)) + bcount += 1 + all_bits.extend(bits) + continue + + # inline captures MOD[mm] REG[rrr] RM[nnn] or REG[111] etc. -- + # can be constant + pb = pattern_binding_pattern.match(w) + if pb: + #msgb("PATTERN BINDING", w) + (field_name,bits) = pb.group('name','bits') + if uppercase_pattern.search(bits): + die("\n\nUpper case letters in capture pattern" + + ": %s in line\n\n %s\n\n" % ( w, line)) + + validate_field_width(agi, field_name, bits) + extra_bindings.append( (field_name,bits) ) + prebinding = prebinding_t(field_name) + bits_str = make_binary(bits) + bits_list = list(bits_str) + #print "BITS %s -> %s" % ( bits, bits_str) + for b in bits_list: + #btype is either bit or dontcare + btype = get_btype(b) + bi = bit_info_t(b,btype,bcount) + bcount += 1 + prebinding.add_bit(bi) + all_bit_infos.append(bi) + all_prebindings[field_name] = prebinding + all_bits.extend(bits_list) + continue + if nonterminal_pattern.search(w): + # got a nonterminal + bits = [ w ] + all_bit_infos.append(bit_info_t(w,'nonterminal', bcount)) + bcount += 1 + all_bits.extend(bits) + continue + + + m = restriction_pattern.search(w) + if m: + (token,test,requirement) = m.groups([0,1,2]) + # got an operand-decider (requirement) + #msge("RESTRICTION PATTERN " + str(w)) + # we skip some field bindings that are only for the encoder. + # They are denoted DS in the fields data-files. + if agi.operand_storage.decoder_skip(token): + #msge("SKIPPING RESTRICTION PATTERN " + str(w)) + continue + bits = [ w ] + all_bit_infos.append(bit_info_t(w,'operand', bcount)) + bcount += 1 + all_bits.extend(bits) + continue + + if formal_binary_pattern.search(w): + bits = make_binary(w) + all_bits.extend(bits) + for b in list(bits): + btype = get_btype(b) + all_bit_infos.append(bit_info_t(b,btype,bcount)) + bcount += 1 + continue + + # remove the underscores now that we know it is a pattern + w = w.replace('_','') + # some binary value or letter + bits = map(str,list(w)) + all_bits.extend(bits) + for b in list(bits): + btype = get_btype(b) + all_bit_infos.append(bit_info_t(b,btype,bcount)) + bcount += 1 + + + # We now also have a a list of bit_info_t's in all_bit_infos and a + # dictionary of prebinding_t's in all_prebindings. + + return (all_bits,extra_bindings,all_bit_infos, all_prebindings,False) + +def add_str(s, name, value): + t = s + '%-15s' % (name) + ': ' + if type(value) == types.ListType: + for q in value: + t += q + ' ' + else: + t += value + t += '\n' + return t + +def add_str_list(s, name, values): + s = s + '%-15s' % (name) + ': ' + for v in values: + s = s + v + ' ' + s = s + '\n' + return s + + +#for the first not commented, non-empty line from lines, +#return if regexp.search succeeds +def accept(regexp, lines): + #msge("In accept!") + line = '' + while line == '': + if lines == []: + return None + line = no_comments(lines[0]) + line = line.strip() + lines.pop(0) + #msge("Testing line :" + line) + if re.search(regexp,line): + return True + return False + + +def read_str(lines,name): + "Read a line emitted by add_str() above. Split on 1st colon" + line = '' + while line == '': + if lines == []: + return None + line = no_comments(lines[0]) + line = line.strip() + lines.pop(0) + #msge("Reading line: " + line) + (iname, rest) = line.split(':',1) + iname = iname.strip() + rest = rest.strip() + if iname != name: + die('Misparsed structured input file. Expecting: [' + + name + '] Observed: [' + iname + ']') + return rest + +def read_str_simple(lines): + "Read a line emitted by add_str() above. Split on 1st colon" + line = '' + while line == '': + if lines == []: + return None + line = no_comments(lines[0]) + line = line.strip() + lines.pop(0) + return line + +############################################################################ +def parse_extra_operand_bindings(agi, extra_bindings): + """Add the captures as operands""" + operands = [] + operand_storage_dict = agi.operand_storage.get_operands() + for (name,bits) in extra_bindings: + # FIXME handle something other than bits + bits_str = make_binary(bits) + # FIXME: add "i#" width codes for the captured operands! + try: + bits = operand_storage_dict[name].bitwidth + oc2= "i%s" % (bits) + except: + die("Could not find field width for %s" % (name)) + + new_operand = opnds.operand_info_t(name, + 'imm', + list(bits_str), + vis='SUPP', + oc2=oc2) + # DENOTE THESE AS INLINE TO ALLOW EARLY CAPTURING + if vbind(): + msge("INLINE OPERAND %s" % (name)) + new_operand.inline = True + operands.append(new_operand) + return operands + +#NOTE: class attributes are not like static member data in C++. They +#are per object type. So if you derive a new class bar from class foo, +#then the instance (attribute) variables of class foo and class bar +#are disjoint. +global_inum = 0 + +# $$ partitionable +class partitionable_info_t(object): + def new_inum(self): + global global_inum + self.inum = global_inum + global_inum += 1 + + def __init__(self, name='', ipattern_input='', operands_input=None): + + self.new_inum() + self.name = name + self.input_str = '' + + self.ipattern_input = ipattern_input + self.ipattern = None # bits_list_t() + self.prebindings = None # dictionary + + if operands_input: + self.operands_input = operands_input + else: + self.operands_input = [] + + self.operands = [] # list of opnds.operand_info_t's + + # FOR HIERARCHICAL RECORDS -- THESE GET SPLIT OFF AFTER RECORD-READ + self.extra_ipatterns = [] + self.extra_operands = [] + self.extra_iforms_input = [] + + # When we consume a prefix, we must apply state modifications + # and that might cause us to jump to a different part of the + # graph, so we must retraverse the state-portion of the graph, + # but remember what byte we were processing and pick up at the + # next byte which may or may not be a prefix. + self.reset_for_prefix = False + + + self.encoder_func_obj = None # an instance of a class function_object_t + + self.encoder_operands = None + + self.otherwise_ok = False + + # simple nonterminals: either all nonterminals or all operand deciders. + self.all_nonterminals = None + self.all_operand_deciders = None + + def get_iclass(self): + if field_check(self,'iclass'): + return self.iclass + return '*NO-ICLASS*' + + def refine_parsed_line(self, agi, state_dict): + """Refine the ipattern_input to ipattern, parse up operands""" + (simple_pattern, + extra_bindings, + all_bit_infos, + all_prebindings, + otherwise_ok) = parse_opcode_spec(agi,self.ipattern_input, state_dict) + + if otherwise_ok: # FIXME: 2008-09-25 - need to remove this for more + # general "otherwise" handling + self.otherwise_ok = True + return + + self.ipattern = bits_list_t() + self.ipattern.bits = all_bit_infos + self.prebindings = all_prebindings + + (self.operands, self.reset_for_prefix) = \ + parse_operand_spec(agi, self.operands_input) + if extra_bindings: + extra_operands = parse_extra_operand_bindings(agi,extra_bindings) + self.operands.extend(extra_operands) + + self.check_for_simple_nts() + + def check_for_simple_nts(self): + """Check for NTs that do not accept bits. We'll make them in to + fast functions""" + all_operand_deciders = True + all_nonterminals = True + for bi in self.ipattern.bits: + if not bi.is_operand_decider(): + all_operand_deciders = False + if not bi.is_nonterminal(): + all_nonterminals = False + + self.all_nonterminals = all_nonterminals + self.all_operand_deciders = all_operand_deciders + + + def __str__(self): + return self.dump_str() + + def dump_str(self, pad=''): + return self.input_str + + def dump_structured(self,pad=''): + lst = [] + s = pad + s += self.ipattern_input + ' | ' + s += ' '.join(self.operands_input) + lst.append( s ) + return lst + + def dump(self, pad=''): + for s in self.dump_structured(pad): + msge(s) + + s = ' ipatternbits:' + str(len(self.ipattern.bits)) + msge("BITLENGTHS: " + s) + s = '' + for b in self.ipattern.bits: + s += ' ' + b.value + + msge("GRAPHBITS: " + s) + +############################################################################ + +# indicates which fields are required in the input parsing +structured_input_tags = {'ICLASS': True, + 'UNAME': False, + 'CATEGORY': True, + 'EXTENSION': True, + 'ISA_SET': False, + 'STATE': False, + 'PATTERN': True, + 'ATTRIBUTES': False, + 'OPERANDS': False, + 'UCODE': False, + 'FLAGS': False, + 'VERSION': False, + 'CPL': False, + 'COMMENT': False, + 'EXCEPTIONS': False, + 'DISASM': False, + 'DISASM_INTEL': False, + 'DISASM_ATTSV': False, + 'IFORM': False + } + + +# $$ instruction_info_t +class instruction_info_t(partitionable_info_t): + def __init__(self, + iclass='', + ipattern_input='', + operands_input=None, + category='DEFAULT', + extension='DEFAULT', + version = 0, + isa_set = None): + partitionable_info_t.__init__(self, iclass,ipattern_input, operands_input) + self.iclass = iclass + self.uname = None + self.ucode = None + self.comment = None + self.exceptions = None + + # Default version. Newer versions replace older versions + self.version = version + + self.category = category + self.extension = extension + self.isa_set = isa_set + self.cpl = None + self.attributes = None + self.flags_input = None + self.flags_info = None # flag_gen.flags_info_t class + + self.iform_input = None + self.iform_num = None + self.iform_enum = None + + def add_attribute(self,s): + if self.attributes: + self.attributes.append(s) + else: + self.attributes = [s] + + def add_stack_attribute(self, memop_index): + for op in self.operands: + if op.bits == 'XED_REG_STACKPUSH': + self.add_attribute('STACKPUSH%d' % (memop_index)) + return + elif op.bits == 'XED_REG_STACKPOP': + self.add_attribute('STACKPOP%d' % (memop_index)) + return + die("Did not find stack push/pop operand") + + def dump_structured(self): + """Return a list of strings representing the instruction in a + structured way""" + + slist = [] + + slist.append('{\n') + + s = add_str('', 'ICLASS', self.iclass) + slist.append(s) + + if self.uname: + s = add_str('', 'UNAME', self.uname) + slist.append(s) + + if self.version != 0: + s = add_str('','VERSION', str(self.version)) + slist.append(s) + + s = add_str('','CATEGORY', self.category) + slist.append(s) + + s = add_str('','EXTENSION', self.extension) + slist.append(s) + s = add_str('','ISA_SET', self.isa_set) + slist.append(s) + s = add_str('','PATTERN', self.ipattern_input) + slist.append(s) + if self.cpl: + s = add_str('','CPL', self.cpl) + slist.append(s) + + + if self.attributes: + s = add_str('','ATTRIBUTES', self.attributes) + slist.append(s) + if self.ucode: + s = add_str('','UCODE', self.ucode) + slist.append(s) + if self.comment: + s = add_str('','COMMENT', self.comment) + slist.append(s) + if self.exceptions: + s = add_str('','EXCEPTIONS', self.exceptions) + slist.append(s) + if self.exceptions: + s = add_str('','DISASM_INTEL', self.disasm_intel) + slist.append(s) + if self.exceptions: + s = add_str('','DISASM_ATTSV', self.disasm_att) + slist.append(s) + if self.iform_input: + s = add_str('','IFORM_INPUT', self.iform_input) + slist.append(s) + if self.iform: + s = add_str('','IFORM', self.iform) + slist.append(s) + + if self.flags_input: + s = add_str('','FLAGS', self.flags_input) + slist.append(s) + + t = '' + for op in self.operands_input: + t = t + op + ' ' + s = add_str('','OPERANDS', t) + slist.append(s) + + slist.append('}\n') + return slist + + def read_structured_flexible(self,lines): + debug = False + accept(r'[{]', lines) + reached_closing_bracket = False + # FIXME add more error checking + structured_input_dict = dict(zip(structured_input_tags.keys(), + len(structured_input_tags)*[False])) + found_operands = False + filling_extra = False + while 1: + line = read_str_simple(lines) + if debug: + msge("Reading: " + line) + if not line: + if debug: + msge("Dead line - ending") + break + if line == '}': + if debug: + msge("Hit bracket") + reached_closing_bracket = True + break + #print "READING [%s]" % (line) + if colon_pattern.search(line): + (token, rest ) = line.split(':',1) + token = token.strip() + rest = rest.strip() + + # Certain tokens can be duplicated. We allow for triples + # of (pattern,operands,iform). The iform is optional. If + # we see "pattern, operand, pattern" without an + # intervening iform, the iform is assumed to be + # auto-generated. But we must have an operand line for + # each pattern line. + #msge("LINE: %s" % (line)) + if token in structured_input_dict: + if structured_input_dict[token] == True: + if token in [ 'PATTERN', 'OPERANDS', 'IFORM']: + filling_extra = True + else: + die("Duplicate token %s in entry:\n\t%s\n" % (token, line)) + structured_input_dict[token] =True + #msge("FILLING EXTRA = %s" %( str(filling_extra))) + + if token == 'ICLASS': + self.iclass = rest + if viclass(): + msgb("ICLASS", rest) + + elif token == 'CATEGORY': + self.category = rest + elif token == 'CPL': + self.cpl = rest + elif token == 'EXTENSION': + self.extension = rest + + # the isa set defaults to the extension. We can override + # the isa set with the ISA_SET token. + if self.isa_set == None: + self.isa_set = self.extension + + elif token == 'ISA_SET': + self.isa_set = rest + elif token == 'ATTRIBUTES': + self.attributes = rest.upper().split() + elif token == 'VERSION': + self.version = int(rest) + elif token == 'FLAGS': + self.flags_input = rest + self.flags_info = flag_gen.flags_info_t(self.flags_input) + if vflag(): + msge("FLAGS parsed = %s" % str(self.flags_info)) + elif token == 'PATTERN': + if filling_extra: + self.extra_ipatterns.append(rest) + #msge("APPENDING None TO IFORMS INPUT") + self.extra_iforms_input.append(None) + self.extra_operands.append(None) + else: + self.ipattern_input = rest + found_operands=False + elif token == 'OPERANDS': + if filling_extra: + # overwrite the one that was added when we had an + # extra pattern. + if len(self.extra_operands) == 0: + die("Need to have a PATTERN line before the " + + "OPERANDS line for " + ii.iclass) + self.extra_operands[-1] = rest.split() + else: + self.operands_input = rest.split() + found_operands=True + elif token == 'UCODE': + self.ucode = rest + elif token == 'COMMENT': + self.comment = rest + elif token == 'EXCEPTIONS': + self.exceptions = rest + elif token == 'DISASM': + self.disasm_intel = rest + self.disasm_att = rest + elif token == 'DISASM_INTEL': + self.disasm_intel = rest + elif token == 'DISASM_ATTSV': # AT&T System V + self.disasm_att = rest + elif token == 'UNAME': + self.uname = rest + if viclass(): + msgb("UNAME", rest) + + elif token == 'IFORM': + if filling_extra: + if len(self.extra_iforms_input) == 0: + die("Need to have a PATTERN line before " + + "the IFORM line for " + ii.iclass) + self.extra_iforms_input[-1] = rest + else: + self.iform_input = rest + else: + setattr(self,token,rest.strip()) + # die("Unhandled token in line: " + line) + else: + print "NEXT FEW LINES: " + for x in lines[0:20]: + print "INPUT LINE: %s" % (x.strip()) + die("Missing colon in line: " + line) + + if reached_closing_bracket: + if found_operands == False: + die("Did not find operands for " + self.iclass) + for k in structured_input_dict.keys(): + if structured_input_dict[k] == False: + if structured_input_tags[k]: + die("Required token missing: "+ k) + + if debug: + msge("\tReturning...") + return True + return False + + def add_scalable_attribute(self, scalable_widths, agi): + """Look for operations that have width codes that are scalable + width codes (z,v,a,p,p2,s,spw8,spw,spw3,spw2, + etc. (auto-derived) , and add an attribute SCALABLE""" + + scalable = False + + for op in self.operands: + if op.oc2: + s= op.oc2.upper() + #msge("RRR Checking for %s in %s" % (s, str(scalable_widths))) + if s in scalable_widths: + scalable=True + break + + if op.lookupfn_name: + #msge("OPNAME: " + op.lookupfn_name) + scalable = look_for_scalable_nt(agi, op.lookupfn_name) + if scalable: + break + + if scalable: + s = "SCALABLE" + self.add_attribute(s) + + + + def add_fixed_base_attribute(self): + """Look for STACKPUSH/STACKPOP operands and then add an + attribute that says fixed_base0 or fixed_base1 depending on + which base reg has the SrSP operand.""" + stack_memop_indx = -1 + if vattr(): + msgb("ATTRIBUTE-FOR-STACKOP: CHECKING", self.iclass) + for op in self.operands: + if op.is_ntluf(): + if vattr(): + msgb("ATTRIBUTE-NTLUF", "%s = %s" % (op.name,op.lookupfn_name)) + if op.lookupfn_name == 'SrSP': + if op.name == 'BASE0': + stack_memop_indx = 0 + elif op.name == 'BASE1': + stack_memop_indx = 1 + else: + pass # skip other fields + if stack_memop_indx != -1: + if vattr(): + msgb("ATTRIBUTE-FOR-STACKOP", + "%s memop index %s" % (self.iclass, stack_memop_indx)) + s = "FIXED_BASE%d" % stack_memop_indx + self.add_attribute(s) + self.add_stack_attribute(stack_memop_indx) + + + def __str__(self): + return self.dump_str() + + def dump_str(self, pad='', brief=False): + s = [] + s.append(pad) + s.append(self.iclass) + if self.uname: + s.append(" uname=%s" % str(self.uname)) + s.append(" inum=%s " % str(self.inum)) + if field_check(self,'iform') and self.iform: + s.append(" iform=%s " % str(self.iform)) + if field_check(self,'iform_input') and self.iform_input: + s.append(" iform_input=%s " % str(self.iform_input)) + s.append("pattern len=%d\n" % len(self.ipattern.bits)) + s.append(" %s ipattern: %s\n" % (pad,self.ipattern.just_bits()) ) + + if brief: + return ''.join(s) + if self.prebindings: + s.append('prebindings: \n\t' + + '\n\t'.join(map(str,self.prebindings.values())) + '\n') + for op in self.operands: + s.append(pad) + s.append(" ") + s.append(op.dump_str(pad)) + s.append("\n") + return ''.join(s) + + +def look_for_scalable_nt(agi, nt_name): + """Look for a nonterminal that is sensitive to EOSZ. It looks + recursively at NTs in the patterns, but that does not occur in x86.""" + try: + gi = agi.generator_dict[nt_name] + except: + die("Generator not found for nt_name: %s" % (nt_name)) + + for rule in gi.parser_output.instructions: + for b in rule.ipattern.bits: + if b.token == 'EOSZ': + return True + elif b.is_nonterminal(): + r_nt_name = b.nonterminal_name() + if look_for_scalable_nt(agi, r_nt_name): + return True + return False + + + +def mk_opnd(agi, s, default_vis='DEFAULT'): + op = opnds.parse_one_operand(s, + default_vis, + agi.xtypes, + agi.widths_dict) + return op + +def add_flags_register_operand(agi,ii): + """If the instruction has flags, then add a flag register operand.""" + if field_check(ii,'flags_info') and \ + ii.flags_info and ii.flags_info.x86_flags(): + rw = ii.flags_info.rw_action() + (memidx_dummy,regidx) = find_max_memidx_and_regidx(ii.operands) + s = "REG%d=rFLAGS():%s:SUPP" % ( regidx, rw ) + if vflag(): + msgb("RFLAGS-APPEND", "%s <-- %s" % ( ii.iclass, s)) + op = mk_opnd(agi,s) + if op: + ii.operands.append(op) + +def add_flags_register_operand_all(agi,parser): + for ii in parser.instructions: + add_flags_register_operand(agi,ii) + + +def rewrite_stack_push(op,memidx,regidx): + s = [] + #s.append("REG%d=SrSP():rw:SUPP" % (regidx)) + s.append("MEM%d:w:%s:SUPP" % (memidx, op.oc2)) + s.append("BASE%d=SrSP():rw:SUPP" % (memidx)) + if memidx == 0: + s.append("SEG0=FINAL_SSEG0():r:SUPP") # note FINAL_SSEG0() + else: + s.append("SEG1=FINAL_SSEG1():r:SUPP") # note FINAL_SSEG1() *** + return s + +def rewrite_stack_pop(op,memidx,regidx): + s = [] + #s.append("REG%d=SrSP():rw:SUPP" % (regidx)) + s.append("MEM%d:r:%s:SUPP" % (memidx, op.oc2)) + s.append("BASE%d=SrSP():rw:SUPP" % (memidx)) + if memidx == 0: + s.append("SEG0=FINAL_SSEG0():r:SUPP") # note FINAL_SSEG() + else: + s.append("SEG1=FINAL_SSEG1():r:SUPP") # note FINAL_SSEG1() *** + return s + + + +def expand_stack_operand(op, memidx, regidx): + """Replace the STACKPUSH and STACKPOP operands by a sequence of operands + @type op: opnds.operand_info_t + @param op: input operand that is a stack push or pop + + @type memidx: integer + @param memidx: index of the memop we should use, either 0 or 1. + + @type regidx: integer + @param regidx: index of the first register we should use for + the rSP() operand + + @rtype: [ strings ] + @return: additional text of operands (to be processed) for the + stack pointer access, memop, base, & seg. + """ + if vstack(): + msgb("EXPANDING STACK OP", "%s memidx %d regidx %d" + % (op.bits, memidx, regidx)) + if op.bits == 'XED_REG_STACKPUSH': + out = rewrite_stack_push(op,memidx,regidx) + elif op.bits == 'XED_REG_STACKPOP': + out = rewrite_stack_pop(op,memidx,regidx) + else: + out = None + if vstack(): + msgb("STACKOPS", str(out)) + return out + + + + +def find_max_memidx_and_regidx(operands): + "find the maximum memidx and regidx" + memidx = 0 + regidx = 0 + verbose = False + for op in operands: + if verbose: + msgb("OPNAME", op.name) + if op.name == 'MEM0': + memidx = 1 + elif op.name == 'MEM1': + memidx = 2 # this should cause an error if it is ever used + rnm = reg_operand_name_pattern.match(op.name) + if rnm: + current_regidx = int(rnm.group('regno')) + if verbose: + msgb("COMPARE REGS", "current %d max %d" % + ( current_regidx, regidx)) + if current_regidx >= regidx: + if verbose: + msgb("BUMPING regidx") + regidx = current_regidx+1 + return (memidx, regidx) + +def parse_operand_spec(agi,operand_spec): + """build a list classes holding operand info""" + #print str(operand_spec) + operands = [] + reset_any = False + for w in operand_spec: + op = mk_opnd(agi,w) + if op: + if op.type == 'xed_reset': + reset_any = True + else: + operands.append(op) + ############################################################## + # expand stack operands + # + found_stackop = None + for op in operands: + # msgb("BITS", str(op.bits)) + if op.bits == 'XED_REG_STACKPUSH' or op.bits == 'XED_REG_STACKPOP': + found_stackop = op + break + if found_stackop: + (memidx, regidx) = find_max_memidx_and_regidx(operands) + new_strings = expand_stack_operand(found_stackop, memidx, regidx) + # make new operands based on these strings. + if new_strings: + for s in new_strings: + new_op = mk_opnd(agi,s) + if new_op: + operands.append(new_op) + # + ############################################################## + return (operands, reset_any) + + +################################################################## +# Structured input / output of instructions +################################################################## + + +def is_nonterminal_line(s): + g = nonterminal_start_pattern.search(s) + if g: + # remove everything from the parens to the end of the line + # including two colons + t = parens_to_end_of_line.sub('', s) + wrds = t.split() + short_nt_name = wrds[-1] + if len(wrds) == 1: + type = None + msge("NONTERMINAL: " + short_nt_name + " notype") + else: + type = wrds[0] + msge("NONTERMINAL: " + short_nt_name + " type= " + type) + return (short_nt_name, type) + return (None,None) + +def remove_instructions(agi): + for g in agi.generator_list: + ii = g.parser_output.instructions[0] + if field_check(ii,'iclass'): + g.parser_output = remove_overridden_versions(g.parser_output) + +def remove_overridden_versions(parser): + """Remove instructions that have newer versions using a dictionary + of lists.""" + d = {} + for ii in parser.instructions: + if ii.iclass in parser.deleted_instructions: + continue # drop this record + if ii.uname in parser.deleted_unames: + msge("DROPPING UNAME %s" % (ii.uname)) + continue # drop this record + if ii.iclass in d: + if ii.version == d[ii.iclass][0].version: + d[ii.iclass].append(ii) + elif ii.version > d[ii.iclass][0].version: + # we have an updated version. drop the old stuff and start over + del d[ii.iclass] + d[ii.iclass] = [ii] + else: + pass # drop this record + else: + # add first element of this iclass + d[ii.iclass] = [ii] + + iis = [] + for ilist in d.values(): + iis.extend(ilist) + parser.instructions = iis + return parser + +def read_input(agi, lines): + """Read the input from a flat token-per-line file or a structured + ISA input file""" + msge("read_input " + str(global_inum)) + # first line must be a nonterminal + (nt_name, nt_type) = is_nonterminal_line(lines[0]) + if not nt_name: + die("Did not find a nonterminal: " + lines[0]) + + parser = None + # see if we have encountered this nonterminal before + try: + gi = agi.generator_dict[nt_name] + # we have a re-occurrence of an earlier nonterminal. We extend it now. + msge("FOUND OLD PARSER FOR " + nt_name) + parser = gi.parser_output + except: + # need to make a new generator & parser + parser = parser_t() + parser.nonterminal_line = lines[0].strip() + parser.nonterminal_name = nt_name + parser.nonterminal_type = nt_type + gi = agi.make_generator(nt_name) + gi.parser_output = parser + agi.nonterminal_dict.record_nonterminal(nt_name, nt_type) + + msge("Nonterminal " + parser.nonterminal_line) + msge("Nonterminal name " + parser.nonterminal_name) + lines.pop(0) + + # The {...} defined patterns must have the substring "INSTRUCTIONS" in them + if instructions_pattern.search(parser.nonterminal_name): + nlines = read_structured_input(agi, + agi.common.options, + parser, + lines, + agi.common.state_bits) + return nlines + else: + return read_flat_input(agi, + agi.common.options,parser, + lines, + agi.common.state_bits) + +def read_structured_input(agi, options, parser, lines, state_dict): + msge("read_structured_input") + while len(lines) != 0: + if verb4(): + msge("NEXTLINE " + lines[0]) + first_line = no_comments(lines[0]) + if first_line == '': + lines.pop(0) + continue + first_line = slash_expand.expand_all_slashes(first_line) + + if udelete_pattern.search(first_line): + m = udelete_full_pattern.search(first_line) + uname = m.group('uname') + msge("REGISTERING UDELETE %s" % (uname)) + parser.deleted_unames[uname] = True + lines.pop(0) + elif delete_iclass_pattern.search(first_line): + m = delete_iclass_full_pattern.search(first_line) + iclass = m.group('iclass') + parser.deleted_instructions[iclass] = True + lines.pop(0) + + + elif nonterminal_start_pattern.search(first_line): + msge("Hit a nonterminal, returning at: " + first_line ) + break + else: + ii = instruction_info_t() + okay = ii.read_structured_flexible(lines) + if okay: + #mbuild.msgb("PATTERN:", ii.ipattern_input) + # when there are multiple patterns/operands in the + # structured input, we flatten them out here, making + # multiple complete records, one per + # pattern/set-of-operands. + flat_ii_recs = expand_hierarchical_records(ii) + + for flat_ii in flat_ii_recs: + flat_ii.refine_parsed_line(agi,state_dict) + flat_ii.add_fixed_base_attribute() + flat_ii.add_scalable_attribute(agi.scalable_widths, agi) + if flat_ii.otherwise_ok: + parser.otherwise_ok = True # FIXME 2008-09-25: is this used? + else: + + parser.instructions.append(flat_ii) + + + msge("parser returning with " + str(len(lines)) + ' lines remaining.') + return lines + +################################################################## + +def junk_line(line): + if len(line) == 0: + return True + if line[0] == '#': + return True + return False + +# $$ parse_t +class parser_t(object): + def __init__(self): + self.nonterminal_line = '' + self.nonterminal_name = '' + # the actual nonterminal_type is NOW IGNORED 2008-07-22 I take + # the value from the operand storage fields type spec. I still + # use the existence of the nonterminal return type to indicate + # that an NT is a NTLUF.. FIXME!! + self.nonterminal_type = None # for lookup functions only + + # list of partitionable_info_t or instruction_info_t, which is a + # subclass of partitionable_info_t. + self.instructions = [] + + self.deleted_instructions = {} + self.deleted_unames = {} + + # if epsilon actions result in errors, otherwise_ok is False. If + # epsilon actions result in no-error, then otherwise_ok should + # be set to true. + self.otherwise_ok = False + + + def is_lookup_function(self): + if self.nonterminal_type != None: + return True + return False + + def dump_structured(self,fp): + "Print out the expanded records." + for ii in self.instructions: + slist = ii.dump_structured() + for s in slist: + fp.write(s) + fp.write('\n') + + + def print_structured_output(self,fp): + "Print the input in a structuctured token-per-line fashion" + fp.write(self.nonterminal_line + "\n") + fp.write("\n") + self.dump_structured(fp) + + + +def read_flat_input(agi, options, parser,lines,state_dict): + """These are the simple format records, one per line. Used for + non-instruction things to make partitionable objects""" + msge("read_flat_input " + str(global_inum)) + while len(lines) > 0: + if verb4(): + msge("NEXTLINE " + lines[0]) + first_line = no_comments(lines[0]) + if first_line == '': + lines.pop(0) + continue + first_line = slash_expand.expand_all_slashes(first_line) + if nonterminal_start_pattern.search(first_line): + msge("Hit a nonterminal, returning at: " + first_line ) + break + + try: + (new_bits, bindings) = first_line.split('|') + except ValueError: + die('Could not split line in to 2 pieces based on vertical bar: [' + + first_line + ']') + + (opcode_spec, + extra_bindings, + all_bit_infos, + all_prebindings, + otherwise_ok) = parse_opcode_spec( agi, new_bits, state_dict) + + if otherwise_ok: + parser.otherwise_ok = True # FIXME 2008-09-25 need to change this + # if 'otherwise' node have RHS support. + lines.pop(0) + continue + + operands_input = bindings.split() + (operands, reset_for_prefix) = parse_operand_spec(agi, operands_input) + if extra_bindings: + extra_operands = parse_extra_operand_bindings(agi, extra_bindings) + operands.extend(extra_operands) + + # now put opcode_spec, and operands in to a data structure + + ## FIXME add a table and line number for the name? + pi = partitionable_info_t('',new_bits, operands_input) + pi.input_str = first_line + + pi.ipattern = bits_list_t() + pi.ipattern.bits = all_bit_infos + + pi.prebindings = all_prebindings + + pi.operands = operands # list of opnds.operand_info_t + pi.reset_for_prefix = reset_for_prefix + + parser.instructions.append(pi) # FIXME: instruction is a misnomer here + + lines.pop(0) + + return lines + + +############################################################################ +## $$ Graph build +############################################################################ + +# $$ graph_node_t +class graph_node(object): + + global_node_num = 0 + + def __init__(self, token,bitpos): + self.id = self.__class__.global_node_num + #msge("CREATE NODE %d" % (self.id)) + self.__class__.global_node_num += 1 + self.token = token + self.instructions = [] # a list of instruction_info_t class items + + # the relative bit position, mod 8, assuming nonterminals return bytes + self.bitpos_mod8 = bitpos & 7 + + # number of bits we use to decide on the next node. + self.decider_bits = 0 + + # number of bits we accept and skip over to get to the next + # decider-group-of-bits + self.skipped_bits = 0 + + # a nonterminal that follows this node + self.nonterminal = None + + # an operand decision point + self.operand_decider = None + + # When we have to go back and pick up a bit that was ignored + # earlier, we list it here. + self.back_split_pos = None + + # Usually we want the epsilon actions to result in decode + # errors. When we want to permit epsilon action for prefix-type + # nonterminals, then we set self.otherwise_ok to True. + self.otherwise_ok = False + + self.next = {} + + # The capture function_object_t for the operands we need to + # capture at this node. + self.capture_function = None + + def is_nonterminal(self): + if self.nonterminal != None: + return True + return False + + def is_operand_decider(self): + if self.operand_decider != None: + return True + return False + def value_test_node(self): + """returns (value_test, value_to_test) """ + if self.is_operand_decider(): + if len(self.next) == 2: + found_value = False + found_other = False + value = None + for k,nxt in self.next.iteritems(): + if k == 'other' and found_other==False: + found_other = True + elif found_value == False: + found_value = True + value = k + else: + # multiple values + return (False, None) + if found_value and found_other: + return (True, value) + return (False, None) + + def leaf(self): + if len(self.next) == 0: + return True + return False + + def dump_str(self,pad=''): + eol = "\n" + s = pad + 'id: ' + str(self.id) + s += ' token: ' + str(self.token) + s += ' next nodes: %d' % (len(self.next)) + s += ' insts: %d' % (len(self.instructions)) + s += eol + s += pad + 'skipped_bits: ' + str(self.skipped_bits) + s += ' decider_bits: ' + str(self.decider_bits) + if self.otherwise_ok: + s += ' otherwise_ok: ' + str(self.otherwise_ok) + if self.back_split_pos: + s += ' back_split_pos: ' + str(self.back_split_pos) + if self.nonterminal != None: + s += " NONTERMINAL:" + str(self.nonterminal) + if self.operand_decider: + s += ' OPERAND-DECIDER:' + str(self.operand_decider) + s += eol + # only print instructions for leaf nodes + if len(self.next) == 0: + s += pad + 'insts: ' + eol + for ii in self.instructions: + s += ii.dump_str(pad + ' ') + eol + return s + def dump(self,pad=''): + msge(self.dump_str(pad)) + + + + +def new_node(graphnode, token, bitpos): + node = graph_node(token,bitpos) + graphnode.next[token] = node + return node + +def get_bit(ii,bitpos): + if bitpos >= len(ii.ipattern.bits): + return 'badbit' + return ii.ipattern.bits[bitpos] + + +def collect_required_values(instructions, bitpos): + """Return a list of the required values for a list of operand + deciders.""" + d = [] + for ii in instructions: + if not ii.ipattern.bits[bitpos].is_operand_decider(): + die("Died looking for an operand decider") + operand_decider = ii.ipattern.bits[bitpos] + if operand_decider.test == 'eq': + if operand_decider.requirement not in d: + d.append(operand_decider.requirement) + return d + + +def partition_by_required_values(options, instructions, bitpos, token, + required_values, state_space, splatter=True, + operand_storage_dict=None): + """Return a dictionary of lists of instructions, split by the + elements of the required_values list""" + #msge("\n\n\nNEW PARTITION:" ) + d = {} + all_values = {} + for ii in instructions: + if not ii.ipattern.bits[bitpos].is_operand_decider(): + die("THIS DOES NOT HAPPEN") + # we have an operand decider + operand_decider = ii.ipattern.bits[bitpos] + if vod(): + msge("PARTITIONING OPERAND DECIDER TOKEN: " + + str(operand_decider.token)) + if operand_decider.token != token: + die("Mixed partitionings of operand_deciders: splitting on " + token + + " but encountered " + operand_decider.token) + if operand_decider.test == 'eq': + # just one instruction needs to be placed + if vod(): + msge("Setting EQ OD %s" % operand_decider.requirement) + if operand_decider.requirement not in d: + d[ operand_decider.requirement ] = [ ii ] + else: + d[ operand_decider.requirement ].append(ii) + all_values[operand_decider.requirement]=True + elif operand_decider.test == 'ne': + # add to trimmed list of req'd vals ( excluding this value) + # THIS DUPLICATES (references to) NODES if there is more than + # one choice. + if operand_decider.token in state_space: + all_values_for_this_od = state_space[operand_decider.token] + if vod(): + msge("NE OD: all values from state space %s" % + (str(all_values_for_this_od))) + else: + try: + osf = operand_storage_dict[operand_decider.token] + if osf.ctype.find('enum') == -1: + nvalues = 1 << int(osf.bitwidth) + #all_values_for_this_od = map(str,range(0,nvalues)) + all_values_for_this_od = range(0,nvalues) + if vod(): + msge("Synthesized values for %s: %s" % + ( operand_decider.token, + ", ".join(map(str,all_values_for_this_od)))) + except: + die("could not find %s in state space dictionary" % + (operand_decider.token)) + + if vod(): + msge("All values for OD: %s" % + ", ".join(map(str,all_values_for_this_od))) + for a in all_values_for_this_od: + all_values[a]=True + trimmed_vals = filter(lambda (x): x != operand_decider.requirement, + all_values_for_this_od) + if len(trimmed_vals) == 0: + die("We had a not-equals requirement but did" + + " not have any other values to bin against.") + + # DO NOT MAKE ONE NODE PER trimmed_vals element - that + # explodes the graph size. + #msge("\tAdding other with values " + str(trimmed_vals)) + other = 'other' + if other not in d: + d[ other ] = [ (trimmed_vals,ii) ] + else: + d[ other ].append((trimmed_vals,ii) ) + + #msge("RETURNING FROM PARTITION: %s" % ( str(d.keys()))) + return (d, all_values.keys() ) + + +def all_same_operand_decider(ilist,bitpos): + """Return false if not all of the next bits are the same + operand-decider, also return operand decider if True""" + last = None + for i in ilist: + plen = len(i.ipattern.bits) + if bitpos >= plen: + #msge("Fell off end of bits") + return (False,None) + + # They can have different required values, but they must be the + # same deciding token. + + if i.ipattern.bits[bitpos].is_operand_decider(): + if last == None: + last = i.ipattern.bits[bitpos] + elif last.token != i.ipattern.bits[bitpos].token: + return (False, None) + else: + return (False, None) # not an operand decider + if last: + return (True, last) + return (False, None) + + + +def all_same_nonterminal(ilist,bitpos): + """Return false if not all of the next bits are the same + nonterminal, also return nonterminal if True""" + last_nonterminal = None + for i in ilist: + + plen = len(i.ipattern.bits) + if bitpos >= plen: + #msge("Fell off end of bits") + return (False,None) + if i.ipattern.bits[bitpos].is_nonterminal(): + if last_nonterminal == None: + last_nonterminal = i.ipattern.bits[bitpos] + elif last_nonterminal != i.ipattern.bits[bitpos]: + #msge("Differing NTs: [" + str(last_nonterminal)+ "] vs [" + #+ str(i.ipattern.bits[bitpos]) + ']') + return (False, None) + else: + #msge("Not a nonterminal") + return (False, None) # not a nonterminal + if last_nonterminal: + return (True, last_nonterminal) + return (False, None) + + +def move_candidate_od_to_front(bitpos, candidate_od, bit_info_t_list): + """Move a speicific od names candidate_od from wherever it is in + the list (after bitpos) to the location bitpos""" + + found = False + for i,b in enumerate(bit_info_t_list[bitpos+1:]): + if b.is_operand_decider(): + if b.token == candidate_od: + found = True + badpos = i + bitpos + 1 + if found: + # move bit_info_t_list[badpos] to just before bitpos + if vrearrange(): + msge("BEFORE REARRANGE: bitpos = %d and badpos = %d" % + (bitpos, badpos)) + for b in bit_info_t_list: + msge( "\t" + str(b) ) + z = bit_info_t_list[badpos] + del bit_info_t_list[badpos] + bit_info_t_list.insert(bitpos,z) + if vrearrange(): + msge("AFTER REARRANGE:") + for b in bit_info_t_list: + msge( "\t" +str(b) ) + + return found + +def renumber_one_ipattern(i): + bitpos = 0 + for p in i.ipattern.bits: + p.pbit = bitpos + bitpos = bitpos + 1 + +def renumber_bitpos(ilist): + for i in ilist: + renumber_one_ipattern(i) + +def rearrange_at_conflict(ilist,bitpos): + """Try to rearrange ODs at a conflict""" + + # build up a list of candidate ods + + # FIXME 2008-11-12 Mark Charney: could search for all sequential + # ODs rather than just one neighboring OD. + + candidate_ods = [] + for i in ilist: + if bitpos >= len(i.ipattern.bits): + return False + if i.ipattern.bits[bitpos].is_operand_decider(): + t = i.ipattern.bits[bitpos].token + if t not in candidate_ods: + candidate_ods.append(t) + + # look ahead one spot too... + nbitpos = bitpos+1 + if nbitpos < len(i.ipattern.bits): + if i.ipattern.bits[nbitpos].is_operand_decider(): + t = i.ipattern.bits[nbitpos].token + if t not in candidate_ods: + candidate_ods.append(t) + + if len(candidate_ods) == 0: + msge("REARRANGE: NO CANDIDATE OD") + return False + + retry = True + for candidate_od in candidate_ods: + if retry == False: + break + msge("REARRANGE ATTEMPT using %s" % (candidate_od)) + retry = False + for i in ilist: + if i.ipattern.bits[bitpos].is_operand_decider(): + if candidate_od == i.ipattern.bits[bitpos].token: + msge("\tSKIPPING %s inum %d -- already fine" % + ( i.get_iclass(), i.inum)) + else: + msge("\tREARRANGE needs to juggle: %s inum %d" % + ( i.get_iclass(), i.inum)) + # attempt to juggle ODs in i.ipattern.bits to get + # candidate_od in to bitpos + if move_candidate_od_to_front(bitpos, + candidate_od, + i.ipattern.bits): + msge("\tREARRANGE one pattern worked for %s inum %d" % + ( i.get_iclass(), i.inum)) + else: + retry = True + msge("\tREARRANGE FAILED for %s. Trying again..." % + (candidate_od)) + break # hit the outer loop + + if retry == True: + msge("REARRANGE FAILED for all ODs") + return False + + # make sure they are all the same OD at this bitpos now + candidate_od = None + for i in ilist: + if i.ipattern.bits[bitpos].is_operand_decider(): + if candidate_od == None: + candidate_od = i.ipattern.bits[bitpos].token + elif candidate_od != i.ipattern.bits[bitpos].token: + msge("REARRANGE FAILED AT END(1)! bitpos = %d" % (bitpos)) + msge( i.dump_str() ) + return False + else: + print_node(ilist) + msge("REARRANGE FAILED AT END(2)!") + return False + msge("REARRANGE: FIXED OD CONFLICT!") + + # since we rearranged, we need to renumber the pbits or the + # extraction will not work properly. + renumber_bitpos(ilist) + return True + + +def some_funky_spot(ilist,bitpos): + """Return true if some pattern has a nonterminal or operand decider""" + for i in ilist: + if bitpos < len(i.ipattern.bits): + if i.ipattern.bits[bitpos].is_nonterminal(): + return True + if i.ipattern.bits[bitpos].is_operand_decider(): + return True + return False + +def print_split(others,ones,zeros,brief=False): + for s,lst in [('Others',others), + ('Ones', ones), + ('Zeros', zeros)]: + msge(s +': ') + for ii in lst: + try: + msge( ii.dump_str(brief=brief)) + except: + msge( "XUNKNOWN: " + str(ii) ) + + +def partition_nodes(ilist,bitpos): + """return a tuple of lists of nodes whose next bit is zero, one or + a letter (others)""" + zeros = [] + ones = [] + others = [] + zero = '0' + one= '1' + for inst in ilist: + bit = inst.ipattern.bits[bitpos] + if bit.value == zero: + zeros.append(inst) + elif bit.value == one: + ones.append(inst) + else: + others.append(inst) + return (ones,zeros,others) + +def print_node(ilist): + for ii in ilist: + msge("\t" + ii.dump_str()) + +def at_end_of_instructions(ilist, bitpos): + """If all instructions are done with their bits, return 1 + None). Check for length problems too. If not done, return 0. + If there is an error, return -1""" + done = False + notdone = False + for ii in ilist: + if isinstance(ii,types.TupleType): + die("Bad tuple where instruction expected: "+ str(ii)) + if bitpos >= len(ii.ipattern.bits): + done = True + else: + notdone = True + if done: + if notdone: + msge("Length error: some instructions done and some" + + " are not done simultaneously") + msge("ilist len = " + str(len(ilist))) + msge("\n\nILIST:") + for ii in ilist: + msge( 'bitpos:' + str(bitpos) + + ' len-pattern:' + str( len(ii.ipattern.bits))) + if (len(ii.ipattern.bits)) == 0: + msge("BAD INST: %s" % ( str(ii))) + msge("\n\nNODE:") + print_node(ilist) + #die("Dying") + return -1 # problem: some done, some not done + else: + return 1 # all is well, all done + return 0 # not done yet + +def no_dont_cares(instructions, bitpos): + "Return True if there are no dont cares" + for i in instructions: + if i.ipattern.bits[bitpos].is_dont_care(): + return False + return True + +def some_different(instructions,bitpos): + """Return True if there are ones and zeros and no don't cares, + nonterminals or operand deciders""" + zero = '0' + one= '1' + + zeros = 0 + ones = 0 + for i in instructions: + if i.ipattern.bits[bitpos].value == zero: + zeros += 1 + elif i.ipattern.bits[bitpos].value == one: + ones += 1 + if zeros > 0 and ones > 0: + return True + return False + +def scan_backwards_for_distinguishing_bit(instructions,bitpos): + """Return a tuple (t/f, bitpos) that says where we can partition + this node further (when possible).""" + + b = bitpos - 1 + while b >= 0: + if no_dont_cares(instructions,b): + if some_different(instructions,b): + msge("FALLBACK: we can parition on the 1s and 0s at bitpos " + + str(b)) + return (True, b) + b = b - 1 + msge("FALLBACK: No bits left to examine: at bit %d" % (bitpos)) + return (False, None) + +def convert_splitpos_to_bit_index(graph,splitpos): + """Convert the fake bitposition in splitpos in to a real bit + position by skipping leading operand deciders. Intervening + nonterminals might mess this up??? FIXME + """ + i = graph.instructions[0] + real_bits = 0 + for b in i.ipattern.bits[0:splitpos]: + if not b.is_operand_decider(): + real_bits += 1 + msge("BACKSPLIT fake bitpos: %d real bitpos: %d\n" % (splitpos, real_bits)) + return real_bits + + + + +def back_split_graph(common, graph, bitpos, skipped_bits, splitpos): + """Partition based on splitpos and then recur in to build_sub_graph + for the partitions.""" + + options = common.options + msge("back_split_graph: based on " + str(splitpos)) + (ones,zeros,others) = partition_nodes(graph.instructions,splitpos) + if vbuild(): + s = "ones %d zeros %d others %d" % (len(ones), len(zeros), len(others)) + msge('back_split_graph: ' + s ) + if len(others) > 0: + die("We encountered some junk on a back-split") + + if len(zeros) == 0: + die("We didn't have any zeros in the back-split partition") + if len(ones) == 0: + die("We didn't have any ones in the back-split partition") + + graph.skipped_bits = skipped_bits + graph.decider_bits = 1 + graph.back_split_pos = convert_splitpos_to_bit_index(graph,splitpos) + + # zero child node + znode = new_node(graph,'0',bitpos) + znode.instructions.extend(zeros) + build_sub_graph(common,znode,bitpos, 0) # RECUR + + # one child node + onode = new_node(graph,'1',bitpos) + onode.instructions.extend(ones) + build_sub_graph(common,onode,bitpos, 0) # RECUR + + + +# global hack -- FIXME: 2007-07-10 to get the operand storage +# dictionary in to +# partition_by_required_values. +g_operand_storage_dict = None + +def build_sub_graph(common, graph, bitpos, skipped_bits): + """Recursively partition instructions based on 1s, 0s and + placeholder letters""" + global g_operand_storage_dict + options = common.options + + # expand_dont_cares is an important control for the graph + # building. If expand_dont_cares is false, whenever we see a + # dont-care in some thing at the next bit position, then we skip + # that bit in the graph formation. This leads to problems when + # skipped 1s and 0s are required to disambiguate the tree + # downstream. When expand_dont_cares is true, then whenever we have + # some 1s or 0s that happen to collide with a dont-care in some + # thing at the next bit positiona, then we copy all the dont-care + # ("others") on both zero and one successor nodes. Something down + # stream will disambiguate them necessarily. The nice thing about + # expand_dont_cares being true is that (a) one does not have the + # problem alluded to above (which I've only seen when processing + # the SIB BASE table, and hacked around by swapping the nonterminal + # argument order). And (b), we don't have to confirm that bits we + # skipped have required values when we get down to just one + # decoding option. + # + # I only expand the don't cares if they happen to line up with some + # nodes that have 1s or 0s in them. This attempts to prevent the + # immediates from exploding the graph. But if immediates line up + # with some 1s and 0s, they'll get expanded. The 1B PUSH does not + # get expanded because the 0101_0xxx is unique once you get to the + # 0101_0 part. So that would have to be coalesced in graph merging + # later on. + # + # + # WARNING: When expand_dont_cares is true the graph currently + # explodes in size. + expand_dont_cares = False + + # skip_constants is an important control for the graph building. If + # skip_constants is false, then when the next bit for all + # instructions is 1 or the next bit for all instructions is 0, then + # we pretend it is decider bit and make a new node. This node is + # trivial because it only has one out-edge, but it enabls the graph + # merger to merge it in to the parent node when merging is + # done. This results in a smaller graph. When skip_constants is + # True, then we "skip" bits where the next bit is always 1 or 0 for + # all instructions. In this case, we still need to confirm that we + # have a 1 or 0 at decode time, but it doesn't contribute new + # information. After node merging, the graph is smaller when + # skip_constants is False at graph build time, so that is the + # preferred setting. + skip_constants = False + + # stop_early is another important control. If stop_early is True, + # then we do not continue building the graph when we are down to + # one instruction. When stop_early is False, we keep going even + # when there is only one instruction. Setting stop_early to False + # is required to get the nonterminals that may be down stream built + # in to the graph. + stop_early = False + + if vbuild(): + msge("[SUBGRAPH BUILD] Token %s ninst %d" % + (str(graph.token), len(graph.instructions))) + for ii in graph.instructions: + msge(ii.dump_str(' ')) + + if stop_early and len(graph.instructions) == 1: + # we are down to one option. We must verify when decoding, but + # the path is now determined fully. + return + + # Go to the next bit. Note: we initialize the bitpos to -1 so that + # when we advance it here the first time, we start with bit zero. + + bitpos += 1 + if vbuild(): + msge("Token " + str(graph.token) + " Reached bit " + str(bitpos)) + + at_end = at_end_of_instructions(graph.instructions,bitpos) + if at_end == 1: + if vbuild(): + msge("Hit end of instructions -- skipped bits " + str(skipped_bits)) + if len(graph.instructions) > 1: + msge("\nBUILD ERROR: more than one leaf when ran out of bits:") + for ii in graph.instructions: + msge(ii.dump_str(' ')) + msge("\n\n") + (okay, splitpos) = scan_backwards_for_distinguishing_bit( + graph.instructions,bitpos) + if okay: + msge("NEED TO BACKSPLIT AT POSITION %d" % (splitpos)) + # redo this bit (hence bitpos-1) once we split based on splitpos + back_split_graph(common, graph, bitpos-1, skipped_bits, splitpos) + return + else: + msge("Back-split failed to solve the problem") + die("BUILD ERROR: more than one leaf when ran out of bits." + + " See stdout.") + graph.skipped_bits = skipped_bits + return + elif at_end == -1: + if vbuild(): + msge("Hit end of SOME instructions -- try back_split") + (okay, splitpos) = \ + scan_backwards_for_distinguishing_bit(graph.instructions,bitpos) + if not okay: + die("Back-split failed to solve ending problem") + else: + # redo this bit (hence bitpos-1) once we split based on splitpos + back_split_graph(common, graph, bitpos-1, skipped_bits, splitpos) + return + + if vpart(): + msge("Here is what we are considering, bitpos" + str(bitpos) + ":") + for ii in graph.instructions: + msge(ii.dump_str(' ') + '\n') + + ##################################################################### + + + iterations = 0 + splitting = True + while splitting: + #msge("SPLIT ITERATION: %d" % (iterations)) + if iterations > 1: + die("We should not be trying to resplit things more than once") + iterations += 1 + + # Check for identical operand deciders + (all_same_decider, operand_decider) = \ + all_same_operand_decider(graph.instructions,bitpos) + if all_same_decider: + if vbuild(): + msge("All same operand decider: %s" % operand_decider) + # hit an operand decider + + # tell current node that it is an operand decider + graph.operand_decider = operand_decider # a special kind of bit_info_t + graph.skipped_bits = skipped_bits + + # Collect up the required values... + required_values = collect_required_values(graph.instructions, bitpos) + if vpart(): + msge("Required values for operand decider " + str(required_values)) + + # When we have things that ignore a particular decider we need + # to copy everything else to all the options. NOTE: this must be + # false because when set to true, it messes up the subsequent bitpos + # ordering for things that were skipped. + splatter_dont_cares = False + + # split up the nodes based on the different values observed. + (node_partition,values) = \ + partition_by_required_values(options, graph.instructions, bitpos, + operand_decider.token, + required_values, common.state_space, + splatter_dont_cares, + g_operand_storage_dict) + + graph.child_od_key_values = values + + + # check to see if all the 'other' conditions are the same. + # if not, we must splatter them. + need_to_splatter = False + previous_trimmed_values = None + scalar_values = set() + for k,partition in node_partition.iteritems(): + if vpart(): + msge("SPATTER SCAN: Operand decider partition key= " + str(k)) + if isinstance(partition[0],types.TupleType): + for trimmed_values, ii in partition: + s = set(trimmed_values) + if previous_trimmed_values == None: + previous_trimmed_values = s + if s != previous_trimmed_values: + # need to splatter! + msge("X9 need to splatter based on differing " + + "other conditions") + need_to_splatter = True + break + else: + scalar_values.add(k) + + # if there is an overlap between the 'other' values and + # values referenced by non "other" nodes (scalar ODs), then + # we need to splatter. MOD=3 and MOD!=3 will not get splattered. + # But X=0, X=1, X!=2 will get splattered since X!=2 -> X= 0 or 1. + # and that overlaps with existing scalar values. + + if not need_to_splatter and previous_trimmed_values: + if scalar_values.intersection(previous_trimmed_values): + msge("X9 need to splatter based on cases overlapping " + + "with scalar dispatch") + need_to_splatter = True + + # fix up the 'other' conditions so that they are partitionable. + if need_to_splatter: + msge("Splattering because of conflicting 'other' conditions") + new_node_partition = {} + for k,partition in node_partition.iteritems(): + if isinstance(partition[0],types.TupleType): + for trimmed_values, ii in partition: + for tv in trimmed_values: + try: + new_node_partition[tv].append(ii) + except: + new_node_partition[tv]=[ii] + else: + try: + new_node_partition[k].extend(partition) + except: + new_node_partition[k]=partition + # replace old partition with splattered partition + node_partition = new_node_partition + + + # set up the next nodes and give them their instructions. + + for k,partition in node_partition.iteritems(): + if vpart(): + msge("PARTITIION: Operand decider partition key= " + str(k)) + next_node = new_node(graph,k,bitpos) + + if isinstance(partition[0],types.TupleType): + # store the key choices in the node for later graph building + for trimmed_values, ii in partition: + next_node.trimmed_values = trimmed_values + next_node.instructions.append(ii) + else: + if k == 'XED': # FIXME: why is this test here? / 2009-02-06 + die("Bad operand decider: " + k ) + next_node.instructions.extend(partition) + + # build the subgraphs for the children + for child in graph.next.itervalues(): + # RECUR for operand-decider + build_sub_graph(common, child, bitpos, 0) + return + + #################################################################### + # Check for identical nonterminals + # nt is the bit_info_t for the nonterminal + (all_same_nt, nt) = all_same_nonterminal(graph.instructions,bitpos) + if all_same_nt: + if vbuild(): + msge("All same nt") + # hit a nonterminal. + + # tell current node that it is a nonterminal + graph.nonterminal = nt + graph.skipped_bits = skipped_bits + if vbuild(): + msge("GRAPHBLD: Nonterminal: " + + str(nt) + " skipped_bits: " + str(skipped_bits)) + # build a new node that follows the nonterminal and give it + # all the instructions. The '-' denotes we go there when the + # nonterminal is done parsing. + nt_next_node = new_node(graph,'-',bitpos) + + nt_next_node.instructions.extend(graph.instructions) + + # carry on build the graph from the nt_next_node + build_sub_graph(common, nt_next_node, bitpos, 0) + return + else: + if vbuild(): + msge("Not all the same nonterminal.") + + ##################################################################### + # *AFTER* we advance the bit, we partition the nodes based on + # *the current bit + + (ones,zeros,others) = partition_nodes(graph.instructions,bitpos) + if vbuild(): + s = "ones %d zeros %d others %d" % (len(ones), + len(zeros), len(others)) + msge('build_sub_graph ' + s ) + + # make sure we do not have some things that hit the Nonterminal + # and some that do not + if some_funky_spot(graph.instructions,bitpos): + msge('FUNKY SPOT: bitpos %d' % (bitpos)) + print_split(others,ones,zeros,brief=True) + if rearrange_at_conflict(graph.instructions, bitpos): + msge("REARRANGED ODs TO BYPASS PROBLEM at bitpos %d" % bitpos ) + # try resplitting the nodes now that we've juggled stuff + continue + + else: + (okay, splitpos) = \ + scan_backwards_for_distinguishing_bit(graph.instructions, + bitpos) + if not okay: + die("Look-ahead error - only some are nonterminal " + + "at next bit position") + else: + # redo this bit (hence bitpos-1) once we split based on + # splitpos. + back_split_graph(common, graph, + bitpos-1, skipped_bits, splitpos) + return + else: + splitting = False # we are good to exit + + if verb7(): + print_split(others,ones,zeros) + + + # FIXME: enabling either of these lines causes a python error at + # this point we never need this nodes instructions again. (Turns + # out we need them anyway for generating args for the nonterminals, + # so all is not lost, just confused.) + #del graph.instructions + #graph.instructions = [] + + # if there are any others in then, we cannot split on this bit, so + # just keep going. Similarly, if there are all 1s or all 0s then we + # just keep going (when skip_constants is True). Only split the + # node if it is a mix of 1s and 0s. + if len(others) > 0: + + ####OLD STUFF build_sub_graph(common,graph, skipped_bits+1) # RECUR + + if expand_dont_cares and (len(ones)>0 or len(zeros)>0): + # we only do the expansion if ones/zeros are floating around + # at this point. Build two nodes. Put all the ones in the + # "one" node, all hte zeros in the "zero" node and the others + # in both nodes! Then recur on both nodes + if vbuild(): + msge("Duplicating dontcares") + graph.skipped_bits = skipped_bits + graph.decider_bits = 1 + + # zero child node + znode = new_node(graph,'0',bitpos) + if len(zeros) > 0: + znode.instructions.extend(zeros) + # Add the "dont-care others" to the zeros + znode.instructions.extend(others) + build_sub_graph(common,znode,bitpos, 0) # RECUR + + # one child node + onode = new_node(graph,'1',bitpos) + if len(ones) > 0: + onode.instructions.extend(ones) + # Add the "dont-care others" to the ones + onode.instructions.extend(others) + build_sub_graph(common,onode,bitpos, 0) # RECUR + + else: + build_sub_graph(common,graph,bitpos, skipped_bits+1) # RECUR + + elif len(ones) > 0 and len(zeros) == 0: + # Some one's but no zeros, no others + if vbuild(): + msge("some ones, no zeros no others") + if skip_constants: + build_sub_graph(common,graph, bitpos, skipped_bits+1) # RECUR + else: + graph.skipped_bits = skipped_bits + graph.decider_bits = 1 + + onode = new_node(graph,'1',bitpos) + onode.instructions.extend(ones) + build_sub_graph(common,onode,bitpos, 0) # RECUR + elif len(ones) == 0 and len(zeros) > 0: + # Some zeros's but no ones, no others + if vbuild(): + msge("some zeros, no ones no others") + if skip_constants: + build_sub_graph(common,graph,bitpos, skipped_bits+1) + else: + graph.skipped_bits = skipped_bits + graph.decider_bits = 1 + + znode = new_node(graph,'0',bitpos) + znode.instructions.extend(zeros) + build_sub_graph(common,znode, bitpos, 0) # RECUR + else: + # some zeros, some ones -> split it + if vbuild(): + msge("Just 0s and 1s, splitting, building a subgraph") + graph.skipped_bits = skipped_bits + graph.decider_bits = 1 + + # zero child node + znode = new_node(graph,'0',bitpos) + znode.instructions.extend(zeros) + build_sub_graph(common,znode, bitpos, 0) # RECUR + + # one child node + onode = new_node(graph,'1',bitpos) + onode.instructions.extend(ones) + build_sub_graph(common,onode,bitpos, 0) # RECUR + + + +def build_graph(common, parser_output, operand_storage_dict): + """Build a graph of the parsed instructions. Return the root""" + if vgraph_res(): + print_resource_usage('build_graph.0') + global g_operand_storage_dict + g_operand_storage_dict = operand_storage_dict + if verb4(): + msge("Building graph:") + print_node(parser_output.instructions) + if parser_output.otherwise_ok: + msge("Otherwise-ok is set to true for this nonterminal") + nt_name = parser_output.nonterminal_name + graph = graph_node(nt_name,0) + #msge("Building new graph: %d" % (graph.id)) + + #THIS LINE IS THE HUGE BIG MEMORY HOG. IS IT REALLY NEEDED??? NO!! + # Removing it cut the memory usage in half and the execution time in half! + #ilist = copy.deepcopy(parser_output.instructions) + ilist = parser_output.instructions + if vgraph_res(): + print_resource_usage('build_graph.1') + graph.instructions.extend(ilist) + if vgraph_res(): + print_resource_usage('build_graph.2') + bitpos = -1 + skipped_bits = 0 + build_sub_graph(common,graph, bitpos, skipped_bits) + if vgraph_res(): + print_resource_usage('build_graph.3') + return graph + + +def print_graph(options, node, pad =''): + s = node.dump_str(pad) + msge(s) + for k,nxt in node.next.iteritems(): # PRINTING + s = pad + ' key: ' + str(k) + msge(s) + print_graph(options, nxt, pad + ' ') + +############################################################################ +## $$ OPCAP capturing operands +############################################################################ + +def collect_immediate_operand_bit_positions(options, opnd, ii): + """Fill in the opnd.bit_positions list with index of each bit in + the immediate operand.""" + limit = len(ii.ipattern.bits) + last_bit_pos = {} # record the next starting point for each letter + # we encounter + for b in opnd.bits: # try to find each bit. + if b in last_bit_pos: + start_at = last_bit_pos[b] + else: + start_at = 0 + found = False + # look at the bits in the ipattern + for p in range(start_at,limit): + if ii.ipattern.bits[p].value == b: + opnd.bit_positions.append( p ) + # bump our new starting point to after the position we just found + last_bit_pos[b] = p+1 + found = True + break + + if not found: + die("Did not find bit %s of operand %s in instruction %s " % + (str(b), str(opnd), ii.dump_str())) + +################################ + +uninteresting_operand_types_list = ['imm_const', 'reg', 'relbr', 'ptr', 'error', + 'nt_lookup_fn', 'mem', 'xed_reset', + 'flag', 'agen'] + +uninteresting_operand_types_dict = \ + dict(zip(uninteresting_operand_types_list, + [True]*len(uninteresting_operand_types_list))) + + +def decorate_operand(options,opnd,ii): + """Set opnd.bit_positions list and opnd.rightmost_bitpos for this + operand in this instruction""" + + global uninteresting_operand_types_dict + + if opnd.type in uninteresting_operand_types_dict: + pass + elif opnd.type == 'imm': + if ii.prebindings and opnd.name in ii.prebindings: + opnd.bit_positions = \ + map(lambda(x): x.pbit, ii.prebindings[opnd.name].bit_info_list) + else: + collect_immediate_operand_bit_positions(options,opnd, ii) + opnd.rightmost_bitpos = max(opnd.bit_positions) + else: + die("Unhandled operand type: " + str(opnd)) + + + +def decorate_operands(options,agi): + for gi in agi.generator_list: + for ii in gi.parser_output.instructions: + for opnd in ii.operands: + decorate_operand(options,opnd,ii) + + +def find_all_operands(options, node): + """Return a set of operand names for this graph node. Just look at + all the instructions.""" + operands = set() + + if vcapture(): + for ii in node.instructions: + for opnd in ii.operands: + msge("FINDALL: " + opnd.name + " type= [" + opnd.type + ']') + + # Get the operands from the first instruction + # Only look at the imm-type operands + ii = node.instructions[0] + for opnd in ii.operands: + if vcapture(): + msge("FINDALL Operand " + opnd.name + " type= [" + opnd.type + ']') + # at leaves, include all operands. at internal nodes, just the + # reg, imm and imm_const operands. + if node.leaf(): + operands.add(opnd.name) + elif opnd.type == 'imm' or opnd.type == 'imm_const' or opnd.type == 'reg': + operands.add(opnd.name) + + # Remove any operands that are not in every instruction. + # (We do not reprocess the first element.) + for ii in node.instructions[1:]: + op2set = set() + for opnd in ii.operands: + if node.leaf(): + # FIXME: this *was* operands.add(opnd.name) + # 2007-06-26. Not sure if it was wrong or equivalent. + op2set.add(opnd.name) + elif opnd.type == 'imm' or opnd.type == 'imm_const' or \ + opnd.type == 'reg': + op2set.add(opnd.name) + operands = operands.intersection(op2set) + return operands + + +def collect_instruction_types(agi, master_list): + """Collect the iclass / category /extension""" + for generator in agi.generator_list: + for ii in generator.parser_output.instructions: + if field_check(ii, 'iclass'): + plist = [] + if field_check(ii, 'attributes'): + plist = ii.attributes + + if field_check(ii, 'iclass_string_index'): + iclass_string_index = ii.iclass_string_index + else: + iclass_string_index = 0 + + t = (ii.iclass, ii.extension, ii.category, ii.isa_set, + plist, + iclass_string_index) + if ii.iform_enum in master_list: + # duplicate iform - check ext/category + (oldi, olde, oldc, + olds, oldp, oldisi) = master_list[ii.iform_enum] + if olde != ii.extension: + mbuild.die("EXTENSION ALIASING IN IFORM TABLE", ii.iform_enum) + msgb("DUPLICATE IFORM", ii.iform_enum) + master_list[ii.iform_enum] = t + + +def collect_isa_sets(agi): + """Collect the isaset info""" + s = set() + for generator in agi.generator_list: + for ii in generator.parser_output.instructions: + if field_check(ii, 'iclass'): + s.add(ii.isa_set.upper()) + return s + + + +def collect_tree_depth(node, depths={}, depth=0): + """Collect instruction field data for enumerations""" + + cdepth = depth + 1 + if len(node.next) == 0: + try: + depths[cdepth] += 1 + except: + depths[cdepth] = 1 + else: + for child in node.next.itervalues(): + collect_tree_depth(child, depths, cdepth) + return depths + +def collect_ifield(options, node, field, master_list): + """Collect instruction field data for enumerations""" + for ii in node.instructions: + if field_check(ii, field): + s = getattr(ii,field) + if s not in master_list: + master_list.append(s) + for child in node.next.itervalues(): + # FIXME: sloppy return value handling??? + collect_ifield(options,child, field,master_list) + return master_list + + +def collect_ofield(options, node, field, master_list): + """Collect operand field data for enumerations""" + for ii in node.instructions: + for opnd in ii.operands: + if field_check(opnd, field): + s = getattr(opnd,field) + if s != None and s not in master_list: + master_list[s] = True + for child in node.next.itervalues(): + collect_ofield(options,child, field,master_list) + +def collect_ofield_operand_type(options, node, field, master_list): + """Collect operand type enumeration data""" + for ii in node.instructions: + for opnd in ii.operands: + if field_check(opnd, field): + s = opnd.get_type_for_emit() + #s = getattr(opnd,field) + if s != None and s not in master_list: + master_list[s] = True + for child in node.next.itervalues(): + collect_ofield_operand_type(options,child, field,master_list) + + +def collect_ofield_name_type(options, node, field, master_list): + """Collect operand field data for enumerations""" + for ii in node.instructions: + for opnd in ii.operands: + if field_check(opnd, field): + s = getattr(opnd,field) + type = getattr(opnd,'type') + if s not in master_list: + master_list[s]=type + for child in node.next.itervalues(): + collect_ofield_name_type(options,child, field,master_list) + + + +def collect_attributes_pre(options, node, master_list): + collect_attributes(options, node, master_list) + # add always-available attributes. These facilitate writing + # unconditional property-checking code in XED. + for attr in [ 'MASKOP_EVEX', 'MASK_AS_CONTROL' ]: + if attr not in master_list: + master_list.append(attr) + + +def collect_attributes(options, node, master_list): + """Collect all attributes""" + for ii in node.instructions: + if field_check(ii, 'attributes'): + s = getattr(ii,'attributes') + if isinstance(s, types.ListType): + for x in s: + if x not in master_list: + master_list.append(x) + elif s != None and s not in master_list: + master_list.append(s) + for nxt in node.next.itervalues(): + collect_attributes(options,nxt, master_list) + + +idata_files = 0 +def write_instruction_data(odir,idata_dict): + """Write a file containing the content of the idata_dict. The keys + are iclass:extension the values are (iclass, extension, category). This + appends to the file if we've already opened this.""" + global idata_files + fn = 'idata.txt' + if idata_files == 0: + open_mode = "w" + else: + open_mode = "a" + idata_files += 1 + f = open(os.path.join(odir,fn),open_mode) + kys = idata_dict.keys() + kys.sort() + s = "#%-19s %-15s %-15s %-30s %-20s %s\n" % ("iclass", + "extension", + "category", + "iform", + "isa_set", + 'attributes') + f.write(s) + for iform in kys: + (iclass,extension,category,isa_set, plist, + iclass_string_index) = idata_dict[iform] + if plist: + attributes = ":".join(plist) + else: + attributes = 'INVALID' + s = "%-19s %-15s %-15s %-30s %-20s %s\n" % (iclass, + extension, + category, + iform, + isa_set, + attributes) + f.write(s) + f.close() + +def attr_dict_cmp(a,b): + av = a[0] + bv = b[0] + if av == bv: + return 0 + if av > bv: + return 1 + return -1 + +def write_attributes_table(agi, odir): + fn = 'xed-attributes-init.c' + if vattr(): + msgb("Writing attributes file", fn) + f = agi.common.open_file(fn, start=False) + f.add_misc_header("#include \"xed-attributes.h\"") + f.add_misc_header("#include \"xed-gen-table-defs.h\"") + f.start() + f.write("\nconst xed_attributes_t ") + f.write("xed_attributes[XED_MAX_REQUIRED_ATTRIBUTES] = {\n") + + if vattr(): + msgb("Unique attributes", len(agi.attributes_dict)) + t = [] + for s,v in agi.attributes_dict.iteritems(): + t.append((v,s)) + t.sort(cmp=attr_dict_cmp) + if vattr(): + msgb("Sorted Unique attributes", len(t)) + agi.attributes_ordered = t + + # agi.attributes_ordered has tuple (i,s) where s is a comma + # separated list of attributes that we'll use to manufacture the + # initialization equations. + if len(agi.attributes_ordered) >= 65536: + die("Too many attributes combinations for the 16b index used" + + " in the xed_inst_t data structure." + + " Please report this to the SDE/XED team.") + + for i,s in agi.attributes_ordered: + if s: + v = s.split(',') + struct_init = make_attributes_structure_init(agi,v) + else: + struct_init = make_attributes_structure_init(agi,None) + f.write("/* %5d */ %s,\n" % (i,struct_init)) + f.write("\n};\n") + f.close() + +def write_quick_iform_map(agi,odir,idata_dict): + fn = 'xed-iform-map-init.c' + f = agi.common.open_file(fn, start=False) + f.add_misc_header("#include \"xed-iform-map.h\"") + f.start() + + # FIXME: declare this type + f.write("\nconst xed_iform_info_t xed_iform_db[XED_IFORM_LAST] = {\n") + first = True + for (iclass,iform_num,iform) in agi.iform_tuples: + try: + (x_iclass,extension,category,isa_set, + plist, + iclass_string_index) = idata_dict[iform] + except: + (x_iclass,extension,category,isa_set, + plist, + iclass_string_index) = ('INVALID', + 'INVALID', + 'INVALID', + 'INVALID', + None, + 0) # FIXME BADNESS + + if first: + first = False + else: + f.write(",\n") + qual_iclass = "XED_ICLASS_%s" % (iclass.upper()) + qual_category = "XED_CATEGORY_%s" % (category.upper()) + qual_extension = "XED_EXTENSION_%s" % (extension.upper()) + qual_isa_set = "XED_ISA_SET_%s" % (isa_set.upper()) + t = '/* %29s */ { (xed_uint16_t) %25s, (xed_uint8_t) %22s, (xed_uint8_t)%20s, (xed_uint8_t)%25s, (xed_uint16_t)%4d }' % \ + (iform, + qual_iclass, + qual_category, + qual_extension, + qual_isa_set, + iclass_string_index) + f.write(t) + f.write("\n};\n") + + f.close() + +def collect_graph_enum_info(agi,graph): + # we ignore the return values because we don't need them. The agi + # fields get written by the collect*() functions. + + # operand fields + collect_ofield_operand_type(agi.common.options, + graph, + 'type', + agi.operand_types) + collect_ofield(agi.common.options,graph, 'oc2', agi.operand_widths) + collect_ofield_name_type(agi.common.options,graph, 'name', + agi.operand_names) + + collect_ifield(agi.common.options,graph, 'iclass',agi.iclasses) + collect_ifield(agi.common.options,graph, 'category', agi.categories) + collect_ifield(agi.common.options,graph, 'extension', agi.extensions) + + collect_attributes_pre(agi.common.options,graph, agi.attributes) + +def add_invalid(lst): + if 'INVALID' not in lst: + lst[0:0] = ['INVALID'] + +############################################################################ + +def cmp_invalid(t1,t2): + """Special sort-comparison function that makes sure the INVALID + entry is first""" + if t1 == t2: + return 0 + if t1 == 'INVALID': + return -1 + if t2 == 'INVALID': + return 1 + if t1 > t2: + return 1 + return -1 + + +def cmp_invalid_vtuple(vt1,vt2): + """Special sort-comparison function that makes sure the INVALID + entry is first""" + t1 = vt1[0] + t2 = vt2[0] + if t1 == t2: + v1 = vt1[1] + v2 = vt2[1] + if v1 == v2: + return 0 + elif v1 > v2: + return 1 + else: + return -1 + if t1 == 'INVALID': + return -1 + if t2 == 'INVALID': + return 1 + if t1 > t2: + return 1 + return -1 + +splitter_pattern= re.compile(r'(?P[A-Za-z]+)(?P[0-9]*)') +def alnum_cmp(a,b): + """Compare a and b. Assume the are of the form + letters-followed-by-numbers. The number part is optional. + """ + global splitter_pattern + + ap = splitter_pattern.match(a) + bp = splitter_pattern.match(b) + (aprefix,asuffix) = ap.group('prefix', 'suffix') + (bprefix,bsuffix) = bp.group('prefix', 'suffix') + if aprefixbprefix: + return 1 + # aprefix == bprefix + if asuffix and bsuffix: + iasuffix = int(asuffix) + ibsuffix = int(bsuffix) + if iasuffix < ibsuffix: + return -1 + if iasuffix > ibsuffix: + return 1 + return 0 + if asuffix: + return 1 + if bsuffix: + return -1 + return 0 + +############################################################################ +class rep_obj_t(object): + def __init__(self, iclass, indx, repkind): + self.iclass = iclass + self.indx = indx + self.repkind = repkind + self.no_rep_iclass = None + self.no_rep_indx = None + + + +def repmap_emit_code(agi, plist, kind, hash_fn): + """Emit table that implements the required mapping of iclasses. plist + is an array of (key,value) pairs. kind is one of repe, repne, rep + or norep. The hash function maps from the keys to a unique + value. """ + + fo = function_object_t(name='xed_' + kind + '_map', + return_type='xed_iclass_enum_t', + dll_export=True) + fo.add_arg('xed_iclass_enum_t iclass') + t = {} + mx = 0 + for (k,v) in plist: + h = hash_fn.apply(k) + t[h] = (k,v) + mx = max(mx, h) + + # For nonlinear hashes, add hash key input validation so that we + # check if the input matches the thing we expect to get on the + # output of the hash. Then the functions won't return undefined + # results for unexpected inputs. + + if hash_fn.kind() == 'linear': + array_limit = mx+1 # no extra room required for validation. + else: + array_limit = 2*(mx+1) # make room for input key validation + fo.add_code('const xed_uint16_t lu_table[{}] = {{'.format(array_limit)) + + hashes = t.keys() + hashes.sort() + + # fill in the rows of the array + for h in range(0,mx+1): + if h in t: + (k,v) = t[h] + else: + k = "0xFFFF" + v = 0 # XED_ICLASS_INVALID + if hash_fn.kind() == 'linear': + fo.add_code( '/* {} -> {} */ {},'.format(k,h,v)) + else: + fo.add_code( '/* {} -> {} */ {}, {},'.format(k,h, k,v)) + + fo.add_code_eol('}') + fo.add_code_eol('const xed_uint_t key = (xed_uint_t)iclass') + fo.add_code_eol('const xed_uint_t hash = {}'.format(hash_fn.emit_cexpr())) + fo.add_code( 'if (hash <= {}) {{'.format(mx)) + if hash_fn.kind() == 'linear': + fo.add_code_eol(' const xed_uint_t v = lu_table[hash]') + fo.add_code_eol(' return (xed_iclass_enum_t) v') + else: + # validate the correct input mapped to the output + fo.add_code_eol(' const xed_uint_t ek = lu_table[2*hash]') + fo.add_code( ' if (ek == key) {') + fo.add_code_eol(' const xed_uint_t v = lu_table[2*hash+1]') + fo.add_code_eol(' return (xed_iclass_enum_t) v') + fo.add_code( ' }') + fo.add_code( '}') + fo.add_code_eol('return XED_ICLASS_INVALID') + return fo + +def emit_iclass_rep_ops(agi): + + """We want to make several functions that map (1) norep -> rep, (2) + norep -> repe, (3) norep ->repne, and (4) rep/repe/repne -> norep. + To do that, we need 2 hash functions. One hash function maps from + rep/repe/repne keys and and another one mapping from norep keys. + """ + import hashfks + import hashmul + import hashlin + + # collect the iclasses of interest by name. + keys = [] + repobjs = [] + for i,iclass in enumerate(agi.iclasses_enum_order): + #msge("TTX-ICLASS: {}".format(str(iclass))) + if 'REPE_' in iclass: + keys.append(i) + repobjs.append(rep_obj_t(iclass,i,'repe')) + if 'REPNE_' in iclass: + keys.append(i) + repobjs.append(rep_obj_t(iclass,i,'repne')) + if 'REP_' in iclass: + keys.append(i) + repobjs.append(rep_obj_t(iclass,i,'rep')) + + # fill in the no-rep info for each object + for o in repobjs: + o.no_rep_iclass = re.sub(r'REP(E|NE)?_', '', o.iclass) + o.no_rep_indx = agi.iclasses_enum_order.index(o.no_rep_iclass) + + # make a list of keys for the norep-to-whatever hash functions + no_rep_keys = uniqueify(map(lambda x:x.no_rep_indx, repobjs)) + no_rep_keys.sort() + + msge("NOREP KEYS: {}".format(str(no_rep_keys))) + msge("REP KEYS: {}".format(str(keys))) + + # find the two required hash functions + all_fn = { 'repinst':None, 'norepinst':None } + for kind, kl in [('repinst',keys), ('norepinst',no_rep_keys)]: + hashfn = hashlin.get_linear_hash_function(kl) + if not hashfn: + hashfn = hashmul.find_perfect(kl) + if not hashfn: + hashfn = hashfks.find_fks_perfect(kl) + + if hashfn: + msge('{}'.format(hashfn.emit_cexpr())) + msge('{}'.format(str(hashfn))) + msge('FOUND PERFECT HASH FUNCTION FOR {}'.format(kind)) + all_fn[kind]=hashfn + else: + # If this ever happens, it is seriously bad news. We'll + # have to upgrade the perfect hash function generation so + # that this succeeds or make a fallback code path that either + # large or slow. Or one could generate a 2-level perfect hash + # but that seems like overkill for this. + die('DID NOT FIND PERFECT HASH FUNCTION FOR {}'.format(kind)) + + functions = [] + # emit the 3 functions that map from norep -> various kinds of + # rep/repe/repne prefixes + for kind in ['repe', 'repne', 'rep']: + plist = [] + for r in repobjs: + if r.repkind == kind: + plist.append((r.no_rep_indx, r.indx)) + fo = repmap_emit_code(agi, plist, kind, all_fn['norepinst']) + functions.append(fo) + + # emit the 1 function that maps from rep/repe/repne -> norep version + plist = [] + for r in repobjs: + plist.append((r.indx, r.no_rep_indx)) + fo = repmap_emit_code(agi, plist, "norep", all_fn['repinst']) + functions.append(fo) + + cfp = agi.open_file('xed-rep-map.c') + for fn in functions: + cfp.write(fn.emit()) + cfp.close() + +############################################################################## + +def emit_iclass_enum_info(agi): + """Emit major enumerations based on stuff we collected from the + graph.""" + msge('emit_iclass_enum_info') + iclasses = map(lambda (s): s.upper(),agi.iclasses) + add_invalid(iclasses) + + # 2...9 # omitting NOP1 + iclasses.extend(map(lambda(x): "NOP%s" % (str(x)), range(2,10))) + + iclasses = uniqueify(iclasses) + # sort each to make sure INVALID is first + iclasses.sort(cmp=cmp_invalid) + gendir = agi.common.options.gendir + xeddir = agi.common.options.xeddir + agi.iclasses_enum_order = iclasses + i_enum = enum_txt_writer.enum_info_t(iclasses, xeddir, gendir, + 'xed-iclass', + 'xed_iclass_enum_t', + 'XED_ICLASS_', + cplusplus=False) + + i_enum.print_enum() + i_enum.run_enumer() + agi.add_file_name(i_enum.src_full_file_name) + agi.add_file_name(i_enum.hdr_full_file_name, header=True) + agi.all_enums['xed_iclass_enum_t'] = iclasses + +def power2(x): + """Return a list of the powers of 2 from 2^0... 2^x""" + if x == 0: + return None + ret = [] + for p in range(0,x): + ret.append(2**p) + return ret + +max_attributes=0 + +def emit_attributes_table(agi, attributes): + """Print a global initializer list of attributes to the + xed_attributes_table[XED_MAX_ATTRIBUTE_COUNT]""" + cfp = agi.open_file('xed-attributes-list.c') + cfp.write('const xed_attribute_enum_t ' + + 'xed_attributes_table[XED_MAX_ATTRIBUTE_COUNT] = {\n') + first = True + for attr in attributes: + if first: + first = False + else: + cfp.write(',\n') + cfp.write(' XED_ATTRIBUTE_%s' % (attr)) + cfp.write('\n};\n') + cfp.close() + + + +def emit_enum_info(agi): + """Emit major enumerations based on stuff we collected from the + graph.""" + msge('emit_enum_info') + # make everything uppercase + nonterminals = map(lambda (s): s.upper(), agi.nonterminal_dict.keys()) + operand_types = map(lambda (s): s.upper(),agi.operand_types.keys()) + operand_widths = map(lambda (s): s.upper(),agi.operand_widths.keys()) + + operand_names = map(lambda (s): s.upper(), + agi.operand_storage.get_operands().keys()) + msge("OPERAND-NAMES " + " ".join(operand_names)) + + + extensions = map(lambda (s): s.upper(),agi.extensions) + categories = map(lambda (s): s.upper(),agi.categories) + attributes = map(lambda (s): s.upper(),agi.attributes) + # remove the things with equals signs + attributes = filter(lambda (s): s.find('=') == -1 ,attributes) + + + # add an invalid entry to each in the first spot if it is not + # already in the list. Sometimes it is there already, so we must + # sort to make INVALID the 0th entry. + add_invalid(nonterminals) + add_invalid(operand_types) + add_invalid(operand_widths) + add_invalid(extensions) + add_invalid(categories) + gendir = agi.common.options.gendir + xeddir = agi.common.options.xeddir + + + nonterminals.sort(cmp=cmp_invalid) + nt_enum = enum_txt_writer.enum_info_t(nonterminals, xeddir, gendir, + 'xed-nonterminal', + 'xed_nonterminal_enum_t', + 'XED_NONTERMINAL_', + cplusplus=False) + + #For xed3 we want to dump a C mapping nt_enum -> nt_capture_function + #for that matter we want a mapping: + #nt_enum_numeric_value -> nt_name + xed3_nt_enum_val_map = {} + upper_dict = {} + for nt_name in agi.nonterminal_dict.keys(): + nt_name_upper = nt_name.upper() + upper_dict[nt_name_upper] = nt_name + for i,upper_nt in enumerate(nonterminals): + if i == 0: + continue #no nt_name for invalid guy + xed3_nt_enum_val_map[i] = upper_dict[upper_nt] + agi.xed3_nt_enum_val_map = xed3_nt_enum_val_map + + operand_names.sort(cmp=alnum_cmp) + add_invalid(operand_names) + on_enum = enum_txt_writer.enum_info_t(operand_names, xeddir, gendir, + 'xed-operand', + 'xed_operand_enum_t', + 'XED_OPERAND_', + cplusplus=False) + #for xed3 we want to create xed3_operand_struct_t + #and it would be nice to order struct members in the + #operand_enum order + agi.xed3_operand_names = operand_names + + operand_types.sort(cmp=cmp_invalid) + ot_enum = enum_txt_writer.enum_info_t(operand_types, xeddir, gendir, + 'xed-operand-type', + 'xed_operand_type_enum_t', + 'XED_OPERAND_TYPE_', + cplusplus=False) + + attributes.sort(cmp=cmp_invalid) + lena = len(attributes) + attributes_list = ['INVALID'] + if lena > 0: + attributes_list.extend(attributes) + if lena > 128: + die("Exceeded 128 attributes. " + + " The SDE/XED team needs to add support for more." + + " Please report this error.") + global max_attributes + max_attributes= lena + + emit_attributes_table(agi, attributes) + + for i,a in enumerate(attributes_list): + agi.sorted_attributes_dict[a] = i + + at_enum = enum_txt_writer.enum_info_t(attributes_list, xeddir, gendir, + 'xed-attribute', + 'xed_attribute_enum_t', + 'XED_ATTRIBUTE_', + cplusplus=False) + + + categories.sort(cmp=cmp_invalid) + c_enum = enum_txt_writer.enum_info_t(categories, xeddir, gendir, + 'xed-category', + 'xed_category_enum_t', + 'XED_CATEGORY_', + cplusplus=False) + + extensions.sort(cmp=cmp_invalid) + e_enum = enum_txt_writer.enum_info_t(extensions, xeddir, gendir, + 'xed-extension', + 'xed_extension_enum_t', + 'XED_EXTENSION_', + cplusplus=False) + + enums = [ nt_enum, on_enum, ot_enum, at_enum, + # ow_enum, + c_enum, e_enum ] + + + for e in enums: + e.print_enum() + e.run_enumer() + agi.add_file_name(e.src_full_file_name) + agi.add_file_name(e.hdr_full_file_name,header=True) + + +############################################################################ + +def emit_code(f,s): + 'A simple function that tacks on a semicolon and a newline' + f.write(s + ';\n') + +def pick_arg_type(arg): + """Arg is a bit string whose name length determines what type we + should use for passing it""" + return 'xed_uint32_t' + #if arg == None or len(arg) <= 32: + # utype = "xed_uint32_t" + #else: + # utype = "xed_uint64_t" + #return utype + +def create_basis(arg): + "return an bit string with the values of the 1s in arg, and zeros elsewhere" + basis = letter_basis_pattern.sub('0',arg) + # squish strings of all zeros down to just a single zero. + if all_zeros_pattern.match(basis): + return '0' + return basis + +def get_inst_from_node(node): + if len(node.instructions) == 0: + die("no instructions when doing cg for nonterminal. graph build error.") + # grab the first instruction since they are all the same when the + # get to a nonterminal + ii = node.instructions[0] + + #FIXME: confirm that the arg bits are in the same positions for all + #the instructions of this node. Otherwise erroneous bits will be + #extracted. + + return ii + +############################################################################ +def compute_iform(options,ii, operand_storage_dict): + """These are really the iforms.""" + iform = [] + if viform(): + msge("IFORM ICLASS: %s" % (ii.iclass)) + iform.append(ii.iclass) + for operand in ii.operands: + if operand.internal: + if viform(): + msge("IFORM SKIPPING INTERNAL %s" % (operand.name)) + pass + elif operand.visibility == 'SUPPRESSED': + if viform(): + msge("IFORM SKIPPING SUPPRESSED %s" % (operand.name)) + pass + elif operand.type == 'nt_lookup_fn': + s = operand.lookupfn_name # .upper() + s = re.sub(r'_SB','',s) + s = re.sub(r'_SR','',s) + s = re.sub(r'_EB','',s) # order counts _EB before _B + s = re.sub(r'_[RBNEI].*','',s) + s = re.sub(r'_DREX','',s) # AMD SSE5 + s = re.sub(r'_SE','',s) + if operand.oc2 and s not in ['X87'] : + if operand.oc2 == 'v' and s[-1] == 'v': + pass # avoid duplicate v's + else: + s += operand.oc2 + iform.append( s ) + elif operand.type == 'reg': + s = operand.bits.upper() + s= re.sub('XED_REG_','',s) + if operand.oc2 and operand.oc2 not in ['f80']: + s += operand.oc2 + iform.append( s ) + elif operand.type == 'imm_const': + s = operand.name.upper() + s=re.sub('IMM[01]','IMM',s) + s=re.sub('MEM[01]','MEM',s) + add_suffix = True + if s == 'IMM': + add_suffix = options.add_suffix_to_imm + if add_suffix: + if operand.oc2: + s += operand.oc2 + iform.append( s ) + else: # this skips MOD/REG/RMp + if viform(): + msge("IFORM SKIPPING %s" % (operand.name)) + if len(iform) == 0: + iform = ['default'] + ii.iform = iform + if viform(): + msgb("IFORMX", "%s: %s" % (ii.iclass, "_".join(iform))) + return tuple(iform) + + +def compute_iforms(options, gi, operand_storage_dict): + """Classify the operand patterns""" + + # look ath the first instruction + ii = gi.parser_output.instructions[0] + if not field_check(ii,'iclass'): + return None + + iforms = {} # dictionary operand tuples pointing instructions + ii_iforms = {} + for ii in gi.parser_output.instructions: + #if ii.iclass == 'VMOVUPS': + # msge("II: %s" %( str(ii))) + iform = compute_iform(options,ii,operand_storage_dict) + #msge("MADE IFORM %s %s" % (ii.iclass, str(iform))) + if viform(): + msge("IFORM %s %s" % (ii.iclass, str(iform))) + s = "_".join(iform) + if ii.iform_input: + #msge("Overriding COMPUTED iform: %s with user-specified iform: %s" % + # (s,ii.iform_input)) + s = ii.iform_input + ii.iform_enum = s + + try: + iforms[s].append(ii) + except: + iforms[s]=[ii] + try: + ii_iforms[ii.iclass].append(s) + except: + ii_iforms[ii.iclass]=[s] + + # printing various ways + if viform(): + for iform,iilist in iforms.iteritems(): + msge("IFORM %s: %s" % (iform, + " ".join(map(lambda(x): x.iclass, iilist)))) + + for iclass,iformlist in ii_iforms.iteritems(): + str_iforms = {} + dups = [] + for iform in iformlist: + if iform in str_iforms: + dups.append(iform) + else: + str_iforms[iform]=True + + + msge("II_IFORM %s: %s" % (iclass, " ".join(str_iforms.keys()))) + if len(dups)!=0: + msge("\tDUPS: %s: %s" % (iclass," ".join(dups))) + +############################################################################ +## CG code generation +############################################################################ + +# $$ code_gen_dec_arg_t +class code_gen_dec_args_t(object): + """Empty class that I fill in as I pass arguments""" + pass + + +operand_max=0 + +def code_gen_itable_operand(agi, + data_table_file, + operand): + """Emit code for one opnds.operand_info_t operand""" + + global operand_max + + if operand.type == 'error': + return False + if operand.internal: + return False + + this_operand = operand_max + oprefix = 'xed_operand+%s' % str(operand_max) + operand_max += 1 + + x_name = None + x_vis = None + x_rw = None + x_oc2 = None + x_type = None + x_xtype = None + x_imm_nt_reg = '0' + + x_name = 'XED_OPERAND_%s' % operand.name.upper() + + if operand.type == 'nt_lookup_fn': + x_imm_nt_reg = 'XED_NONTERMINAL_' + operand.lookupfn_name.upper() + elif operand.type == 'imm_const': + x_imm_nt_reg = operand.bits + elif operand.type == 'reg': + x_imm_nt_reg = operand.bits + elif operand.type == 'flag': # FIXME: not used + x_imm_nt_reg = operand.bits + + try: + x_vis = 'XED_OPVIS_%s' % operand.visibility.upper() + x_type = 'XED_OPERAND_TYPE_%s' % operand.get_type_for_emit() + + # + # Some "PUBLIC" operands captured in the pattern do not have + # xtypes specified. I just make them int types. + # + if operand.xtype == None: + operand.xtype = 'int' + x_xtype ='XED_OPERAND_XTYPE_%s' % operand.xtype.upper() + + x_rw = 'XED_OPERAND_ACTION_%s' % operand.rw.upper() + x_cvt_index = str(operand.cvt_index) + except: + mbuild.die("ERROR processing operand %s" % (str(operand))) + + if operand.oc2: + x_oc2 ='XED_OPERAND_WIDTH_%s' % (operand.oc2.upper()) + else: + try: + if operand.type == 'nt_lookup_fn': + x_oc2 ='XED_OPERAND_WIDTH_%s' % ( + agi.extra_widths_nt[operand.lookupfn_name].upper() ) + elif operand.type == 'reg': + tname = re.sub('XED_REG_', '', operand.bits) + x_oc2 ='XED_OPERAND_WIDTH_%s' % ( + agi.extra_widths_reg[tname].upper() ) + elif operand.type == 'imm_const': + x_oc2 ='XED_OPERAND_WIDTH_%s' % ( + agi.extra_widths_imm_const[operand.name].upper() ) + else: + mbuild.msgb("INVALID WIDTH CODE", str(operand)) + x_oc2 ='XED_OPERAND_WIDTH_INVALID' + except: + mbuild.msgb("INVALID WIDTH CODE", str(operand)) + x_oc2 ='XED_OPERAND_WIDTH_INVALID' + + if operand.type == 'nt_lookup_fn': + nt = '1' + else: + nt = '0' + args = [ x_name, x_vis, x_rw, x_oc2, x_type, x_xtype, + x_cvt_index, x_imm_nt_reg, nt ] + + try: + #msgb("X_NAME", x_name) + s_args = ",".join(args) + data_table_file.add_code( '/*%4d*/ XED_DEF_OPND(%s),' % + (this_operand, s_args) ) + except: + die("Bad token in list: %s" % (str(args))) + + return True + +def memorize_attributes_equation(agi, attr_string_or): + try: + return agi.attributes_dict[attr_string_or] + except: + p = agi.attr_next_pos + if vattr(): + msgb("Memorizing attribute", + "%d -> %s" % (p, attr_string_or)) + + agi.attributes_dict[attr_string_or] = p + agi.attr_next_pos = p + 1 + return p + + + +def make_one_attribute_equation(attr_grp,basis): + one = '((xed_uint64_t)1)' + attr_string_or = None + for a in attr_grp: + if vattr(): + msgb("ADDING ATTRIBUTE", "%s for %s" % ( a, ii.iclass)) + + if basis: + rebase = "(%s<<(XED_ATTRIBUTE_%s-%d))" % (one, a, basis) + else: + rebase = "(%s< global_final_inum: + global_final_inum = ii.inum + + global global_emitted_zero_inum + if ii.inum == 0: + if global_emitted_zero_inum: + return + global_emitted_zero_inum = True + + has_iclass = field_check(ii,'iclass') + if verb1(): + s = "code_gen_instruction - inum: " + str(ii.inum) + ' ' + if has_iclass: + s += ii.iclass + else: + s += 'no-iclass' + msge( s) + + # print the operands - separate table with 'index & count" pointers + # in this table + operand_count = 0 + for operand in ii.operands: + if operand.type == 'error': + continue + if operand.internal: + continue + + operand_count = operand_count + 1 + if operand_count != len(ii.oid_list): + die("Mismatch on operand list for %s" % (str(ii))) + + # print the flags - separate table with "index & count" pointers in + # this table + flgrec=0 + complex =False + if field_check(ii,'flags_info'): + if ii.flags_info: + # emit the rflags info + #FIXME: OLD (flgrec, complex) = ii.flags_info.code_gen(itable, fo) + (flgrec, complex) = ii.flags_info.emit_data_record(agi.flag_simple_file, + agi.flag_complex_file, + agi.flag_action_file) + + + # not using "1ULL" because that does not work with VC6 (!!!) + one = '((xed_uint64_t)1)' + # emit attributes + attributes_index = make_attributes_equation(agi,ii) + + operand_names = map(lambda(x): x.name.upper(), ii.operands) + + # THE NEW WAY - DATA INITIALIZATION -- see include/private/xed-inst-defs.h + cpl = '3' + if has_iclass: + args = [ 'XED_ICLASS_%s' % (ii.iclass.upper()), + 'XED_CATEGORY_%s' % (ii.category.upper()), + 'XED_EXTENSION_%s' % (ii.extension.upper()) ] + if ii.cpl: + cpl = str(ii.cpl) + args.append(cpl) + args.append('XED_IFORM_%s' %( ii.iform_enum)) + + else: + args = [ 'XED_ICLASS_INVALID', + 'XED_CATEGORY_INVALID', + 'XED_EXTENSION_INVALID'] + args.append(cpl) + args.append('XED_IFORM_INVALID') + + + #if field_check(ii,'ucode') and ii.ucode: + # args.append(str(ii.ucode)) + #else: + # args.append('0') + + + args.append(str(ii.oid_sequence_start)) + args.append(str(operand_count)) + if operand_count > max_operand_count: + max_operand_count = operand_count + + args.append(str(flgrec)) + if complex: + flagtype = '1' + else: + flagtype = '0' + args.append(flagtype) + + args.append(str(attributes_index)) + if field_check(ii,'exceptions') and ii.exceptions: + args.append('XED_EXCEPTION_' + ii.exceptions) + else: + args.append('XED_EXCEPTION_INVALID') + + s_args = ",".join(args) + + fp.add_code( '/*%4d*/ XED_DEF_INST(%s),' % (ii.inum, s_args) ) + + + + +#$$ table_init_object +class table_init_object_t(object): + def __init__(self, file_name, function_name): + self.file_name_prefix = file_name + self.function_name_prefix = function_name + + self.fp = None # file pointer + self.fo = None # function_object_t + self.init_functions = [] + self.max_lines_per_file = 3000 + + def get_init_functions(self): + return self.init_functions + + def get_fo(self,gi): + if not self.fp: + # make a new output file and new function obj if we don't + # already have one + n = str(len(self.init_functions)) + self.fp = gi.common.open_file(self.file_name_prefix + n + '.c', + start=False) + self.fp.start() + + full_function_name = self.function_name_prefix + n + self.fo = function_object_t(full_function_name,"void") + self.init_functions.append(self.fo) + return self.fo + + def check_file(self): + if self.fo: + if self.fo.lines() >= self.max_lines_per_file: + + self.fp.write(self.fo.emit()) + self.fp.close() + del self.fp + + self.fo = None + self.fp = None + + def finish_fp(self): + # write anything that didn't get emitted already + if self.fp: + self.fp.write(self.fo.emit()) + self.fp.close() + del self.fp + + self.fo = None + self.fp = None + + + + + +def code_gen_instruction_table(agi, gi, itable_init, nonterminal_dict, + operand_storage_dict): + """Emit a table of all instructions. itable_init is a + table_init_object_t with a list of function_object_ts to which we add + those that we create.""" + if vtrace(): + msge("code_gen_instruction_table") + + for ii in gi.parser_output.instructions: + fo = itable_init.get_fo(gi) + code_gen_instruction(agi, + gi.common.options, + ii, + gi.common.state_bits, + fo, + nonterminal_dict, + operand_storage_dict) + + itable_init.check_file() + + +def rewrite_default_operand_visibilities(generator, + operand_field_dict): + """Change the default visibilty of any operand to the visibilty + indicated by the operand_field_t in the dictionary.""" + + if not generator.parser_output.is_lookup_function(): + for ii in generator.parser_output.instructions: + #if field_check(ii,'iclass'): + # mbuild.msgb("Processing", ii.iclass) + for opnd in ii.operands: + #mbuild.msgb("Operand", "\t%s" % (str(opnd))) + if opnd.visibility == 'DEFAULT': + new_vis = operand_field_dict[opnd.name].default_visibility + if vopvis(): + msge("OPVIS-DELTA: " + opnd.name + " to " + new_vis ) + opnd.visibility = new_vis + +################################################################# +def emit_string_table(agi, iclass_strings): + + f = agi.common.open_file('xed-iclass-string.c', start=False) + f.add_misc_header('#include "xed-gen-table-defs.h"') + f.add_misc_header('#include "xed-tables-extern.h"') + f.start() + s = 'char const* const xed_iclass_string[XED_ICLASS_NAME_STR_MAX] = {\n' + f.write(s) + for i in iclass_strings: + f.write('"%s",\n' % (i)) + f.write('};\n') + f.close() + + +def collect_iclass_strings(agi): + """We collect the disasm strings in pairs. One for Intel, One for + ATT SYSV syntax""" + iclass_strings = ['invalid','invalid'] + + # string table indexed by intel syntax dotted with the att syntax + st = { 'invalid.invalid': 0 } + n = 2 + for generator in agi.generator_list: + ii = generator.parser_output.instructions[0] + if not field_check(ii,'iclass'): + continue + for ii in generator.parser_output.instructions: + if field_check(ii,'disasm_intel'): + if not field_check(ii,'disasm_att'): + die("Missing att syntax when intel sytnax" + + " is provided for %s" % (ii.iclass)) + if field_check(ii,'disasm_att'): + if not field_check(ii,'disasm_intel'): + die("Missing intel syntax when att sytnax " + + " is provided for %s" % (ii.iclass)) + if field_check(ii,'disasm_att'): + k = '%s.%s' % (ii.disasm_intel, ii.disasm_att) + if k in st: + ii.iclass_string_index = st[k] + else: + st[k] = n + ii.iclass_string_index = n + iclass_strings.append(ii.disasm_intel) + iclass_strings.append(ii.disasm_att) + n = n + 2 + + agi.max_iclass_strings = n + emit_string_table(agi, iclass_strings) + +def compress_iform_strings(values): + # values are a list of 3 tuples (iform string, index, comment) and + # the comments are generally empty strings. + bases = {} + operand_sigs = { '':0 } + o_indx = 1 + b_indx = 0 + h = {} # map index to base, operand indices + + # split the bases (iclass name, mostly) and operand sigs. + # assign ids to the bases and to the operand sigs + for iform,index,comment in values: + try: + s,rest = iform.split("_",1) + if s not in bases: + bases[s]=b_indx + b = b_indx + b_indx += 1 + if rest not in operand_sigs: + operand_sigs[rest] = o_indx + o = o_indx + o_indx += 1 + except: + if iform not in bases: + bases[iform]=b_indx + b = b_indx + o = 0 + b_indx += 1 + # store the base,operand_sig pair + h[int(index)] = (b,o) + + print "XZ: NTUPLES {} BASES {} OPERAND_SIGS {}".format(len(values), + len(bases), + len(operand_sigs)) + + if len(h) != (max(map(lambda x: int(x), h.keys()))+1): + print "PROBLEM IN h LENGTH" + # make an numerically indexed version of the bases table + bi = {} + for k,v in bases.iteritems(): + bi[v] = k + # make an numerically indexed version of the operand_sig table + oi = {} + for k,v in operand_sigs.iteritems(): + oi[v] = k + + f = sys.stdout + + f.write('static const char* base[] = {\n') + for i in range(0,len(bases)): + f.write( '/* {} */ "{}",\n'.format(i,bi[i]) ) + f.write('};\n') + + f.write('static const char* operands[] = {\n') + for i in range(0,len(operand_sigs)): + f.write('/* {} */ "{}",\n'.format(i,oi[i])) + f.write('};\n') + + f.write('static const iform_name_chunks[] = {\n') + for i in range(0,len(h)): + a,b = h[i] + f.write( '/* {} */ {{ {},{} }},\n'.format(i,a,b)) + f.write('};\n') + + +def generate_iform_enum(agi,options,values): + # values are a list of 3 tuples (iform string, index, comment) and + # the comments are generally empty strings. + string_convert = 1 + if options.limit_enum_strings: + string_convert = 0 + enum = enum_txt_writer.enum_info_t(values, + options.xeddir, options.gendir, + 'xed-iform', + 'xed_iform_enum_t', 'XED_IFORM_', + cplusplus=False, + extra_header = ['xed-common-hdrs.h', + 'xed-iclass-enum.h'], + upper_case=False, + string_convert=string_convert) + enum.print_enum() + enum.run_enumer() + agi.add_file_name(enum.src_full_file_name) + agi.add_file_name(enum.hdr_full_file_name,header=True) + +def generate_iform_first_last_enum(agi,options,values): + enum = enum_txt_writer.enum_info_t(values, + options.xeddir, options.gendir, + 'xed-iformfl', + 'xed_iformfl_enum_t', + 'XED_IFORMFL_', + cplusplus=False, + extra_header = ['xed-common-hdrs.h', + 'xed-iclass-enum.h'], + upper_case=False, + string_convert=-1) + enum.print_enum() + enum.run_enumer() + agi.add_file_name(enum.src_full_file_name) + agi.add_file_name(enum.hdr_full_file_name,header=True) + + + +global_max_iforms_per_iclass = 0 + +def collect_and_emit_iforms(agi,options): + iform_dict = {} # build dictionary by iclass of iforms + for generator in agi.generator_list: + ii = generator.parser_output.instructions[0] + if not field_check(ii,'iclass'): + continue + for ii in generator.parser_output.instructions: + try: + iform_dict[ii.iclass].append(ii.iform_enum) + except: + iform_dict[ii.iclass] = [ii.iform_enum] + + # number them from zero, per iclass + vtuples = [('INVALID', 0, 'INVALID') ] + imax = {} # maximum number of iforms per iclass + for ic,ol in iform_dict.iteritems(): + #msge("XZ BEFORE " + ic + " --- " + str(ol)) + ol = uniqueify(ol) + #msge("XZ AFTER " + ic + " --- " + str(ol)) + sz= len(ol) + vsub = zip([ic.upper()]*sz, # the iclass + range(0,sz), # number the iforms + ol) # the list of iform names + imax[ic] = sz + vtuples.extend(vsub) + + #msge("VTUPLES %s" % (str(vtuples))) + vtuples.sort(cmp=cmp_invalid_vtuple) + + agi.iform_tuples = vtuples + + # number the tuples from 0 + ntuples = [] + for i,v in enumerate(vtuples): + lv = list(v) + lv.extend([str(i),'']) + t = tuple(lv) + ntuples.append(t) + + #msge("NTUPLES %s" % (str(ntuples))) + # add a first and last element for each group of iforms (per iclass) + first_last_tuples = [] + last_tuple = None + ifirst = {} + for v in ntuples: + if last_tuple and last_tuple[0] != v[0]: + if last_tuple[0] != 'INVALID': + t = ( 'INVALID', 0, last_tuple[0] + "_LAST", last_tuple[3], '') + first_last_tuples.append(t) + t = ( 'INVALID', 0, v[0] + "_FIRST", v[3], '') + ifirst[v[0]] = int(v[3]) + first_last_tuples.append(t) + last_tuple = v + if last_tuple and last_tuple[0] != 'INVALID': + t = ( 'INVALID', 0, last_tuple[0] + "_LAST", last_tuple[3], '') + first_last_tuples.append(t) + + + #msge("NTUPLES %s" % (str(ntuples))) + # rip off first two fields of vtuples + vtuples = map(lambda(x): x[2:], ntuples) + + #for t in vtuples: + # msge("TUPLE " + str(t)) + generate_iform_enum(agi,options,vtuples) + # compress_iform_strings(vtuples) + + # rip off first two fields of vtuples + first_last_tuples = map(lambda(x): x[2:], first_last_tuples) + generate_iform_first_last_enum(agi,options,first_last_tuples) + + #emit imax in global iclass order for data-initialization! + cfp = agi.open_file('xed-iform-max.c') + cfp.write('const xed_uint32_t ' + + 'xed_iform_max_per_iclass_table[XED_ICLASS_LAST] = {\n') + first = True + gmax = 0 # maximum number of iforms for any iclass + niform = 0 # total number of iforms + for ic in agi.iclasses_enum_order: + if first: + first = False + else: + cfp.write(',\n') + try: + mx = imax[ic] + except: + mx = 0 # for the INVALID entry + if mx > gmax: + gmax = mx + niform = niform + mx + cfp.write(' /* %25s */ %2d' % (ic,mx)) + cfp.write('\n};\n') + + + cfp.write('const xed_uint32_t' + + ' xed_iform_first_per_iclass_table[XED_ICLASS_LAST] = {\n') + first = True + niform = 0 # total number of iforms + for ic in agi.iclasses_enum_order: + if first: + first = False + else: + cfp.write(',\n') + try: + firstiform = ifirst[ic] + except: + firstiform = 0 # for the INVALID entry + + cfp.write(' /* %25s */ %2d' % (ic,firstiform)) + cfp.write('\n};\n') + + if 0: + # this is not required now that we have the xed_iform_info_t + cfp.write('const xed_iclass_enum_t ' + + 'xed_iform_to_iclass_table[XED_IFORM_LAST] = {\n') + first = True + niform = 0 # total number of iforms + for (iclass, n, iform, k, s) in ntuples: + if first: + first = False + else: + cfp.write(',\n') + cfp.write(' /* %25s */ XED_ICLASS_%s' % (iform,iclass)) + cfp.write('\n};\n') + + cfp.close() + + global global_max_iforms_per_iclass + global_max_iforms_per_iclass = gmax + + +############################################################################ + +def relabel_itable(agi): + """Renumber the itable so that it is sequential.""" + global global_inum + inum = 1 + for gi in agi.generator_list: + if not gi.parser_output.is_lookup_function(): + for ii in gi.parser_output.instructions: + has_iclass = field_check(ii,'iclass') + if has_iclass: + ii.inum = inum + inum += 1 + else: + # make all the non-instruction leaves point to node zero + ii.inum = 0 + global_inum = inum + + +############################################################################ +# The renum_node_id is global because we renumber each graph so that +# we have contiguous numbers for graph code-gen for the distinct subgraphs. +renum_node_id = -1 +def renumber_nodes(options,node): + """renumber the nodes now that we've deleted some""" + #msge("renumbering graph nodes..") + renumber_nodes_sub(options,node) + global renum_node_id + #msge(" ...last node id = %d" % (renum_node_id)) + +def renumber_nodes_sub(options,node): + """renumber the nodes now that we've deleted some""" + # bump the 'global' node counter + global renum_node_id + renum_node_id = renum_node_id + 1 + # update the current node + #msge("RENUMBER NODE %d becomes %d" % ( node.id, renum_node_id)) + node.id = renum_node_id + # recur + for nxt in node.next.itervalues(): + node_id = renumber_nodes_sub(options,nxt) + + + +def merge_child_nodes(options,node): + """Merge the children and grandchildren of this node.""" + candidates = len(node.next) + if vmerge(): + msge(str(candidates) + " merge candidate") + # merge tokens?? + # should not need to merge instructions + # bit_pos* becomes a bigger range + # more "next" nodes. + tnode = {} + for k,child in node.next.iteritems(): # children # MERGING + for j in child.next.keys(): # grandchildren + bigkey = str(k) + str(j) + if vmerge(): + msge("Bigkey= %s" % (bigkey)) + child.next[j].token = bigkey + tnode[bigkey] = child.next[j] + # overwrite the current nodes next pointers: + node.next = tnode + + # increment number of decider bits + node.decider_bits = node.decider_bits + 1 + if vmerge(): + msge("Decider bits after merging = " + str(node.decider_bits)) + + + +def merge_nodes(options,node): + """Merge compatible nodes, deleting some nodes and increasing the + arity of others""" + # If nodes are sequential in their bit positions and the next one + # is not a leaf, consider merging them. + + #FIXME: must not merge across state bits. + if (not node.is_nonterminal() and + not node.leaf() and + not node.is_operand_decider()): + merging = True + while merging: + all_match = True + decider_bits = map(lambda(k): node.next[k].decider_bits , + node.next.keys()) + if not all_the_same(decider_bits): + if vmerge(): + msge("Not merging because unequal numbers of decider" + + " bits follow:" + str(decider_bits)) + for nxt in node.next.itervalues(): + msge("\tChildNode:\n" +nxt.dump_str('\t\t')) + all_match = False + break + + + # stop at byte boundaries. All the children have the same + # number of decider bits at this point. Look at the first + # one. + if decider_bits[0] == 8: + msge("Stopping child nodes with 8 decider bits") + break + if vmerge(): + msge("PREMRG node decider " + + "bits= %d child decider bits= %d bitpos_mod8= %d\n" % + ( node.decider_bits, decider_bits[0], node.bitpos_mod8)) + + # FIXME: the following is not right. We want the bitpos_mod8 + # of the child because that is what we are merging with the + # grandchild. We also don't care about the decider its of the parent. + + # FIXME: we are not updating the bitpos_mod8 of the children + # when we merge them. + + # NOTE: IT IS BETTER NOT DO DO THIS TEST AT ALL. THE GRAPH IS + # MUCH SMALLER. but more 'next' nodes, which are much + # smaller. so that is good! + + # Do not want to merge across byte boundaries. + #if node.decider_bits + decider_bits[0] + node.bitpos_mod8 > 8: + #if node.decider_bits + decider_bits[0] + node.bitpos_mod8 > 8: + # msge("Stopping child node merging at a byte boundary") + # break + + + # look at all the next nodes + for child in node.next.itervalues(): + if child.back_split_pos != None: + if vmerge(): + msge("Not merging because a child is back-split") + all_match = False + break + if child.is_nonterminal(): + if vmerge(): + msge("Not merging because a child is a nonterminal") + all_match = False + break + if child.decider_bits == 0: # FIXME: WHY WOULD THIS HAPPEN? + if vmerge(): + msge("Not merging because zero decider bits follow: " + + str(child.decider_bits)) + msge("\tChildNode:\n" + child.dump_str('\t')) + all_match = False + break + if child.skipped_bits != 0: + if vmerge(): + msge("Not merging because skipped bits at child level: " + + str(child.skipped_bits)) + all_match = False + break + + + if all_match: + merge_child_nodes(options,node) + + else: + merging = False + + # recur + for child in node.next.itervalues(): + merge_nodes(options,child) + +def optimize_graph(options, node): + """return an optimized graph. Merge compatible nodes.""" + if vgraph_res(): + print_resource_usage('optimize-graph.0') + merge_nodes(options,node) + if vgraph_res(): + print_resource_usage('optimize-graph.1') + renumber_nodes(options,node) + if vgraph_res(): + print_resource_usage('optimize-graph.2') + + +def epsilon_label_graph(options, node): + node.otherwise_ok = True + # recur + for child in node.next.itervalues(): + epsilon_label_graph(options,child) + +############################################################################ +## Packers and extractors +############################################################################ +# $$ bit_group_info_t +class bit_group_info_t(object): + """Tell us where physical bits are symbolically. Each bit_group_info_t has: + + a bit name + a bit instance - the i'th copy of the named bit + + a length - number of bits in this group. So this group is bit i + though bit i+length-1. + + a position - not counting NONTERMINALS or OPERAND DECIDERS. + + a nonterminal adder - a string describing all previous + nonterminals encountered) + + a nonterminal instance - counting any and all kinds of + nonterminals in this pattern + """ + def __init__(self, + bit_name, + instance, + position_count, + nonterminal_adder, + nonterminal_instance=0): + self.bit_name = bit_name + # number of the first bit of this run + self.bit_instance = instance + # length of this run of bits + self.length = 1 + self.position_count = position_count + self.position_nonterminal_adders = nonterminal_adder + + # for nonterminals, the nonterminal_instance says the numeric id + # of this sub-nonterminal in the current nonterminal. If there + # are 4 sub-nonterminals in a nonterminal, they are numbered 0 + # to 3. This index is used to index in to the nonterminal storage + # associated with the current nonterminal. + self.nonterminal_instance = 0 + + def emit(self): + "return a string" + lst = [self.bit_name ] + if self.bit_instance != 0: + lst.append('instnc:'+str(self.bit_instance)) + lst.append( 'len:'+str(self.length) ) + lst.append( 'pos:'+str(self.position_count) ) + if self.position_nonterminal_adders != '': + lst.append('ntadders:'+self.position_nonterminal_adders) + s = '/'.join(lst) + return s + +def code_gen_extract_sub_runs_old(sub_runs, vname, start_clean = True): + """Write code that assigns bits to vname based on the sub runs. If + start_clean is false, we OR in our first stuff. Otherwise we do an + assignment for the very first bits extracted.""" + + # position is the position of the start of the bit run, treated as + # a string, so shifts must be adjusted for the width of the run. + + eol = ';\n' + nl = '\n' + if start_clean: + first = True + else: + first = False + s = '' + + for (bit,count,position_str, nonterminal_addr) in sub_runs: + print "PROCESSING SUBRUN (%s, %d, %s, %s)" % ( + bit, count ,position_str, nonterminal_addr) + # control whether or not we do an assignment or and |= in to our + # dest var c. + if first: + bar = '' + first = False + else: + bar = '|' + # must shift last "c" by the amount we are or-ing in on this iteration + t += "%s=%s<<%s%s" % (vname, vname, str(count), eol) + s += t + print "ADDING SHIFT OF PREV STUFF: %s" % t + + sindex = str(position_str) + if nonterminal_addr != '': + sindex += nonterminal_addr + sindex += '+xed_decoded_inst_nonterminal_bitpos_start(xds)' + s += "%s %s=xed_decoded_inst_read_any_bits(xds,%s,%s)%s" % ( + vname, bar, sindex, str(count), eol ) + return s + + +def print_bit_groups(bit_groups, s=''): + q = "BITGRP:" + for b in bit_groups: + q = q + b.emit() + ' ' + msge(s + " " + q) + +############################################################################ + +def emit_function_headers(fp, fo_dict): + """For each function in the fo_dict dictionary, emit the function + prototype to the fp file emitter object.""" + for fname in fo_dict.keys(): + fo = fo_dict[fname] + fp.write(fo.emit_header()) + +############################################################################ +def mark_operands_internal(agi, parser_output): + """Go through all the operands in the parser and mark each + internal or not. They have already been expanded and cleaned + up.""" + + for ii in parser_output.instructions: + for op in ii.operands: # opnds.operand_info_t list + ip = agi.operand_storage.get_operand(op.name).internal_or_public + if ip == "INTERNAL": + op.internal = True + + +def rewrite_state_operands(agi, state_bits, parser_output): + """For each operand in the parser output, make sure we denote state + modifcations as operands and not flags""" + for pi in parser_output.instructions: + expand_operands(agi, pi, state_bits) + +def expand_operands(agi, pi, state_bits): + """make opnds.operand_info_t's for any un-expanded operands based on the + strings stored in the state_bits.""" + new_list = [] + for x in pi.operands: # opnds.operand_info_t list + found = None + if x.name in state_bits: + found = x.name + else: + lwr = x.name.lower() + if lwr in state_bits: + found = lwr + + # the state name we found might expand in to more than one operand. + if found: + for v in state_bits[found].list_of_str: + if vmacro(): + msge("Expanding %s to %s" % (found,v)) + eqp = equals_pattern.match(v) + if eqp: + new_operand = mk_opnd(agi, v, default_vis='SUPP') + if new_operand: + new_operand.set_suppressed() + new_list.append(new_operand) + else: + die("Could not find equals sign in state macro definition of " + + x.name) + elif x.type == 'flag': + die("THIS SHOULD NOT HAPPEN - FLAG: %s" % (x.name)) + else: + new_list.append(x) + pi.operands = new_list + + + +def expand_hierarchical_records(ii): + """Return a list of new records splitting the extra_ipatterns and + extra_operands in to new stuff""" + new_lines = [] + + # FIXME: perf: 2007-08-05 mjc could skip this expansion when not + # needed and save the copying. + + extra_operands = ii.extra_operands + extra_ipatterns = ii.extra_ipatterns + extra_iforms_input = ii.extra_iforms_input + ii.extra_operands = None + ii.extra_ipatterns = None + ii.extra_iforms_input = None + + # start with the first instruction, then expand the "extra" ones + new_lines.append(ii) + + if len(extra_ipatterns) != len(extra_operands) or \ + len(extra_ipatterns) != len(extra_iforms_input): + die("Missing some patterns, operands or iforms for " + ii.iclass) + + for (ipattern, operands, iform) in zip(extra_ipatterns, + extra_operands, + extra_iforms_input): + new_rec = copy.deepcopy(ii) + new_rec.new_inum() + new_rec.extra_operands = None + new_rec.extra_ipatterns = None + new_rec.extra_iforms_input = None + new_rec.ipattern_input = ipattern + new_rec.operands_input = operands + new_rec.iform_input = iform + #msge("ISET2: %s -- %s" % (iform, str(operands))) + new_lines.append(new_rec) + + del extra_ipatterns + del extra_operands + return new_lines + + + +# $$ generator_common_t +class generator_common_t(object): + """This is stuff that is common to every geneator and the + agi. Basically all the globals that are needed by most generator + specific processing.""" + + def __init__(self): + self.options = None + self.state_bits = None # dictionary of state_info_t's + self.state_space = None # dictionary of all values of each state + # restriction (operand_decider) + + self.enc_file = None + self.inst_file = None + self.operand_storage_hdr_file = None + self.operand_storage_src_file = None + + self.header_file_names = [] + self.source_file_names = [] + self.file_pointers = [] + + self.inst_table_file_names = [] + + + def open_file(self,fn, arg_shell_file=False, start=True): + 'open and record the file pointers' + if True: #MJC2006-10-10 + fp = xed_file_emitter_t(self.options.xeddir, + self.options.gendir, + fn, + shell_file=arg_shell_file) + if is_header(fn): + self.header_file_names.append(fp.full_file_name) + else: + self.source_file_names.append(fp.full_file_name) + + if start: + fp.start() + else: + fp = base_open_file(fn,'w') + self.file_pointers.append(fp) + return fp + + def build_fn(self,tail,header=False): + 'build and record the file names' + if True: # MJC2006-10-10 + fn = tail + else: + fn = os.path.join(self.options.gendir,tail) + if header: + self.header_file_names.append(fn) + else: + self.source_file_names.append(fn) + return fn + + def open_all_files(self): + "Open the major output files" + msge("Opening output files") + + header = True + + + self.inst_file = self.open_file(self.build_fn( + self.options.inst_init_file)) + + def open_new_inst_table_file(self): + i = len(self.inst_table_file_names) + base_fn = 'xed-inst-table-init-' + fn = self.build_fn(base_fn + str(i) + ".c") + self.inst_table_file_names.append(fn) + fp = self.open_file(fn) + return fp + + + def close_output_files(self): + "Close the major output files" + for f in self.file_pointers: + f.close() + +# $$ generator_info_t +class generator_info_t(generator_common_t): + """All the information that we collect and generate""" + def __init__(self, common): + super(generator_info_t,self).__init__() + self.common = common + + if self.common.options == None: + die("Bad init") + #old style generator_common_t.__init__(self,generator_common) + self.parser_output = None # class parser_t + self.graph = None + # unique list of iclasses + self.iclasses = {} + + # list of tuples of (nonterminal names, max count of how many + # there are of this one per instruction) + self.nonterminals = [] + + # list of opnds.operand_info_t's + self.operands = None + + self.storage_class = None + + #For thing that are directly translateable in to tables, we + #generate a table here. + self.luf_arrays = [] + self.marshalling_function = None + + def nonterminal_name(self): + """The name of this subtree""" + s = self.parser_output.nonterminal_name + return nonterminal_parens_pattern.sub('', s) + + def build_unique_iclass_list(self): + "build a unique list of iclasses" + self.iclasses = {} + for ii in self.parser_output.instructions: + if field_check(ii,'iclass'): + if ii.iclass not in self.iclasses: + self.iclasses[ii.iclass] = True + +def cmp_tuple_first(a,b): + (a1,a2)=a + (b1,b2)=b + if a1==b1: + return 0 + if a1>b1: + return 1 + return -1 + + +# $$ all_generator_info_t +class all_generator_info_t(object): + """List of generators, each with its own graph""" + def __init__(self,options): + #common has mostly input and output files and names + self.common = generator_common_t() + self.common.options = options + self.common.open_all_files() + + self.generator_list = [] + self.generator_dict = {} # access by NT name + self.nonterminal_dict = nonterminal_dict_t() + + self.src_files=[] + self.hdr_files=[] + + # enum lists + self.operand_types = {} # typename -> True + self.operand_widths = {} # width -> True # oc2 + self.operand_names = {} # name -> Type + self.iclasses = [] + self.categories = [] + self.extensions = [] + self.attributes = [] + + # this is the iclasses in the order of the enumeration for us in + # initializing other structures. + self.iclasses_enum_order = None + + # function_object_ts + self.itable_init_functions = table_init_object_t('xed-init-inst-table-', + 'xed_init_inst_table_') + self.encode_init_function_objects = [] + + # dictionaries of code snippets that map to function names + self.extractors = {} + self.packers = {} + + self.operand_storage = None # operand_storage_t + + + # function_object_t + self.overall_lookup_init = None + + # functions called during decode traverals to capture required operands. + self.all_node_capture_functions = [] + + # data for instruction table + self.inst_fp = None + + # list of (index, initializer) tuples for all the entire decode graph + self.all_decode_graph_nodes=[] + + self.data_table_file=None + self.operand_sequence_file=None + + # dict "iclass:extension" -> ( iclass,extension, + # category, iform_enum, properties-list) + self.iform_info = {} + + self.attributes_dict = {} + self.attr_next_pos = 0 + self.attributes_ordered = None + self.sorted_attributes_dict = {} + # a dict of all the enum names to thier values. + # passed to operand storage in order to calculate + # the number of requiered bits + self.all_enums = {} + + # these are xed_file_emitter_t objects + self.flag_simple_file = self.common.open_file("xed-flags-simple.c", start=False) + self.flag_complex_file = self.common.open_file("xed-flags-complex.c", start=False) + self.flag_action_file = self.common.open_file("xed-flags-actions.c", start=False) + self.flag_simple_file.add_header('xed-flags.h') + self.flag_complex_file.add_header('xed-flags.h') + self.flag_complex_file.add_header('xed-flags-private.h') + self.flag_action_file.add_header('xed-flags.h') + + self.flag_simple_file.start() + self.flag_complex_file.start() + self.flag_action_file.start() + + self.emit_flag_simple_decl() + self.emit_flag_complex_decl() + self.emit_flag_action_decl() + + def close_flags_files(self): + self.emit_close_array(self.flag_simple_file) + self.emit_close_array(self.flag_complex_file) + self.emit_close_array(self.flag_action_file) + + def emit_flag_simple_decl(self): + self.flag_simple_file.add_code("const xed_simple_flag_t xed_flags_simple_table[] = {") + self.flag_simple_file.add_code("/* 0 */ {0,0,0,{0},{0},{0},0}, /* invalid */") + + def emit_flag_action_decl(self): + self.flag_action_file.add_code("const xed_flag_action_t xed_flag_action_table[] = {") + + def emit_flag_complex_decl(self): + self.flag_complex_file.add_code("const xed_complex_flag_t xed_flags_complex_table[] = {") + self.flag_complex_file.add_code("/* 0 */ {0,0,{0,0,0,0,0},}, /* invalid */") + + def emit_close_array(self,f): + f.add_code_eol("}") + + + def open_operand_data_file(self): + self.data_table_file=self.open_file('xed-init-operand-data.c', + start=False) + self.data_table_file.add_header('xed-inst-defs.h') + self.data_table_file.start() + s = 'XED_DLL_EXPORT const xed_operand_t ' + \ + 'xed_operand[XED_MAX_OPERAND_TABLE_NODES] = {\n' + self.data_table_file.write(s) + + def close_operand_data_file(self): + self.data_table_file.write('};\n') + self.data_table_file.close() + + + + + def open_operand_sequence_file(self): + self.operand_sequence_file = \ + self.open_file('xed-init-operand-sequences.c', + start=False) + self.operand_sequence_file.add_header('xed-inst-defs.h') + self.operand_sequence_file.start() + s = 'XED_DLL_EXPORT const xed_uint16_t ' + \ + 'xed_operand_sequences[XED_MAX_OPERAND_SEQUENCES] = {\n' + self.operand_sequence_file.write(s) + + def close_operand_sequence_file(self): + self.operand_sequence_file.write('};\n') + self.operand_sequence_file.close() + + + def add_file_name(self,fn,header=False): + if type(fn) == types.StringType: + fns = [fn] + elif type(fn) == types.ListType: + fns = fn + else: + die("Need string or list") + + for f in fns: + if header: + self.hdr_files.append(f) + else: + self.src_files.append(f) + + def dump_generated_files(self): + output_file_list = mbuild.join(self.common.options.gendir, + "DECGEN-OUTPUT-FILES.txt") + f = base_open_file(output_file_list,"w") + for fn in self.hdr_files + self.src_files: + f.write(fn+"\n") + f.close() + + def mk_fn(self,fn): + if True: #MJC2006-10-10 + return fn + else: + return self.real_mk_fn(fn) + + def real_mk_fn(self,fn): + return os.path.join(self.common.options.gendir,fn) + + def close_output_files(self): + "Close the major output files" + self.common.close_output_files() + + def make_generator(self, nt_name): + g = generator_info_t(self.common) + self.generator_list.append(g) + self.generator_dict[nt_name] = g + return g + + + def open_file(self, fn, keeper=True, arg_shell_file=False, start=True): + 'open and record the file pointers' + if True: #MJC2006-10-10 + fp = xed_file_emitter_t(self.common.options.xeddir, + self.common.options.gendir, + fn, + shell_file=arg_shell_file) + if keeper: + self.add_file_name(fp.full_file_name, is_header(fn)) + + if start: + fp.start() + else: + fp = base_open_file(fn,'w') + return fp + + + + def code_gen_table_sizes(self): + """Write the file that has the declarations of the tables that we + fill in in the generator""" + fn = "xed-gen-table-defs.h" + # we do not put this in a namespace because it is included while + # in the XED namespace. + fi = xed_file_emitter_t(self.common.options.xeddir, + self.common.options.gendir, + fn, + namespace=None) + + self.add_file_name(fi.full_file_name,header=True) + fi.replace_headers([]) # no headers + fi.start() + + global global_final_inum + irecs = global_final_inum + 1 # 7000 + + global global_max_iforms_per_iclass + + global operand_max + orecs = operand_max+1 + + fi.add_code("#define XED_ICLASS_NAME_STR_MAX %d" % + (self.max_iclass_strings)) + + global max_attributes + fi.add_code("#define XED_MAX_ATTRIBUTE_COUNT %d" % (max_attributes)) + + fi.add_code("#define XED_MAX_INST_TABLE_NODES %d" % (irecs)) + + global global_operand_table_id + fi.add_code("#define XED_MAX_OPERAND_TABLE_NODES %d" % + (global_operand_table_id)) + + global global_max_operand_sequences + fi.add_code("#define XED_MAX_OPERAND_SEQUENCES %d" % + (global_max_operand_sequences)) + + # flags + fi.add_code("#define XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES %d" % + (flag_gen.flags_info_t._flag_simple_rec)) + fi.add_code("#define XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES %d" % + (flag_gen.flags_info_t._flag_complex_rec)) + fi.add_code("#define XED_MAX_GLOBAL_FLAG_ACTIONS %d" % + (flag_gen.flags_info_t._max_flag_actions)) + + + fi.add_code("#define XED_MAX_IFORMS_PER_ICLASS %d" % + (global_max_iforms_per_iclass)) + + fi.add_code("#define XED_MAX_REQUIRED_ATTRIBUTES %d" % + (len(self.attributes_dict))) + + + fi.add_code("#define XED_MAX_CONVERT_PATTERNS %d" % + (self.max_convert_patterns)) + fi.add_code("#define XED_MAX_DECORATIONS_PER_OPERAND %d" % + (self.max_decorations_per_operand)) + + fi.close() + + + def handle_prefab_enum(self,enum_fn): + # parse the enum file and get the c and h file names + gendir = self.common.options.gendir + m=metaenum.metaenum_t(enum_fn,gendir) + m.run_enumer() + # remember the c & h file names + self.add_file_name(m.src_full_file_name) + self.add_file_name(m.hdr_full_file_name,header=True) + all_values = map(lambda x: x.name ,m.tuples) + return all_values + + + + + def handle_prefab_enums(self): + """Gather up all the enum.txt files in the datafiles directory""" + prefab_enum_shell_pattern = os.path.join(self.common.options.xeddir, + "datafiles/*enum.txt") + prefab_enum_files = glob.glob( prefab_enum_shell_pattern ) + for fn in prefab_enum_files: + msge("PREFAB-ENUM: " + fn) + self.handle_prefab_enum( fn ) + + def extend_operand_names_with_input_states(self): + type ='xed_uint32_t' + for operand_decider in self.common.state_space.keys(): + #msge("STATESPACE: considering " + operand_decider) + if operand_decider not in self.operand_names: + self.operand_names[operand_decider] = type + + + +def init_functions_for_table(agi, fp, function_name, init_object): + """emit, to the file pointer fp, headers and calls to each init + function for the init_object. The function we build is named + function_name.""" + print_resource_usage('init.0') + # emit prototype for each subgraph init function + for dfo in init_object.get_init_functions(): + #print_resource_usage('init.1') + fp.write(dfo.emit_header()) + + #print_resource_usage('init.2') + # a function that calls each init function + init_fo = function_object_t(function_name,'void') + for dfo in init_object.get_init_functions(): + init_fo.add_code_eol(dfo.function_name + '()') + fp.write(init_fo.emit()) + fp.close() + del fp + #print_resource_usage('init.3') + +############################################################################ + +def generator_emit_function_list(fo_list, file_emitter): + """Emit the function_object_t-s in the fo_list list via the file_emitter""" + for fo in fo_list: + fo.emit_file_emitter(file_emitter) + +def generator_emit_function_header_list(fo_list, file_emitter): + """Emit the function headers for the function_object_t-s in the + fo_list list via the file_emitter""" + for fo in fo_list: + file_emitter.add_code(fo.emit_header()) + +def make_cvt_key(lst): + return ",".join(lst) +def make_cvt_values(s,n): + if s == '': + return ['INVALID']*n + t = s.split(",") + len_t = len(t) + if len_t < n: + t.extend(['INVALID']*(n-len_t)) + return t + +def collect_convert_decorations(agi): + """Find all instruction operands. Each operand has 0...N where N=3 + currently conversion decorations. Number each combination of + convert decorations. Assign that number to the instruction. Emit a + initialized array of convert decoration enumeration names, N-wide. + Element 0 is special: That means no convert decorations. + """ + cvt_dict = {'0':'INVALID'} + cvt_list = ['INVALID'] + n = 1 + for gi in agi.generator_list: + for ii in gi.parser_output.instructions: + for op in ii.operands: + if op.cvt: + key = make_cvt_key(op.cvt) + try: + op.cvt_index = cvt_dict[key] + except: + cvt_dict[key] = n + cvt_list.append(key) + op.cvt_index = n + n = n + 1 + else: + op.cvt_index = 0 + if n >= 256: + die("NOTIFY XED DEVELOPERS: NEED MORE BITS IN operand cvt_idx field") + msgb("NUMBER OF CONVERT PATTERNS", str(n)) + agi.max_convert_patterns = n + agi.max_decorations_per_operand = 3 + fn = 'xed-operand-convert-init.c' + f = agi.common.open_file(fn, start=False) + f.add_misc_header("#include \"xed-operand-convert-enum.h\"") + f.add_misc_header("#include \"xed-gen-table-defs.h\"") + f.start() + f.write("\nconst xed_operand_convert_enum_t ") + f.write("xed_operand_convert[XED_MAX_CONVERT_PATTERNS][%s] = {\n" % + ('XED_MAX_DECORATIONS_PER_OPERAND')) + + + for i,cvt_key in enumerate(cvt_list): + cvals = make_cvt_values(cvt_key,agi.max_decorations_per_operand) + s = ("{ XED_OPERAND_CONVERT_%s, " + + "XED_OPERAND_CONVERT_%s, " + + "XED_OPERAND_CONVERT_%s }, ") % tuple(cvals) + f.write("/* %d */ %s\n" % (i,s)) + f.write("\n};\n") + f.close() + + + +############################################################################ +# Generate the graph and most tables +############################################################################ + + +def gen_everything_else(agi): + """This is the major work function of the generator. We read the + main input files and build the decoder graph and then the decoder""" + + msge("Reading state bits") + if agi.common.options.input_state != '': + #parse the xed-state-bits.txt (or something similar) file and return + #a dictionary from a token_name to an object of + #{token_name, [token_expansion]} + #for example for "no_refining_prefix REFINING=0 OSZ=0" line we will + #have an entry no_refining_prefix: + #{no_refning_prefix, [REFINING=0, OSZ=0]} + agi.common.state_bits = read_state_spec(agi.common.options.input_state) + else: + die("Could not find state bits file in options") + msge("Done reading state bits") + + #for each of the requirement statements (eg EOSZ=1), found in the state + #file, save for each token (eg EOSZ) all its possible values + #(eg [0,1,2,3]), return a dictionary from token to its possible values + #eg EOSZ: [0,1,2,3] + agi.common.state_space = compute_state_space(agi.common.state_bits) + + lines = [] + spine = base_open_file(agi.common.options.spine,"r").readlines() + lines.extend(spine) + + msge("Reading structured input") + misc = base_open_file( + agi.common.options.structured_input_fn,"r").readlines() + lines.extend(misc) + + msge("Reading Instructions (ISA) input") + isa_lines = base_open_file( + agi.common.options.isa_input_file,"r").readlines() + lines.extend(isa_lines) + del isa_lines + + lines = process_continuations(lines) + + # Open structured output file + if agi.common.options.structured_output_fn.startswith(os.path.sep): + fn = agi.common.options.structured_output_fn + else: + fn = os.path.join(agi.common.options.gendir, + agi.common.options.structured_output_fn) + print_structured_output = False + if print_structured_output: + sout = open(fn,"w") + print_resource_usage('everything.0') + + # read all the input + while len(lines) != 0: + msge("=============================================") + msge("Creating a generator " + str(len(agi.generator_list))) + msge("=============================================") + print_resource_usage('everything.1') + msge("ALines (lines before reading input) = " + str(len(lines))) + lines = read_input(agi, lines) + msge("BLines (lines remaining after reading input) = " + str(len(lines))) + + #after this we will have all deleted and udeleted instructions + #removed for all parsers, that have instructions. + #Also all instructions with old versions will be dropped. + remove_instructions(agi) + + # first pass on the input, build the graph, collect information + for gi in agi.generator_list: + # if anything has flags, then add a flags register + add_flags_register_operand_all(agi,gi.parser_output) + + if agi.common.state_bits == None: + die("Bad agi state bits") + + if gi.common.state_bits == None: + die("Bad state bits") + + rewrite_state_operands(agi, gi.common.state_bits, gi.parser_output) + mark_operands_internal(agi, gi.parser_output) + if print_structured_output: + gi.parser_output.print_structured_output(sout) + ############################################### + # BUILD THE GRAPH BY RECURSIVE PARTITIONING + ############################################### + gi.graph = build_graph(agi.common, + gi.parser_output, + agi.operand_storage.get_operands()) + + if not gi.parser_output.is_lookup_function(): + optimize_graph(agi.common.options, gi.graph) + nt_name = gi.graph.token + #msge("GRAPHROOT: " + nt_name) + agi.nonterminal_dict.add_graph_node(nt_name, gi.graph.id) + + # For epsilon nodes, where errors are allowed, we label all + # nodes in the subgraph with "otherwise_ok". + if gi.parser_output.otherwise_ok: + epsilon_label_graph(agi.common.options, gi.graph) + + # do not collect operands from nonterminals that are lookup functions: + if not gi.parser_output.is_lookup_function(): + #msge("Collecting graph enum info") + collect_graph_enum_info(agi,gi.graph) + d = {} + d =collect_tree_depth(gi.graph, d) + #msge("DEPTHS: "+ str(d)) + if agi.common.options.print_graph: + print_graph(agi.common.options,gi.graph) + + print_resource_usage('everything.2') + if print_structured_output: + sout.close() + del sout + + print_resource_usage('everything.3') + # Renumber the itable nodes so that they are sequential, skipping + # over the lookup function itable entries. + relabel_itable(agi) + + print_resource_usage('everything.3a') + + # some stuff needs to be created first so that the pass2 stuff can + # refer to it. + for generator in agi.generator_list: + print_resource_usage('everything.4') + rewrite_default_operand_visibilities(generator, + agi.operand_storage.get_operands()) + + compute_iforms(generator.common.options, + generator, + agi.operand_storage.get_operands()) + + collect_convert_decorations(agi) + + # We emit the iform enum here so that we can use the ordering for + # initializing other structures. + emit_iclass_enum_info(agi) + emit_iclass_rep_ops(agi) + + collect_and_emit_iforms(agi,agi.common.options) + collect_iclass_strings(agi) + collect_instruction_types(agi, agi.iform_info) + agi.isa_sets = collect_isa_sets(agi) + + # idata.txt file write + write_instruction_data(agi.common.options.gendir,agi.iform_info) + write_quick_iform_map(agi,agi.common.options.gendir,agi.iform_info) + + print_resource_usage('everything.4b') + # mark bit positions in each "instruction" + decorate_operands(agi.common.options,agi) + print_resource_usage('everything.4c') + + decorate_instructions_with_exception_types(agi) + + agi.inst_fp = agi.open_file('xed-init-inst-table-data.c', start=False) + agi.inst_fp.add_header('xed-inst-defs.h') + agi.inst_fp.start() + agi.inst_fp.write('const xed_inst_t ' + + 'xed_inst_table[XED_MAX_INST_TABLE_NODES] = {\n') + + agi.open_operand_data_file() + agi.open_operand_sequence_file() + + cg_args = code_gen_dec_args_t() + + agi.encode_init_function_objects.append( + function_object_t('xed_encode_init', 'void')) + print_resource_usage('everything.5') + + find_common_operand_sequences(agi) + + for generator in agi.generator_list: + print_resource_usage('everything.6') + if generator.parser_output.is_lookup_function(): + pass + else: + cg_args.gi = generator + cg_args.options = generator.common.options + cg_args.node = generator.graph + cg_args.nonterminal_dict = agi.nonterminal_dict + cg_args.state_bits = agi.common.state_bits + cg_args.itable_init_functions = agi.itable_init_functions + + cg_args.encode_init_function_object = \ + agi.encode_init_function_objects[0] + cg_args.operand_storage_dict = agi.operand_storage.get_operands() + + # generate the itable + code_gen_instruction_table(agi, + cg_args.gi, + cg_args.itable_init_functions, + cg_args.nonterminal_dict, + cg_args.operand_storage_dict) + + print_resource_usage('everything.7') + + global max_operand_count + msgb("MAX OPERAND COUNT {}".format(max_operand_count)) + + code_gen_unique_operands(agi) + code_gen_operand_sequences(agi) + agi.close_operand_data_file() + agi.close_operand_sequence_file() + agi.inst_fp.write('};\n') + agi.inst_fp.close() + + # finish emitting the last function for the itable and the decode graph + agi.itable_init_functions.finish_fp() + + print_resource_usage('everything.10') + + # THIS NEXT FUNCTION IS THE BIGGEST TIME HOG + init_functions_for_table(agi, + agi.common.inst_file, + 'xed_init_inst_table', + agi.itable_init_functions) + + print_resource_usage('everything.12') + # some states are not assigned to in the graph and we must reserve + # storage for them anyway. MODE is one example. + agi.extend_operand_names_with_input_states() + + emit_enum_info(agi) + agi.handle_prefab_enums() + + agi.add_file_name(agi.common.source_file_names) + agi.add_file_name(agi.common.header_file_names, header=True) + + write_attributes_table(agi,agi.common.options.gendir) + + # defines for emitted tables + agi.code_gen_table_sizes() + agi.close_flags_files() + print_resource_usage('everything.16') + + call_chipmodel(agi) + call_ctables(agi) + emit_operand_storage(agi) + +################################################ +def emit_operand_storage(agi): + agi.operand_storage.emit(agi) + +def call_ctables(agi): + """Conversion tables for operands""" + lines = file(agi.common.options.ctables_input_fn).readlines() + srcs = ctables.work(lines, + xeddir=agi.common.options.xeddir, + gendir=agi.common.options.gendir) + +def call_chipmodel(agi): + args = chipmodel.args_t() + args.input_file_name = agi.common.options.chip_models_input_fn + args.xeddir = agi.common.options.xeddir + args.gendir = agi.common.options.gendir + # isaset is a list of the ISA_SETs mentioned in the chip hierarchy. + # we need to check that all of those are used/mentioned by some chip. + files_created,chips,isaset = chipmodel.work(args) + agi.all_enums['xed_chip_enum_t'] = chips + agi.all_enums['xed_isa_set_enum_t'] = isaset + print "Created files: %s" % (" ".join(files_created)) + for f in files_created: + agi.add_file_name(f,is_header(f)) + + genutil.msgb("FROM CHIP MODEL", isaset) + genutil.msgb("FROM INSTRUCTIONS ", agi.isa_sets) + for v in isaset: # stuff from the chip hierarchy model + v = v.upper() + if v in ['INVALID']: + continue + if v not in agi.isa_sets: # stuff from the instructions + genutil.warn("isa_set referenced by chip model hierarchy," + + "but not used by any instructions: {}".format(v)) + +################################################ +def read_cpuid_mappings(fn): + lines = open(fn,'r').readlines() + lines = map(no_comments, lines) + lines = filter(blank_line, lines) + d = {} # isa-set to list of cpuid records + for line in lines: + wrds = line.split(':') + isa_set = wrds[0] + #cpuid_bits = re.sub('[.]','_',wrds[1].upper()).split() + cpuid_bits = wrds[1].upper().split() + if isa_set in d: + die("Duplicate cpuid definition for isa set. isa-set={} old ={} new={}".format( + isa_set, d[isa_set], cpuid_bits)) + d[isa_set] = cpuid_bits + return d + +def make_cpuid_mappings(agi,mappings): + + # 'mappings' is a dict of isa_set -> list of cpuid_bit_names + + # collect all unique list of cpuid bit names + cpuid_bits = {} + for vlist in mappings.itervalues(): + for bit in vlist: + if bit == 'N/A': + data = bitname = 'INVALID' + else: + try: + bitname,orgdata = bit.split('.',1) + data = re.sub('[.]','_',orgdata) + except: + die("splitting problem with {}".format(bit)) + if bitname in cpuid_bits: + if cpuid_bits[bitname] != data: + die("Mismatch on cpuid bit specification for bit {}: {} vs {}".format( + bitname, cpuid_bits[bitname], data)) + cpuid_bits[bitname]=data + + + cpuid_bit_string_names = sorted(cpuid_bits.keys()) + + # move INVALID to 0th element: + p = cpuid_bit_string_names.index('INVALID') + del cpuid_bit_string_names[p] + cpuid_bit_string_names = ['INVALID'] + cpuid_bit_string_names + + # emit enum for cpuid bit names + cpuid_bit_enum = enum_txt_writer.enum_info_t(cpuid_bit_string_names, + agi.common.options.xeddir, + agi.common.options.gendir, + 'xed-cpuid-bit', + 'xed_cpuid_bit_enum_t', + 'XED_CPUID_BIT_', + cplusplus=False) + cpuid_bit_enum.print_enum() + cpuid_bit_enum.run_enumer() + agi.add_file_name(cpuid_bit_enum.src_full_file_name) + agi.add_file_name(cpuid_bit_enum.hdr_full_file_name,header=True) + + fp = agi.open_file('xed-cpuid-tables.c') + + fp.add_code('const xed_cpuid_rec_t xed_cpuid_info[] = {') + # emit initialized structure mapping cpuid enum values to descriptive structures + for bitname in cpuid_bit_string_names: + cpuid_bit_data = cpuid_bits[bitname] + if bitname == 'INVALID': + leaf = subleaf = bit = 0 + reg = 'INVALID' + else: + (leaf,subleaf,reg,bit) = cpuid_bit_data.split('_') + + s = "/* {:18s} */ {{ 0x{}, {}, {}, XED_REG_{} }},".format( + bitname, leaf,subleaf, bit, reg) + fp.add_code(s) + fp.add_code('};') + + + # emit initialized structure of isa-set mapping to array of cpuid bit string enum. + n = 4 + fp.add_code('const xed_cpuid_bit_enum_t xed_isa_set_to_cpuid_mapping[][XED_MAX_CPUID_BITS_PER_ISA_SET] = {') + + for isaset in agi.all_enums['xed_isa_set_enum_t']: + print "ISASET: ", isaset + x = 'XED_ISA_SET_' + isaset + raw = n*['XED_CPUID_BIT_INVALID'] + if x in mappings: + for i,v in enumerate(mappings[x]): + if v == 'N/A': + bit_symbolic_name = 'INVALID' + else: + (bit_symbolic_name,leaf,subleaf,reg,bit) = v.split('.') + + if i >= n: + die("Make XED_MAX_CPUID_BITS_PER_ISA_SET bigger") + raw[i] = 'XED_CPUID_BIT_' + bit_symbolic_name + bits = ", ".join(raw) + s = '/* {} */ {{ {} }} ,'.format(isaset, bits) + fp.add_code(s) + fp.add_code('};') + fp.close() + +def gen_cpuid_map(agi): + fn = agi.common.options.cpuid_input_fn + if fn: + if os.path.exists(fn): + mappings = read_cpuid_mappings(fn) + make_cpuid_mappings(agi, mappings) + return + die("Could not read cpuid input file: {}".format(str(fn))) + +################################################ + +def gen_ild(agi): + #do the ild things + if agi.common.options.ild_scanners_input_fn != '': + agi.common.ild_scanners_dict = \ + read_ild_scanners_def(agi.common.options.ild_scanners_input_fn) + else: + die("Could not find scanners file in options") + #getters are optional + if agi.common.options.ild_getters_input_fn != '': + agi.common.ild_getters_dict = \ + read_ild_getters_def(agi.common.options.ild_getters_input_fn) + else: + agi.common.ild_getters_dict = None + + ild.work(agi) + + +def emit_regs_enum(options, regs_list): + + #FIXME: sort the register names by their type. Collect all the + #types-and-widths, sort them by their ordinals. Special handling + #for the AH/BH/CH/DH registers is requried. + + enumvals = refine_regs.rearrange_regs(regs_list) + + reg_enum = enum_txt_writer.enum_info_t(enumvals, + options.xeddir, options.gendir, + 'xed-reg', 'xed_reg_enum_t', + 'XED_REG_', cplusplus=False) + reg_enum.print_enum() + reg_enum.run_enumer() + return (reg_enum.src_full_file_name,reg_enum.hdr_full_file_name) + +def emit_reg_class_enum(options, regs_list): + rclasses = {} + for ri in regs_list: + if ri.type not in rclasses: + rclasses[ri.type]=True + + #Add GPR8,16,32,64 as reg classes + if ri.type == 'GPR': + fine_rclass = 'GPR' + ri.width + if fine_rclass not in rclasses: + rclasses[fine_rclass]=True + + del rclasses['INVALID'] + just_rclass_names = rclasses.keys() + # FIXME: would really prefer alphanumeric sort (low priority) + just_rclass_names.sort() + + just_rclass_names[0:0] = ['INVALID'] # put INVALID at the start of the list + reg_enum = enum_txt_writer.enum_info_t(just_rclass_names, + options.xeddir, + options.gendir, + 'xed-reg-class', + 'xed_reg_class_enum_t', + 'XED_REG_CLASS_', + cplusplus=False) + reg_enum.print_enum() + reg_enum.run_enumer() + return (reg_enum.src_full_file_name,reg_enum.hdr_full_file_name) + +def emit_reg_class_mappings(options, regs_list): + """Emit code to map any reg to its regclass. Also emit code to map + GPRs to a more specific GPR regclass (GPR8,16,32,64)""" + + fo = function_object_t('xed_init_reg_mappings', 'void') + for ri in regs_list: + s = 'xed_reg_class_array[XED_REG_%s]= XED_REG_CLASS_%s' % (ri.name, + ri.type) + fo.add_code_eol(s) + + for ri in regs_list: + s = 'xed_largest_enclosing_register_array[XED_REG_%s]= XED_REG_%s' % ( + ri.name, ri.max_enclosing_reg) + fo.add_code_eol(s) + + if ri.max_enclosing_reg_32: + m32 = ri.max_enclosing_reg_32 + else: + m32 = ri.max_enclosing_reg + + s = 'xed_largest_enclosing_register_array_32[XED_REG_%s]= XED_REG_%s' % ( + ri.name, m32) + fo.add_code_eol(s) + + for ri in regs_list: + if ri.type == 'GPR': + s = 'xed_gpr_reg_class_array[XED_REG_%s]= XED_REG_CLASS_%s%s' % ( + ri.name, ri.type, ri.width) + fo.add_code_eol(s) + + + for ri in regs_list: + if 'NA' == ri.width: + width = '0' + width64 = '0' + elif '/' in ri.width: + chunks = ri.width.split('/') + width = chunks[0] + width64 = chunks[1] + else: + width = ri.width + width64 = ri.width + + s = 'xed_reg_width_bits[XED_REG_%s][0] = %s' % (ri.name, width) + fo.add_code_eol(s) + s = 'xed_reg_width_bits[XED_REG_%s][1] = %s' % (ri.name, width64) + fo.add_code_eol(s) + + # write the file in our customized way + fp = xed_file_emitter_t(options.xeddir, + options.gendir, + 'xed-init-reg-class.c') + fp.start() + fp.write(fo.emit()) + fp.close() + return fp.full_file_name + + +def gen_regs(options,agi): + """Generate the register enumeration & reg class mapping functions""" + + lines = base_open_file(options.input_regs,"r","registers input").readlines() + + # remove comments and blank lines + # regs_list is a list of reg_info_t's + regs_list = refine_regs.refine_regs_input(lines) + regs = map(lambda x: x.name, regs_list) + agi.all_enums['xed_reg_enum_t'] = regs + + (cfn, hfn) = emit_regs_enum(options, regs_list) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + (cfn, hfn) = emit_reg_class_enum(options, regs_list) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + cfn_map = emit_reg_class_mappings(options, regs_list) + agi.add_file_name(cfn_map) + + agi.regs_info = regs_list + + +############################################################################ +# $$ width_info_t +class width_info_t(object): + def __init__(self, name, dtype, widths): + """ a name and a list of widths, 8, 16,32, and 64b""" + self.name = name.upper() + self.dtype = dtype + self.widths = widths + +def is_bits(val): + """Return a number if the value is in explicit bits form: + [0-9]+bits, or None""" + length = len(val) + if length > 4: + if val[-4:] == "bits": + number_string = val[0:-4] + if completely_numeric.match(number_string): + return number_string + return None + +def refine_widths_input(lines): + """Return a list of width_info_t. Skip comments and blank lines""" + global comment_pattern + widths_list = [] + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + ntokens = len(wrds) + if ntokens == 3: + (name, dtype, all_width) = wrds + width8 = all_width + width16 = all_width + width32 = all_width + width64 = all_width + elif ntokens == 5: + width8='0' + (name, dtype, width16, width32, width64) = wrds + else: + die("Bad number of tokens on line: " + line) + + # convert from bytes to bits, unless in explicit bits form "b'[0-9]+" + bit_widths = [] + for val in [width8, width16, width32, width64]: + number_string = is_bits(val) + if number_string: + bit_widths.append(number_string) + else: + bit_widths.append(str(int(val)*8)) + widths_list.append(width_info_t(name, dtype, bit_widths)) + return widths_list + +def emit_widths_enum(options, widths_list): + just_width_names = map(lambda(x) : x.name, widths_list) + width_enum = enum_txt_writer.enum_info_t(just_width_names, + options.xeddir, options.gendir, + 'xed-operand-width', + 'xed_operand_width_enum_t', + 'XED_OPERAND_WIDTH_', + cplusplus=False) + width_enum.print_enum() + width_enum.run_enumer() + return (width_enum.src_full_file_name,width_enum.hdr_full_file_name) + + +def emit_width_lookup(options, widths_list): + """Emit code to map XED_OPERAND_WIDTH_* and an effective operand size to a + number of bytes. """ + + fo = function_object_t('xed_init_width_mappings', 'void') + for ri in widths_list: + for i,w in enumerate(ri.widths): + s = 'xed_width_bits[XED_OPERAND_WIDTH_%s][%d] = %s' % (ri.name, i, w) + fo.add_code_eol(s) + + if 0: # DISABLED!!! + if int(w) % 8 == 0: + multiple = '1' + else: + multiple = '0' + s = 'xed_width_is_bytes[XED_OPERAND_WIDTH_%s][%d] = %s' % ( + ri.name, i, multiple) + fo.add_code_eol(s) + + # write the file in our customized way + fp = xed_file_emitter_t(options.xeddir, + options.gendir, + 'xed-init-width.c') + fp.start() + fp.write(fo.emit()) + fp.close() + return fp.full_file_name + + +def gen_element_types_base(agi): + """Read in the information about element base types""" + fn = agi.common.options.input_element_type_base + msge("MAKING ELEMENT BASE TYPE ENUM") + all_values = agi.handle_prefab_enum(fn) + agi.all_enums['xed_operand_element_type_enum_t'] = all_values + +def gen_element_types(agi): + """Read in the information about element types""" + lines = base_open_file(agi.common.options.input_element_types, + "r","element types").readlines() + agi.xtypes_dict = opnd_types.read_operand_types(lines) + agi.xtypes = set(agi.xtypes_dict.keys()) + + (cfn,hfn) = opnd_types.write_enum(agi,agi.xtypes_dict) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + cfn = opnd_types.write_table(agi,agi.xtypes_dict) + agi.add_file_name(cfn) + +def gen_extra_widths(agi): + """Read the extra decorations for NTs and REGs that lack width + information""" + lines = base_open_file(agi.common.options.input_extra_widths, + "r", "extra widths input").readlines() + agi.extra_widths_reg = {} + agi.extra_widths_nt = {} + agi.extra_widths_imm_const = {} + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + ntokens = len(wrds) + if ntokens != 3: + die("Bad number of tokens on line: " + line) + (nt_or_reg, name, oc2) = wrds + if nt_or_reg == 'nt': + agi.extra_widths_nt[name] = oc2 + elif nt_or_reg == 'reg': + agi.extra_widths_reg[name] = oc2 + elif nt_or_reg == 'imm_const': + agi.extra_widths_imm_const[name] = oc2 + else: + die("Bad NT/REG on line: " + line) + + + +def gen_widths(options,agi): + """Generate the oc2 operand width enumeration & width lookup function""" + + lines = base_open_file(options.input_widths,"r","widths input").readlines() + + # remove comments and blank lines + # widths_list is a list of width_info_t's + widths_list = refine_widths_input(lines) + + (cfn, hfn) = emit_widths_enum(options, widths_list) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + cfn_map = emit_width_lookup(options, widths_list) + agi.add_file_name(cfn_map) + + agi.widths_list = widths_list + + # sets the default data type for each width + agi.widths_dict = {} + for w in widths_list: + agi.widths_dict[w.name] = w.dtype + + # compute the scalable widths + agi.scalable_widths = set() + for w in widths_list: + (w8,w16,w32,w64) = w.widths + if w16 != w32 or w16 != w64 or w32 != w64: + msge("Adding scalable width: " + w.name) + agi.scalable_widths.add(w.name) + + +############################################################################ +def emit_pointer_name_lookup(options, widths_list): + """Emit code to map integers representing a number of bytes accessed to a + pointer name for disassembly.""" + + max_width = 0 + for bytes, name, suffix in widths_list: + if int(bytes) > max_width: + max_width = int(bytes)+1 + + hfp = xed_file_emitter_t(options.xeddir, + options.gendir, + 'xed-init-pointer-names.h') + hfp.start() + hfp.write("#define XED_MAX_POINTER_NAMES %d\n" % max_width) + hfp.close() + + + fo = function_object_t('xed_init_pointer_names', 'void') + fo.add_code_eol("memset((void*)xed_pointer_name,0," + + "sizeof(const char*)*XED_MAX_POINTER_NAMES)") + for bytes, name, suffix in widths_list: + # add a trailing space to the name for formatting. + s = 'xed_pointer_name[%s] = \"%s \"' % (bytes, name) + fo.add_code_eol(s) + + fo.add_code_eol("memset((void*)xed_pointer_name_suffix,0,"+ + "sizeof(const char*)*XED_MAX_POINTER_NAMES)") + for bytes, name, suffix in widths_list: + # add a trailing space to the name for formatting. + s = 'xed_pointer_name_suffix[%s] = \"%s \"' % (bytes, suffix) + fo.add_code_eol(s) + + # write the file in our customized way + fp = xed_file_emitter_t(options.xeddir, + options.gendir, + 'xed-init-pointer-names.c') + fp.start() + fp.write("#include \"xed-init-pointer-names.h\"\n") + fp.write("#include \n") # for memset + fp.write("const char* xed_pointer_name[XED_MAX_POINTER_NAMES];\n") + fp.write("const char* xed_pointer_name_suffix[XED_MAX_POINTER_NAMES];\n") + fp.write(fo.emit()) + fp.close() + return [fp.full_file_name, hfp.full_file_name] + +def refine_pointer_names_input(lines): + """Return a list of width_info_t. Skip comments and blank lines""" + global comment_pattern + widths_list = [] + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + ntokens = len(wrds) + if ntokens == 3: + (bytes, name, suffix) = wrds + else: + die("Bad number of tokens on line: " + line) + widths_list.append((bytes,name,suffix)) + return widths_list + +def gen_pointer_names(options,agi): + """Generate the pointer name lookup function""" + lines = base_open_file(options.input_pointer_names,"r", + "pointer names input").readlines() + widths_list = refine_pointer_names_input(lines) + (cfn, hfn) = emit_pointer_name_lookup(options, widths_list) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + +def emit_exception_enum(agi): + if 'INVALID' not in agi.exception_types: + agi.exception_types.append('INVALID') + agi.exception_types = uniqueify(agi.exception_types) + agi.exception_types.sort(cmp=cmp_invalid) + enum = enum_txt_writer.enum_info_t( agi.exception_types, + agi.common.options.xeddir, + agi.common.options.gendir, + 'xed-exception', + 'xed_exception_enum_t', + 'XED_EXCEPTION_', + cplusplus=False) + enum.print_enum() + enum.run_enumer() + agi.add_file_name(enum.src_full_file_name) + agi.add_file_name(enum.hdr_full_file_name,header=True) + + +def decorate_instructions_with_exception_types(agi): + """Put a default exception on instructions that lack a specific + exception.""" + agi.exception_types = [] + for generator in agi.generator_list: + ii = generator.parser_output.instructions[0] + if not field_check(ii,'iclass'): + continue + for ii in generator.parser_output.instructions: + if field_check(ii,'exceptions') and ii.exceptions: + # clean it up a little + ii.exceptions = re.sub('-','_',ii.exceptions) + ii.exceptions = ii.exceptions.upper() + agi.exception_types.append(ii.exceptions) + else: + ii.exceptions = 'INVALID' + # writes agi.exception_types list of exceptions + emit_exception_enum(agi) + + + +############################################################################ + +def emit_ctypes_enum(options, ctypes_dict): + ctypes_dict['INVALID']=True + type_names = ctypes_dict.keys() + type_names.sort(cmp=cmp_invalid) + ctypes_enum = enum_txt_writer.enum_info_t(type_names, + options.xeddir, options.gendir, + 'xed-operand-ctype', + 'xed_operand_ctype_enum_t', + 'XED_OPERAND_CTYPE_', + cplusplus=False) + ctypes_enum.print_enum() + ctypes_enum.run_enumer() + return (ctypes_enum.src_full_file_name,ctypes_enum.hdr_full_file_name) + +def emit_ctypes_mapping(options, operand_ctype_map, operand_bits_map): + """Map operand names to ctypes and bits. Return c and h filenames""" + fn = 'xed-operand-ctype-map' + cf = xed_file_emitter_t(options.xeddir, options.gendir, fn + '.c') + hf = xed_file_emitter_t(options.xeddir, options.gendir, fn + '.h') + cf.start() + hf.start() + cf.write("#include \"%s\"\n" % (hf.file_name)) + + mfo = function_object_t('xed_operand_get_ctype', 'xed_operand_ctype_enum_t') + mfo.add_arg("xed_operand_enum_t opname") + mfo.add_code_eol(" xed_assert(opname True + for of in operand_fields.values(): + ctypes[of.ctype]=True + + + operand_ctype_map = {} + operand_bits_map = {} + for of in operand_fields.itervalues(): + operand_ctype_map[of.name] = of.ctype + operand_bits_map[of.name] = of.bitwidth + + + #msge("OPERAND STORAGE: %s" %(agi.operand_storage.operand_field.keys())) + + # make an enumeration of the ctypes used for passing operands around. + (cfn, hfn) = emit_ctypes_enum(options, ctypes) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + (cfn, hfn) = emit_ctypes_mapping(options, + operand_ctype_map, operand_bits_map) + agi.add_file_name(cfn) + agi.add_file_name(hfn,header=True) + + + +############################################################################ +# MAIN +############################################################################ + +def main(): + arg_parser = setup_arg_parser() + (options, args ) = arg_parser.parse_args() + set_verbosity_options(options.verbosity) + if options.xeddir == '': + path_to_generator = sys.argv[0] + (path_to_src, configure) = os.path.split(path_to_generator) + options.xeddir = path_to_src + msge("[ASSUMING PATH TO XED SRC] " + options.xeddir) + + agi = all_generator_info_t(options) + + if not os.path.exists(agi.common.options.gendir): + die("Need a subdirectory called " + agi.common.options.gendir) + + print_resource_usage('main.1') + gen_operand_storage_fields(options,agi) + + print_resource_usage('main.2') + gen_regs(options,agi) + + print_resource_usage('main.2.5') + gen_widths(options,agi) # writes agi.widths_list and agi.widths_dict + gen_extra_widths(agi) # writes agi.extra_widths_nt and agi.exta_widths_reg + gen_element_types_base(agi) + gen_element_types(agi) # write agi.xtypes dict, agi.xtypes + gen_pointer_names(options,agi) + + print_resource_usage('main.3') + + # this reads the pattern input, builds a graph, emits the decoder + # graph and the itable, emits the extractor functions, computes the + # iforms, writes map using iforms, computes capture + # functions, gathers and emits enums. (That part should move out). + gen_everything_else(agi) + + print_resource_usage('main.4') + gen_ild(agi) + gen_cpuid_map(agi) + + print_resource_usage('main.5') + agi.close_output_files() + print_resource_usage('main.6') + agi.dump_generated_files() + +################################################ + +if __name__ == '__main__': + _profile = False + if _profile: + # profiling takes A REAL LONG TIME + import profile + profile.run('main()','profile.out') + else: + main() + sys.exit(0) +#eof diff --git a/pysrc/genutil.py b/pysrc/genutil.py new file mode 100755 index 0000000..ce1b4b5 --- /dev/null +++ b/pysrc/genutil.py @@ -0,0 +1,417 @@ +#-*- python -*- +# Mark Charney +# Generic utilities +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import sys, os, math, traceback, types, copy, re, stat +import platform + +psystem = platform.system() +if psystem == 'Microsoft' or psystem == 'Windows' or psystem.find('CYGWIN') != -1 : + on_windows = True +else: + on_windows = False + +if not on_windows: + import resource + +def msgerr(s): + "Write to stderr" + sys.stderr.write("%s\n" % s) + +msgout = sys.stdout +def set_msgs(fp): + global msgout + msgout = fp + +def msge(s): + "Write to msgout" + msgout.write("%s\n" % s) +def msg(s): + "Write to msgout" + msgout.write("%s\n" % s) +def msgn(s): + "Write to msgout" + msgout.write(s) +def msgb(s,t=''): + "Write to msgout" + msgout.write('[%s] %s\n' % (s,t)) + +def cond_die(v, cmd, msg): + if v != 0: + s = msg + '\n [CMD] ' + cmd + die(s) + +def die(m): + msgerr('[ERROR] ' + m) + traceback.print_stack() + sys.exit(1) +def warn(m): + msgerr('[WARNING] ' + m) + + +def check_python_version(argmaj, argmin): + tuple = sys.version_info + major = tuple[0] + minor = tuple[1] + if (major > argmaj ) or \ + (major == argmaj and minor >= argmin): + return + die('Need Python version %d.%d or later.' % (argmaj, argmin)) + +def make_readable_by_all_writeable_by_owner(fn): + try: + rwx = stat.S_IRUSR|stat.S_IWUSR|stat.S_IRGRP|stat.S_IROTH + os.chmod(fn, rwx) + except IOError: + die('Could not chmod: ' + errorname + ' file: [' + fn + ']' ) + +def base_open_file(fn, rw, errorname=''): + try: + fp = open(fn,rw) + except IOError: + die('Could not open: ' + errorname + ' file: [' + fn + ']' ) + make_readable_by_all_writeable_by_owner(fn) + return fp + +def resource_usage(): + if on_windows: + x = (0,0,0,0,0,0) + else: + x = resource.getrusage(resource.RUSAGE_SELF) + return x + +def format_resource_usage(x): + s = '' + s += 'user: ' + str(x[0]) + s += ' sys: ' + str(x[1]) + # These don't work on linux + #s += ' maxrss: ' + str(x[2]) + #s += ' maxshd: ' + str(x[3]) + #s += ' maxprv: ' + str(x[4]) + #s += ' maxstk: ' + str(x[5]) + return s + +def get_memory_usage(): + """Return a tuple of (vmsize, vmrss, vmdata) on linux systems with + /proc filesystems.""" + try: + lines = file('/proc/%s/status' % os.getpid()).readlines() + pairs = map(lambda(x): x.split(':'), lines) + dct = dict(pairs) + return (dct['VmSize'].strip(), dct['VmRSS'].strip(), dct['VmData'].strip()) + except: + return (0,0,0) + +def print_resource_usage(i=''): + # 2014-05-19: disabled for now. + return + + x = resource_usage() + s = format_resource_usage(x) + mem = get_memory_usage() + msge('RUSAGE: %s %s vmsize: %s' % (str(i), str(s), str(mem[0]))) + + + +def flatten_sub(all,cur_list,rest): + if len(rest)==0: + all.append(cur_list) + return + + r0 = rest[0] + if type(r0) == types.ListType: + for v in r0: + tlist = copy.copy(cur_list) + tlist.append(v) + flatten_sub(all,tlist,rest[1:]) + else: + cur_list.append(r0) + flatten_sub(all,cur_list,rest[1:]) + + +def flatten(list_with_sublists): + """Take a list with some possible sublists, and return a list of + lists of flat lists. All possible combinations.""" + retval = [] + flatten_sub(retval, [], list_with_sublists) + return retval + + +def flatten_dict_sub(all,cur_dict,main_dict_with_lists,rest_keys): + if len(rest_keys)==0: + all.append(cur_dict) + return + + # pick off the first key and see what it gives us from the dict + r0 = rest_keys[0] + rhs = main_dict_with_lists[r0] + if type(rhs) == types.ListType: + for v in rhs: + tdict = copy.copy(cur_dict) + # change the list-valued entry to a scalar-valued entry + tdict[r0]=v + flatten_dict_sub(all,tdict,main_dict_with_lists,rest_keys[1:]) + else: + cur_dict[r0] = rhs + flatten_dict_sub(all,cur_dict,main_dict_with_lists,rest_keys[1:]) + + +def flatten_dict(dict_with_lists): + """Take a dict with some possible sublists, and return a list of + dicts where no rhs is a list. All possible combinations""" + retval = [] + kys = dict_with_lists.keys() + flatten_dict_sub(retval, {}, dict_with_lists,kys) + return retval + +def cmkdir(path_to_dir): + """Make a directory if it does not exist""" + if not os.path.exists(path_to_dir): + msgb("MKDIR", path_to_dir) + os.makedirs(path_to_dir) + + + +def convert_binary_to_hex(b): + "convert a bit string to hex" + decimal = 0 + radix = 1 + blist = list(b) + blist.reverse() + for bit in blist: + if bit == '1': + decimal = decimal + radix + radix = radix + radix + hexnum = hex(decimal) + return hexnum + +def decimal_to_binary(i): + "Take a decimal integer, and return a list of bits MSB to LSB" + if i == 0: + return [ '0' ] + rev_out = [] + while i > 0: + bit = i & 1 + #print hex(i),ig, bit + rev_out.append(str(bit)) + i = i >> 1 + #print str(rev_out) + rev_out.reverse() + return rev_out + +def hex_to_binary(x): + "Take a hex number, no 0x prefix required, and return a list of bits MSB to LSB" + i = int(x,16) + return decimal_to_binary(i) + +def stringify_list(lst): + return ' '.join(map(str,lst)) + +def round_up_power_of_two(x): + lg = math.ceil(math.log(x,2)) + return 1 << int(lg) + + + +make_numeric_decimal_pattern = re.compile(r'^[0-9]+$') +make_numeric_hex_pattern = re.compile(r'^0[xX][0-9A-Fa-f]+$') +make_numeric_binary_pattern = re.compile(r'^0b[01_]+$') + +make_numeric_old_binary_pattern = re.compile(r"B['](?P[01_]+)") # leading "B'" +make_numeric_old_decimal_pattern = re.compile(r'^0m[0-9]+$') # only base 10 numbers + +def make_binary(bits): + "return a string of 1s and 0s. Could return letter strings as well" + # binary numbers must preserve the number of bits. If we are + # doing a conversion, then we just go with the number of bits we get. + + if make_numeric_binary_pattern.match(bits): + # strip off the 0b prefix + bits = re.sub('_','',bits) + return bits[2:] + # this might return fewer than the expected number of binary bits. + # for example, if you are in a 4 bit field and use a 5, you will + # only get 3 bits out. Because this routine is not cognizant of + # the field width. + + if numeric(bits): + v = make_numeric(bits) + d = decimal_to_binary(v) # a list of bits + return ''.join(d) + bits = re.sub('_','',bits) + return bits + +def numeric(s): + if make_numeric_decimal_pattern.match(s): + return True + if make_numeric_hex_pattern.match(s): + return True + if make_numeric_binary_pattern.match(s): + return True + return False + +def is_binary(s): + if make_numeric_binary_pattern.match(s): + return True + return False + +def make_numeric(s, restriction_pattern=None): + global make_numeric_old_decimal_pattern + global make_numeric_hex_pattern + global make_numeric_binary_pattern + global make_numeric_old_binary_pattern + + if type(s) == types.IntType: + die("Converting integer to integer") + elif make_numeric_hex_pattern.match(s): + out = int(s,16) + elif make_numeric_binary_pattern.match(s): + # I thought that I could leave the '0b' prefix. Python >= 2.6 + # handles '0b' just fine but Python 2.5 cannot. As of + # 2012-06-20 the pin team currently still relies upon python + # 2.5. + just_bits = s.replace('0b','') + just_bits = just_bits.replace('_','') + out = int(just_bits,2) + #msgb("MAKE BINARY NUMERIC", "%s -> %d" % (s,out)) + elif make_numeric_old_decimal_pattern.match(s): + sys.stderr.write("0m should not occur. Rewrite files!") + sys.exit(1) + elif make_numeric_old_binary_pattern.match(s): + sys.stderr.write("B' binary specifer should not occur. Rewrite files!") + sys.exit(1) + else: + out = int(s) + return out + + +######################### + +def find_runs(blist): + """Accept a bit list. Return a list tuples (letter,count) + describing bit runs, the same bit repeated n times""" + last = None + run = 1 + output = [] + if blist == None: + return output + for b in blist: + if last != None: + if b == last: + run = run + 1 + else: + output.append( (last, run) ) + run = 1 + last = b + if last != None: + output.append( (last, run) ) + return output + +def print_runs(runs): + s = [] + for (val, count) in runs: + s.append("(%s,%d)" % (val,count)) + msge("Runs: %s" % ' '.join(s) ) + +def no_underscores(s): + v = s.replace('_','') # remove underscores + return v + +comment_pattern = re.compile(r'[#].*$') +def no_comments(line): + global comment_pattern + oline = comment_pattern.sub('',line) + oline = oline.strip() + return oline + +continuation_pattern = re.compile(r'\\$') +def process_continuations(lines): + global continuation_pattern + olines=[] + while len(lines) != 0: + line = no_comments(lines[0]) + line = line.strip() + lines.pop(0) + if line == '': + continue + if continuation_pattern.search(line): + # combine this line with the next line if the next line exists + line = continuation_pattern.sub('',line) + if len(lines) >= 1: + combined_lines = [ line + lines[0] ] + lines.pop(0) + lines = combined_lines + lines + continue + olines.append(line) + del lines + return olines + +def skip_junk(lines): + while len(lines) != 0: + line = no_comments(lines[0]) + line = line.strip() + if line == '': + lines.pop(0) + else: + break + return lines +def field_check(obj,fld): + "Return true if fld exists in obj" + + try: + # ignore returned value + s = getattr(obj,fld) + return True + except AttributeError: + retval = False + + return retval +def generate_lookup_function_basis(gi,state_space): + """Return a dictionary whose values are dictionaries of all the values + that the operand decider might have""" + argnames = {} # tokens -> list of all values for that token + for ii in gi.parser_output.instructions: + for bt in ii.ipattern.bits: + if bt.is_operand_decider(): + if bt.token not in argnames: + argnames[bt.token] = {} + + if bt.test == 'eq': + argnames[bt.token][bt.requirement]=True + elif bt.test == 'ne': + all_values_for_this_od = state_space[bt.token] + trimmed_vals = filter(lambda (x): x != bt.requirement, + all_values_for_this_od) + for tv in trimmed_vals: + argnames[bt.token][tv]=True + else: + die("Bad bit test (not eq or ne) in " + ii.dump_str()) + elif bt.is_nonterminal(): + pass # FIXME make a better test + else: + die("Bad patten bit (not an operand decider) in " + ii.dump_str()) + return argnames + +def uniqueify(values): + s = {} + for a in values: + s[a] = True + k = s.keys() + k.sort() + return k diff --git a/pysrc/hash_compare.py b/pysrc/hash_compare.py new file mode 100755 index 0000000..865e554 --- /dev/null +++ b/pysrc/hash_compare.py @@ -0,0 +1,92 @@ +#!/usr/bin/env python +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +class hnode_t: + def __init__(self, lst=None, id=None): + self.lst = lst + self.token = id + + +class hash_compare_t: + def __init__(self): + self.bins = {} # indexed by hash values + self.token = 1 + + def hash_list(self, inlist): + """Return a hash of the content of inlist""" + h = 0 + i = 1 + for v in inlist: + h = h + v*i + i = i + 1 + return h + + def find(self,inlist): + h = self.hash_list(inlist) + if h in self.bins: + bucket = self.bins[h] + for b in bucket: + if b.lst == inlist: + return b.token + return None + + def insert(self,inlist): + """Return a identifier for this list upon insertion, creating + one if necessary.""" + + h = self.hash_list(inlist) + if h in self.bins: + bucket = self.bins[h] + for node in bucket: + if node.lst == inlist: + return node.token + # not found... add it to the bucket + n = hnode_t(inlist, self.token) + bucket.append(n) + self.token = self.token + 1 + return n.token + else: + # nothing with this hash value, add a bucket + n = hnode_t(inlist, self.token) + self.bins[h] = [ n ] + self.token = self.token + 1 + return n.token + + + +def test_hash(): + h = hash_compare_t() + a = [1,2,3] + b = [1,2,4] + c = [1,2,3] + d = [1,2,5] + e = [1,2] + v = h.insert(a) + print "A's UID: %d" % ( v ) + v = h.insert(b) + print "B's UID: %d" % ( v ) + v = h.insert(c) + print "C's UID: %d" % ( v ) + v = h.insert(d) + print "D's UID: %d" % ( v ) + v = h.insert(e) + print "E's UID: %d" % ( v ) + +if __name__ == "__main__": + test_hash() diff --git a/pysrc/hashfks.py b/pysrc/hashfks.py new file mode 100644 index 0000000..acfaee7 --- /dev/null +++ b/pysrc/hashfks.py @@ -0,0 +1,153 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os + +import tup2int +import xedhash +#paper of Fredman Komlos and Szemeredi (1984) : +#following hash function family is universal: +# x -> (kx mod p) mod s +# s ~ n^2 +# p > s +# k is in 1,3,..., 2k+1 +#Implementation of the hash_fun_interface_t +class hash_fun_fks_t(xedhash.hash_fun_interface_t): + def __init__(self, k, p, m): + self.k = k + self.p = p + if p < m: + self.m = p + else: + self.m = m + def kind(self): + return "fks" + + def get_table_size(self): + return self.m + + def tuple2int(self, tuple_val, cnames, op_widths_dict):#FIXME NOT USED + return tup2int.tuple2int(tuple_val, cnames, op_widths_dict) + + def apply(self, x): + return ((self.k*x) % self.p) % self.m + + def emit_cexpr(self, key_str='key'): + if self.m == 1: + return '(0)' + if self.p == self.m: + #when m==p it is unnecessary to do "mod m" + expr = '(%d*%s %% %d)' % (self.k, key_str, self.p) + else: + expr = '((%d*%s %% %d) %% %d)' % (self.k, key_str, self.p, self.m) + return expr + + def need_hash_index_validation(self): + return True + + def add_key_validation(self, strings_dict): + key_str = strings_dict['key_str'] + hentry_str ='%s[%s]' % (strings_dict['table_name'], + strings_dict['hidx_str']) + + return 'if(%s.key == %s)' % (hentry_str, key_str) + def __str__(self): + lines = [] + lines.append('x = Sigma(Ti << bit_shift)') + lines.append('FKS(x) = (%dx mod %d) mod %d' % (self.k, self.p, self.m)) + return '\n'.join(lines) + + +_primes = [ + 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, + 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, + 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, +127, 131, 137, 139, 149, 151, 157, 163, 167, 173, +179, 181, 191, 193, 197, 199, 211, 223, 227, 229, +233, 239, 241, 251, 257, 263, 269, 271, 277, 281, +283, 293, 307, 311, 313, 317, 331, 337, 347, 349, +353, 359, 367, 373, 379, 383, 389, 397, 401, 409, +419, 421, 431, 433, 439, 443, 449, 457, 461, 463, +467, 479, 487, 491, 499, 503, 509, 521, 523, 541, +547, 557, 563, 569, 571, 577, 587, 593, 599, 601, +607, 613, 617, 619, 631, 641, 643, 647, 653, 659, +661, 673, 677, 683, 691, 701, 709, 719, 727, 733, +739, 743, 751, 757, 761, 769, 773, 787, 797, 809, +811, 821, 823, 827, 829, 839, 853, 857, 859, 863, +877, 881, 883, 887, 907, 911, 919, 929, 937, 941] + +#FIXME: BTW the tuple->int computation itself is a good hash function. +#Moreover, when m is a prime, the functions h(t) = (Sigma(AiTi)) mod m +#where Ti and Ai are arbitrary values in Zm Galois field +#are a universal hash function family! +#Hence our tuple2int function might be a good hash function itself, and +#if we parametrize it with Ai, we can get perfect hash functions! +#This can be faster than FKS because we do the tuple2int computation +#for FKS anyway before applying the FKS hash function. +#TODO: check if this approach is better than FKS. +_max_k = 32 + +_l1_bucket_max = 8 # FIXME: make this a parameter. Also in ild_phash.py + + +def _get_l1_mlist(n): + """n is the number of keys in the hash function. Guessing a good size + for the hash table. Try squaring number of keys but that is too + much. if we use n, we get minimal perfect hash functions """ + global _l1_bucket_max + if n == 1: + mlist = [1] + elif n <= _l1_bucket_max: + mlist = [n, 2*n, n*n] + else: + mlist = [n, 2*n] #just to try + return mlist + +def find_fks_perfect(keylist): + """Return a perfect hash function for a given key list. Or None if no + perfect hash function could be found.""" + global _max_k + mlist = _get_l1_mlist(len(keylist)) + for m in mlist: # of buckets + for p in _primes: + for k in range(3, _max_k): + hash_f = hash_fun_fks_t(k,p,m) + if xedhash.is_perfect(keylist, hash_f): + return hash_f + del hash_f + return None + + + +def find_fks_well_distributed(keylist): + """Return a hash well-distributed function (not necessarily perfect!) + for a given key list""" + global _max_k + global _l1_bucket_max + mlist = _get_l1_mlist(len(keylist)) # number of buckets + for m in mlist: + for p in _primes: + for k in range(3, _max_k): + hash_f = hash_fun_fks_t(k,p,m) + if xedhash.is_well_distributed(keylist, hash_f, _l1_bucket_max): + return hash_f + del hash_f + return None diff --git a/pysrc/hashlin.py b/pysrc/hashlin.py new file mode 100644 index 0000000..7b6d071 --- /dev/null +++ b/pysrc/hashlin.py @@ -0,0 +1,90 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os +import math +import xedhash + + + +class linear_func_t(xedhash.hash_fun_interface_t): + ''' This function is used when the keys are sequential ''' + def __init__(self,k,max_key): + ''' @param k: the lowest key in the range + @param max_key: the highest key in range + ''' + + self.k = k + self.max_key = max_key - k #used for range validation + #total number of keys, used for lu table creation + self.m = self.max_key + 1 + def kind(self): + return "linear" + def get_table_size(self): + return self.m + + def apply(self, x): + return x - self.k + def emit_cexpr(self, key_str='key'): + return "%s - %d" % (key_str,self.k) + def need_hash_index_validation(self): + ''' the linear function does not need to do hash index validation since + it does not do hashing''' + return False + def add_key_validation(self,strings_dict): + hidx_str = strings_dict['hidx_str'] + if self.max_key == 0: + # 2016-07-28 Added an equality test to remove bogus + # warnings from klocwork (KW) about negative numbers after + # subtraction on 1-entry hash tables. Many of the linear + # hashes have one entry and this removes a bunch of + # completely inappropriate warnings from the frequently + # stupid klockwork tool. + return 'if(%s == %d)' % (hidx_str, self.max_key) + else: + # 2016-07-28 klockwork complains about unsigned hidx with + # hidx < 0. I considered adding adding "&& hidx >= 0" to + # the test to quiet KW warnings. But that extra clause + # causes the clang compiler to complain that I did + # something stupid (with -Wall) since that that expression + # is always true for unsigned numbers. Stupid KW just does + # not understand unsigned arithmetic. Someone should make + # KW smarter... + return 'if(%s <= %d)' % (hidx_str, self.max_key) + def __str__(self): + + return 'h(x) = linear(x - %d)' % self.k + + + +def get_linear_hash_function(keylist, tolerable_sparsity=0.2): + ''' returns phash_t object with a linear_funct_t as the hash function''' + min_key = min(keylist) + max_key = max(keylist) + nelem = len(keylist) + nslots = max_key - min_key + 1 + + # if the array is more than 20% empty (or overridden value), bail. + if nslots > nelem: + if (nelem * (1.0 + tolerable_sparsity)) < nslots: + return None + hash_f = linear_func_t(min_key,max_key) + return hash_f diff --git a/pysrc/hashmul.py b/pysrc/hashmul.py new file mode 100755 index 0000000..2d80fc6 --- /dev/null +++ b/pysrc/hashmul.py @@ -0,0 +1,210 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os +import math +import xedhash + +class hashmul_t(xedhash.hash_fun_interface_t): + """Implement multiplicative hashing.""" + + def __init__(self, table_size): + # golden ratio phi is (1+sqrt(5))/2. From Knuth, volume 3, page 516 + # 1/phi = (sqrt(5)-1)/2 (after some arithmetic) + # We are using 1/phi * 2**n + # where n is the number of bits in the data type (32) + + + self.golden_ratio_recip2to32 = 2654435769 + self.table_size = table_size + + # pow2 is True if the table is a power of 2. + # ilog2_table_size is only valid if pow2 is True + self.pow2, self.ilog2_table_size = self.power_of_2() + + def kind(self): + return "mult" + + def power_of_2(self): + ilog2_table_size = int(math.log(self.table_size,2)) + if pow(2,ilog2_table_size) == self.table_size: + return (True, ilog2_table_size) + return (False, -1) + + def get_table_size(self): + return self.table_size + + def __str__(self): + return "h(x) = hashmul({})".format(self.table_size) + + def apply(self, k): + """Apply the hash function to the key k""" + #sys.stderr.write("Apply {} --> ".format(k)) + q = self.golden_ratio_recip2to32 * k + fraction = q & ((1<<32)-1) + r = fraction * self.table_size + v = r >> 32 + #sys.stderr.write(" {}\n".format(v)) + return v + + def apply_pow2(self, k): + """Apply the hash function to the key k, for power of 2 table sizes""" + q = self.golden_ratio_recip2to32 * k + fraction = q & ((1<<32)-1) + v = fraction >> (32-self.ilog2_table_size) + return v + + def is_perfect(self, key_list): + values = set() + for k in key_list: + #sys.stderr.write("Checking {}\n".format(k)) + v = self.apply(k) + if v in values: + # collision - not perfect + return False + values.add(v) + + # no collisions in the output of the hash: perfect + return True + + def need_hash_index_validation(self): + """Need to validate that we landed on live bucket""" + return True + + def add_key_validation(self, strings_dict): + key_str = strings_dict['key_str'] + hentry_str ='%s[%s]' % (strings_dict['table_name'], + strings_dict['hidx_str']) + + return 'if(%s.key == %s)' % (hentry_str, key_str) + + + def emit_cvar_decl(self): + if self.pow2: + return "xed_union64_t t" + else: + return "xed_union64_t t, u" + + + def emit_cexpr(self, key_str="key"): + """Emit a C expression for the hash function given a C variable + key_str.""" + if self.pow2: + # power of 2 table size can replace the 2nd multiply with a shift + c_hash_expr = """(t.u64 = {0} * {1}, t.s.lo32 >> (32-{2}))""".format( + str(self.golden_ratio_recip2to32), + key_str, + self.ilog2_table_size) + else: + # the ULL cast on the constant is important to get 64b math. + c_hash_expr = """(t.u64 = {0} * {1}, u.u64 = t.s.lo32 * {2}ULL, u.s.hi32)""".format( + str(self.golden_ratio_recip2to32), + key_str, + str(self.table_size)) + + return c_hash_expr + +def find_perfect(keylist): + n = len(keylist) + for m in range(n,2*n): + f = hashmul_t(n) + if f.is_perfect(keylist): + return f + return None + +def test1(): + f = hashmul_t(128) + + for k in range(0,128): + v = f.apply(k) + print "{} -> {}".format(k,v) + + if f.is_perfect(range(0,128)): + print "Hash function is perfect" + else: + print "Hash function has collisions" + + print f.emit_cexpr() + return 0 +def test2(): + f = hashmul_t(9) + inputs = [225,2273,737,2785,241,2289,753,2801] + for k in inputs: + v = f.apply(k) + print "{} -> {}".format(k,v) + + if f.is_perfect(inputs): + print "Hash function is perfect" + else: + print "Hash function has collisions" + + print f.emit_cexpr() + return 0 +def test3(): + f = hashmul_t(16) + inputs = [225,2273,737,2785,241,2289,753,2801] + for k in inputs: + v1 = f.apply(k) + v2 = f.apply_pow2(k) + if v1 != v2: + print "ERROR {} -> {} {}".format(k,v1,v2) + else: + print "OK {} -> {} {}".format(k,v1,v2) + + if f.is_perfect(inputs): + print "Hash function is perfect" + else: + print "Hash function has collisions" + + print f.emit_cexpr() + return 0 + +def test4(): + f = hashmul_t(1) + inputs = [68002] + for k in inputs: + v1 = f.apply(k) + v2 = f.apply_pow2(k) + if v1 != v2: + print "ERROR {} -> {} {}".format(k,v1,v2) + else: + print "OK {} -> {} {}".format(k,v1,v2) + + if f.is_perfect(inputs): + print "Hash function is perfect" + else: + print "Hash function has collisions" + + print f.emit_cexpr() + return 0 + +def test(): + for f in [test1, test2, test3, test4]: + r = f() + if r: + print "FAIL: {}".format(f.__name__) + else: + print "PASS: {}".format(f.__name__) + +if __name__ == "__main__": + r = test() + sys.exit(r) + diff --git a/pysrc/hlist.py b/pysrc/hlist.py new file mode 100755 index 0000000..1495222 --- /dev/null +++ b/pysrc/hlist.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +class hlist_t(object): + """A hashable integer list""" + + def __init__(self,l): + self.lst = l + def __eq__(self,other): + if self.lst == other.lst: + return True + return False + def __hash__(self): + h = 0 + for v in self.lst: + h = h ^ v + h = h << 1 + return h + def __str__(self): + s = ",".join(map(lambda(x):str(x),self.lst)) + return s + + +def test_hlist(): + a = hlist_t([1,2,3]) + b = hlist_t([1,2,3]) + c = hlist_t([1,3]) + + if a == b: + print 'a==b' + if a == c: + print 'a==c' + + d = {} + + d[a] = 1 + d[b] = 2 + d[c] = 3 + for k in d.keys(): + print str(k) + +if __name__ == '__main__': + test_hlist() diff --git a/pysrc/ild.py b/pysrc/ild.py new file mode 100755 index 0000000..f9999b6 --- /dev/null +++ b/pysrc/ild.py @@ -0,0 +1,771 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import sys +import re +import copy +import genutil +import ildutil +import mbuild +import ild_info +import ild_storage +import ild_storage_data +import ild_eosz +import ild_easz +import ild_nt +import ild_imm +import ild_disp +import ild_modrm +import codegen +import os +import collections +import shutil +import ild_phash +import ild_codegen +import math +import opnds +import ild_cdict +import xed3_nt +import actions +import verbosity + + +op_bin_pattern = re.compile(r'[_10]{2,}$') +op_hex_pattern = re.compile(r'[0-9a-f]{2}$', flags=re.IGNORECASE) +reg_binding_pattern = re.compile(r'REG[[](?P0b[01_]+)]') +mod_eq_pattern = re.compile(r'MOD=(?P[0123]{1})') +mod_neq_pattern = re.compile(r'MOD(!=|=!)(?P[0123]{1})') + + +#debugdir is updated in init_debug +#the module. +debugdir = '.' + +#the debug file +debug = None + +storage_fn = 'ild_storage_data.py' + +#FIXME: can we get it from generator.py? +_xed_3dnow_category = '3DNOW' + +_mode_token = 'MODE' + +_vexvalid_op = 'VEXVALID' + + +#checks if we have 3dnow instructions +#some of these instructions have 0f 0f ... opcode pattern +#hence we need to discard second 0f and not treat it as opcode +#this is a special case, there is no way to treat it in a general way +#hence we need to check for it +def _is_amd3dnow(agi): + for g in agi.generator_list: + ii = g.parser_output.instructions[0] + if genutil.field_check(ii,'iclass'): + for ii in g.parser_output.instructions: + if ii.category == _xed_3dnow_category: + return True + return False + +#just to know how many there are and how hard it is +#42 nested NTs.. +#mostly modrm-related +def _get_nested_nts(agi): + nested_nts = set() + for nt_name in agi.nonterminal_dict.keys(): + g = agi.generator_dict[nt_name] + ii = g.parser_output.instructions[0] + if genutil.field_check(ii,'iclass'): + continue #only real NTs, not instructions + for rule in g.parser_output.instructions: + for bt in rule.ipattern.bits: + if bt.is_nonterminal(): + nested_nts.add(nt_name) + for op in rule.operands: + if op.type == 'nt_lookup_fn': + nested_nts.add(nt_name) + return nested_nts + + +########################################################################### +## < Interface for generator > +########################################################################### + +#needed to init the debug directory +def init_debug(agi): + global debug + global debugdir + debugdir = agi.common.options.gendir + debug = open(mbuild.join(debugdir, 'ild_debug.txt'), 'w') + +def gen_xed3(agi,ild_info,is_3dnow,ild_patterns, + all_state_space,ild_gendir,all_ops_widths): + all_cnames = set() + ptrn_dict = {} + maps = ild_info.get_maps(is_3dnow) + for insn_map in maps: + ptrn_dict[insn_map] = collections.defaultdict(list) + for ptrn in ild_patterns: + ptrn_dict[ptrn.insn_map][ptrn.opcode].append(ptrn) + #FIXME:bad name + vv_lu = {} + #mapping between a operands to their look up function + op_lu_map = {} + + for vv in sorted(all_state_space['VEXVALID'].keys()): + #cdict is a 2D dictionary: + #cdict[map][opcode] = ild_cdict.constraint_dict_t + #each constraint_dict_t describes all the patterns that fall + #into corresponding map-opcode + #cnames is a set of all constraint names from the patterns + #in the given vv space + cdict,cnames = ild_cdict.get_constraints_lu_table(ptrn_dict, + is_3dnow, + all_state_space, + vv, + all_ops_widths) + all_cnames = all_cnames.union(cnames) + _msg("vv%s cnames: %s" % (vv,cnames)) + + #now generate the C hash functions for the constraint + #dictionaries + (ph_lu,lu_fo_list,operands_lu_list) = ild_cdict.gen_ph_fos( + agi, + cdict, + is_3dnow, + mbuild.join(ild_gendir, + 'all_constraints_vv%s.txt' %vv), + ptrn_dict, + vv) + #hold only one instance of each function + for op in operands_lu_list : + if op.function_name not in op_lu_map: + op_lu_map[op.function_name] = op + + vv_lu[str(vv)] = (ph_lu,lu_fo_list) + _msg("all cnames: %s" % all_cnames) + #dump the hash functions and lookup tables for obtaining these + #hash functions in the decode time + ild_codegen.dump_vv_map_lookup(agi, + vv_lu, + is_3dnow, + op_lu_map.values(), + h_fn='xed3-phash.h') + #xed3_nt.work generates all the functions and lookup tables for + #dynamic decoding + xed3_nt.work(agi, all_state_space, all_ops_widths, ild_patterns) + +#Main entry point of the module +def work(agi): + ild_gendir = agi.common.options.gendir + init_debug(agi) + is_3dnow = _is_amd3dnow(agi) + + debug.write("state_space:\n %s" % agi.common.state_space) + #return + + debug.write("DUMP STORAGE %s\n" % agi.common.options.gen_ild_storage) + + # Collect up interesting NT names. + # We are going to use them when we generate pattern_t objects + # and also when we build resolution functions. + eosz_nts = ild_eosz.get_eosz_binding_nts(agi) + easz_nts = ild_easz.get_easz_binding_nts(agi) + imm_nts = ild_imm.get_imm_binding_nts(agi) + + disp_nts = ild_disp.get_disp_binding_nts(agi) + brdisp_nts = ild_disp.get_brdisp_binding_nts(agi) + + #just for debugging + _msg("EOSZ NTS:") + for nt_name in eosz_nts: + _msg(nt_name) + + _msg("\nEASZ NTS:") + for nt_name in easz_nts: + _msg(nt_name) + + _msg("\nIMMNTS:") + for nt_name in imm_nts: + _msg(nt_name) + + _msg("\nDISP NTS:") + for nt_name in disp_nts: + _msg(nt_name) + + _msg("\nBRDISP NTS:") + for nt_name in brdisp_nts: + _msg(nt_name) + + nested_nts = _get_nested_nts(agi) + _msg("\NESTED NTS:") + for nt_name in nested_nts: + _msg(nt_name) + + #Get dictionary with all legal values for all interesting operands + all_state_space = ild_cdict.get_all_constraints_state_space(agi) + _msg("ALL_STATE_SPACE:") + for k,v in all_state_space.items(): + _msg("%s: %s"% (k,v)) + + #Get widths for the operands + all_ops_widths = ild_cdict.get_state_op_widths(agi, all_state_space) + + _msg("ALL_OPS_WIDTHS:") + for k,v in all_ops_widths.items(): + _msg("%s: %s"% (k,v)) + + #generate a list of pattern_t objects that describes the ISA. + #This is the main data structure for XED3 + ild_patterns = get_patterns(agi, is_3dnow, eosz_nts, easz_nts, imm_nts, + disp_nts, brdisp_nts, all_state_space) + + if ild_patterns: + if agi.common.options.gen_ild_storage: + #dump the ild_storage_data.py file + emit_gen_info_lookup(agi, ild_patterns, is_3dnow, debug) + reload(ild_storage_data) + + #get ild_storage_t object - the main data structure for ILD + #essentially a 2D dictionary: + #united_lookup[map][opcode] == [ ild_info_t ] + #the ild_info_t objects are obtained both from grammar and + #ild_storage_data.py file, so that if ild_info_t objects are + #defined in ild_storage_data.py file, ILD will have information + #about illegal map-opcodes too. + united_lookup = _get_united_lookup(ild_patterns,is_3dnow) + + #generate modrm lookup tables + ild_modrm.work(agi, united_lookup, debug) + + #dump_patterns is for debugging + if verbosity.vild(): + dump_patterns(ild_patterns, + mbuild.join(ild_gendir, 'all_patterns.txt')) + + + eosz_dict = ild_eosz.work(agi, united_lookup, + eosz_nts, ild_gendir, debug) + + easz_dict = ild_easz.work(agi, united_lookup, + easz_nts, ild_gendir, debug) + + #dump operand accessor functions + agi.operand_storage.dump_operand_accessors(agi) + + + if eosz_dict and easz_dict: + ild_imm.work(agi, united_lookup, imm_nts, ild_gendir, + eosz_dict, debug) + ild_disp.work(agi, united_lookup, disp_nts, brdisp_nts, + ild_gendir, eosz_dict, easz_dict, debug) + + + #dump scanners headers - they might be different for different + #models. + scanners_dict = agi.common.ild_scanners_dict + dump_header_with_header(agi, 'xed-ild-scanners.h', scanners_dict) + + getters_dict = agi.common.ild_getters_dict + dump_header_with_header(agi, 'xed-ild-getters.h', getters_dict) + + gen_xed3(agi,ild_info,is_3dnow,ild_patterns, + all_state_space,ild_gendir,all_ops_widths) + +def dump_header_with_header(agi, fname, header_dict): + """ emit the header fname. + add the header in header_dict with the maximal id. + + this mechanism is used in order to choose header + files in the build time, + different build configuration use different header files. + e.g. when building without AVX512 we are using the basic getters. + when building with AVX512 the header that is used comes + form avx512 layer. + + FIXME: when all avx512 will move into the base layer + we can removed this + mechanism and use C defines. """ + + _msg("HEADER DICT: %s" % header_dict) + + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = mbuild.join(agi.common.options.gendir,'include-private') + if header_dict: + header = max(header_dict, key=header_dict.get) + header = os.path.normcase(header) + + header_basename = os.path.basename(header) + + _msg("HEADER: %s" %header) + if os.path.exists(header): + _msg("HEADER EXISTS: %s" %header) + else: + _msg("BADNESS - HEADER DOES NOT EXIST: %s" %header) + try: + shutil.copyfile(header, os.path.join(gendir, header_basename)) + except: + ildutil.ild_err("Failed to copyfile src=%s dst=%s"% + (header, + os.path.join(gendir, header_basename))) + else: + header_basename = None + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + fname, shell_file=False, + is_private= True) + if header_basename: + h_file.add_header(header_basename) + h_file.start() + h_file.close() + +def get_patterns(agi, is_3dnow, eosz_nts, easz_nts, + imm_nts, disp_nts, brdisp_nts, all_state_space): + """ + This function generates the pattern_t objects that have all the necessary + information for the ILD. Returns these objects as a list. + """ + patterns = [] + for g in agi.generator_list: + ii = g.parser_output.instructions[0] + if genutil.field_check(ii,'iclass'): + for ii in g.parser_output.instructions: + ptrn = pattern_t(ii, is_3dnow, eosz_nts, + easz_nts, imm_nts, disp_nts, brdisp_nts, + ildutil.mode_space, all_state_space) + patterns.append(ptrn) + if ptrn.incomplete_opcode: + expanded_ptrns = ptrn.expand_opcode() + patterns.extend(expanded_ptrns) + return patterns + + +def _get_united_lookup(ptrn_list,is_3dnow): + """ + Combine storage obtained from grammar and from ILD storage + @return: ild_info.storage_t object + """ + #build an ild_info_storage_t object from grammar + from_grammar = get_info_storage(ptrn_list, 0, is_3dnow) + + #get an ild_info_storage_t object from ild python-based storage + from_storage = ild_storage_data.gen_ild_info() + + #FIXME: should we make is_amd=(is_3dnow or from_storage.is_3dnow)? + united_lookup = ild_storage.ild_storage_t(is_amd=is_3dnow) + + #unite the lookups, conflicts will be resolved by priority + for insn_map in ild_info.get_maps(is_3dnow): + for op in range(0, 256): + ulist = (from_grammar.get_info_list(insn_map, hex(op)) + + from_storage.get_info_list(insn_map, hex(op))) + united_lookup.set_info_list(insn_map, hex(op), ulist) + return united_lookup + + +def get_info_storage(ptrn_list, priority, is_3dnow): + """ + convert list of pattern_t objects to ild_storage_t object + """ + storage = ild_storage.ild_storage_t(is_amd=is_3dnow) + + for p in ptrn_list: + info = ild_info.ptrn_to_info(p, priority) + if not (info in storage.get_info_list(p.insn_map,p.opcode)): + storage.append_info(p.insn_map, p.opcode, info) + return storage + + +def emit_gen_info_lookup(agi, ptrn_list, is_3dnow, debug): + debug.write("DUMPING ILD STORAGE\n") + f = codegen.xed_file_emitter_t(agi.common.options.xeddir, + agi.common.options.xeddir, + storage_fn, + shell_file=True) + + storage = get_info_storage(ptrn_list, ild_info.storage_priority, is_3dnow) + #list_name = "info_lookup['%s']['%s']" + list_name = 'info_list' + indent = ' ' * 4 + f.start() + f.add_code("import ild_info") + f.add_code("import ild_storage\n\n\n") + + f.add_code("#GENERATED FILE - DO NOT EDIT\n\n\n") + f.write("def gen_ild_info():\n") + f.write(indent + "storage = ild_storage.ild_storage_t(is_amd=%s)\n" % + is_3dnow) + + for insn_map in ild_info.get_dump_maps(): + for op in range(0, 256): + for info in storage.get_info_list(insn_map, hex(op)): + f.write("%s#MAP:%s OPCODE:%s\n" % + (indent, info.insn_map, info.opcode)) + f.write("%sinfo_list = storage.get_info_list('%s','%s')\n" % + (indent, insn_map, hex(op))) + emit_add_info_call(info, list_name, + f, indent) + f.write(indent + "return storage\n") + f.close() + +def emit_add_info_call(info, list_name, f, indent=''): + s = [] + tab = ' ' * 4 + s.append(indent + "%s.append(ild_info.ild_info_t(\n%sinsn_map='%s'" % + (list_name,(indent+tab),info.insn_map)) + s.append("opcode='%s'" % info.opcode) + s.append("incomplete_opcode=%s" % info.incomplete_opcode) + s.append("missing_bits=%s" % info.missing_bits) + s.append("has_modrm='%s'" % info.has_modrm) + s.append("imm_nt_seq=%s" % info.imm_nt_seq) + s.append("disp_nt_seq=%s" % info.disp_nt_seq) + s.append("eosz_nt_seq=%s" % info.eosz_nt_seq) + s.append("easz_nt_seq=%s" % info.easz_nt_seq) + s.append("ext_opcode=%s" % info.ext_opcode) + s.append("mode=%s" % info.mode) + s.append("priority=%s" % ild_info.storage_priority) + f.write((",\n%s" % (indent + tab)).join(s) + "))\n\n") + + + +#this is for debugging mostly. Also a good source of info on instruction set. +def dump_patterns(patterns, fname): + f = open(fname, 'w') + for pattern in patterns: + f.write( '%s\n' % pattern) + f.close() + +########################################################################### +## +########################################################################### + + + +#Maybe pattern_t should inherit from instruction_info_t +#Let it inherit from object for now. +class pattern_t(object): + + # keys will be in a special order which is why we build it + # from a list. + phys_map_keys = [] + phys_map_dir = {} + first = True + + def __init__(self, ii, is_3dnow, eosz_nts, + easz_nts, imm_nts, disp_nts, brdisp_nts, mode_space, + state_space): + + # FIXME 2012-06-19 MJC: is there a better way to do complex + # init of class attributes? + if pattern_t.first: + pattern_t.first = False + self._setup_phys_map(is_3dnow) + + self.ptrn = ii.ipattern_input + self.ptrn_wrds = self.ptrn.split() + self.iclass = ii.iclass + self.legal = True + + #amd 3dnow instructions have nasty 0f 0f ... opcode pattern + #in which second 0f is not an opcode! This should be treated + #in a special way + self.amd3dnow_build = is_3dnow #this one is NOT used DELETE IT ??? + + self.category = ii.category + #FIXME: remove all members of ii stored directly as members + self.ii = ii + + #incomplete_opcode is used for expanding opcodes that have registers + #embedded in them + self.incomplete_opcode = False + + #number of missing bits in incomplete opcode. usually 0 or 3 + self.missing_bits = 0 + + self.insn_map = None + self.opcode = None + + self.space = None # LEGACY|VEX|EVEX + self.has_modrm = False + + self.imm_nt_seq = None + + self.disp_nt_seq = None + + #modrm.reg bits value, set only when it is explicitly + #e.g. bounded: REG[010] + self.ext_opcode = None + + #all legal values for MODE operand in this pattern + self.mode = None + + + #an ordered string of EOSZ setting NTs in the pattern + #we will use it to create the eosz lookup table for the pattern + self.eosz_nt_seq = None + + + #same for EASZ + self.easz_nt_seq = None + + #operand deciders of the pattern + #FIXME: not finished yet + self.constraints = collections.defaultdict(dict) + + + insn_map,opcode = self.get_map_opcode() + self.insn_map = insn_map + self.opcode = opcode + + self.has_modrm = ild_modrm.get_hasmodrm(self.ptrn) + self.set_ext_opcode() + + self.set_mode(ii, mode_space) + + + self.eosz_nt_seq = ild_eosz.get_eosz_nt_seq(self.ptrn_wrds, + eosz_nts) + + self.easz_nt_seq = ild_easz.get_easz_nt_seq(self.ptrn_wrds, + easz_nts) + + self.imm_nt_seq = ild_imm.get_imm_nt_seq(self.ptrn_wrds, imm_nts) + + self.disp_nt_seq = ild_disp.get_disp_nt_seq(self.ptrn_wrds, + disp_nts.union(brdisp_nts)) + + self.set_constraints(ii, state_space) + self.actions = [actions.gen_return_action(ii.inum)] + + #Not implementing this yet. + #Will implement after code review for has_modrm + #self.set_hasimm() + #self.set_pfx_table() + + #FIXME: for anaisys only + if self.is_3dnow(): + if not self.has_modrm: + _msg('3DNOW with no MODRM: %s\n' % self) + + def is_3dnow(self): + return self.category == _xed_3dnow_category + + def is_legal(self): + return (self.legal and + self.opcode != None and + self.insn_map != None and + self.space != None) + + + def set_ext_opcode(self): + #inline captures MOD[mm] REG[rrr] RM[nnn] + #or REG[111] etc. -- can be constant + for w in self.ptrn_wrds: + pb = reg_binding_pattern.match(w) + if pb: + bits = pb.group('bits') + self.ext_opcode = genutil.make_numeric(bits) + return + + def set_constraints(self, ii, state_space): + #FIXME: this assumes, that there are no contradictions + #between constraints on the same operand. + #If there are, e.g. MOD=3 ... MOD=1, both values will be + #set as legal.. check such things here? + + #set constraints that come from operands deciders + xed3_nt.get_ii_constraints(ii, state_space, self.constraints) + #print "CONSTRAINTS: {}".format(self.constraints) + + #special care for VEXVALID - it makes it easy to dispatch + #vex and legacy instructions: + #for legacy we will explicitly set VEXVALID=0 + if _vexvalid_op not in self.constraints: + self.constraints[_vexvalid_op] = {0:True} + + def set_mode(self, ii, mode_space): + for bit_info in ii.ipattern.bits: + if bit_info.token == _mode_token: + #self.refining = [111555] + if bit_info.test == 'eq': + self.mode = [bit_info.requirement] + else: + mod_space = copy.deepcopy(mode_space) + mod_space.remove(bit_info.requirement) + self.mode = mod_space + return + #FIXME: when MODE is not mentioned, we assume that any value is + #legal, it should not mess the conflict resolution. + #But maybe None is better + self.mode = ildutil.mode_space + + def parse_opcode(self, op_str): + val = None + if genutil.numeric(op_str): + val = genutil.make_numeric(op_str) + + # special check for partial binary numbers as opcodes + if genutil.is_binary(op_str): + bin_str = re.sub('^0b', '', op_str) + bin_str = re.sub('_', '', bin_str) + #if it is bin string, it might be incomplete, and we + #assume that given bits are msb. Hence we have to + #shift left + + if len(bin_str) > 8: + ildutil.ild_err("Unexpectedly long binary opcode: %s" % + bin_str) + + if len(bin_str) < 8: + self.missing_bits = 8-len(bin_str) + val = val << (self.missing_bits) + self.incomplete_opcode = True + _msg('incomplete opcode for iclass %s, pttrn %s' % + (self.iclass, self.ptrn)) + + return val + + def err(self, msg): + self.legal = False + sys.stderr.write("ILD_PARSER PATTERN ERROR: %s\n\nPattern:\n%s\n" % + (msg, self)) + mbuild.msgb("ILD_PARSER ERROR", msg) + mbuild.msgb("ILD_PARSER", "ABORTED ILD generation") + #sys.exit(1) + + #if opcode is incomplete, than we have 0's in all the missing bits and + #need to create copies of the pattern_t that have all other possible + #variations of the opcode. For example PUSH instruction has opcode 0x50 + #and in expand_opcode method we will create a list of pattern_t objects + #that have opcodes 0x51-0x57 + #We don't need to create the 0x50 variant, because it already exists + #(it is the current self) + #That way we will cover all the legal opcodes for the given incomplete + #opcode. + def expand_opcode(self): + expanded = [] + if self.incomplete_opcode: + if 'RM[rrr]' in self.ptrn or 'REG[rrr]' in self.ptrn: + _msg('Expanding opcode for %s' % self.iclass) + #FIXME: MJC: was assuming hex for self.opcode (2012-06-19) + opcode = genutil.make_numeric(self.opcode) + #iterating through all legal variations of the incomplete + #opcode. + #Since the variant with all missing bits == 0 was already + #created (it is the current self), we need to iterate through + #1 to 2 ^ (self.missing_bits) + for i in range(1, 2**self.missing_bits): + new_ptrn = copy.deepcopy(self) + new_ptrn.opcode = hex(opcode | i) + expanded.append(new_ptrn) + return expanded + + def get_opcode(self, tokens): + opcode = None + for token in tokens: + opcode = self.parse_opcode(token) + if opcode != None: + break + if opcode == None: + ildutil.ild_err("Failed to parse op_str with " + + "from tokens %s" %( tokens)) + return hex(opcode) + + def _setup_phys_map(self,include_amd): + phys_map_list = [ + ('0x0F 0x38','0x0F38'), + ('0x0F 0x3A','0x0F3A'), + ('V0F38','0x0F38'), + ('V0F3A','0x0F3A'), + # V0F must be after the V0F38 & V0F3A + ('V0F','0x0F'), + ('MAP5','MAP5'), + ('MAP6','MAP6') ] + + # The AMD map must be before the naked 0x0F map + if include_amd: + phys_map_list.append(('0x0F 0x0F','0x0F0F')) + phys_map_list.append(('XMAP8','XMAP8')) + phys_map_list.append(('XMAP9','XMAP9')) + phys_map_list.append(('XMAPA','XMAPA')) + + # and finally Map 1 ... + phys_map_list.append(('0x0F','0x0F')) + + # keys will be in a special order which is why we build it + # from a list. + pattern_t.phys_map_keys = [] + pattern_t.phys_map_dir = {} + + for a,b in phys_map_list: + pattern_t.phys_map_keys.append(a) + pattern_t.phys_map_dir[a] = b + + def get_map_opcode(self): + insn_map = '0x0' + s = self.ptrn + for mpat in pattern_t.phys_map_keys: + if s.find(mpat) != -1: + insn_map = pattern_t.phys_map_dir[mpat] + # remove the first matching map-like thing + s = re.sub(mpat,'',s, count=1) + break + + tokens = s.split() + opcode = self.get_opcode(tokens) + return insn_map, opcode + + def has_emit_action(self): + ''' This function is needed in order to match the interface of rule_t + it has no real meaning for the docoder ''' + return False + + def __str__(self): + printed_members = [] + printed_members.append('ICLASS\t: %s' % self.iclass) + printed_members.append('PATTERN\t: %s' % self.ptrn) + #putting map and opcode in one line for easier grepping + #of the pattern list dump - very handy for different kinds of analysis + printed_members.append('MAP:%s OPCODE:%s' % + (self.insn_map, self.opcode)) + printed_members.append('EXT_OPCODE\t: %s' % self.ext_opcode) + printed_members.append('MODE\t: %s' % self.mode) + printed_members.append('INCOMPLETE_OPCODE\t: %s' % + self.incomplete_opcode) + printed_members.append('HAS_MODRM\t: %s' % self.has_modrm) + printed_members.append('EOSZ_SEQ:\t %s' % self.eosz_nt_seq) + printed_members.append('EASZ_SEQ:\t %s' % self.easz_nt_seq) + printed_members.append('IMM_SEQ\t: %s' % self.imm_nt_seq) + printed_members.append('DISP_SEQ\t: %s' % self.disp_nt_seq) + printed_members.append('CONSTRAINTS\t: %s' % self.constraints) + printed_members.append('INUM\t: %s' % self.ii.inum) + + return "{\n"+ ",\n".join(printed_members) + "\n}" + + def __eq__(self, other): + return (other != None and + self.ptrn == other.ptrn and + self.iclass == other.iclass) + + def __ne__(self, other): + return (other == None or + self.ptrn != other.ptrn or + self.iclass != other.iclass) + +def _msg(s): + debug.write("%s\n" % (s)) + diff --git a/pysrc/ild_cdict.py b/pysrc/ild_cdict.py new file mode 100755 index 0000000..56d3053 --- /dev/null +++ b/pysrc/ild_cdict.py @@ -0,0 +1,738 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import genutil +import ildutil +import ild_info +import collections +import opnds +import math +import ild_phash +import ild_codegen +import ild_phash +import ild_eosz +import ild_easz +import ild_nt +import genutil +import actions_codegen +import actions +import copy +import verbosity +import tup2int + +# _token_2_module is for fields that might be modified in the pattern. +# if fields are modified in the pattern by some NT, then we must be +# consistent across buckets (legacy/vex/evex, opcode,map). This is +# only relevant for fields that would be used in the "dynamic decode +# part 1". + +# EASZ is only rarely modified in experimental extensions. +_token_2_module = {'EOSZ':ild_eosz, 'EASZ':ild_easz} + +_find_fn_pfx = 'xed3_phash_find' + +def _log(f,s): + if verbosity.vild(): + f.write(s) + +def _set_state_space_from_ii(agi, ii, state_space): + """ + state_space is a 2D dictionary, ii is generator.instruction_info_t + this functions sets: + state_space[OPNAME][OPVAL] = True for every operand decider or prebinding + with name OPNAME and value OPVAL legal for the given ii. + """ + for bt in ii.ipattern.bits: + if bt.is_operand_decider(): + if bt.test == 'eq': + state_space[bt.token][bt.requirement] = True + #look at prebindings too + #for things like ZEROING that don't have all possible + #values mentioned in patterns + for (name, binding) in ii.prebindings.items(): + + bitnum = len(binding.bit_info_list) + #dirty hack: we don't want big prebidnings to explode + #our dictionaries + #FIXME: this assumes that all constraints used for + #pattern dispatching (all constraints explicitly mentioned + #in patterns) have bit widths up to 3 bits. + #This is true now, but might change later. Should put an + #assertion somewhere. + #Also better to use a genutil.max_constraint_bitwidth than + #3. + if bitnum < 4: + if not name in state_space: + state_space[name] = {} + for val in range(0, 2**bitnum): + state_space[name][val] = True + elif binding.is_constant(): + val = int(binding.get_value(), 2) + state_space[name][val] = True + +def _set_space_from_operands(agi, operands, state_space): + state_dict = agi.common.state_bits + for op in operands: + ops = [] + #if binding operand is a macro + if op.name.lower() in state_dict: + op_spec = state_dict[op.name.lower()].list_of_str + found_op = False + for w in op_spec: + exapnded_op = opnds.parse_one_operand(w) + ops.append(exapnded_op) + else: + ops.append(op) + + for op in ops: + if (op.bits and op.name in state_space and + op.type == 'imm_const'): + op_val = int(op.bits, 16) + state_space[op.name][op_val] = True + +def get_all_constraints_state_space(agi): + """ + Returns a 2D dictionary state_space: + state_space[OPNAME][OPVAL] == True if there is an operand with + name OPNAME and value OPVAL. + In other words dictionary contains all legal values for + operands in grammar. + Only operands that appear as operand deciders, prebindings, or + instruction operands are added to the returned dictionary. + """ + state_space = collections.defaultdict(dict) + for g in agi.generator_list: + for ii in g.parser_output.instructions: + _set_state_space_from_ii(agi, ii, state_space) + #set state_space from operands + #These are NTs partition tables right parts + for g in agi.generator_list: + ii = g.parser_output.instructions[0] + if genutil.field_check(ii,'iclass'): + continue #only real NTs, not instructions + for ii in g.parser_output.instructions: + _set_space_from_operands(agi, ii.operands, state_space) + + # in some configurations xed can be build without any AVX + # instructions, in this case the operand VEXVALID will no be added. + # the ild relies on this operand so we add it manually + if 'VEXVALID' not in state_space: + state_space['VEXVALID'][0] = True + else: # KNC/AVX/EVEX builds... + # 2014-10-10: when I got rid of the NTs for decoding the + # VEX/EVEX/XOP prefixes, I ended up losing the only NTs that + # mention ZEROING=1 and VLBAD (VL=3). So we add them here. + # They are required for proper splattering of don't care + # cases. in the hash function generation. For example when, + # EVEX.RC is rounding control and co-opting the EVEX.LL field, + # we need to have the value of VL=3 because it is not + # "corrected" when we are still picking an instruction (aka + # 'static decode'). + state_space['ZEROING'][1] = True + state_space['VL'][3] = True + + return state_space + +def get_state_op_widths(agi, state_space): + """ + Returns a dictionary from operand name to operands bit width + """ + widths_dict = {} + for opname,val_dict in state_space.items(): + if opname in agi.operand_storage.get_operands(): + opnd = agi.operand_storage.get_operand(opname) + widths_dict[opname] = int(opnd.bitwidth) + continue + maxval = max(val_dict.keys()) + if maxval == 0: + #log doesn't work on 0 so well + width = 1 + else: + width = int(math.floor(math.log(maxval, 2))) + 1 + widths_dict[opname] = width + #Special, "compressed" operands + #FIXME: we can add these special operands widths in grammar + widths_dict[_bin_MOD3] = 1 + widths_dict[_vd_token_7] = 1 + widths_dict[_rm_token_4] = 1 + widths_dict[_mask_token_n0] = 1 + widths_dict[_mask_token_zero] = 1 + #constraints on uimm0 operands are 8 bits width max + widths_dict['UIMM0'] = 8 + return widths_dict + +#Following functions are for operands compressing + +_bin_MOD3 = 'MOD3' +#FIXME: could have made a generic function is_binary_op_X +#but it seems to be an overkill - most common binary ops are MOD +#and RM +def _is_binary_MOD3(ptrn_list): + mod3_eq = 'MOD=3' + mod3_neq = 'MOD!=3' + for ptrn in ptrn_list: + if not (mod3_eq in ptrn.ptrn or mod3_neq in ptrn.ptrn): + return False + return True + +def _replace_MOD_with_MOD3(cnames, ptrn_list): + cnames.remove('MOD') + cnames.add(_bin_MOD3) + for ptrn in ptrn_list: + if 'MOD=3' in ptrn.ptrn: + ptrn.constraints[_bin_MOD3] = {1: True} + else: + ptrn.constraints[_bin_MOD3] = {0: True} + +_vd_token = 'VEXDEST210' +_vd_token_7 = 'VEXDEST210_7' +#FIXME: too hardcoded +#this one is different: there are two possibilities: VD=7 and VD in [0..7] +#hence VD7=1 will mean VD=7 and {VD7=0, VD7=0} will mean VD is any value +# +def _is_binary_VEXDEST210_7(cnames, ptrn_list): + found = False + if _vd_token not in cnames: + return False + for ptrn in ptrn_list: + cvals = ptrn.constraints[_vd_token] + if (len(cvals) == 1 and 7 in cvals): + found = True + elif (len(cvals) != 0): + return False + return found + +def _replace_VEXDEST210_with_VD2107(cnames, ptrn_list): + cnames.remove(_vd_token) + cnames.add(_vd_token_7) + for ptrn in ptrn_list: + found = False + for bt in ptrn.ii.ipattern.bits: + if bt.token == _vd_token: + if bt.test == 'eq': + found = True + ptrn.constraints[_vd_token_7] = {1:True} + break + if not found: + #vd7==0 says any VD + ptrn.constraints[_vd_token_7] = {0:True, 1:True} + +_rm_token = 'RM' +_rm_token_4 = 'RM4' +#FIXME: make one function for RM4 and VD7 +def _is_binary_RM_4(cnames, ptrn_list): + found = False + if _rm_token not in cnames: + return False + for ptrn in ptrn_list: + cvals = ptrn.constraints[_rm_token] + if (len(cvals)==1) and 4 in cvals : + found = True + elif len(cvals) != 0: + return False + else: #len(cvals)==0 + ptrn.constraints.pop(_rm_token) + return found + +def _replace_RM_with_RM4(cnames, ptrn_list): + # This looks for RM=4 in the pattern. It will not find "RM[0b100]" + # so the patterns should NOT use that for specifying RM=4 + # requirements. + # + # FIXME:2016-01-29: MJC I have a concern that other instructions + # with RM[...] constraints might be being mishandled. Need to test. + cnames.remove(_rm_token) + cnames.add(_rm_token_4) + for ptrn in ptrn_list: + found = False + #print "PATTERN BITS", "\t\n".join(map(str,ptrn.ii.ipattern.bits)) + for bt in ptrn.ii.ipattern.bits: + if bt.token == _rm_token: + if bt.test == 'eq': + found = True + ptrn.constraints[_rm_token_4] = {1:True} + break + if not found: + #print "X", str(cnames) + #print "\t\n".join(map(str,ptrn_list)) + ptrn.constraints[_rm_token_4] = {0:True, 1:True} + +#FIXME: probably should move this one to layers +_mask_token = 'MASK' +_mask_token_n0 = 'MASK_NOT0' +_mask_token_zero = 'MASK_ZERO' +#FIXME: make one function for is binary and replace_binary +def _is_binary_MASK_NOT0(cnames, ptrn_list): + found = False + if _mask_token not in cnames: + return False + for ptrn in ptrn_list: + cvals = ptrn.constraints[_mask_token] + # 7 of the 8 possible mask values without 0 + if (len(cvals)==7) and 0 not in cvals : + found = True + elif len(cvals)==0: #no constraint values -> any mask is ok + ptrn.constraints.pop(_mask_token) + else: + return False + return found + +def _is_binary_MASK_ZERO(cnames, ptrn_list): + found = False + if _mask_token not in cnames: + return False + for ptrn in ptrn_list: + cvals = ptrn.constraints[_mask_token] + if (len(cvals)==1) and 0 in cvals : + found = True + elif len(cvals)==0: #any mask, ok + ptrn.constraints.pop(_mask_token) + else: + return False + return found + + +def _replace_MASK_with_MASK_NOT0(cnames, ptrn_list): + cnames.remove(_mask_token) + cnames.add(_mask_token_n0) + for ptrn in ptrn_list: + found = False + for bt in ptrn.ii.ipattern.bits: + if bt.token == _mask_token: + if bt.test == 'ne': + found = True + ptrn.constraints[_mask_token_n0] = {1:True} + break + if not found: + #mask is not in the pattern, all values of MASK_NOT0 are valid + ptrn.constraints[_mask_token_n0] = {0:True, 1:True} + + + +def _replace_MASK_with_MASK_ZERO(cnames, ptrn_list): + cnames.remove(_mask_token) + cnames.add(_mask_token_zero) + for ptrn in ptrn_list: + found = False + for bt in ptrn.ii.ipattern.bits: + if bt.token == _mask_token: + if bt.test == 'eq': + found = True + ptrn.constraints[_mask_token_zero] = {1:True} + break + if not found: + #mask is not in the pattern, all values of MASK_ZERO are valid + ptrn.constraints[_mask_token_zero] = {0:True, 1:True} + +_compressed_ops = [_mask_token_n0, + _mask_token_zero, + _rm_token_4, + _vd_token_7, + _bin_MOD3 ] + +def is_compressed_op(opname): + """ + Compressed operands are special - we do not capture them + in ILD and do not derive them in NTs. (though we could.. + FIXME: is it worthy?), hence in order to get their value we can not + use regular xed3_operand_get_* function - we use special getters + for them. + is_compressed_op(opname) helps us to determine whether we need to use a + special getter. + """ + return opname in _compressed_ops + +def get_compressed_op_getter_fn(opname): + """ + Compressed operands are special - we do not capture them + in ILD and do not derive them in NTs. (though we could.. + FIXME: is it worthy?), hence in order to get their value we can not + use regular xed3_operand_get_* function - we use special getters + for them. + get_compressed_op_getter_fn(opname) returns a name of the special getter + for a given compressed operand name. + FIXME: right now we just use the same operand naming scheme as for + regular operands. Do we need this function? + """ + return operand_storage.get_op_getter_fn(opname) + +def _get_united_cdict(ptrn_list, state_space, vexvalid, all_ops_widths): + """ + @param ptrn_list: list of ild.pattern_t + @param state_space: all legal values for xed operands: + state_space['REXW'][1] = True, + state_space['REXW'][0]=True + @param vexvalid: VEXVALID value we want to filter by. vevxavlid==0 + will include only patterns with vexvalid==0 constraint + value. + @param all_ops_widths: dict of operands to their bit widths. + @return ild_cdict.constrant_dict_t which unites patterns constraint dicts + """ + cnames = [] + + #take only requested space patterns + ptrns = [] + for ptrn in ptrn_list: + if vexvalid in ptrn.constraints['VEXVALID'].keys(): + ptrns.append(ptrn) + + if len(ptrns) == 0: + return None + + for ptrn in ptrns: + cnames.extend(ptrn.constraints.keys()) + cnames = set(cnames) + + cdicts = [] + if _is_binary_MOD3(ptrns): + _replace_MOD_with_MOD3(cnames, ptrns) + + if _is_binary_VEXDEST210_7(cnames, ptrn_list): + _replace_VEXDEST210_with_VD2107(cnames, ptrn_list) + + if _is_binary_RM_4(cnames, ptrn_list): + _replace_RM_with_RM4(cnames, ptrn_list) + + if _is_binary_MASK_NOT0(cnames, ptrn_list): + _replace_MASK_with_MASK_NOT0(cnames, ptrn_list) + + if _is_binary_MASK_ZERO(cnames, ptrn_list): + _replace_MASK_with_MASK_ZERO(cnames, ptrn_list) + + # For each pattern we have a list of constraints. ptrn.constraints + # is the legal values for those constraints. In each map opcode + # bin, we have several patterns with different constraints. We + # want to make one hash table for these different patterns. Thats + # why we want to take the union of all the constraints and make + # one dictionary (and ultimately a hash table). Need to add all + # legal variations of all constraints, cross product. (dangerous) + #For example if we have two patterns: + #PATTERN1: MOD=1 + #PATTERN2: REG=2 + #then for PATTERN1 we will create a constraint dictionary with all + #combinations (MOD=1 REG=0), (MOD=1, REG=1) ,..., (MOD=1, REG=7) + #and for PATTERN2 we will have (MOD=0 REG=2), (MOD=1 REG=2), ... + for ptrn in ptrns: + cdict = constraint_dict_t(cnames, ptrn.constraints, state_space, ptrn) + cdicts.append(cdict) + insn_map = ptrns[0].insn_map + opcode = ptrns[0].opcode + msg = [] + msg.append("cdict conflict in pattern") + msg.append('MAP:%s OPCODE:%s\n' % (insn_map, opcode)) + msg = "\n".join(msg) + # now we unite (cross-product) after exploding/back-filling all the + # constraints. All patterns now have same constraints. + united_dict = constraint_dict_t.unite_dicts(cdicts, msg, cnames) + + #generate the int value for each tuple + united_dict.create_tuple2int(all_ops_widths) + united_dict.strings_dict = ild_codegen._dec_strings + + #creating the default action that will be taken when we did not hit + #a valid hash entry + default_action = [actions.gen_return_action('0')] + united_dict.action_codegen = actions_codegen.actions_codegen_t( + united_dict.tuple2rule, + default_action, + united_dict.strings_dict) + return united_dict + + + +#FIXME: maybe it should contain tuple2int function? +#Now tuple2int is a part of phash object. +class constraint_dict_t(object): + def __init__(self, cnames=[], state_space={}, all_state_space={}, + rule=None): + #cnames is sorted list of strings - constraints' names that we want + #this cdict to have + self.cnames = sorted(list(cnames)) + + #state_space is a dict with constraints' values we want + #this cdict to represent. + #For example if we want cdict to allow only MODE=0 we will + #have state_space['MODE'][0] = True + self.state_space = state_space + + #all_state_space is a dict with all legal values that constraints + #have in grammar. + #For example: + #all_state_space['REXW'][0]=True, all_state_space['REXW'][1]=True + #It is used when state_space doesn't have a constraint from cnames. + #We need this when we build united constraint dict for a set of + #patterns: + #first we build a separate constraint dict for each pattern, but + #it includes all the cnames that set has, and then we unite those + #cdicts. See _get_united_cdict() function + self.all_state_space = all_state_space + + self.rule = rule + + #dict mapping tuples to rules. + #tuples are the constraint values (without the constraint names). + self.tuple2rule = {} + + #tuple2int maps the same tuples as tuple2int to hash key values. + self.tuple2int = {} + + #reverse mapping from hash key to list of constraint value tuples. + self.int2tuple = {} + + #dict of all operands -> bit width. + self.op_widths = {} + + if len(state_space) > 0: + self.tuple2rule = self.make_cdict(self.cnames, {}) + + @staticmethod + def unite_dicts(dict_list, err_msg, cnstr_names): + """ dict_list is a list of constraint dictionaries. The keys + in the dictionary are the values of the constraints as tuples. + If we see the same values in more than one pattern, we have a + decoding conflict in the grammar. The dictionaries have been + expanded so that they all have the same constraint names upon + entry. + """ + + if len(dict_list) == 0: + return None + if len(dict_list) == 1: + return dict_list[0] + res = constraint_dict_t(cnames=cnstr_names) + for cdict in dict_list: + for key in cdict.tuple2rule.keys(): + if key in res.tuple2rule: + msg = [] + msg.append("key: %s" % (key,)) + msg.append("cdict:%s" % cdict) + msg.append("res:%s" % res) + msg = "\n".join(msg) + ildutil.ild_err(err_msg + msg) + return None + else: + res.tuple2rule[key] = cdict.tuple2rule[key] + + return res + + + def make_cdict(self, cnames, tuple2rule): + if len(cnames) == 0: + return tuple2rule + name = cnames[0] + if name in self.state_space: + vals = sorted(self.state_space[name].keys()) + else: + vals = sorted(self.all_state_space[name].keys()) + if len(tuple2rule) == 0: + #initialize tuple2rule with singleton tuples + for val in vals: + tuple2rule[(val,)] = self.rule + return self.make_cdict(cnames[1:], tuple2rule) + else: + new_tuple2rule = {} + for key_tuple in tuple2rule.keys(): + for val in vals: + new_key = key_tuple + (val,) + new_tuple2rule[new_key] = self.rule + return self.make_cdict(cnames[1:], new_tuple2rule) + + def get_all_keys_by_val(self, val): + return [k for k,v in self.tuple2rule.iteritems() if v == val] + + def create_tuple2int(self, all_ops_widths): + ''' create the mapping of tuple to its int value ''' + tuple2int = {} + int2tuple = {} + for t in self.tuple2rule.iterkeys(): + res = tup2int.tuple2int(t, self.cnames, all_ops_widths) + if res in int2tuple: + err = "the tuple % and the tuple %s generate the same value:%d" + die(err % (t,str(int2tuple[res]),res)) + else: + tuple2int[t] = res + int2tuple[res] = t + + #later using the op_widths for the code generation + self.op_widths = all_ops_widths + self.tuple2int = tuple2int + self.int2tuple = int2tuple + + def get_ptrn(self, tuple): + ''' return the pattern that represents the given tuple ''' + return self.tuple2rule[tuple].ptrn + + def filter_tuples(self,tuples): + ''' from all the dictionaries in self, remove the tuples that are not + in the input tuples list. + return new instance of cdict ''' + + new_cdict = copy.copy(self) + new_cdict.tuple2int = {} + new_cdict.tuple2rule = {} + for t in tuples: + new_cdict.tuple2int[t] = self.tuple2int[t] + new_cdict.tuple2rule[t] = self.tuple2rule[t] + + + new_cdict.int2tuple = dict((i,t) for t,i in + new_cdict.tuple2int.iteritems()) + + return new_cdict + + def get_operand_accessor(self, cname): + ''' return a tuple of the operand accessor function and the constraint + names that it represents ''' + + ptrn_list = self.tuple2rule.values() + if cname in _token_2_module.keys(): + nt_module = _token_2_module[cname] + getter_fn = nt_module.get_getter_fn(ptrn_list) + if not getter_fn: + msg = 'Failed to resolve %s getter fn for ' + msg += 'MAP:%s OPCODE:%s' + insn_map = ptrn_list[0].insn_map + opcode = ptrn_list[0].opcode + ildutil.ild_err(msg % (cname, insn_map, opcode)) + access_str = '%s(%s)' % (getter_fn, self.strings_dict['obj_str']) + nt = ild_nt.get_nt_from_lufname(getter_fn) + return access_str, nt + else: + access_str = ild_codegen.emit_ild_access_call(cname, + self.strings_dict['obj_str']) + return access_str, cname + + def __str__(self): + rows = [] + size = len(self.tuple2rule) + rows.append("cdict_size=%d" % size) + if size >= 100: + rows.append('HUGE!') + elif size >= 50: + rows.append('BIG!') + legend = " ".join(self.cnames) + legend += ' \t-> VALUE' + rows.append(legend) + if len(self.tuple2rule) == 0: + rows.append("_ \t-> %s" % self.rule) + for key in sorted(self.tuple2rule.keys()): + val = self.tuple2rule[key] + rows.append("%s \t-> %s" % (key, str(val))) + return "\n".join(rows) + + + +def get_constraints_lu_table(ptrns_by_map_opcode, is_amd, state_space, + vexvalid, all_ops_widths): + """ + returns a tuple (cdict_by_map_opcode,cnames) + cnames is a set of all constraint names used in patterns. + cdict_by_map_opcode is a traditional 2D lookup dict from map,opcode to + constraint_dict_t objects that represent the mapping from constraints + values to different patterns of the corresponding (map,opcode,vexvalid) + bin. These cdict objects can later be used for generating hash functions + from constraint values to patterns (inums). + """ + maps = ild_info.get_maps(is_amd) + cdict_by_map_opcode = collections.defaultdict(dict) + cnames = set() + for insn_map in maps: + for opcode in range(0, 256): + opcode = hex(opcode) + ptrns = ptrns_by_map_opcode[insn_map][opcode] + cdict = _get_united_cdict(ptrns, state_space, vexvalid, + all_ops_widths) + cdict_by_map_opcode[insn_map][opcode] = cdict + if cdict: + cnames = cnames.union(set(cdict.cnames)) + return cdict_by_map_opcode,cnames + +def gen_ph_fos(agi, cdict_by_map_opcode, is_amd, log_fn, + ptrn_dict, vv): + """ + Returns a tuple (phash_lu_table,phash_fo_list,op_lu_list) + phash_lu_table is a traditional 2D dict by map, opcode to a + hash function name. + phash_fo_list is a list of all phash function objects created + (we might have fos that are not in lookup table - when we have + 2-level hash functions). + op_lu_list is a list for all the operands lookup functions + Also writes log file for debugging. + """ + maps = ild_info.get_maps(is_amd) + log_f = open(log_fn, 'w') + cnames = set() + stats = { + '0. #map-opcodes': 0, + '1. #entries': 0, + '2. #hentries': 0, + '3. #hashes': 0, + '4. #min_hashes': 0, + '5. #cdict_size_1_to_10': 0, + '6. #cdict_size_10_to_20': 0, + '7. #cdict_size_20_to_100': 0, + '8. #cdict_size_at_least_100': 0 + }## + lu_fo_list = [] + op_lu_map = {} + phash_lu = {} + for insn_map in maps: + phash_lu [insn_map] = {} + for opcode in range(0, 256): + opcode = hex(opcode) + cdict = cdict_by_map_opcode[insn_map][opcode] + if cdict: + stats['0. #map-opcodes'] += 1 + stats['1. #entries'] += len(cdict.tuple2rule) + cnames = cnames.union(set(cdict.cnames)) + _log(log_f,'MAP:%s OPCODE:%s:\n%s\n' % (insn_map, opcode, + cdict)) + + phash = ild_phash.gen_hash(cdict) + if phash: + _log(log_f,"%s" % phash) + phash_id = 'map%s_opcode%s_vv%d' % (insn_map, opcode, + vv) + fname = "%s_%s" % (_find_fn_pfx,phash_id) + (fo_list,op_lu_fo) = phash.gen_find_fos(fname) + lu_fo_list.extend(fo_list) + + #hold only one instance of each function + if op_lu_fo.function_name not in op_lu_map: + op_lu_map[op_lu_fo.function_name] = op_lu_fo + for fo in fo_list: + _log(log_f,'//find function:\n') + _log(log_f,fo.emit()) + _log(log_f,'-----------------------------\n') + #FIXME: assumption: L2 function is last in the list + #maybe return dict or tuple to make a distinction between + #L2 and L1 functions? + phlu_fn = lu_fo_list[-1] + phash_lu[insn_map][opcode] = phlu_fn.function_name + phash.update_stats(stats) + else: + _log(log_f,'---NOPHASH-----\n') + msg = "Failed to gen phash for map %s opcode %s" + ildutil.ild_err(msg % (insn_map, opcode)) + else: + phash_lu[insn_map][opcode] = '(xed3_find_func_t)0' + _log(log_f,"cnames: %s\n" %cnames) + for key in sorted(stats.keys()): + _log(log_f,"%s %s\n" % (key,stats[key])) + log_f.close() + return phash_lu,lu_fo_list,op_lu_map.values() + diff --git a/pysrc/ild_codegen.py b/pysrc/ild_codegen.py new file mode 100755 index 0000000..ee5c59f --- /dev/null +++ b/pysrc/ild_codegen.py @@ -0,0 +1,709 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import ild_nt +import genutil +import ildutil +import codegen +import mbuild +import ild_info +import operand_storage +import os + +_arg_const_suffix = 'CONST' + +_dec_strings = {'obj_str':'d', + 'obj_type':'xed_decoded_inst_t', + 'obj_const': 'const ', + 'lu_namespace':'dec', + 'static':True + } +_dec_strings.update(ildutil.xed_strings) + +def get_derived_op_getter_fn(op_nts, opname): + return ild_nt.get_lufn(op_nts, opname) + '_getter' + +def get_l2_fn(target_nt_names, target_opname, arg_nts, arg_name, + empty_seq_name, is_const): + """Generate L2 function name from IMM NT names list and EOSZ NT names list. + + Each L2 function is defined by a single PATTERN row in xed's grammar. + (By pattern's IMM-binding and EOSZ-binding NTs) + Hence, it is enough to know the IMM NTs sequence and EOSZ NTs sequence to + define a L2 function. Or in this case to define a L2 function name. + + ATTENTION: as we decided to hardcode special AMD's double immediate + instruction's L1 functions, the length of imm_nt_names can be ONLY 1 + + @param imm_nt_names: list of IMM-binding NT names + @param eosz_nt_names: list of EOSZ-binding NT names + + @return: L2 function name + + """ + #if there are no target NTs in pattern, then L2 function is + #the default function for empty sequences + #(return 0 for immediates and return; for disp) + if len(target_nt_names) == 0: + return empty_seq_name + + #currently there are no supported target NT sequences that have more + #than 1 NT. Check that. + if len(target_nt_names) > 1: + ildutil.ild_err("Cannot generate L2 function name for NT seq %s" % + target_nt_names) + + if is_const: + arg_suffix = _arg_const_suffix + else: + arg_suffix = "_".join(arg_nts + [arg_name]) + #L2 function name is a concatenation of L3 function name and possible + #argument(e.g EOSZ or EASZ) NT names + l3_prefix = ild_nt.get_lufn(target_nt_names, target_opname) + return l3_prefix + '_%s_l2' % arg_suffix + + +#generate L2 function that doesn't depend on arguments +def gen_const_l2_function(agi, nt_name, target_opname, ild_t_member): + return_type = 'void' + l3_fn = ild_nt.get_lufn([nt_name], target_opname, flevel='l3') + l2_fn = get_l2_fn([nt_name], target_opname, [], None, + None, True) + + fo = codegen.function_object_t(l2_fn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + + temp_var = '_%s' % ild_t_member + ctype = ildutil.ild_c_op_type + fo.add_code_eol('%s %s' % (ctype, temp_var)) + + fcall = l3_fn + '()' + fo.add_code_eol('%s = (%s)%s' % (temp_var, ctype, fcall)) + setter_fn = operand_storage.get_op_setter_fn(ild_t_member) + fo.add_code_eol('%s(%s, %s)' % (setter_fn, data_name,temp_var)) + return fo + +def gen_derived_operand_getter(agi, opname, op_arr, op_nt_names): + return_type = agi.operand_storage.get_ctype(opname) + + op_lufn = ild_nt.get_lufn(op_nt_names, opname) + getter_fn = get_derived_op_getter_fn(op_nt_names, opname) + + fo = codegen.function_object_t(getter_fn, return_type, static=True, + inline=True) + data_name = 'x' + fo.add_arg('const ' +ildutil.ild_c_type + ' %s' % data_name) + + for range_tuple in op_arr.ranges: + range_type, range_min, range_max, paramname = range_tuple + param_name = '_%s' % paramname.lower() + fo.add_code_eol(ildutil.ild_c_op_type + ' %s' % param_name) + + params = [] + for range_tuple in op_arr.ranges: + range_type, range_min, range_max, paramname = range_tuple + param_name = '_%s' % paramname.lower() + access_call = emit_ild_access_call(paramname, data_name) + + fo.add_code_eol('%s = (%s)%s' %(param_name, ildutil.ild_c_op_type, + access_call)) + params.append(param_name) + + lu_fn = op_arr.lookup_fn.function_name + + lu_call = lu_fn + '(%s)' + lu_call = lu_call % (', '.join(params)) + fo.add_code_eol('return %s' % lu_call) + return fo + +#generate L2 function that depends on argument +def gen_scalable_l2_function(agi, nt_name, target_opname, + ild_t_member, + arg_arr, arg_nt_names): + return_type = 'void' + l3_fn = ild_nt.get_lufn([nt_name], target_opname, flevel='l3') + arg_name = arg_arr.get_target_opname() + l2_fn = get_l2_fn([nt_name], target_opname, arg_nt_names, arg_name, + None, False) + + fo = codegen.function_object_t(l2_fn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + arg_type = agi.operand_storage.get_ctype(arg_name) + arg_var = '_%s' % arg_name.lower() + fo.add_code_eol('%s %s' % (arg_type, arg_var)) + + temp_var = '_%s' % ild_t_member + ctype = ildutil.ild_c_op_type + fo.add_code_eol('%s %s' % (ctype, temp_var)) + + + + for range_tuple in arg_arr.ranges: + range_type, range_min, range_max, paramname = range_tuple + param_name = '_%s' % paramname.lower() + fo.add_code_eol(ildutil.ild_c_op_type + ' %s' % param_name) + + params = [] + for range_tuple in arg_arr.ranges: + range_type, range_min, range_max, paramname = range_tuple + param_name = '_%s' % paramname.lower() + access_call = emit_ild_access_call(paramname, data_name) + + fo.add_code_eol('%s = (%s)%s' %(param_name, ildutil.ild_c_op_type, + access_call)) + params.append(param_name) + + arg_fn = arg_arr.lookup_fn.function_name + + arg_call = arg_fn + '(%s)' + arg_call = arg_call % (', '.join(params)) + fo.add_code_eol('%s = %s' % (arg_var, arg_call)) + + fcall = '%s(%s)' % (l3_fn, arg_var) + + fo.add_code_eol('%s = (%s)%s' % (temp_var, ctype, fcall)) + setter_fn = operand_storage.get_op_setter_fn(ild_t_member) + fo.add_code_eol('%s(%s, %s)' % (setter_fn, data_name,temp_var)) + return fo + + +def gen_l2_func_list(agi, target_nt_dict, arg_nt_dict, + ild_t_member): + """generate L2 functions""" + l2_func_list = [] + for (nt_name,array) in target_nt_dict.iteritems(): + target_opname = array.get_target_opname() + if array.is_const_lookup_fun(): + fo = gen_const_l2_function(agi, nt_name, + target_opname, ild_t_member) + l2_func_list.append(fo) + else: + for arg_nt_seq,arg_arr in arg_nt_dict.iteritems(): + fo = gen_scalable_l2_function(agi, nt_name, + target_opname, ild_t_member, arg_arr, list(arg_nt_seq)) + l2_func_list.append(fo) + return l2_func_list + +def dump_flist_2_header(agi, fname, headers, functions, + is_private=True, + emit_headers=True, + emit_bodies=True): + if is_private: + h_file = agi.open_file(mbuild.join('include-private', fname), + start=False) + else: + h_file = agi.open_file(fname, start=False) + + codegen.dump_flist_2_header(h_file, functions, headers, + emit_headers, + emit_bodies) + +def is_constant_l2_func(nt_seq, nt_dict): + if len(nt_seq) == 0: + return True + if len(nt_seq) > 1: + ildutil.ild_err("Unexpected NT SEQ while determining" + + " constness of a l3 function: %s" % nt_seq) + nt_arr = nt_dict[nt_seq[0]] + return nt_arr.is_const_lookup_fun() + +_ordered_maps = [''] + +def _test_map_all_zero(vv,phash_map_lu): + """phash_map_lu is a dict[maps][0...255] pointing to a 2nd level lookup """ + all_zero_map = {} + for xmap in phash_map_lu.keys(): + omap = phash_map_lu[xmap] + all_zero=True + for i in range(0,256): + value = omap[hex(i)] + #mbuild.msgb("MAP VAL", "VV={} MAP={} OPCODE={} VALUE={}".format( + # vv, xmap, i, value)) + if value != '(xed3_find_func_t)0': + all_zero=False + break + if all_zero: + mbuild.msgb("ALL ZEROS", "VV={} MAP={}".format(vv, xmap)) + all_zero_map[xmap]=True + else: + all_zero_map[xmap]=False + return all_zero_map + +def dump_vv_map_lookup(agi, + vv_lu, + is_3dnow, + op_lu_list, + h_fn='xed3-phash.h'): + phash_headers = ['xed-ild-eosz-getters.h', + 'xed-ild-easz-getters.h', + 'xed-internal-header.h', + 'xed-ild-getters.h', + 'xed-ild-private.h'] + maplu_headers = [] + all_zero_by_map = {} + for vv in sorted(vv_lu.keys()): + (phash_map_lu, lu_fo_list) = vv_lu[vv] + all_zero_by_map[vv] =_test_map_all_zero(vv,phash_map_lu) + + # dump a file w/prototypes and per-opcode functions pointed to + # by the elements of the various 256-entry arrays. + pheader = 'xed3-phash-vv{}.h'.format(vv) + dump_flist_2_header(agi, pheader, ['xed3-operand-lu.h'], lu_fo_list) + + # dump 256-entry arrays for each (vv,map) + map_lu_cfn = 'xed3-phash-lu-vv{}.c'.format(vv) + map_lu_hfn = 'xed3-phash-lu-vv{}.h'.format(vv) + maplu_headers.append(map_lu_hfn) + + name_pfx = 'xed3_phash_vv{}'.format(vv) + elem_type = 'xed3_find_func_t' + + dump_lookup(agi, #dump the 256 entry array + phash_map_lu, + name_pfx, + map_lu_cfn, + [pheader], + elem_type, + output_dir=None, + all_zero_by_map=all_zero_by_map[vv]) + + # dump a header with the decls for the 256-entry arrays or + # #define NAME 0 for the empty arrays. + h_file = agi.open_file(mbuild.join('include-private',map_lu_hfn), + start=False) + h_file.start() + for insn_map in sorted(phash_map_lu.keys()): + arr_name = _get_map_lu_name(name_pfx, insn_map) + if all_zero_by_map[vv][insn_map]: + #h_file.add_code("#define {} 0".format(arr_name)) + pass + else: + h_file.add_code("extern const {} {}[256];".format( + elem_type, arr_name)) + h_file.close() + + + #dump all the operand lookup functions in the list to a header file + hdr = 'xed3-operand-lu.h' + dump_flist_2_header(agi, hdr, + phash_headers, + op_lu_list, + emit_bodies=False) + dump_flist_2_header(agi, 'xed3-operand-lu.c', + [hdr], + op_lu_list, + is_private=False, + emit_headers=False) + + + # write xed3-phash.h (top most thing) + h_file = agi.open_file(mbuild.join('include-private',h_fn), + start=False) + for header in maplu_headers: + h_file.add_header(header) + h_file.start() + + maps = ild_info.get_maps(is_3dnow) + + vv_num = map(lambda x: int(x),vv_lu.keys()) + vv_index = max(vv_num) + 1 + map_num = len(maps) + arr_name = 'xed3_phash_lu' + elem_type = 'xed3_find_func_t*' + h_file.add_code('#define XED_PHASH_MAP_LIMIT {}'.format(map_num)) + h_file.add_code('const {} {}[{}][XED_PHASH_MAP_LIMIT] = {{'.format( + elem_type, arr_name, vv_index)) + #vv is not sequential it may have holes + for vv in range(vv_index): + map_lus = [] + #it's important that maps are correctly ordered + for imap in maps: + if vv in vv_num: + if all_zero_by_map[str(vv)][imap]: + arr_name = '0' + else: + arr_name = _get_map_lu_name('xed3_phash_vv%d' % vv, imap) + else: + arr_name = '0' + map_lus.append(arr_name) + vv_arr_name = '{' + ', '.join(map_lus) + '},' + h_file.add_code(vv_arr_name) + h_file.add_code('};') + h_file.close() + +def _get_map_lu_name(pfx, insn_map): + return '%s_map_%s' % (pfx, insn_map) + +def dump_lookup(agi, l1_lookup, name_pfx, lu_h_fn, headers, + lu_elem_type, define_dict=None, + all_zero_by_map=None, + output_dir='include-private'): + """Dump the lookup tables - from opcode value to + the L1 function pointers (in most cases they are L2 function pointers, + which doesn't matter, because they have the same signature) + @param l1_lookup: 2D dict so that + l1_lookup[string(insn_map)][string(opcode)] == string(L1_function_name) + all 0..255 opcode values should be set in the dict, so that if 0x0,0x0F + map-opcode is illegal, then l1_lookup['0x0']['0x0F'] should be set + to some string indicating that L1 function is undefined. + + all_zero_by_map is an optional dict[map] -> {True,False}. If False + skip emitting the map """ + if output_dir: + ofn = mbuild.join(output_dir,lu_h_fn) + else: + ofn = lu_h_fn + h_file = agi.open_file(ofn, start=False) + for header in headers: + h_file.add_header(header) + h_file.start() + + if define_dict: + print_defines(h_file, define_dict) + + for insn_map in sorted(l1_lookup.keys()): + arr_name = _get_map_lu_name(name_pfx, insn_map) + if all_zero_by_map==None or all_zero_by_map[insn_map]==False: + ild_dump_map_array(l1_lookup[insn_map], arr_name, + lu_elem_type, h_file) + + h_file.close() + +def _gen_bymode_fun_dict(info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun): + fun_dict = {} + insn_map = info_list[0].insn_map + opcode = info_list[0].opcode + for mode in ildutil.mode_space: + #get info objects with the same modrm.reg bits + infos = filter(lambda(info): mode in info.mode, info_list) + if len(infos) == 0: + ildutil.ild_warn('BY MODE resolving: No infos for mode' + + '%s opcode %s map %s' % (mode, opcode, insn_map)) + #we need to allow incomplete modrm.reg mappings for the + #case of map 0 opcode 0xC7 where we have infos only for + #reg 0 (MOV) and 7 + continue + #if these info objects conflict, we cannot refine by modrm.reg + is_conflict = is_conflict_fun(infos, nt_dict) + if is_conflict == None: + return None + if is_conflict: + ildutil.ild_warn('BY MODE resolving:Still conflict for mode' + + '%s opcode %s map %s' % (mode, opcode, insn_map)) + return None + l2_fn = gen_l2_fn_fun(infos[0], nt_dict) + if not l2_fn: + return None + fun_dict[mode] = l2_fn + return fun_dict + +def _gen_byreg_fun_dict(info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun): + fun_dict = {} + insn_map = info_list[0].insn_map + opcode = info_list[0].opcode + for reg in range(0,8): + #get info objects with the same modrm.reg bits + infos = filter(lambda(info): info.ext_opcode==reg, info_list) + if len(infos) == 0: + ildutil.ild_warn('BYREG resolving: No infos for reg' + + '%s opcode %s map %s' % (reg, opcode, insn_map)) + #we need to allow incomplete modrm.reg mappings for the + #case of map 0 opcode 0xC7 where we have infos only for + #reg 0 (MOV) and 7 + continue + #if these info objects conflict, we cannot refine by modrm.reg + is_conflict = is_conflict_fun(infos, nt_dict) + if is_conflict == None: + return None + if is_conflict: + ildutil.ild_warn('BYREG resolving:Still conflict for reg' + + '%s opcode %s map %s' % (reg, opcode, insn_map)) + return None + l2_fn = gen_l2_fn_fun(infos[0], nt_dict) + if not l2_fn: + return None + fun_dict[reg] = l2_fn + return fun_dict + +def _gen_intervals_dict(fun_dict): + """ + If there are consequent keys that map to the same value, we want to unite + them to intervals in order to have less conditional branches in code. + For example if fun_dict is something like: + {0:f1, 1:f1, 2:f2, 3:f2 , ...} + we will generate dict + {(0,1):f1, (2,3,4,5,6,7):f2} + """ + sorted_keys = sorted(fun_dict.keys()) + cur_int = [sorted_keys[0]] + int_dict = {} + for key in sorted_keys[1:]: + if fun_dict[key] == fun_dict[key-1]: + cur_int.append(key) + else: + int_dict[tuple(cur_int)] = fun_dict[key-1] + cur_int = [key] + int_dict[tuple(cur_int)] = fun_dict[sorted_keys[-1]] + return int_dict + +def gen_l1_byreg_resolution_function(agi,info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun, fn_suffix): + if len(info_list) < 1: + ildutil.ild_warn("Trying to resolve conflict for empty info_list") + return None + insn_map = info_list[0].insn_map + opcode = info_list[0].opcode + ildutil.ild_warn('generating by reg fun_dict for opcode %s map %s' % + (opcode, insn_map)) + fun_dict = _gen_byreg_fun_dict(info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun) + if not fun_dict: + #it is not ild_err because we might have other conflict resolution + #functions to try. + #In general we have a list of different conflict resolution functions + #that we iterate over and try to resolve the conflict + ildutil.ild_warn('Failed to generate by reg fun_dict for opcode ' + '%s map %s' % (opcode, insn_map)) + return None + + #if not all modrm.reg values have legal instructions defined, we don't + #have full 0-7 dict for modrm.reg here, and we can't generate the interval + #dict + if len(fun_dict.keys()) == 8: + int_dict = _gen_intervals_dict(fun_dict) + else: + int_dict = None + + lufn = ild_nt.gen_lu_names(['RESOLVE_BYREG'], fn_suffix)[2] + lufn += '_map%s_op%s_l1' % (insn_map, opcode) + operand_storage = agi.operand_storage + return_type = 'void' + fo = codegen.function_object_t(lufn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + + reg_type = 'xed_uint8_t' + reg_var = '_reg' + fo.add_code_eol('%s %s' % (reg_type, reg_var)) + + #get modrm value + fo.add_code_eol("%s = %s" % (reg_var, + emit_ild_access_call('REG', data_name))) + + #now emit the resolution code, that checks conditions from dict + #(in this case the modrm.reg value) + #and calls appropriate L2 function for each condition + + #if we have an interval dict, we can emit several if statements + if int_dict: + _add_int_dict_dispatching(fo, int_dict, reg_var, data_name) + #if we don't have interval dict, we emit switch statement + else: + _add_switch_dispatching(fo, fun_dict, reg_var, data_name) + + fo.add_code("/*We should not ever get here*/") + fo.add_code_eol('xed_assert(0)') + return fo + +def _add_int_dict_dispatching(fo, int_dict, dispatch_var, data_name): + cond_starter = 'if' + for interval in int_dict.keys(): + min = interval[0] + max = interval[-1] + #avoid comparing unsigned int to 0, this leads to build errors + if int(min) == 0 and int(max) != 0: + condition = '%s(%s <= %s) {' % (cond_starter, dispatch_var, max) + elif min != max: + condition = '%s((%s <= %s) && (%s <= %s)) {' % (cond_starter ,min, + dispatch_var, dispatch_var, max) + else: + condition = '%s(%s == %s) {' % (cond_starter, min, dispatch_var) + fo.add_code(condition) + call_stmt = '%s(%s)' % (int_dict[interval], data_name) + fo.add_code_eol(call_stmt) + fo.add_code_eol('return') + fo.add_code('}') + cond_starter = 'else if' + +def _add_switch_dispatching(fo, fun_dict, dispatch_var, data_name): + fo.add_code("switch(%s) {" % dispatch_var) + for key in fun_dict.keys(): + fo.add_code('case %s:' % key) + call_stmt = '%s(%s)' % (fun_dict[key], data_name) + fo.add_code_eol(call_stmt) + fo.add_code_eol('return') + fo.add_code("/*We should not ever get here*/") + fo.add_code("/*If we got here, it means that we need" ) + fo.add_code("to fill ild_storage entries for those MODE") + fo.add_code(" values that led us here*/") + fo.add_code_eol('default: xed_assert(0)') + fo.add_code("}") + +def gen_l1_bymode_resolution_function(agi,info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun, fn_suffix): + if len(info_list) < 1: + ildutil.ild_warn("Trying to resolve conflict for empty info_list") + return None + insn_map = info_list[0].insn_map + opcode = info_list[0].opcode + ildutil.ild_warn('generating by mode fun_dict for opcode %s map %s' % + (opcode, insn_map)) + fun_dict = _gen_bymode_fun_dict(info_list, nt_dict, is_conflict_fun, + gen_l2_fn_fun) + if not fun_dict: + #it is not ild_err because we might have other conflict resolution + #functions to try. + #In general we have a list of different conflict resolution functions + #that we iterate over and try to resolve the conflict + ildutil.ild_warn('Failed to generate by mode fun_dict for opcode '+ + '%s map %s' % (opcode, insn_map)) + return None + + #if not all modrm.reg values have legal instructions defined, we don't + #have full 0-7 dict for modrm.reg here, and we can't generate the interval + #dict + if len(fun_dict.keys()) == len(ildutil.mode_space): + int_dict = _gen_intervals_dict(fun_dict) + else: + int_dict = None + + lufn = ild_nt.gen_lu_names(['RESOLVE_BYMODE'], fn_suffix)[2] + lufn += '_map%s_op%s_l1' % (insn_map, opcode) + operand_storage = agi.operand_storage + return_type = 'void' + fo = codegen.function_object_t(lufn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + + + mode_type = ildutil.ild_c_op_type + mode_var = '_mode' + fo.add_code_eol(mode_type + ' %s' % mode_var) + #get MODE value + access_call = emit_ild_access_call("MODE", data_name) + if not access_call: + return None + + fo.add_code_eol('%s = (%s)%s' %(mode_var, mode_type, access_call)) + + #now emit the resolution code, that checks condtions from dict + #(in this case the MODE value) + #and calls appropriate L2 function for each condition + + #if we have an interval dict, we can emit several if statements + if int_dict: + _add_int_dict_dispatching(fo, int_dict, mode_var, data_name) + #if we don't have interval dict, we emit switch statement + else: + _add_switch_dispatching(fo, fun_dict, mode_var, data_name) + + fo.add_code("/*We should not ever get here*/") + fo.add_code_eol('xed_assert(0)') + return fo + +def print_defines(file, define_dict): + for def_name in sorted(define_dict.keys()): + def_val = define_dict[def_name] + file.add_code("#define %s %s\n" %(def_name, def_val)) + file.add_code("\n") + + +def ild_dump_map_array(opcode_dict, arr_name, arr_elem_type, xfile): + xfile.add_code('const %s %s[256] = {' % (arr_elem_type, arr_name)) + for opcode in range(0, 256): + ops = hex(opcode) + value = opcode_dict[ops] + xfile.add_code("/*opcode %s*/ %s," % (ops, value)) + xfile.add_code_eol('}') + + + +xed_mode_cvt_fn = 'xed_ild_cvt_mode' + +#FIXME: add REG here too? +_special_ops_dict = { + #Don't need special care for RM since we renamed + #partial opcodes with SRM + #'RM' : 'xed_ild_get_rm' + } + +#FIXME: need more descriptive name. +def _is_special_op(opname): + """ + Some operands are "special" - like RM: Sometimes we don't have modrm, + but grammar still likes to use RM operand - in this case it is first + 3 bits of the opcode. + In this case we can't just use regular RM operand scanned with ILD - + we must check if MODRM exists and if not take 3 LSB nits from opcode. + This is what getter should do for RM, that's why RM is special. + REG is probably the same. + is_special_op(opname) checks if the operand has special getter. + """ + return opname in _special_ops_dict + +#FIXME: need more descriptive name. +def _get_special_op_getter_fn(opname): + """ + Returns special operand's getter name. + See is_special_op comment. + """ + return _special_ops_dict[opname] + +def emit_ild_access_call(opname, data_name, eoasz_set=False): + """ + @param opname: the name of the operand of xed grammar. + @type opname: string + + @param data_name: the name of xed_decoded_inst_t* pointer + @type data_name: string + + @param eoasz_set: when doing static decoding EOSZ and EASZ are not + yet set correctly in the operands structure and we have to use + special ILD getters to get their correct value. + After dynamic decoding (and before we do operands decoding) EOSZ + and EASZ are already set and we can use regular getter for them. + @type eoasz_set: boolean + + IMPORTANT: EASZ and EOSZ cannot be computed with this function, + see how it's done in ild_imm and ild_disp for these two. + + @return: C statement (no semicolon, no eol) that returns the + value of corresponding operand. + """ + + if opname in ['EASZ', 'EOSZ'] and not eoasz_set: + #EASZ and EOSZ should be computed in a special way + #see how it's done in ild_phash.phash_t.add_cgen_lines + ildutil.ild_err('No simple getter for %s operand' % opname) + elif _is_special_op(opname): + getter_fn = _get_special_op_getter_fn(opname) + else: + getter_fn = operand_storage.get_op_getter_fn(opname) + + call_str = '%s(%s)' % (getter_fn, data_name) + return call_str + + diff --git a/pysrc/ild_disp.py b/pysrc/ild_disp.py new file mode 100755 index 0000000..c110269 --- /dev/null +++ b/pysrc/ild_disp.py @@ -0,0 +1,421 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import collections +import ild_nt +import genutil +import ildutil +import codegen +import ild_eosz +import ild_easz +import ild_info +import ild_codegen +import operand_storage +import mbuild + +_disp_token = 'DISP_WIDTH' +_brdisp_token = 'BRDISP_WIDTH' +_disp_tokens = [_brdisp_token, _disp_token] + +_ild_t_disp_member = 'disp_width' + + + +_l3_header_fn = 'xed-ild-disp-l3.h' +_l3_c_fn = 'xed-ild-disp-l3.c' + +_l2_header_fn = 'xed-ild-disp-l2.h' +_l1_header_fn = 'xed-ild-disp-l1.h' +_l2_c_fn = 'xed-ild-disp-l2.c' + +_const_suffix = 'CONST' + +_empty_fn = 'xed_lookup_function_EMPTY_DISP_CONST_l2' + +_l1_header_fn = 'xed-ild-disp-l1.h' + +_disp_lu_header_fn = 'xed-ild-disp-bytes.h' + +_l1_ptr_typename = 'disp_bytes_l1_func_t' + + + +def get_disp_nt_seq(ptrn_wrds, disp_nts): + """ + @param ptrn_wrds: list of tokens in instructions pattern + @type ptrn_wrds: [string] + @param disp_nts: list of names of [BR]?DISP_WIDTH-binding NTs + @type disp_nts: [string] + + @return nt_names: list of names of [BR]?DISP_WIDTH binding NTs + @type nt_names: [string] + + Returns a list of names of [BR]?DISP_WIDTH NTs in the pattern. + """ + return ild_nt.get_nt_seq(ptrn_wrds, list(disp_nts)) + + + +def get_all_disp_seq(united_lookup): + """ + @param uinted_lookup: lookup of ild_info.ild_info_t objects representing + current ISA. This lookup should have been built from storage+grammar + @type uinted_lookup: ild_info.ild_storage_t + + @return seq_list: list of all variations of DISP-binding NT sequences in + united_lookup. + @type seq_list: [ [string] ] + """ + all_seq = set() + infos = united_lookup.get_all_infos() + #infos = plist + for info in infos: + #lists are unhashable, hence we have to use tuples instead + all_seq.add(tuple(info.disp_nt_seq)) + #convert back to lists, in order not to surprise user + return_list = [] + for nt_tuple in all_seq: + return_list.append(list(nt_tuple)) + return return_list + + +def get_disp_binding_nts(agi): + """ + Go through all defined NTs in agi and return names of those, + that bind DISP_WIDTH + """ + return ild_nt.get_setting_nts(agi, _disp_token) + +def get_brdisp_binding_nts(agi): + """ + Go through all defined NTs in agi and return names of those, + that bind BRDISP_WIDTH + """ + return ild_nt.get_setting_nts(agi, _brdisp_token) + + +def get_target_opnames(): + """ + @return opnames: names of the DISP operand - [DISP_WIDTH, BRDISP_WIDTH] + @type opnames: [string] + """ + return _disp_tokens + +def get_l2_fn_from_info(info, disp_dict): + """ + Return L2 function name defined by the info. + disp_dict is a dictionary from [BR]DISP NT name to codegen.array + of the corresponding NT. + """ + is_const = ild_codegen.is_constant_l2_func(info.disp_nt_seq, disp_dict) + if len(info.disp_nt_seq) == 0: + return _empty_fn + disp_nt = disp_dict[info.disp_nt_seq[0]] + disp_token = disp_nt.get_target_opname() + if ild_eosz.get_target_opname() in disp_nt.get_arg_names(): + argname = ild_eosz.get_target_opname() + arg_seq = info.eosz_nt_seq + else: + argname = ild_easz.get_target_opname() + arg_seq = info.easz_nt_seq + + if is_const: + arg_seq = [] + arg_name = None + l2_fn = ild_codegen.get_l2_fn(info.disp_nt_seq, disp_token, + arg_seq, + argname, + _empty_fn, is_const) + return l2_fn + +def _is_disp_conflict(info_list, disp_dict): + """ + Return True|False whether infos in info_list conflict on L2 + functions (and then we need to define L1 function for this list). + """ + if len(info_list) <= 1: + return False + first = info_list[0] + l2_fn_first = get_l2_fn_from_info(first, disp_dict) + for info in info_list[1:]: + l2_fn_cur = get_l2_fn_from_info(info, disp_dict) + if (l2_fn_first != l2_fn_cur): + return True + return False + +#a list of conflict resolution functions to use when we have conflicts +#between info objects in the same map-opcode +_resolution_functions = [ + ild_codegen.gen_l1_byreg_resolution_function, + ild_codegen.gen_l1_bymode_resolution_function + ] + +def _resolve_conflicts(agi, info_list, disp_dict): + """Try to resolve conflicts by applying the conflict resolution + functions defined in _resolution_functions list. + + @param info_list: list of info objects to that have a conflict + @type info_list: [ild_info.ild_info_t + + @param disp_dict: dictionary from DISP-NT names to corresponding + codegen.array_t objects describing those NTs + @type disp_dict: { string(nt_name) : codegen.array_t(nt_arr) } + + @return: codegen.function_object_t defining the conflict resolution (L1) + function for info_list's map-opcode + + """ + for func in _resolution_functions: + fo = func(agi,info_list, disp_dict, _is_disp_conflict, + get_l2_fn_from_info, 'DISP') + if fo: + return fo + return None + +harcoded_res_functions = {} + +def gen_l1_functions_and_lookup(agi, united_lookup, disp_dict): + """Compute L1(conflict resolution) functions list and disp_bytes lookup + tables dict. + @param agi: all generators info + + @param united_lookup: the 2D lookup by map-opcode to info objects list. + united_lookup['0x0']['0x78'] == [ild_info1, ild_info2, ... ] + @type united_lookup: + {string(insn_map) : {string(opcode): [ild_info.ild_info_t]} } + + + """ + #list of L1 function objects that resolve conflicts in map-opcodes + #functions. This list will be dumped to xed_ild_imm_l1.h + l1_resolution_fos = [] + + #dictionary l1_lookup[insn_map][opcode] = l1_function_name + #this dictionary will be used to dump the has_imm lookup tables + l1_lookup = {} + + #dictionary from function body(as string) to list of function objects + #with that body. + #This dict will be used to bucket identical functions in order to + #not define same functions more than once. + l1_bucket_dict = collections.defaultdict(list) + + + for insn_map in ild_info.get_maps(united_lookup.is_amd): + l1_lookup[insn_map] = {} + for opcode in range(0, 256): + #look in the hardcoded resolution functions + if (insn_map, hex(opcode)) in harcoded_res_functions: + l1_fn = harcoded_res_functions[(insn_map, hex(opcode))] + l1_lookup[insn_map][hex(opcode)] = l1_fn + continue + info_list = united_lookup.get_info_list(insn_map, hex(opcode)) + #get only info objects with minimum priority + info_list = ild_info.get_min_prio_list(info_list) + is_conflict = _is_disp_conflict(info_list, disp_dict) + if len(info_list) > 1 and is_conflict: + l1_fo = _resolve_conflicts(agi, info_list, disp_dict) + if not l1_fo: + ildutil.ild_err('FAILED TO GENERATE L1 CONFLICT ' + + 'RESOLUTION FUNCTION FOR DISP\n infos: %s' % + "\n".join([str(info) for info in info_list])) + l1_bucket_dict[l1_fo.emit_body()].append(l1_fo) + l1_fn = l1_fo.function_name + + elif len(info_list) == 0: + #if map-opcode pair is undefined the lookup function ptr is + #NULL. + #This will happen for opcodes like 0F in 0F map - totally + #illegal opcodes, that should never be looked up in runtime. + #We define NULL pointer for such map-opcodes + l1_fn = '(%s)0' % (ildutil.l1_ptr_typename) + else: + #there are no conflicts, we can use L2 function as L1 + info = info_list[0] + l1_fn = get_l2_fn_from_info(info, disp_dict) + l1_lookup[insn_map][hex(opcode)] = l1_fn + + #there are 18 L1 functions with same body (currently, may change + #in future) + #we are going to bucket L1 functions with identical body but different + #names in order to have only one function for each unique body + #FIXME: the bucketed function name is not self descriptive + bucket_name = 'xed_lookup_function_DISP_BUCKET_%s_l1' + cur_bucket = 0 + for res_fun_list in l1_bucket_dict.values(): + if len(res_fun_list) == 1: + #only one such function - we should define it as is + l1_resolution_fos.append(res_fun_list[0]) + else: + #more than one L1 function with identical body + #we should define L1 function with that body + #and fix references in the lookup table + + #the function name + cur_buck_name = bucket_name % cur_bucket + cur_bucket += 1 + + #fix references in the lookup table + for res_fun in res_fun_list: + for insn_map in l1_lookup.keys(): + for opcode in l1_lookup[insn_map].keys(): + cur_fn = l1_lookup[insn_map][opcode] + if cur_fn == res_fun.function_name: + l1_lookup[insn_map][opcode] = cur_buck_name + #define the L1 function and add it to the list of L1 functions + #to dump + buck_fo = res_fun_list[0] + buck_fo.function_name = cur_buck_name + l1_resolution_fos.append(buck_fo) + + return l1_resolution_fos,l1_lookup + + + +def _gen_empty_function(agi): + """ + This function is for patterns that don't set [BR]DISP_WIDTH tokens. + These patterns have disp_bytes set earlier in xed-ild.c + and we define a L2 lookup function that does nothing + """ + operand_storage = agi.operand_storage + #return_type = operand_storage.get_ctype(_imm_token) + return_type = 'void' + fo = codegen.function_object_t(_empty_fn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + fo.add_code('/*This function does nothing for map-opcodes whose') + fo.add_code('disp_bytes value is set earlier in xed-ild.c') + fo.add_code('(regular displacement resolution by modrm/sib)*/\n') + fo.add_code('/*pacify the compiler*/') + fo.add_code_eol('(void)%s' % data_name) + return fo + + + +def _gen_l3_array_dict(agi, nt_names, target_op): + """ + For each NT from nt_names, generate and codegen.array_t object + return a dictionary from nt_name to array_t. + """ + nt_dict = {} + for nt_name in nt_names: + array = ild_nt.gen_nt_lookup(agi, nt_name, target_op, + target_type=ildutil.ild_c_op_type, level='l3') + nt_dict[nt_name] = array + return nt_dict + + +def work(agi, united_lookup, disp_nts, brdisp_nts, ild_gendir, + eosz_dict, easz_dict, debug): + """ + Main entry point of the module. + Generates all the L1-3 functions and dumps disp_bytes lookup + tables. + """ + + #get all used DISP NT sequences that appear in patterns + #we are going to generate L1-3 functions only for these sequences + all_disp_seq = get_all_disp_seq(united_lookup) + + #check that all sequences are actually single NTs + #(each sequence has only one NT) + #my observation is that they really are. This simplifies things + #and we are going to rely on that. + all_nts = [] + for ntseq in all_disp_seq: + if len(ntseq) > 1: + ildutil.ild_err("Unexpected DISP NT SEQ %s" % ntseq) + if len(ntseq) == 0: + continue #the empty NT sequence + all_nts.append(ntseq[0]) + + #get only those NTs that actually appear in PATTERNs + disp_nts = filter(lambda(nt): nt in all_nts, disp_nts) + brdisp_nts = filter(lambda(nt): nt in all_nts, brdisp_nts) + + + debug.write('DISP SEQS: %s\n' % all_disp_seq) + debug.write('DISP NTs: %s\n' % disp_nts) + debug.write('BRDISP NTs: %s\n' % brdisp_nts) + + brdisp_dict = _gen_l3_array_dict(agi, brdisp_nts, _brdisp_token) + disp_dict = _gen_l3_array_dict(agi, disp_nts, _disp_token) + + + nt_arr_list = brdisp_dict.values() + disp_dict.values() + #create function that calls all intialization functions + init_f = ild_nt.gen_init_function(nt_arr_list, 'xed_ild_disp_l3_init') + + #dump L3 functions + ild_nt.dump_lu_arrays(agi, nt_arr_list, _l3_c_fn, + mbuild.join('include-private',_l3_header_fn), + init_f) + + #create L2 functions + + #The thing is that we need to know for each + #DISP NT whether it depends on EOSZ or EASZ and supply appropriate arg_dict + #to gen_l2_func_list() + l2_functions = [] + eosz_op = ild_eosz.get_target_opname() + easz_op = ild_easz.get_target_opname() + for nt_name,array in disp_dict.items() + brdisp_dict.items(): + #Some DISP NTs depend on EOSZ, others on EASZ, we need to know + #that when we generate L2 functions + if eosz_op in array.get_arg_names(): + arg_dict = eosz_dict + else: + arg_dict = easz_dict + flist = ild_codegen.gen_l2_func_list(agi, {nt_name:array}, + arg_dict, _ild_t_disp_member) + l2_functions.extend(flist) + + #create the doing-nothing L2 function for map-opcodes + #with regular displacement resolution + l2_functions.append(_gen_empty_function(agi)) + + #dump L2 functions + l2_headers = [ild_eosz.get_ntseq_header_fn(), + ild_easz.get_ntseq_header_fn(), + _l3_header_fn, ildutil.ild_private_header, + operand_storage.get_operand_accessors_fn()] + ild_codegen.dump_flist_2_header(agi, _l2_header_fn, l2_headers, + l2_functions) + + #create the L1 functions and lookup tables + + #unite brdisp and dips dictionaries + disp_dict.update(brdisp_dict) + + #generate L1 functions and lookup tables + res = gen_l1_functions_and_lookup(agi, united_lookup, disp_dict) + + l1_functions,l1_lookup = res + #dump L1 functions + ild_codegen.dump_flist_2_header(agi, _l1_header_fn, [_l2_header_fn], + l1_functions) + #dump lookup tables + headers = [_l1_header_fn, ildutil.ild_private_header, + operand_storage.get_operand_accessors_fn()] + ild_codegen.dump_lookup(agi, l1_lookup, _ild_t_disp_member, + _disp_lu_header_fn, headers, + ildutil.l1_ptr_typename) + + diff --git a/pysrc/ild_easz.py b/pysrc/ild_easz.py new file mode 100755 index 0000000..6003dcd --- /dev/null +++ b/pysrc/ild_easz.py @@ -0,0 +1,189 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +import ild_nt +import mbuild +import ild_codegen +import operand_storage +import genutil +import ildutil +import ild_info + +_easz_token = 'EASZ' +_easz_binding_pattern = re.compile(r'EASZ=(?P[0-9]+)') + +#FIXME: we can get default NT by looking at the spine +_easz_default_nt = 'ASZ_NONTERM' + +_easz_lookup_def_str = 'XED_ILD_EASZ_LOOKUP' + +_easz_defines = { + 'XED_ILD_EASZ_0' : 0, + 'XED_ILD_EASZ_1' : 1, + 'XED_ILD_EASZ_2' : 2, + 'XED_ILD_EASZ_3' : 3, + } +#set up LOOKUP define to be the biggest defined value +_easz_defines[_easz_lookup_def_str] = len(_easz_defines) + +#reverted _eosz_defines +_easz_defines_reverse = dict((v,k) for k, v in _easz_defines.iteritems()) + +_easz_c_fn = 'xed-ild-easz.c' +_easz_header_fn = 'xed-ild-easz.h' + +def get_getter_fn(ptrn_list): + if len(ptrn_list) == 0: + l1_fn = '(%s)0' % (ildutil.ild_getter_typename) + first = ptrn_list[0] + for cur in ptrn_list[1:]: + if first.easz_nt_seq != cur.easz_nt_seq: + #conflict in easz resolution functions.. should not happen + return None + return ild_codegen.get_derived_op_getter_fn(first.easz_nt_seq, _easz_token) + +def is_easz_conflict(info_list): + """ + Return True/False if info list conflicts + on EASZ resolution function (EOSZ NT sequence). + """ + first_info = info_list[0] + for cur_info in info_list[1:]: + if first_info.easz_nt_seq != cur_info.easz_nt_seq: + return True + return False + +def gen_getter_fn_lookup(agi, united_lookup, easz_dict): # NOT USED + """Compute L1(conflict resolution) functions list and easz + lookup tables dict. + @param agi: all generators info + + @param united_lookup: the 2D lookup by map-opcode to info objects list. + united_lookup['0x0']['0x78'] == [ild_info1, ild_info2, ... ] + @type united_lookup: + {string(insn_map) : {string(opcode): [ild_info.ild_info_t]} } + + + """ + l1_lookup = {} + for insn_map in united_lookup.get_maps(): + l1_lookup[insn_map] = {} + for opcode in range(0, 256): + info_list = united_lookup.get_info_list(insn_map, hex(opcode)) + #get only info objects with minimum priority + info_list = ild_info.get_min_prio_list(info_list) + is_conflict = False + if len(info_list) > 1: + is_conflict = is_easz_conflict(info_list) + + if is_conflict: + l1_fn = None + #if map-opcode pair is undefined the lookup function ptr is NULL + #this will happen for opcodes like 0F in 0F map - totally illegal + #opcodes, that should never be looked up in runtime. + elif len(info_list) == 0: + l1_fn = '(%s)0' % (ildutil.l1_ptr_typename) + else: + #there are no conflicts, we can use the eosz_nt_seq + #function + info = info_list[0] + l1_fn = ild_nt.get_lufn(info.easz_nt_seq, _easz_token) + l1_lookup[insn_map][hex(opcode)] = l1_fn + return l1_lookup + + +#returns a list of names of EASZ-binding NTs in the pattern +def get_easz_nt_seq(ptrn_wrds, easz_nts): + return ild_nt.get_nt_seq(ptrn_wrds, easz_nts, + implied_nt=_easz_default_nt) + + +#returns a list of all sequences of EOSZ setting NTs in patterns +#each sequence is a list of strings (NT names) +def get_all_easz_seq(united_lookup): + all_seq = set() + for info in united_lookup.get_all_infos(): + #lists are unhaashable, hence we have to use tuples instead + all_seq.add(tuple(info.easz_nt_seq)) + #convert back to lists, in order not to surprise user + return_list = [] + for nt_tuple in all_seq: + return_list.append(list(nt_tuple)) + return return_list + +#Parameters: agi - all generator info object +#returns a list of names of NTs that bind EASZ operand +def get_easz_binding_nts(agi): + return ild_nt.get_setting_nts(agi, _easz_token) + +def get_target_opname(): + return _easz_token + +def get_ntseq_header_fn(): + return _easz_header_fn + +#dumps the xed_ild_easz.c file that defines all lookup functions +#for EASZ resolution +#FIXME: should dump header file too +def work(agi, united_lookup, easz_nts, ild_gendir, debug): + + #dump lookup tables for each NT + #just for debugging + nt_arrays = [] + for nt_name in easz_nts: + array = ild_nt.gen_nt_lookup(agi, nt_name, 'EASZ') + if not array: + return + nt_arrays.append(array) + ild_nt.dump_lu_arrays(agi, nt_arrays, 'ild_easz_debug.txt', + 'ild_easz_debug_header.txt') + + all_easz_seq = get_all_easz_seq(united_lookup) + debug.write('EASZ SEQS: %s\n' % all_easz_seq) + + nt_seq_arrays = {} + for nt_seq in all_easz_seq: + array = ild_nt.gen_nt_seq_lookup(agi, nt_seq, _easz_token) + if not array: + return + nt_seq_arrays[tuple(nt_seq)] = array + #init function calls all single init functions for the created tables + init_f = ild_nt.gen_init_function(nt_seq_arrays.values(), + 'xed_ild_easz_init') + ild_nt.dump_lu_arrays(agi, nt_seq_arrays.values(), _easz_c_fn, + mbuild.join('include-private', _easz_header_fn), + init_f) + getter_fos = [] + for names in nt_seq_arrays.keys(): + arr = nt_seq_arrays[names] + getter_fo = ild_codegen.gen_derived_operand_getter(agi, _easz_token, + arr, list(names)) + getter_fos.append(getter_fo) + + headers = [ildutil.ild_private_header, + _easz_header_fn, + operand_storage.get_operand_accessors_fn()] + ild_codegen.dump_flist_2_header(agi, 'xed-ild-easz-getters.h', + headers, + getter_fos) + + #getter_lookup = gen_getter_fn_lookup(agi, united_lookup, nt_seq_arrays) + + return nt_seq_arrays + diff --git a/pysrc/ild_eosz.py b/pysrc/ild_eosz.py new file mode 100755 index 0000000..fb08abf --- /dev/null +++ b/pysrc/ild_eosz.py @@ -0,0 +1,231 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +import ild_nt +import mbuild +import ild_info +import genutil +import ildutil +import operand_storage +import ild_codegen + + +_eosz_token = 'EOSZ' +_eosz_binding_pattern = re.compile(r'EOSZ=(?P[0-9]+)') + +#FIXME: we can get default NT by looking at the spine +_eosz_default_nt = 'OSZ_NONTERM' + + + +_eosz_c_fn = 'xed-ild-eosz.c' +_eosz_header_fn = 'xed-ild-eosz.h' + + +harcoded_res_functions = {} + +#FIXME: I hope there are no conflicts on EOSZ in map,opcodes which +#patterns have EOSZ as an operand decider. +#If it is true, then in general case we can postpone resolving EOSZ +#to the stage when xed_inst_t is already known, +#and resolve EOSZ before that stage only when it is really +#needed - for immediate, displacement and pattern dispatching where +#EOSZ is in constraint dict. + +#IF there are such conflicts, then we need to develop a general mechanism +#for conflict resolution based on patterns' constraints. +#Probably use the constraint dict for that. That would be similar to xed2's +#decoding graph generation. I hope there is no need for that. +def _resolve_conflicts(agi, info_list, nt_dict): # NOT USED + """Try to resolve conflicts by applying the conflict resolution + functions defined in _resolution_functions list. + + @param info_list: list of info objects to that have a conflict + @type info_list: [ild_info.ild_info_t + + @param nt_dict: dictionary from EOSZ-NT names to corresponding + codegen.array_t objects describing those NTs + @type nt_dict: { string(nt_name) : codegen.array_t(nt_arr) } + + @return: codegen.function_object_t defining the conflict resolution (L1) + function for info_list's map-opcode + + """ + for func in _resolution_functions: + fo = func(agi,info_list, imm_dict, is_eosz_conflict, + get_l2_fn_from_info, _eosz_token) + if fo: + return fo + return None + +#FIXME: use info_list instead? +def get_getter_fn(ptrn_list): + if len(ptrn_list) == 0: + l1_fn = '(%s)0' % (ildutil.ild_getter_typename) + first = ptrn_list[0] + for cur in ptrn_list[1:]: + if first.eosz_nt_seq != cur.eosz_nt_seq: + #conflict in eosz resolution functions.. should not happen + return None + return ild_codegen.get_derived_op_getter_fn(first.eosz_nt_seq, _eosz_token) + +def gen_getter_fn_lookup(agi, united_lookup, eosz_dict): # NOT USED + """Compute L1(conflict resolution) functions list and eosz + lookup tables dict. + @param agi: all generators info + + @param united_lookup: the 2D lookup by map-opcode to info objects list. + united_lookup['0x0']['0x78'] == [ild_info1, ild_info2, ... ] + @type united_lookup: + {string(insn_map) : {string(opcode): [ild_info.ild_info_t]} } + + + """ + l1_lookup = {} + for insn_map in united_lookup.get_maps(): + l1_lookup[insn_map] = {} + for opcode in range(0, 256): + info_list = united_lookup.get_info_list(insn_map, hex(opcode)) + #get only info objects with minimum priority + info_list = ild_info.get_min_prio_list(info_list) + is_conflict = False + if len(info_list) > 1: + is_conflict = is_eosz_conflict(info_list) + + if is_conflict: +# l1_fo = _resolve_conflicts(agi, info_list, nt_dict) +# if not l1_fo: +# ildutil.ild_err('FAILED TO GENERATE CONFLICT ' + +# 'RESOLUTION FUNCTION FOR EOSZ\n infos:\n %s' % +# "\n".join([str(info) for info in info_list])) +# +# l1_resolution_fos.append(l1_fo) +# l1_fn = l1_fo.function_name + l1_fn = None + #if map-opcode pair is undefined the lookup function ptr is NULL + #this will happen for opcodes like 0F in 0F map - totally illegal + #opcodes, that should never be looked up in runtime. + elif len(info_list) == 0: + l1_fn = '(%s)0' % (ildutil.l1_ptr_typename) + else: + #there are no conflicts, we can use the eosz_nt_seq + #function + info = info_list[0] + l1_fn = ild_nt.get_lufn(info.eosz_nt_seq, _eosz_token) + l1_lookup[insn_map][hex(opcode)] = l1_fn + return l1_lookup + + +def is_eosz_conflict(info_list): + """ + Return True/False if info list conflicts + on EOSZ resolution function (EOSZ NT sequence). + """ + first_info = info_list[0] + for cur_info in info_list[1:]: + if first_info.eosz_nt_seq != cur_info.eosz_nt_seq: + return True + return False + +#returns a list of names of EOSZ-binding NTs in the pattern +def get_eosz_nt_seq(ptrn_wrds, eosz_nts): + return ild_nt.get_nt_seq(ptrn_wrds, eosz_nts, + implied_nt=_eosz_default_nt) + + +#returns a list of all sequences of EOSZ setting NTs in patterns +#each sequence is a list of strings (NT names) +def get_all_eosz_seq(united_lookup): + all_seq = set() + for info in united_lookup.get_all_infos(): + #lists are unhaashable, hence we have to use tuples instead + all_seq.add(tuple(info.eosz_nt_seq)) + #convert back to lists, in order not to surprise user + return_list = [] + for nt_tuple in all_seq: + return_list.append(list(nt_tuple)) + return return_list + +#Parameters: agi - all generator info object +#returns a list of names of NTs that bind EOSZ operand +def get_eosz_binding_nts(agi): + return ild_nt.get_setting_nts(agi, _eosz_token) + + +def get_target_opname(): + return _eosz_token + +def get_ntseq_header_fn(): + return _eosz_header_fn + +#dumps the xed-ild-eosz.c file that defines all lookup functions +#for EOSZ resolution +#FIXME: should dump header file too +def work(agi, united_lookup, eosz_nts, ild_gendir, debug): + + #dump lookup tables for each NT + #just for debugging + nt_arrays = [] + for nt_name in eosz_nts: + array = ild_nt.gen_nt_lookup(agi, nt_name, 'EOSZ') + if not array: + return None + nt_arrays.append(array) + ild_nt.dump_lu_arrays(agi, nt_arrays, 'ild_oesz_debug.txt', + 'ild_eosz_debug_header.txt') + + #get all sequences of NTs that set EOSZ + #we will use these sequences to create EOSZ-computing functions + all_eosz_seq = get_all_eosz_seq(united_lookup) + debug.write('EOSZ SEQS: %s\n' % all_eosz_seq) + + #for each EOSZ sequence create a lookup array + nt_seq_arrays = {} + for nt_seq in all_eosz_seq: + array = ild_nt.gen_nt_seq_lookup(agi, nt_seq, _eosz_token) + if not array: + return None + nt_seq_arrays[tuple(nt_seq)] = array + #init function calls all single init functions for the created tables + init_f = ild_nt.gen_init_function(nt_seq_arrays.values(), + 'xed_ild_eosz_init') + #dump init and lookup functions for EOSZ sequences + ild_nt.dump_lu_arrays(agi, nt_seq_arrays.values(), _eosz_c_fn, + mbuild.join('include-private', _eosz_header_fn), + init_f) + #generate EOSZ getter functions - they get xed_decoded_inst_t* + #and return EOSZ value (corresponding to EOSZ NT sequence + #that they represent) + getter_fos = [] + for names in nt_seq_arrays.keys(): + arr = nt_seq_arrays[names] + getter_fo = ild_codegen.gen_derived_operand_getter(agi, _eosz_token, + arr, list(names)) + getter_fos.append(getter_fo) + + ild_codegen.dump_flist_2_header(agi, 'xed-ild-eosz-getters.h', + [ildutil.ild_private_header, + _eosz_header_fn, + operand_storage.get_operand_accessors_fn()], getter_fos) + + #getter_lookup = gen_getter_fn_lookup(agi, united_lookup, nt_seq_arrays) + + return nt_seq_arrays + + diff --git a/pysrc/ild_imm.py b/pysrc/ild_imm.py new file mode 100755 index 0000000..08bc2aa --- /dev/null +++ b/pysrc/ild_imm.py @@ -0,0 +1,388 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +import ild_nt +import mbuild +import genutil +import ildutil +import codegen +import ild_eosz +import ild_info +import ild_codegen +import operand_storage + +_imm_token = 'IMM_WIDTH' +_ild_t_imm_member = 'imm_width' + +_uimm1_nt = 'UIMM8_1' + + +_l3_header_fn = 'xed-ild-imm-l3.h' +_l3_c_fn = 'xed-ild-imm-l3.c' + +_l2_header_fn = 'xed-ild-imm-l2.h' +_l1_header_fn = 'xed-ild-imm-l1.h' +_l2_c_fn = 'xed-ild-imm-l2.c' + +_eosz_const_suffix = 'CONST' + +_imm0_fn = 'xed_lookup_function_0_IMM_WIDTH_CONST_l2' + +_l1_header_fn = 'xed-ild-imm-l1.h' + +_imm_lu_header_fn = 'xed-ild-imm-bytes.h' + + + +def get_imm_nt_seq(ptrn_wrds, imm_nts): + """ + @param ptrn_wrds: list of tokens in instructions pattern + @type ptrn_wrds: [string] + @param imm_nts: list of names of IMM_WIDTH-binding NTs + @type imm_nts: [string] + + @return nt_names: list of names of IMM_WIDTH binding NTs + @type nt_names: [string] + + Returns a list of names of IMM-binding NTs in the pattern. + generally there is only one NT for IMM_WIDTH. + But ENTER, EXTRQ and INSERTQ instructions have two immediate + NTs in pattern. This strange NT UIMM8_1 doesn't bind IMM_WIDTH. + We should take special care of it. + It is also possible to track captured operands and to check if UIMM1 + is among them, that would be a more generic way, but more complicated + and it seems a waste to implement it for just one rare UIMM_1 NT. + """ + return ild_nt.get_nt_seq(ptrn_wrds, list(imm_nts) + [_uimm1_nt]) + + + +def get_all_imm_seq(united_lookup): + """ + @param united_lookup: lookup of ild_info.ild_info_t objects representing + current ISA. This lookup should have been built from storage+grammar + @type uinted_lookup: ild_info.ild_storage_t + + @return seq_list: list of all variations of IMM-binding NT sequences in + united_lookup. + @type seq_list: [ [string] ] + """ + all_seq = set() + infos = united_lookup.get_all_infos() + for info in infos: + #lists are unhashable, hence we have to use tuples instead + all_seq.add(tuple(info.imm_nt_seq)) + #convert back to lists, in order not to surprise user + return_list = [] + for nt_tuple in all_seq: + return_list.append(list(nt_tuple)) + return return_list + + +def get_imm_binding_nts(agi): + """ + @param agi: all generator info object. main data structure of generator. + + @return nt_list: list of names of NTs in the grammar that bind IMM_WIDTH + operand. + @type nt_list: [string] + """ + nt_names = ild_nt.get_setting_nts(agi, _imm_token) + #filter ONE nt + #FIXME: remove ONE nt from grammar + return filter(lambda(x): x!='ONE', nt_names) + + +def get_target_opname(): + """ + @return opname: name of the IMM operand - IMM_WIDTH + @type opname: string + """ + return _imm_token + + +def get_l2_fn_from_info(info, imm_dict): + is_const = ild_codegen.is_constant_l2_func(info.imm_nt_seq, imm_dict) + + if is_const: + l2_fn = ild_codegen.get_l2_fn(info.imm_nt_seq, _imm_token, [], None, + _imm0_fn, True) + else: + l2_fn = ild_codegen.get_l2_fn(info.imm_nt_seq, _imm_token, + info.eosz_nt_seq, + ild_eosz.get_target_opname(), + _imm0_fn, False) + return l2_fn + + + +def _gen_imm0_function(agi): + """ + for patterns that don't set IMM_WIDTH token + these patterns have has_im==0 + and we define a L2 lookup function that returns 0 + """ + #return_type = operand_storage.get_ctype(_imm_token) + return_type = 'void' + fo = codegen.function_object_t(_imm0_fn, return_type, + static=True, inline=True) + data_name = 'x' + fo.add_arg(ildutil.ild_c_type + ' %s' % data_name) + setter_fn = operand_storage.get_op_setter_fn(_ild_t_imm_member) + fo.add_code_eol('%s(%s, %s)' % (setter_fn, data_name,'0')) + return fo + + +def _is_imm_conflict(info_list, imm_dict): + """Check if info list conflicts on imm_bytes property. + Sometimes info objects conflict on L2 function name, but those + different functions actually return same values. + For example: + L2 functions defined by UIMM8() and SIMM8() NTs have different names + but both are const functions returning 8. If info list has those + two L2 functions, we should discover that and return that there is no + conflict + + @param info_list: list of info objects to check + @type info_list: [ild_info.ild_info_t + + @param imm_dict: dictionary from IMM-NT names to corresponding + codegen.array_t objects describing those NTs + @type imm_dict: { string(nt_name) : codegen.array_t(nt_arr) } + + @return: True|False - if there is a conflict in lookup function name + + """ + if len(info_list) <= 1: + return False + first = info_list[0] + l2_fn_first = get_l2_fn_from_info(first, imm_dict) + + for info in info_list[1:]: + l2_fn_cur = get_l2_fn_from_info(info, imm_dict) + + if (l2_fn_first != l2_fn_cur): + #there are const l3 functions that return only one value: + #SIMM8 UIMM8 etc. If they return same value, they should not + #conflict + nt_seq1 = first.imm_nt_seq + nt_seq2 = info.imm_nt_seq + + #check if we have double imm patterns + if len(nt_seq1) > 1 or len(nt_seq2) > 1: + #function names are different, hence conflict + return True + + if len(nt_seq1) != len(nt_seq2): + return True + imm_arr1 = imm_dict[nt_seq1[0]] + imm_arr2 = imm_dict[nt_seq2[0]] + val_space1 = imm_arr1.get_values_space() + val_space2 = imm_arr2.get_values_space() + if len(val_space1) == len(val_space2) == 1: + if val_space1[0] == val_space2[0]: + continue + return True + return False + +#fixme: write a good comment about conflict resolution in eosz and imm +#a list of conflict resolution functions to use when we have conflicts +#between info objects in the same map-opcode +#for example map 0, opcode c7 has xbegin and mov instructions that have +#different immediate nts - SIMMz for mov and no imm for xbegin +#and we decide by REG field which lookup function to use +_resolution_functions = [ + #it seems that one resolution function is enough + ild_codegen.gen_l1_byreg_resolution_function, + ] + +#these are for second immediate guys. +#It also happens that AMD second immediate guys define uneasy conflicts +#so we are killing two birds with one stone +harcoded_res_functions = { + #(map, opcode) L1_function_name + ('0x0F', '0x78') : 'xed_ild_hasimm_map0x0F_op0x78_l1', + ('0x0', '0xc8') : 'xed_ild_hasimm_map0x0_op0xc8_l1' + } + +def _resolve_conflicts(agi, info_list, imm_dict): + """Try to resolve conflicts by applying the conflict resolution + functions defined in _resolution_functions list. + + @param info_list: list of info objects to that have a conflict + @type info_list: [ild_info.ild_info_t + + @param imm_dict: dictionary from IMM-NT names to corresponding + codegen.array_t objects describing those NTs + @type imm_dict: { string(nt_name) : codegen.array_t(nt_arr) } + + @return: codegen.function_object_t defining the conflict resolution (L1) + function for info_list's map-opcode + + """ + #FIXME: we can use ild_cdict.constraint_dict_t for resolving + #conflicts it would work for any patterns (now we try to resolve + #only by REG operand) + for func in _resolution_functions: + fo = func(agi,info_list, imm_dict, _is_imm_conflict, + get_l2_fn_from_info, _imm_token) + if fo: + return fo + return None + +def gen_l1_functions_and_lookup(agi, united_lookup, imm_dict): + """Compute L1(conflict resolution) functions list and imm_bytes + lookup tables dict. + @param agi: all generators info + + @param united_lookup: the 2D lookup by map-opcode to info objects list. + united_lookup['0x0']['0x78'] == [ild_info1, ild_info2, ... ] + @type united_lookup: + {string(insn_map) : {string(opcode): [ild_info.ild_info_t]} } + + + """ + l1_resolution_fos = [] + l1_lookup = {} + for insn_map in ild_info.get_dump_maps(): + l1_lookup[insn_map] = {} + for opcode in range(0, 256): + #look in the hard-coded resolution functions + #they are manually written for the two-immediates instructions + if (insn_map, hex(opcode)) in harcoded_res_functions: + l1_fn = harcoded_res_functions[(insn_map, hex(opcode))] + l1_lookup[insn_map][hex(opcode)] = l1_fn + continue + info_list = united_lookup.get_info_list(insn_map, hex(opcode)) + #get only info objects with minimum priority + info_list = ild_info.get_min_prio_list(info_list) + is_conflict = _is_imm_conflict(info_list, imm_dict) + + if len(info_list) > 1 and is_conflict: + l1_fo = _resolve_conflicts(agi, info_list, imm_dict) + if not l1_fo: + ildutil.ild_err('FAILED TO GENERATE L1 CONFLICT ' + + 'RESOLUTION FUNCTION FOR IMM\n infos:\n %s' % + "\n".join([str(info) for info in info_list])) + + l1_resolution_fos.append(l1_fo) + l1_fn = l1_fo.function_name + #if map-opcode pair is undefined the lookup function ptr is NULL + #this will happen for opcodes like 0F in 0F map - totally illegal + #opcodes, that should never be looked up in runtime. + elif len(info_list) == 0: + l1_fn = '(%s)0' % (ildutil.l1_ptr_typename) + else: + #there are no conflicts, we can use L2 function as L1 + info = info_list[0] + l1_fn = get_l2_fn_from_info(info, imm_dict) + if not l1_fn: + return None + l1_lookup[insn_map][hex(opcode)] = l1_fn + return l1_resolution_fos,l1_lookup + +def _filter_uimm1_nt(imm_nt_names): + """Filter UIMM8_1 NT from list""" + return filter(lambda(x): x!=_uimm1_nt, imm_nt_names) + + +def work(agi, united_lookup, imm_nts, ild_gendir, eosz_dict, + debug): + """ + main entry point of the module. + """ + #dump lookup functions for each NT + #Let's call these function Level3 functions (L3) + nt_dict = {} + + #generate the L3 functions + #Every NT, that changes IMM_WIDTH, defines a L3 function. + #For example SIMM8() NT defines a L3 function that returns 1 (1 byte). + #And SIMMv() NT defines a function that gets EOSZ and returns IMM_WIDTH + #value depending on EOSZ. + + #UIMM8_1 doesn't bind IMM_WIDTH operand, it is a special case + #there is nothing to generate for it. + for nt_name in _filter_uimm1_nt(imm_nts): + array = ild_nt.gen_nt_lookup(agi, nt_name, _imm_token, + target_type=ildutil.ild_c_op_type, + level='l3') + nt_dict[nt_name] = array + + #create function that calls all initialization functions for L3 + init_f = ild_nt.gen_init_function(nt_dict.values(), + 'xed_ild_imm_l3_init') + + #dump L3 functions + ild_nt.dump_lu_arrays(agi, nt_dict.values(), _l3_c_fn, + mbuild.join('include-private',_l3_header_fn), + init_f) + + #get all IMM NT sequences that are used in patterns + #The only case of IMM sequence is when we have UIMM1() NT - the second + #immediate NT. + all_imm_seq = get_all_imm_seq(united_lookup) + debug.write('IMM SEQS: %s\n' % all_imm_seq) + + # L2 / Level2 functions: set imm_width + # Now we define functions that compute EOSZ value (using one of + # the EOSZ-resolution functions) and then use + # one of the L3 functions(that need EOSZ) to set IMM_WIDTH. + + # The names of these functions should be something like + # xed_ild_SIMMz_OSZ_NONTERM_DF64 - to define the imm-binding nonterm + # and to define the EOSZ-resolution NT sequence. + # L2 functions are defined by single ild_info_t object - by its + # eosz_nt_seq and imm_nt_seq + l2_functions = ild_codegen.gen_l2_func_list(agi, nt_dict, eosz_dict, + _ild_t_imm_member) + #append function for imm_bytes==0 + l2_functions.append(_gen_imm0_function(agi)) + + l2_headers = [ild_eosz.get_ntseq_header_fn(), + _l3_header_fn, ildutil.ild_header, + operand_storage.get_operand_accessors_fn()] + ild_codegen.dump_flist_2_header(agi, _l2_header_fn, l2_headers, + l2_functions) + + # L1 / Level1 functions: + # Now we define functions that resolve conflicts (if any) + # using modrm.reg bits, and that way decide which L2 function to + # call to set the IMM value. + # These functions will be the value of map,opcode lookup tables. + + # These functions should be dumped after we have a look on the + # united_lookup mapping in order to know what conflicts exist and + # for each conflict to create a resolution lookup table. + + # L1 functions are defined by a list of ild_info_t objects that + # have same map,opcode. + res = gen_l1_functions_and_lookup(agi, united_lookup, nt_dict) + + l1_functions,l1_lookup = res + + ild_codegen.dump_flist_2_header(agi, _l1_header_fn, [_l2_header_fn], + l1_functions) + + headers = [_l1_header_fn, ildutil.ild_private_header, + operand_storage.get_operand_accessors_fn()] + ild_codegen.dump_lookup(agi, l1_lookup, _ild_t_imm_member, + _imm_lu_header_fn, headers, + ildutil.l1_ptr_typename) + diff --git a/pysrc/ild_info.py b/pysrc/ild_info.py new file mode 100755 index 0000000..04d2910 --- /dev/null +++ b/pysrc/ild_info.py @@ -0,0 +1,175 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +#maps without AMD +#it's important that maps are correctly ordered +ild_maps = ['0x0', '0x0F', '0x0F38', '0x0F3A', + 'MAP4', 'MAP5', 'MAP6'] + +#0F0F is for AMD's 3dnow 0F0F instructions +#it's important that maps are correctly ordered +ild_maps_with_amd = ild_maps + ['0x0F0F','XMAP8','XMAP9','XMAPA'] + +#maps to dump in C header files. +ild_dump_maps = ['0x0', '0x0F'] + +def get_maps(is_with_amd): + if is_with_amd: + return ild_maps_with_amd + else: + return ild_maps + +#return maps that should be dumped in C header files. +#Now it seems that only 0 and 0F maps should be dumped. +def get_dump_maps(): + return ild_dump_maps + + +#10 is enough i think +storage_priority = 10 + + +class ild_info_t(object): + def __init__(self, insn_map=None, opcode=None, incomplete_opcode=None, + missing_bits=None, has_modrm=None, eosz_nt_seq=None, + easz_nt_seq=None, + imm_nt_seq=None, disp_nt_seq=None,ext_opcode=None, + mode=None, + priority=storage_priority): + self.insn_map = insn_map + self.opcode = opcode + + #Boolean, indicates if given opcode is incomplete + #that happens when last 3 bits of the opcode are taken + #for operand register definition like in 0x40 opcodes for push(or pop) + self.incomplete_opcode = incomplete_opcode + + #Integer, indicates number of bits that incomplete opcode misses. + #Usually 3, but added that for generality + self.missing_bits = missing_bits + + #Integer. The value of opcode << 3 + MODRM.REG when the MODRM.REG + #is the extension of the opcode. None if opcode is not extended + self.ext_opcode = ext_opcode + + self.mode = mode + + #String. Indicates whether instruction has MODRM byte + #and whether it is ignored. + #XED_ILD_HASMODRM_[TRUE|FALSE|IGNORE_MOD] + self.has_modrm = has_modrm + + #[string] - list of EOSZ-binding NT names in pattern + self.eosz_nt_seq = eosz_nt_seq + + #[string] - list of EASZ-binding NT names in pattern + self.easz_nt_seq = easz_nt_seq + + #[string] - list of IMM_WIDTH-binding NT names in pattern + self.imm_nt_seq = imm_nt_seq + + self.disp_nt_seq = disp_nt_seq + + #Integer. Indicates the priority of the object in conflict + #resolution with other objects wit same map-opcode pair. + #Priority 0 is the highest. + #For example storage's objects have priority 10 and objects + #obtained from grammar parsing have priority 0. + self.priority = priority + + #This method is important because it defines which objects conflict + def __eq__(self, other): + return (other != None and + self.insn_map == other.insn_map and + self.opcode == other.opcode and + self.has_modrm == other.has_modrm and + self.ext_opcode == other.ext_opcode and + self.mode == other.mode and + self.eosz_nt_seq == other.eosz_nt_seq and + self.easz_nt_seq == other.easz_nt_seq and + self.imm_nt_seq == other.imm_nt_seq and + self.disp_nt_seq == other.disp_nt_seq) + + #This method is not less important than __eq__ + def __ne__(self, other): + return (other == None or + self.insn_map != other.insn_map or + self.opcode != other.opcode or + self.has_modrm != other.has_modrm or + self.ext_opcode != other.ext_opcode or + self.mode != other.mode or + self.eosz_nt_seq != other.eosz_nt_seq or + self.easz_nt_seq != other.easz_nt_seq or + self.imm_nt_seq != other.imm_nt_seq or + self.disp_nt_seq != other.disp_nt_seq) + + #not currently used. But helps to conveniently sort + #objects for pretty printing (by map-opcode values) + def sort_key(self): + return (int(self.insn_map,16) << 8) + int(self.opcode, 16) + + def __str__(self): + printed_members = [] + printed_members.append('MAP\t: %s' % self.insn_map) + printed_members.append('OPCODE\t: %s' % self.opcode) + printed_members.append('EXT_OPCODE\t: %s' % self.ext_opcode) + printed_members.append('MODE\t: %s' % self.mode) + printed_members.append('INCOMPLETE_OPCODE\t: %s' % + self.incomplete_opcode) + printed_members.append('HAS_MODRM\t: %s' % self.has_modrm) + printed_members.append('EOSZ_SEQ:\t %s' % self.eosz_nt_seq) + printed_members.append('IMM_SEQ\t: %s' % self.imm_nt_seq) + printed_members.append('DISP_SEQ\t: %s' % self.disp_nt_seq) + + return "{\n"+ ",\n".join(printed_members) + "\n}" + +#convert pattern_t object to ild_info_t object +def ptrn_to_info(pattern, prio=storage_priority): + return ild_info_t(insn_map=pattern.insn_map, opcode=pattern.opcode, + incomplete_opcode=pattern.incomplete_opcode, + missing_bits=pattern.missing_bits, + has_modrm=pattern.has_modrm, + eosz_nt_seq=pattern.eosz_nt_seq, + easz_nt_seq=pattern.easz_nt_seq, + imm_nt_seq=pattern.imm_nt_seq, + disp_nt_seq=pattern.disp_nt_seq, + ext_opcode=pattern.ext_opcode, + mode=pattern.mode, + priority=prio) + +#Get pattern_t object and set of infos , create info_t object and add it +#to the set +def add_ild_info(info_set, pattern): + info = ptrn_to_info(pattern) + info_set.add(info) + +#info object has property 'priority' and min priority +#will win the conflict resolution. +#For example storage's info objects have priority=10, so that +#info objects obtained from grammar (priority=0) could override them +def get_min_prio_list(info_list): + if len(info_list) == 0: + return [] + min_prio = min(info_list, key=lambda(x): x.priority).priority + min_list = [] + for info in info_list: + if info.priority == min_prio: + min_list.append(info) + return min_list + + diff --git a/pysrc/ild_modrm.py b/pysrc/ild_modrm.py new file mode 100755 index 0000000..d036ff5 --- /dev/null +++ b/pysrc/ild_modrm.py @@ -0,0 +1,139 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import ild_info +import ild_codegen +import genutil +import ildutil + +_modrm_nt = 'MODRM()' +_vmodrm = 'VMODRM' +_modrm_bind = 'MOD[' +_mod3_req = 'MOD=3' + +_modrm_header_fn = 'xed-ild-modrm.h' + +_has_modrm_true = 'XED_ILD_HASMODRM_TRUE' +_has_modrm_false = 'XED_ILD_HASMODRM_FALSE' +_has_modrm_undef = 'XED_ILD_HASMODRM_UNDEF' +#for MOV_DR and MOV_CR that ignore MODRM.MOD bits +_has_modrm_ignore = 'XED_ILD_HASMODRM_IGNORE_MOD' +_has_modrm_typename = 'xed_uint8_t' + +_hasmodrm_defines = { + _has_modrm_false : 0, + _has_modrm_true : 1, + _has_modrm_ignore : 2, + _has_modrm_undef : 3, + } + + +#FIXME: do we want to check by NT names or do something similar to +#EOSZ/EASZ - find all NTs that bind interesting operand and look +#for them in the pattern. +#FIXME2: it seems we need to check VMODRM() NT too +def get_hasmodrm(ptrn): + """ + Return XED_ILD_HASMODRM_[TRUE|FALSE|IGNORE_MOD] string + """ + if is_ignored_mod(ptrn): + return _has_modrm_ignore + has_modrm = (_modrm_nt in ptrn) or (_modrm_bind in ptrn) + return _bool2has_modrm_str(has_modrm) + +def is_ignored_mod(ptrn): + """ + Return True|False if MODRM.MOD bits are ignored + e.g. MOV_DR instruction + """ + #if MODRM.MOD is ignored then MODRM's fields should + #be bounded, but it should not be a VMODRM (SIMD + #instructions, there should not be MODRM() that uses + #MODRM's fields and there should not be a constraint MOD=3 + #which is usage of MODRM.MOD too. + return (_modrm_bind in ptrn and + not _vmodrm in ptrn and + not _modrm_nt in ptrn and + not _mod3_req in ptrn) + +def _resolve_modrm_conflict(info_list): + """ + Not trying to dispatch by prefixes, mode or anything else. + Because modrm doesn't have such conflicts. + """ + return None + +def _is_modrm_conflict(info_list): + if len(info_list) <= 1: + return False + first = info_list[0] + for info in info_list[1:]: + if first.has_modrm != info.has_modrm: + return True + return False + +def _bool2has_modrm_str(val): + """ + Returns C define string for has_modrm + """ + if val == None: + return _has_modrm_undef + if val: + return _has_modrm_true + return _has_modrm_false + + +def gen_modrm_lookup(united_lookup, debug): + modrm_lookup = {} + for insn_map in ild_info.get_dump_maps(): + modrm_lookup[insn_map] = {} + for opcode in range(0, 256): + info_list = united_lookup.get_info_list(insn_map, hex(opcode)) + info_list = ild_info.get_min_prio_list(info_list) + if len(info_list) == 0: + #no infos in map-opcode, illegal opcode + has_modrm = _has_modrm_undef + elif _is_modrm_conflict(info_list): + #conflict in has_modrm value in map-opcode's info_list + #try to resolve + info = _resolve_modrm_conflict(info_list) + if not info: + ildutil.ild_err( + 'UNRESOLVED CONFLICT IN MODRM\n infos:\n%s\n' % + "\n".join([str(info) for info in info_list])) + has_modrm = info.has_modrm + else: + #several infos that agree on has_modrm property, we can choose + #any of them to get has_modrm + info = info_list[0] + has_modrm = info.has_modrm + modrm_lookup[insn_map][hex(opcode)] = has_modrm + return modrm_lookup + + + +def work(agi, united_lookup, debug): + """ + dumps MODRM lookup tables to xed_ild_modrm.h + """ + modrm_lookup = gen_modrm_lookup(united_lookup, debug) + ild_codegen.dump_lookup(agi, modrm_lookup, 'has_modrm', _modrm_header_fn, + [], _has_modrm_typename, + define_dict=_hasmodrm_defines) + + diff --git a/pysrc/ild_nt.py b/pysrc/ild_nt.py new file mode 100755 index 0000000..8990199 --- /dev/null +++ b/pysrc/ild_nt.py @@ -0,0 +1,600 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import genutil +import ildutil +import codegen +import copy +import re +import opnds + + +def is_target_op(agi, op, target_op): + """ + @param op: instruction_info_t.operands[i] - the binded operand by an NT row + @param target_op: string - the name of the target operand + @param agi: all_generator_info_t - the main generator's data structure + (as usual) + Function returns true if op's name is target_op or if op is a macro which + expansion contains target_op + """ + state_dict = agi.common.state_bits + return (op.name.upper() == target_op or + (op.name.lower() in state_dict and + target_op in state_dict[op.name.lower()].dump_str())) + +#Parameters: + +def get_setting_nts(agi, opname): + """ + @param opname: string - name of the operand + Function returns a list of strings which are the names of NTs that bind + an operand with name opname + """ + state_dict = agi.common.state_bits + nt_set = set() + for nt_name in agi.nonterminal_dict.keys(): + gi = agi.generator_dict[nt_name] + parser = gi.parser_output + for rule in parser.instructions: + for op in rule.operands: + if is_target_op(agi, op, opname): + nt_set.add(nt_name) + return nt_set + + +def get_nt_seq(ptrn_wrds, nt_list, implied_nt=None): + """ + @param ptrn_wrds: [string] - list of tokens of pattern string of an + instruction (result of split() on pattern string) + + @param nt_list: [string] - list of strings which are names of NTs that + we look for in the pattern + + @param implied_nt: string - name of an NT which is prepended to the + output list this NT is implied and doesn't appear in the instruction's + pattern (e.g. OSZ_NONTERM) + + @return: a list of strings which are names of NTs from nt_list that + were found in ptrn_wrds first NT is implied default NT (for EOSZ for + example it's OSZ_NONTERM) + """ + seq = [] + if implied_nt: + seq.append(implied_nt) + + for w in ptrn_wrds: + no_brackets = re.sub('[(][)]', '',w) + if no_brackets in nt_list: + seq.append(no_brackets) + return seq + + +def gen_nt_seq_lookup(agi, nt_seq, target_op, target_type=None): + """ + @param nt_seq: [string] - list of strings which are names of the NTs that + bind the target_op. Nts appear in the same order as they were found + in instruction's pattern (e.g [OSZ_NONTERM, DF64] + + @param target_op: string - name of the operand that is bound by NTs + (e.g. EOSZ) + + @param target_type: string - the type of target operand + (xed_bits_t for example). + Used when we need to override the type specified in grammar. + + @return: codegen.array_gen_t lookup array which defines a mapping + from certain operand deciders to the value of target_op + e.g. a mapping from {OSZ, MOD, REXW} to EOSZ + This mapping is defined by the sequence of NTs (nt_seq) + by collapsing individual mapping of each NT into one combined mapping + """ + + #first NT in sequence is the implicit base one + #for EOSZ and EASZ. For immediate lookup we don't have such + #a notion of implicit base NT. + state_space = agi.common.state_space + gi = agi.generator_dict[nt_seq[0]] + argnames = generate_lookup_function_basis(gi,state_space) + base_dict = gen_lookup_dict(agi, nt_seq[0], target_op, argnames) + if not base_dict: + return None + map_list = [] + for nt_name in nt_seq[1:]: + lookup_dict = gen_lookup_dict(agi, nt_name, target_op, argnames) + if not lookup_dict: + return None + map_list.append(lookup_dict) + + comb_map = combine_mapping_seq(base_dict, map_list) + if not comb_map: + return None + return gen_lookup_array(agi, nt_seq, comb_map, target_op, argnames, + target_type) + +#nt_name: string - the name of NT that defines the mapping +#target_opname: string - the name of the operand the mapping maps to +#(e.g. EOSZ) +#argnames: {string -> { string -> Boolean } } a dict of dicts +#first key is operand decider name, second key is operand decider value +#argnames['MOD']['0'] == True iff operand decider MOD can have value '0' +#Returns list of tuples +# [ ([{token:string -> index_value:string}], return-value:string) ] +#this list defines a mapping from operand deciders values to target_op value +#described by given NT (with nt_name) +#FIXME: sometimes (ONE():: NT) target_op bounded by all different rows has +#same value. It happens when there are other operands bounded too. We need +#to detect such cases and generate empty dict so that constant function would +#be generated for such NTs. +def gen_lookup_dict(agi, nt_name, target_opname, argnames): + gi = agi.generator_dict[nt_name] + options = agi.common.options + state_space = agi.common.state_space + operand_storage = agi.operand_storage + + + all_values = [] + for ii in gi.parser_output.instructions: + #First check if current rule sets the operand, if not + #go to next rule + target_op = None + for op in ii.operands: + if is_target_op(agi, op, target_opname): + target_op = op + break + + if not target_op: + continue + + state_dict = agi.common.state_bits + #if binding operand is a macro + if target_op.name.lower() in state_dict: + op_spec = state_dict[target_op.name.lower()].list_of_str + found_op = False + for w in op_spec: + if w.startswith(target_opname): + found_op = True + break + if not found_op: + ildutil.ild_err("Failed to find operand %s" % str(target_op)) + expansion = w + target_op = opnds.parse_one_operand(expansion) + + # the operand is the table output value + if target_op.bits: # RHS of the 1st operand + this_row_output = target_op.bits + else: + ildutil.ild_err("NTLUF operand %s" % str(target_op)) + # Now we must get the table index values as a dictionary + indices = _generate_lookup_function_indices(ii,state_space,argnames) + all_values.append((indices,this_row_output)) + return all_values + +def get_nt_from_lufname(fname): + suffix = re.sub('xed_lookup_function_', '', fname) + nt = re.sub('_getter', '', suffix) + return nt + +def get_lufn_suffix(array): + lufn = array.lookup_fn.function_name + suffix = re.sub('xed_lookup_function_', '', lufn) + return suffix + + +def get_lufn(nt_seq, target_op, flevel=''): + lu_name = '_'.join(nt_seq) + + lu_fn = 'xed_lookup_function_%s_%s' % (lu_name, target_op) + if len(flevel) > 0: + lu_fn += '_%s' % flevel + return lu_fn + +def gen_lu_names(nt_seq, target_op, level=''): + """ + @param nt_seq: List of NT names. + @type nt_seq: C{[string]} + + @param target_op: Name of bounded operand. + @type target_op: C{string} + + @return (lu_arr, init_fn, lu_fn): + Tuple of 3 names: lookup array name, init function name and + lookup function name. + """ + lu_name = '_'.join(nt_seq) + lu_arr = 'xed_lookup_%s_%s' % (lu_name, target_op) + init_fn = 'xed_lookup_function_init_%s_%s' % (lu_name, target_op) + lu_fn = get_lufn(nt_seq, target_op, flevel=level) + return (lu_arr, init_fn, lu_fn) + +def get_luf_name_suffix(luf_name): + return re.sub('xed_lookup_function_', '', luf_name) + + +def _is_constant_mapping(val_dict): + """ + @param val_dict: + Defines the mapping, by defining an output value for each row of + constrains. Each row is defined by a dictionary of operand names to + operand values. + @type val_dict: + [ ([ dict(opname:string -> opval:string) ], value:string) ] + The return type of gen_lookup_dict function + + @return bool: True if mapping defined by val_dict always returns same + value. And hence we can define a constant function, not dependent on + parameters. + This is relevant for ONE() NT that has same IMM_WIDTH output operand + value for several different index values. + A good question is why it was defined that way. + """ + #check if we have same output values for all rows, + #then we should generate a constant function, independent from parameters + #This happens in ONE() NT for IMM_WIDTH + #ONE() seems to be pretty useless NT. + (_first_indices, first_output) = val_dict[0] + all_same = True + for _indices,out_val in val_dict[1:]: + if out_val != first_output: + all_same = False + break + return all_same + + +#Parameters: +#nt_seq: [string] - list of NT names that define the mapping +#val_dict: [ ([{token:string -> index_value:string}], return-value:string) ] +#(the type returned by gen_lookup_dict), it defines the mapping +#opname: string - the name of target operand e.g. EOSZ +#argnames: {string -> { string -> Boolean } } a dict of dicts +#optype: string - the type of target op (the return type of the +#lookup function). If optype is specified it is used instead of +#agi's defined operand type for opname. Useful for IMM_WIDTH which is defined +#as xed_uint8_t by grammar, but for ILD purposes should be natural int +#(xed_bits_t), because byte-sized operations are sub-optimal in performance in +#32 or 64 modes. +#first key is operand decider name, second key is operand decider value +#argnames['MOD']['0'] == True iff operand decider MOD can have value '0' +#returns codegen.array_gen_t lookup array that defines the mapping +def gen_lookup_array(agi, nt_seq, val_dict, opname, argnames, + optype=None, flevel=''): + operand_storage = agi.operand_storage + (lu_arr, init_fn, lu_fn) = gen_lu_names(nt_seq, opname, level=flevel) + if not optype: + luf_return_type = operand_storage.get_ctype(opname) + else: + luf_return_type = optype + array= codegen.array_gen_t(lu_arr, type=luf_return_type, target_op=opname) + + #check if the mapping is constant (ONE() NT), if so, + #redefine the mapping to have no index operands so that + #we will have lookup function with no parameters for this + #mapping + if _is_constant_mapping(val_dict): + argnames = {} + (_first_indices, value) = val_dict[0] + val_dict = [([{}], value)] + + for od in argnames.keys(): + values = argnames[od].keys() + array.add_dimension(operand_storage.get_ctype(od), + min(values), + max(values) + 1, + argname = od) + # fill in all the values + for list_of_dict_of_indices, value in val_dict: + for index_dict in list_of_dict_of_indices: + array.add_value(index_dict, value) + + static = True + + #FIXME: these functions should be inline, but that leads to a compilation + #error on linux : + # cc1: warnings being treated as errors + # error: inline function ... declared but never defined + #making it not inline until I figure out how to fix that warning + inline = True + array.gen_lookup_function(lu_fn, static=static, inline=inline, + check_const=True) + + array.make_initialization_function(init_fn) + return array + +#Parameters: +#array_list: [codegen.array_t] - list of arrays, each of them defines +#a c array, array init function and array lookup function +#c_fn: string - name of the c file, where the arrays and function definitions +#should be dumped +#header_fn: string - name of the .h file where declarations of fucntions should +#be dumped +#Dumps arrays and init and lookup functions if c and h files +def dump_lu_arrays(agi, array_list, c_fn, header_fn, init_f=None): + c_file = agi.open_file(c_fn, start=False) + header_file = agi.open_file(header_fn, start=False) + #header_file.replace_headers(['xed-types.h', 'xed-reg-enum.h']) + header_file.start() + + c_file.start() + for array in array_list: + #the optimization for constant functions - we do not need + #arrays for them since their lookup functions are just "return const;" + if not array.is_const_lookup_fun(): + c_file.add_code("/*Array declaration*/") + c_file.add_code(array.emit_declaration(static=False)) + c_file.add_code("/*Array initialization*/") + array.init_fn.emit_file_emitter(c_file) + + init_decl = array.emit_initialization_function_header() + header_file.add_code(init_decl) + + #lookup functions need to be inline, hence we should put them + #in header + for array in array_list: + #the optimization for constant functions - we do not need + #arrays for them since their lookup functions are just "return const;" + if not array.is_const_lookup_fun(): + #declare the lookup arrays + header_file.add_code("/*Array declaration*/") + header_file.add_code(array.emit_declaration(static=False, + extern=True)) + + #define the function + header_file.add_code("/*Lookup function*/") + array.lookup_fn.emit_file_emitter(header_file) + + if init_f: + init_f.emit_file_emitter(c_file) + init_decl = init_f.emit_header() + header_file.add_code(init_decl) + c_file.close() + header_file.close() + + +def gen_init_function(arr_list, name): + #make a function_object_t to call all the individual init routines + overall_init_f = codegen.function_object_t(name,return_type='void') + for array in arr_list: + if not array.is_const_lookup_fun(): + overall_init_f.add_code_eol(array.init_fn.function_name + '()') + return overall_init_f + +#just for debugging. +#Parameters: +#nt_name: string - the name of the NT +#target_op: string - the name of the target operand +#target_type: string - the type of target operand (xed_bits_t for example). +#Used when we need to override the type specified in grammar. +#return lookup array:codegen.array_t and for a single NT +def gen_nt_lookup(agi, nt_name, target_op, target_type=None, level=''): + state_space = agi.common.state_space + gi = agi.generator_dict[nt_name] + argnames = generate_lookup_function_basis(gi,state_space) + all_values = gen_lookup_dict(agi, nt_name, target_op, argnames) + return gen_lookup_array(agi, [nt_name], all_values, target_op, argnames, + target_type, flevel=level) + +#Parameters: +#base_row: {op_name:string -> op_val:string} +#row: {op_name:string -> op_val:string} +#Rows here are the dispatching rows in NT definitions in grammar. +#something like +#MOD=0 | +#MOD=1 | +#MOD=2 | +#each one of these is a row. +#base_row matches a row if all constrains that are true in row are true +#also in base_row +#for example base_row REXW=0 MOD=0 matches a row MOD=0 +#ASSUMPTION: base_row has all operands mentioned, +#e.g for EOSZ base_row dict must have OSZ,MOD,REXW operands as keys +def row_match(base_row, row): + #ildutil.ild_err("ILD_DEBUG BASE ROW %s" % (base_row,)) + for (op, val) in row.items(): + if op in base_row: + if base_row[op] != val: + return False + else: + ildutil.ild_err("BASE ROW %s doesn't have OD %s from row %s" % + (base_row, op, row)) + return None + return True + +#base_mapping and all_values are both of the type +#[ ([dict token->index_value], return-value) ] +#the gen_lookup_dict return type. +#For each row defined in all_values mapping that matches a row from bas_mapping +#this function sets the mapped value to the all_values mapping value. +#For example when we have OSZ_NONTERM-CR_BASE NT sequence, +#base_mapping is defined by OSZ_NONTERM and all_values mapping is +#defined by CR_BASE +#and we need to override the value of EOSZ in those rows of OSZ_NONTERM +#mapping, that match rows from CR_BASE mapping. +#This function behaves similarly to what decode graph traversing does to EOSZ +#operand value when it sees two EOSZ-binding NTs in the pattern. +def override_mapping(base_mapping, all_values): + for indices,value in all_values: + for row in indices: + temp_map = [] + for base_indices,base_value in base_mapping: + for base_row in base_indices: + #if indices match (it is the same logical constraint) + #we override the value those indices map to + is_match = row_match(base_row, row) + #None is returned on internal error. + #We dontexit(1) on this because we don't want to break + #xed's build if ild's build fails. + #This is temporary. + if is_match == None: + return None + elif row_match(base_row, row): + temp_map.append(([base_row], value)) + else: + temp_map.append(([base_row], base_value)) + base_mapping = temp_map + return base_mapping + + +#Parameters: +#base_mapping: [ ([{token:string -> index_value:string}], return-value:string)] +#the gen_lookup_dict return type, it is the object that defines the mapping +#map_list: list of objects of the same type with base_mapping +#take a list of mapping objects and return a mapping +#object that is a result of overriding of first mapping by next ones +def combine_mapping_seq(base_mapping, map_list): + cur_map = base_mapping + for all_values in map_list: + #this one overrides values of those entries in base_mapping + #that match entries in all_values mapping + #stores overriden mapping in cur_map + cur_map = override_mapping(cur_map, all_values) + if not cur_map: + return None + return cur_map + + + +#Parameters: +#ii: generator.instruction_info_t - a row from NT definition +#state_space: {opname:string -> [op_val:string] } a dict from operand +#name to a list of its possible values. Obtained from generator +#argnames: {string -> { string -> Boolean } } a dict of dicts +#first key is operand decider name, second key is operand decider value +#argnames['MOD']['0'] == True iff operand decider MOD can have value '0' +#Returns [{opname:string -> op_val:string}] - a list of dicts, each +#defining a row in NT definition. It is a list, because ii can define +#several logical rows e.g for EOSZ: +#if ii represents row: MOD=0 OSZ!=0 +#then we will return representation of rows: +#MOD=0 OSZ=1 REXW=1 +#MOD=0 OSZ=1 REXW=0 +def _generate_lookup_function_indices(ii,state_space,argnames): + """Return a list of dictionaries where each dictionary is a + complete set of token->index_value""" + + indices = {} # dict describing index -> value or list of vlaues + for bt in ii.ipattern.bits: + if bt.is_operand_decider(): + + if bt.test == 'eq': + indices[bt.token] = bt.requirement + elif bt.test == 'ne': + all_values_for_this_od = state_space[bt.token] + trimmed_vals = filter(lambda (x): x != bt.requirement, + all_values_for_this_od) + #Add the list of values; We flaten it later + indices[bt.token] = trimmed_vals + else: + ildutil.ild_err("Bad bit test (not eq or ne) in " + ii.dump_str()) + elif bt.is_nonterminal(): + pass # FIXME make a better test + else: + #We should ignore non-operand deciders: IMM Nts have captures in their + #rules, and it is OK, they don't affect mappings defined by NTs + pass + #ildutil.ild_err("Bad pattern bit (not an operand decider) in %s" % + # ii.dump_str()) + #return None + + #in order to match lookup rows correctly, we need to have all indices + #mentioned in the "indices" dict. + #For example if all operand deciders are [OSZ, REXW, MOD] and in the + #ii.ipattern we have only MOD=0 mentioned, it means that this row matches + #all combinations of MOD=0 with all other values for OSZ and REXW. + #We need to add all those combinations explicitly here, otherwise later + #when we match rows MOD=0 row may match MOD=0 OSZ=0 row and also + #MOD=0 OSZ=1 row and these rows define different binding value, we will not + #know which value to choose. + #of course there are other ways to solve this problem, but this seems to be + #the easiest. + for bt_token in argnames.keys(): + if not (bt_token in indices): + indices[bt_token] = argnames[bt_token].keys() + + + ### NOW, we must flatten any list-valued RHS's & return a list of + ### dicts where the RHS is always a scalar. + indices_flattened = genutil.flatten_dict(indices) + + return indices_flattened + +def add_op_deciders_temp(ipattern, state_space, argnames): # NOT USED + """ + @param ipattern: the ipattern member of instruction_info_t + @param state_space: dictionary from op deciders tokens to list + of their legal values. + + @param argnames: dict where to append op deciders values: + 2D argnames[op_decider_token][accepted_value]=True + """ + for bt in ipattern.bits: + if bt.is_operand_decider(): + if bt.token not in argnames: + argnames[bt.token] = {} + + if bt.test == 'eq': + argnames[bt.token][bt.requirement]=True + elif bt.test == 'ne': + argnames[bt.token]['!=' + ('%s'%bt.requirement)]=True + else: + ildutil.ild_err("Bad bit test (not eq or ne) in %s" % + ipattern) + return + +def add_op_deciders(ipattern, state_space, argnames): + """ + @param ipattern: the ipattern member of instruction_info_t + @param state_space: dictionary from op deciders tokens to list + of their legal values. + + @param argnames: dict where to append op deciders values: + 2D argnames[op_decider_token][accepted_value]=True + """ + for bt in ipattern.bits: + if bt.is_operand_decider(): + if bt.token not in argnames: + argnames[bt.token] = {} + + if bt.test == 'eq': + argnames[bt.token][bt.requirement]=True + elif bt.test == 'ne': + all_values_for_this_od = state_space[bt.token] + trimmed_vals = filter(lambda (x): x != bt.requirement, + all_values_for_this_od) + for tv in trimmed_vals: + argnames[bt.token][tv]=True + else: + ildutil.ild_err("Bad bit test (not eq or ne) in %s" % + ipattern) + return + +def extend_2d_dict(dst, src): # NOT USED + for key1 in src: + if key1 in dst: + dst[key1].update(src[key1]) + else: + dst[key1] = src[key1] + return + +def generate_lookup_function_basis(gi,state_space): + """Return a dictionary whose values are dictionaries of all the values + that the operand decider might have""" + argnames = {} # tokens -> list of all values for that token + for ii in gi.parser_output.instructions: + add_op_deciders(ii.ipattern, state_space, argnames) + return argnames + diff --git a/pysrc/ild_phash.py b/pysrc/ild_phash.py new file mode 100755 index 0000000..b34dfa7 --- /dev/null +++ b/pysrc/ild_phash.py @@ -0,0 +1,577 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import random +import math +import sys +import genutil +import ildutil +import collections +import itertools +import operator +import ild_codegen +import codegen +import ild_nt +import hashmul +import hashfks +import hashlin +import xedhash +# phash means "perfect hash". + +_l1_bucket_max = 8 # FIXME: also in hashfks.py + + +#FIXME: using 64 bits for _hkey_ctype because sometimes 16bi-UIMM00 is +#a constraint and we are out of 32 bits for hashing. +#However, this takes too much space. We can check how many bits +#are used and decide based on that about the key type, and in most cases +#that will be 32 bits. +_notfound_str = '0' + +class phash_t(object): + def __init__(self, cdict, hash_f): + self.cdict = cdict + self.hash_f = hash_f + self.x2hx = {} + self.hx2x = {} + + def is_minimal(self): + return self.hash_f.get_table_size() == len(self.cdict.tuple2rule) + + #generate the operands getters + def add_cgen_key_lines(self, fo): + #declare hash key variable + key_str = self.cdict.strings_dict['key_str'] + key_type = self.cdict.strings_dict['key_type'] + fo.add_code_eol('%s %s = 0' % (key_type,key_str)) + bit_shift = 0 + nt_lups = [] + for i,cname in enumerate(self.cdict.cnames): + access_str, lu_name = self.cdict.get_operand_accessor(cname) + nt_lups.append(lu_name) + + #constraints might have 1,2 or 3 bit widths + #and we allocate bits in the key vector appropriately + #e.g REXB operand gets only 1 bit in the key + #and RM gets 3 bits + shift_val = ('(%s)' % bit_shift) + bit_shift += self.cdict.op_widths[cname] + code = 'key += (%s) << (%s)' % (access_str, shift_val) + fo.add_code_eol(code) + fo.add_code_eol('return %s' % key_str) + return nt_lups + + def add_lookup_lines(self, fo): + + key_validation = self.hash_f.add_key_validation(self.cdict.strings_dict) + fo.add_code('%s {' % key_validation) + + actions = self.cdict.action_codegen.emit_actions() + for a in actions: + fo.add_code_eol(" " + a) + if self.cdict.action_codegen.has_fcall(): + fo.add_code_eol(" return res") + #FIXME: this is a temporary, when we will implement the iform encoding + # we will be able to remove this code + if genutil.field_check(self.cdict, 'ntluf') or \ + genutil.field_check(self.cdict, 'nt'): + fo.add_code_eol(" return 1") + fo.add_code('}') + + # get the default action that will executed when we did not hit valid + # look up table entry + default = self.cdict.action_codegen.emit_default() + fo.add_code('else{') + for line in default: + fo.add_code_eol(" %s" % line) + + fo.add_code('}') + + def add_find_lines(self, fo): + + #apply hash function on the key + hash_expr = self.hash_f.emit_cexpr(self.cdict.strings_dict['key_str']) + fo.add_code_eol('%s = %s' % (self.cdict.strings_dict['hidx_str'], hash_expr)) + #lookup entry in the table + self.add_lookup_lines(fo) + + #emit the operands lookup function + def add_op_lu_function(self,fo,lu_function): + if hasattr(self.hash_f,'emit_cvar_decl'): + fo.add_code_eol(self.hash_f.emit_cvar_decl()) + + fo.add_code_eol('%s %s = 0' % (self.cdict.strings_dict['key_type'], + self.cdict.strings_dict['key_str'])) + fo.add_code_eol('%s %s = 0' % (self.cdict.strings_dict['hidx_type'], + self.cdict.strings_dict['hidx_str'])) + + #Initializing res to 1 since it will not always be read. + if self.cdict.action_codegen.has_fcall(): + fo.add_code_eol('%s %s = 1' % (self.cdict.strings_dict['hidx_type'], + 'res')) + obj_str = self.cdict.strings_dict['obj_str'] + #FIXME: this is a temporary, when we will implement the iform encoding + # we will be able to remove this code + if genutil.field_check(self.cdict, 'ntluf'): + fo.add_code_eol('xed3_operand_set_outreg(%s,arg_reg)' % obj_str) + + lu_code = 'key = %s(%s)' % (lu_function, obj_str) + fo.add_code_eol(lu_code) + + def add_lu_table(self, fo): + need_validation = self.hash_f.need_hash_index_validation() + if self.cdict.action_codegen.no_actions() and not need_validation: + #if we do not have any actions and we do not need to do + #hash index validation, we do not need to add a look up + #table. + return + + actions_str = self.cdict.action_codegen.get_actions_desc() + entry_desc = 'typedef struct {' + if need_validation: + entry_desc += 'xed_uint32_t key;' + entry_desc += ' %s} ' % actions_str + entry_type = self.cdict.strings_dict['lu_entry'] + entry_desc += '%s' % entry_type + + + fo.add_code_eol(entry_desc) + arr_def = 'static const %s %s[%d] = {' % ( + entry_type, + self.cdict.strings_dict['table_name'], + self.hash_f.get_table_size() ) + fo.add_code(arr_def) + + elems = [] + + for hx in range(0, self.hash_f.get_table_size()): + if hx in self.hx2x: + x = self.hx2x[hx] + t = self.cdict.int2tuple[x] + actions = self.cdict.action_codegen.get_values(t) + ptrn = self.cdict.get_ptrn(t) + + if need_validation: + elem = '/*h(%d)=%d %s*/ {%d, %s}' + elem = elem % (x, hx, ptrn , x, actions) + else: + elem = '/*h(%d)=%d %s*/ {%s}' + elem = elem % (x, hx, ptrn , actions) + else: + + #FIXME: make hx signed int and fill empty + #slots with -1? + #Seems it is enough to set value=0, saying that it's an + #illegal instruction + + # FIXME: x is always just one slot ['0']. That works + # correctly but the code logic makes absolutely no + # sense. + x = self.cdict.action_codegen.get_empty_slots() + empty_val = ['0'] + x + elem = '/*empty slot1 */ {%s}' % (",".join(empty_val)) + if hx != (self.hash_f.get_table_size()-1): + elem += ',' + fo.add_code(elem) + + fo.add_code_eol('}') + + def get_find_fn(self, func_id): + return '%s_%s' %(_find_fn_pfx, func_id) + + def gen_find_fos(self, fname): + obj_str = self.cdict.strings_dict['obj_str'] + obj_type = self.cdict.strings_dict['obj_type'] + key_str= self.cdict.strings_dict['key_str'] + hidx_str = self.cdict.strings_dict['hidx_str'] + const = self.cdict.strings_dict['obj_const'] + lu_namespace = self.cdict.strings_dict['lu_namespace'] + + #FIXME: this is a temporary, when we will implement the iform encoding + # we will be able to remove this code + if genutil.field_check(self.cdict, 'ntluf') or \ + genutil.field_check(self.cdict, 'nt'): + return_type = 'xed_uint32_t' + else: + return_type = self.cdict.action_codegen.get_return_type() + static = self.cdict.strings_dict['static'] + fo = codegen.function_object_t(fname, + return_type=return_type, + static=static, + inline=False) + + lu_operands = '_'.join(self.cdict.cnames) + lu_operands_fn = 'xed_lu_%s' % lu_operands + key_ctype = self.cdict.strings_dict['key_type'] + operand_lu_fo = codegen.function_object_t(lu_operands_fn, + return_type=key_ctype, + static=False, + inline=False, + force_no_inline=True) + ild_arg = "%s%s* %s" % (const,obj_type, obj_str) + fo.add_arg(ild_arg) + if genutil.field_check(self.cdict, 'ntluf'): + fo.add_arg('xed_reg_enum_t arg_reg') + operand_lu_fo.add_arg(ild_arg) + #add key-computing code (constraints tuple to integer) + nt_lups = self.add_cgen_key_lines(operand_lu_fo) + #several non terminals has special getter functions + #the add-cgen_kiet function returns a list of all the nt_lups and + #regular cnames + lu_operands_fn = 'xed_%s_lu_%s' % (lu_namespace,'_'.join(nt_lups)) + operand_lu_fo.set_function_name(lu_operands_fn) + + #add the operands lookup function + self.add_lu_table(fo) + self.add_op_lu_function(fo,lu_operands_fn) + self.add_find_lines(fo) + + return ([fo],operand_lu_fo) + + def __str__(self): + lines = ['-----------PHASH-------------'] + lines.append('tuple scheme:') + line = '' + lines.append(' '.join(self.cdict.cnames)) + lines.append('m=%d' % self.hash_f.get_table_size()) + lines.append('%s' % self.hash_f) + lines.append('tuple x -> value') + for tuple_val in self.tuple_dict.keys(): + x = self.t2x[tuple_val] + value = self.tuple_dict[tuple_val] + line = '%s %s -> %s' % (tuple_val,x, str(value)) + lines.append(line) + lines.append('-------------------------------------') + return '\n'.join(lines)+ '\n' + + def get_size(self): + return self.hash_f.get_table_size() + + def update_stats(self, stats): + stats['3. #hashes'] += 1 + size = self.get_size() + stats['2. #hentries'] += size + stats['4. #min_hashes'] += self.is_minimal() + if size <= 10: + stats['5. #cdict_size_1_to_10'] += 1 + elif 10 < size and size <= 20: + stats['6. #cdict_size_10_to_20'] += 1 + elif 20 < size and size <= 100: + stats['7. #cdict_size_20_to_100'] += 1 + else: + stats['8. #cdict_size_at_least_100'] += 1 + +class l1_phash_t(phash_t): + def __init__(self, cdict, hash_f): + phash_t.__init__(self, cdict, hash_f) + for t,x in cdict.tuple2int.iteritems(): + hash_val = self.hash_f.apply(x) + if hash_val in self.x2hx.values(): + msg = "l1_phash_t: %s\n function is not perfect!\n" + msg += 'hashval=%d , x2hx: %s' % (hash_val, self.x2hx) + ildutil.ild_err(msg) + self.x2hx[x] = hash_val + self.hx2x[hash_val] = x + + # the index attribute is used to determine the ordinal of the emit + # rule, adding 1 since legal hash values starts in 0 but + # legal ordinal starts at 1 + self.cdict.tuple2rule[t].index = hash_val + 1 + + #for key sequence postprocessing analysis + #sys.stderr.write("KEYS:" + " ".join(map(str,sorted(self.x2hx.keys()))) + '\n') + + def __str__(self): + lines = ['-----------1-LEVEL-PHASH-------------'] + lines.append('tuple scheme:') + line = '' + lines.append(' '.join(self.cdict.cnames)) + lines.append('m=%d' % self.hash_f.get_table_size()) + lines.append('%s' % self.hash_f) + lines.append('tuple x h(x) -> value') + for tuple_val in sorted(self.cdict.tuple2rule.keys()): + x = self.cdict.tuple2int[tuple_val] + ptrn = self.cdict.get_ptrn(tuple_val) + action = self.cdict.action_codegen.get_values(tuple_val) + hx = self.x2hx[x] + line = '%s %s %s -> %s, %s' % (tuple_val,x, hx, ptrn, action) + lines.append(line) + lines.append('-------------------------------------') + return '\n'.join(lines) + '\n' + +class l2_phash_t(phash_t): + def __init__(self, cdict, hash_f): + global _l1_bucket_max + phash_t.__init__(self, cdict, hash_f) + + hx2tuples = collections.defaultdict(list) + for t,x in self.cdict.tuple2int.iteritems(): + hx = self.hash_f.apply(x) + if len(hx2tuples[hx]) >= _l1_bucket_max: + msg = "l2_phash_t: function does not distribute well!\n" + msg += 'hashval=%d , hx2tuples: %s' % (hx, hx2tuples) + ildutil.ild_err(msg) + hx2tuples[hx].append(t) + self.x2hx[x] = hx + self.hx2x[hx] = x + + self.hx2phash = {} + for hx,tuples in hx2tuples.iteritems(): + new_cdict = self.cdict.filter_tuples(tuples) + + # try (1)linear, then (2)hashmul then (3) fks for the 2nd + # level of hash function. + phash = None + if _is_linear(new_cdict.int2tuple.keys()): + phash = _get_linear_hash_function(new_cdict) + if not phash: + phash = _find_l1_phash_mul(new_cdict) + if not phash: + phash = _find_l1_phash_fks(new_cdict) + + if phash: + self.hx2phash[hx] = phash + else: + lines = [] + for k,v in new_cdict.tuple2rule.items(): + lines.append('%s -> %s'% ((k,), v)) + str = '\n'.join(lines) + ildutil.ild_err("Failed to find l1 phash for dict %s" % + str) + + def add_lu_type(self, fo): + if genutil.field_check(self.cdict, 'ntluf') or \ + genutil.field_check(self.cdict, 'nt'): + ret_type = 'xed_uint32_t' + else: + ret_type = self.cdict.action_codegen.get_return_type() + fname = self.cdict.strings_dict['luf_name'] + param_name = "%s%s*" % (self.cdict.strings_dict['obj_const'], + self.cdict.strings_dict['obj_type']) + luf_type = "typedef %s (*%s)(%s)" % (ret_type, fname, param_name) + fo.add_code_eol(luf_type) + + lu_entry = self.cdict.strings_dict['lu_entry'] + entry_desc = 'typedef struct {xed_uint32_t key;' + entry_desc += ' %s l2_func;} %s' % (fname, lu_entry) + fo.add_code_eol(entry_desc) + + def add_lu_table(self, fo, hx2fo): + self.add_lu_type(fo) + tname = self.cdict.strings_dict['table_name'] + entry = self.cdict.strings_dict['lu_entry'] + arr_def = 'static const %s %s[%d] = {' % (entry, tname, self.hash_f.get_table_size()) + fo.add_code(arr_def) + + elems = [] + #invert the x2hx mapping + hx2x = dict((hx,x) for x,hx in self.x2hx.iteritems()) + + for hx in range(0, self.hash_f.get_table_size()): + if hx in hx2fo: + l1_fo = hx2fo[hx] + x = hx2x[hx] + elem = '/*h(%d)=%d */ {%d, %s},' + elem = elem % (x, hx, x, l1_fo.function_name) + else: + #FIXME: make hx signed int and fill empty + #slots with -1? + #Seems it is enough to set value=0, saying that it's an + #illegal instruction + elem = '/*empty slot2 */ {0, xed_phash_invalid},' + fo.add_code(elem) + + fo.add_code_eol('}') + + def add_lookup_lines(self, fo): + hentry_str ='%s[%s]' % (self.cdict.strings_dict['table_name'], + self.cdict.strings_dict['hidx_str']) + #fo.add_code('if(%s.key != 0) {' % hentry_str) + fo.add_code_eol('return (*%s.l2_func)(%s)' % ( + hentry_str, + self.cdict.strings_dict['obj_str'] )) + #fo.add_code('}') + #fo.add_code_eol('return %s' % _notfound_str) + + def gen_find_fos(self, fname): + obj_str = self.cdict.strings_dict['obj_str'] + obj_type = self.cdict.strings_dict['obj_type'] + const = self.cdict.strings_dict['obj_const'] + hx2fo = {} + for hx,phash in self.hx2phash.items(): + fid = '%s_%d_l1' % (fname, hx) + (hx2fo_list,operand_lu_fo) = phash.gen_find_fos(fid) + hx2fo[hx] = hx2fo_list[0] + + fname = '%s' % fname + if genutil.field_check(self.cdict, 'ntluf') or \ + genutil.field_check(self.cdict, 'nt'): + return_type = 'xed_uint32_t' + else: + return_type = self.cdict.action_codegen.get_return_type() + + static = self.cdict.strings_dict['static'] + fo = codegen.function_object_t(fname, + return_type=return_type, + static=static, + inline=False) + fo.add_arg('%s%s* %s' % (const,obj_type,obj_str)) + self.add_lu_table(fo, hx2fo) + #we only need to override add_lookup_lines + lu_fname = operand_lu_fo.function_name + self.add_op_lu_function(fo, lu_fname) + self.add_find_lines(fo) + fos = hx2fo.values() + fos.append(fo) + #all the operand_lu_fo going to be the same so we just take the last one + return fos,operand_lu_fo + + def get_size(self): + size = self.hash_f.get_table_size() + for phash in self.hx2phash.values(): + size += phash.get_size() + return size + + def __str__(self): + lines = ['-----------2-LEVEL-PHASH-------------'] + lines.append('m=%d' % self.hash_f.get_table_size()) + lines.append('%s' % self.hash_f) + for tuple_val in self.cdict.tuple2rule.keys(): + lines.append('-------------------------------------') + lines.append('tuple x h(x) -> l1_phash') + x = self.cdict.tuple2int[tuple_val] + hx = self.hash_f.apply(x) + phash = self.hx2phash[hx] + line = '%s %s %s ->\n%s' % (tuple_val,x, hx, phash) + lines.append(line) + lines.append('-------------------------------------') + return '\n'.join(lines) + '\n' + + +def _is_linear(keys): + ''' @param keys: list of keys + @return: True is the keys in the input list are sequential + ''' + + max_key = max(keys) + min_key = min(keys) + if (max_key - min_key + 1) == len(keys): + return True + return False + +def _get_linear_hash_function(cdict): + ''' returns phash_t object with a linear_funct_t as the hash function''' + keylist = cdict.int2tuple.keys() + hash_f = hashlin.get_linear_hash_function(keylist) + return l1_phash_t(cdict, hash_f) + + + +def _find_l1_phash_fks(cdict): + hashfn = hashfks.find_fks_perfect(cdict.tuple2int.values()) + if hashfn: + return l1_phash_t(cdict, hashfn) + return None + + +def _find_candidate_lengths_mul(lst): + """Return integer lengths n, n*1.1, n*1.2, ... n*1.9, n*2""" + n = len(lst) + r = map(lambda x: int(math.ceil((1 + x/10.0)*n)), range(0,11)) + # avoid duplicates + s = set() + for a in r: + # we avoid length 1 tables for hashmul since they throw away + # all the bits and should really use the linear hash function + # stuff. + if a > 1: + s.add(a) + return sorted(list(s)) + +def _find_l1_phash_mul(cdict): + candidate_lengths = _find_candidate_lengths_mul(cdict.tuple2int) + for p in candidate_lengths: + hash_f = hashmul.hashmul_t(p) + if hash_f.is_perfect(cdict.tuple2int.itervalues()): + return l1_phash_t(cdict, hash_f) + del hash_f + return None + + + +def _find_l2_hash_mul(cdict): + """Similar to the _find_l1_phash_mul, but not looking for perfection, just + well distributed stuff""" + global _l1_bucket_max + candidate_lengths = _find_candidate_lengths_mul(cdict.tuple2int) + for p in candidate_lengths: + hash_f = hashmul.hashmul_t(p) + if xedhash.is_well_distributed(cdict.tuple2int, hash_f, _l1_bucket_max): + return hash_f + del hash_f + return None + + +def _find_l2_phash(cdict): + """Find a 2 level hash table for more complex cases""" + + # try hashmul first for the first level of the 2 level + # hash function. + hash_f = _find_l2_hash_mul(cdict) + if hash_f: + return l2_phash_t(cdict, hash_f) + + # otherwise try a FKS for the first level of the 2 level hash + # function. + hash_f = hashfks.find_fks_well_distributed(cdict.tuple2int) + if hash_f: + return l2_phash_t(cdict, hash_f) + + ildutil.ild_warn("Failed to find L2 hash function for %s" % cdict) + return None + + +def _gen_hash_one_level(cdict): + """Generate a 1 level hash function or give up""" + + # linear means all keys are sequential. not required to be zero-based. + if _is_linear(cdict.int2tuple.keys()): + return _get_linear_hash_function(cdict) + + phash = _find_l1_phash_mul(cdict) + if phash: + return phash + + phash = _find_l1_phash_fks(cdict) + if phash: + return phash + + return None + +def gen_hash(cdict): + """ Main entry point for generating hash functions.""" + + phash = _gen_hash_one_level(cdict) + if phash: + return phash + + l2_phash = _find_l2_phash(cdict) + if l2_phash: + return l2_phash + + return None + diff --git a/pysrc/ild_storage.py b/pysrc/ild_storage.py new file mode 100755 index 0000000..168a6a5 --- /dev/null +++ b/pysrc/ild_storage.py @@ -0,0 +1,63 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import collections +import ild_info +import sys + +def _die(s): + sys.stderr.write('ERROR: ') + sys.stderr.write(s) + sys.stderr.write('\n') + sys.exit(1) + +class ild_storage_t(object): + """Storage for table indexed by map and opcode. Storing lists of + ild_info_t objects.""" + + def __init__(self, is_amd=True, info_lookup=None): + self.is_amd = is_amd + if info_lookup == None: + self.lookup = {} + for insn_map in ild_info.get_maps(is_amd): + self.lookup[insn_map] = collections.defaultdict(list) + else: + self.lookup = info_lookup + + #returns by reference + def get_info_list(self, insn_map, opcode): + try: + return self.lookup[insn_map][opcode] + except: + _die("get_info_list failed map: %s opcode: %s" % + (insn_map, opcode)) + + def append_info(self, insn_map, opcode, info): + self.lookup[insn_map][opcode].append(info) + + def set_info_list(self, insn_map, opcode, info_list): + self.lookup[insn_map][opcode] = info_list + + def get_all_infos(self): + all_infos = [] + for opcode_dict in self.lookup.itervalues(): + for info_list in opcode_dict.itervalues(): + all_infos.extend(info_list) + return all_infos + + def get_maps(self): + return self.lookup.keys() diff --git a/pysrc/ild_storage_data.py b/pysrc/ild_storage_data.py new file mode 100755 index 0000000..951dc9e --- /dev/null +++ b/pysrc/ild_storage_data.py @@ -0,0 +1,27 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +import ild_info +import ild_storage + + +def gen_ild_info(): + # FIXME: can use this to define length properties for illegal opcodes + storage = ild_storage.ild_storage_t(is_amd=True) + return storage diff --git a/pysrc/ildutil.py b/pysrc/ildutil.py new file mode 100644 index 0000000..157bdc2 --- /dev/null +++ b/pysrc/ildutil.py @@ -0,0 +1,61 @@ +#-*- python -*- +# Mark Charney +# Generic utilities +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import genutil + +# ild and operand_storage +xed_strings = {'key_str':'key', + 'hidx_str':'hidx', + 'key_type':'xed_uint64_t', + 'hidx_type':'xed_uint64_t', + 'op_accessor':'xed3_operand', + 'table_name':'lu_table', + 'lu_entry':'lu_entry_t', + 'luf_name':'xed_find_func_t', + 'operand_type':'xed_operand_values_t', + 'return_type':'xed_uint32_t'} +# ild +ild_c_type = 'xed_decoded_inst_t*' +ild_c_op_type = 'xed_bits_t' + +# ild and xed3_nt +ild_header = 'xed-ild.h' +# ild +ild_private_header = 'xed-ild-private.h' + +#ild +l1_ptr_typename = 'xed_ild_l1_func_t' +ild_getter_typename = 'xed_ild_getter_func_t' + +# xed3_nt +xed3_decoded_inst_t = 'xed_decoded_inst_t' +xed3_operand_t = 'xed_operand_values_t' + +# ild +#FIXME: get mod_space from generator +mode_space = [0,1,2] + +def ild_err(msg): + genutil.die("ILD_PARSER ERROR: %s\n" % (msg)) + +def ild_warn(msg): + genutil.msgb("ILD_PARSER WARNING", msg) + diff --git a/pysrc/importfinder.py b/pysrc/importfinder.py new file mode 100755 index 0000000..4c9fc5c --- /dev/null +++ b/pysrc/importfinder.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# Returns a list of imported modules but it is unacceptably slow. For +# the execution of "pysrc/importfinder.py generator pysrc" it takes 23 +# seconds. + +import os +import sys +import modulefinder + +def _get_modules(fn): + finder = modulefinder.ModuleFinder() + finder.run_script(fn) + all = [] + for m in finder.modules.itervalues(): + if not isinstance(m, modulefinder.Module): + continue + if not m.__file__: + continue + # skip shared object files + if m.__file__.endswith('.so'): + continue + # skip mac system stuff... + # FIXME: would need to augment with other OS's system stuff + if m.__file__.startswith('/Library/Frameworks'): + continue + all.append(m) + return all + +def find(root_module): + worklist = [] + d = {} # remember what we've seen + all = [] # output: list of path-prefixed modules + + mods = _get_modules(root_module) + worklist.extend(mods) + while worklist: + x = worklist.pop(0) + for m in _get_modules(x.__file__): + if m.__name__ not in d: + worklist.append(m) + all.append(m.__file__) + d[m.__name__]=True + all.sort() + return all + + +if __name__ == "__main__": + sys.path = [sys.argv[2]] + sys.path + print find(os.path.join(sys.argv[2],sys.argv[1]+'.py')) diff --git a/pysrc/ins_emit.py b/pysrc/ins_emit.py new file mode 100755 index 0000000..a1e3c24 --- /dev/null +++ b/pysrc/ins_emit.py @@ -0,0 +1,765 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys +import os +import codegen +import encutil +import genutil +import actions +import verbosity + +max_in_byte = 256 #max unsigned int per byte +emit_function_prefix = 'xed_encode_instruction_emit_pattern' +bind_function_prefix = 'xed_encode_instruction_fb_pattern' +get_field_value = 'xed_encoder_get_start_field_value' +legacy_maps = {'map0':'XED_ILD_MAP0', + 'map1':'XED_ILD_MAP1', + 'map2':'XED_ILD_MAP2', + 'map3':'XED_ILD_MAP3', + '3dnow':'XED_ILD_MAPAMD' } + +def sort_field_bindings(a,b): + ''' sort action_t of type emit ''' + + if a.field_name.lower() > b.field_name.lower(): + return 1 + elif a.field_name.lower() < b.field_name.lower(): + return -1 + return 0 + +def cmp_iforms_by_bind_ptrn(a,b): + if a.bind_ptrn > b.bind_ptrn: + return 1 + elif a.bind_ptrn < b.bind_ptrn: + return -1 + return 0 + +def cmp_iform_len(a,b): + if a.priority > b.priority: + return 1 + elif a.priority < b.priority: + return -1 + + alen = len(a.rule.get_all_emits() + a.rule.get_all_nts()) + blen = len(b.rule.get_all_emits() + b.rule.get_all_nts()) + if alen > blen: + return 1 + elif alen < blen: + return -1 + return cmp_iforms_by_bind_ptrn(a,b) + + +class instructions_group_t(object): + ''' each encoding iform has: + 1. conditions ( e.g.REG1=GPRv_r() ) + 2. actions, one type of the actions is a nonterminal (nt) + + the conditions and the nt's are called "bind patterns". + + if two different iclasses have the same bind patterns + for all of their iforms, + we can put those iclasses in the same group. + + this is what we are doing in _join_iclasses_to_groups + ''' + + def __init__(self,iarray,log_dir): + self.groups = [] + self.iclass2group = {} + self.log_name = 'groups_log.txt' + self._join_iclasses_to_groups(iarray,log_dir) + + def _group_good_for_iclass(self,group,iforms): + ''' Check if the incoming group represents the list of iforms. + A group represents a list of iforms if: + 1. it has same number of iforms. + 2. for each iform there is an iform in the group that has the same + bind pattern + + @param group: ins_group_t object + @param iforms: a list of iform_t + + @return: True if group represents the the ifoms list ''' + + if len(group.iforms) != len(iforms): + return False + for iform,group_iform in zip(iforms,group.iforms): + if iform.bind_ptrn != group_iform.bind_ptrn: + return False + + return True + + def _put_iclass_in_group(self,groups,iclass,instruction_iforms): + ''' tries to find a group that represents the incoming iclass. + 'represents' means that all the iforms have exactly the same + bind patterns. + if no group was found, then create new group for the iclass. + + @param groups: a list of ins_group_t object + @param iclass: the iclass name + @param instruction_iforms: a list of iform_t, the + iforms of the iclass + + @return: function_object_t ''' + + for group in groups: + # check if group represents the iclass + if self._group_good_for_iclass(group,instruction_iforms): + group.add_iclass(iclass,instruction_iforms) + return + + #no matching groups + #create new one + group = ins_group_t() + group.add_iclass(iclass,instruction_iforms) + groups.append(group) + return + + def _join_iclasses_to_groups(self,iarray,log_dir): + ''' + 1. dividing the iclasses into groups. + 2. creating a mapping from iclass to its group Id. + 3. generating a log + + return: a list of ins_group_t objects ''' + + + groups = [] + #1. generate the groups + for iclass,iforms in iarray.items(): + iforms.sort(cmp=cmp_iforms_by_bind_ptrn) + self._put_iclass_in_group(groups,iclass,iforms) + + # 2. generate the iclass to group Id mapping + self.iclass2group = {} + for i,group in enumerate(groups): + for iclass in group.get_iclasses(): + self.iclass2group[iclass] = i + + # 3. print the log + if verbosity.vencode(): + log_file = os.path.join(log_dir,self.log_name) + df = open(log_file,'w') #debug file + df.write("number of iclasses: %d\n" % len(iarray)) + df.write("number of groups: %d\n" % len(groups)) + for i,group in enumerate(groups): + df.write("GROUP Id: %d\n" % i) + df.write("ICLASSES: %s\n" % str(group.get_iclasses())) + for iform in group.iforms: + df.write("%s: %s\n" % ('BIND PATTERN: ', iform.bind_ptrn )) + df.write("\n\n") + + df.close() + self.groups = groups + + def get_groups(self): + ''' return the groups list ''' + return self.groups + + def num_groups(self): + ''' return the number of groups ''' + return len(self.groups) + + def get_iclass2group(self): + ''' return a dic of iclass to it group Id''' + return self.iclass2group + + def get_iclass2index_in_group(self): + ''' return a dictionary of iclass to its index in the group''' + d = {} + for group in self.groups: + iclasses = sorted(group.get_iclasses()) + for i,iclass in enumerate(iclasses): + d[iclass] = i + + return d + +class ins_group_t(object): + ''' This class represents one group. + it holds the list of iclasses that have the same bind patterns. + ''' + + def __init__(self): + ''' params: + 1. iclass2iforms: mapping from iclass to a list of iforms + 2.iforms: list of iform_t objects + ''' + + self.iclass2iforms = {} + self.iforms = [] + + def add_iclass(self,iclass,iforms): + ''' add the iclass and iforms list to the group ''' + + self.iclass2iforms[iclass] = iforms + if not self.iforms: + self.iforms = iforms + + def get_iclasses(self): + ''' return a list of iclasses in the group''' + return self.iclass2iforms.keys() + + def get_iform_ids_table(self): + ''' generate C style table of iform Id's. + the table is 2D. one row per iclass. + the columns are the different iform Ids ''' + + table = [] + iclasses = sorted(self.get_iclasses()) + for iclass in iclasses: + values = '' + iforms_sorted_by_length = self.iclass2iforms[iclass] + iforms_sorted_by_length.sort(cmp=cmp_iform_len) + for iform in iforms_sorted_by_length: + values += '%4d,' % iform.rule.iform_id + line = "/*%10s*/ {%s}," % (iclass,values) + table.extend([ line ]) + + return table + + +class instruction_codegen_t(): + def __init__(self,iform_list,iarray,logs_dir, amd_enabled=True): + self.amd_enabled = amd_enabled + self.iform_list = iform_list + self.iarray = iarray + self.logs_dir = logs_dir #directory for the log file + + #list of field binding function_object_t + self.fb_ptrs_fo_list = None + #list of emit patterns function_object_t + self.emit_ptrs_fo_list = None + + # number of field binding patterns + self.max_fb_ptrns = None + # number of emit patterns + self.max_emit_ptrns = None + + # a list of all values been set to field ordered sequentially + self.fb_values_list = None + # the length of fb_values_list + self.fb_values_table_size = None + + # list of groups (instructions_group_t) + self.instruction_groups = None + + def get_values(self,encoder_config): + ''' copy the necessary fields to encoder_confing object ''' + + encoder_config.fb_values_list = self.fb_values_list + encoder_config.fb_values_table_size = self.fb_values_table_size + + encoder_config.emit_ptrs_fo_list = self.emit_ptrs_fo_list + encoder_config.max_emit_ptrns = self.max_emit_ptrns + + encoder_config.fb_ptrs_fo_list = self.fb_ptrs_fo_list + encoder_config.max_fb_ptrns = self.max_fb_ptrns + + encoder_config.ins_groups = self.instruction_groups + + + def _make_emit_fo(self, iform, i): + ''' create the function object for this emit pattern + + @param iform: iform_t object + @param i: index of the pattern function + @return: function_object_t + ''' + + fname = "%s_%d" % (emit_function_prefix,i) + fo = codegen.function_object_t(fname, + return_type='void') + + # obj_str is the function parameters for the emit function + obj_str = encutil.enc_strings['obj_str'] + enc_arg = "%s* %s" % (encutil.enc_strings['obj_type'], + obj_str) + fo.add_arg(enc_arg) + + for action in iform.rule.actions: + if action.field_name and action.field_name == 'MAP': + emit_map = 'xed_encoder_request_emit_legacy_map' + code = " %s(%s)" % (emit_map,obj_str) + fo.add_code_eol(code) + + elif action.field_name and action.field_name == 'NOM_OPCODE': + code = '' + get_opcode = 'xed_encoder_get_nominal_opcode(%s)' % obj_str + if action.nbits == 8: + emit_func = 'xed_encoder_request_emit_bytes' + else: + emit_func = 'xed_encoder_request_encode_emit' + code = ' '*4 + code += '%s(%s,%d,%s)' % (emit_func,obj_str, + action.nbits,get_opcode) + fo.add_code_eol(code) + else: + code = action.emit_code('EMIT') + for c in code: + fo.add_code(c) + + return fo + + def _make_fb_setter_fo(self, iform, i): + ''' create the function object for pattern of fields bindings + + @param iform: iform_t object + @param i: index of the pattern function + @return: function_object_t + ''' + + fname = "%s_%d" % (bind_function_prefix,i) + fo = codegen.function_object_t(fname, + return_type='void') + + obj_name = encutil.enc_strings['obj_str'] + enc_arg = "%s* %s" % (encutil.enc_strings['obj_type'], + obj_name) + fo.add_arg(enc_arg) + + if not iform.fbs: + #no field binding we need to set, pacify the compiler + fo.add_code_eol('(void)%s' % obj_name) + return fo + + fo.add_code_eol(' const xed_uint8_t* val') + fo.add_code_eol(' val = %s(%s)' % (get_field_value, obj_name)) + for i,fb_action in enumerate(iform.fbs): + value_from_lu_table = '*(val+%d)' % i + operand_setter = "%s_set_%s" % (encutil.enc_strings['op_accessor'], + fb_action.field_name.lower()) + code = ' %s(%s,%s);' % (operand_setter, + obj_name, value_from_lu_table) + fo.add_code(code) + + return fo + + def _verify_naked_bits_in_unique_pattern(self): + ''' calculate how many references we have per each full + instruction emit pattern. + + naked bits are bits in the pattern without a field name + like 0x0F or 0b110. earlier functions decorated + opcode/legacy map. + + If the naked bits just show up once, then we can hardcode + those bits in the emit function. This is a test for that. + + Current design relies on the naked bits being the same in + similar instruction patterns. If two patterns differ in + any naked bits, they cannot share emit functions and we die. + The workaround would be to capture the bits in some field to + allow the emit function to be shared & generic. + + The current inputs to XED have no such conflicts. + ''' + refs_per_ptrn ={} + for iform in self.iform_list: + if iform.emit_actions not in refs_per_ptrn: + refs_per_ptrn[iform.emit_actions] = 1 + else: + refs_per_ptrn[iform.emit_actions] += 1 + if iform.rule.has_naked_bit_action(): + err = 'emit pattern: %s has more than one reference ' +\ + 'use of naked bits is not allowed'%iform.emit_actions + genutil.die(err) + + def _make_emit_pattern_fos(self): + ''' collect all the different patterns for emit phase. + for each pattern create a function representing it. + adds to each rule in iform_t the index of the pattern function + + @return: list of emit pattern function name to function object + ''' + emit_patterns = {} + fo_list = [] + i = 0 + + for iform in self.iform_list: + if iform.emit_actions not in emit_patterns: + fo = self._make_emit_fo(iform,i) + emit_patterns[iform.emit_actions] = (fo,i) + fo_list.append(fo) + iform.emit_func_index = i + i += 1 + + else: + fo, index = emit_patterns[iform.emit_actions] + iform.emit_func_index = index + + return fo_list + + + def _make_fb_pattern_fos(self): + ''' collect all the different patterns for bind phase. + for each pattern create a function representing it. + adds to each rule in iform_t the index of the pattern function + + @return: list of emit pattern function name to function object + ''' + bind_ptterns = {} + fo_list = [] + i = 0 + + for iform in self.iform_list: + if iform.fb_ptrn not in bind_ptterns: + fo = self._make_fb_setter_fo(iform,i) + bind_ptterns[iform.fb_ptrn] = (fo,i) + fo_list.append(fo) + iform.bind_func_index = i + i += 1 + + else: + fo,index = bind_ptterns[iform.fb_ptrn] + iform.bind_func_index = index + + return fo_list + + def _identify_map_and_nominal_opcode(self,iform): + ''' scan the list of actions and identify the nominal opcode and + the legacy map. + replace the actions that describe the bytes of the nom opcode + and map with dummy action as place holders. + ''' + + #list of all prefixes + prefixes = [0x66,0x67,0xf2,0xf3,0xf0,0x64,0x65,0x2e,0x3e,0x26,0x36] + vv = 0 + first_naked_bits_index = None + for i,action in enumerate(iform.rule.actions): + if action.is_field_binding() and action.field_name == 'VEXVALID': + # we are in vex valid 1/2/3 + vv = 1 + if action.naked_bits(): + if vv == 0 and action.int_value in prefixes: + #we are in legacy space and this byte is + #a prefix, don't care + continue + else: + #this byte represents the nominal opcode or the legacy map + first_naked_bits_index = i + break + + if first_naked_bits_index == None: + err = "did not find nominal opcode for iform: %s" % str(iform) + genutil.die(err) + + last_index = len(iform.rule.actions) - 1 + + first = iform.rule.actions[first_naked_bits_index] + if first.int_value != 0x0F or vv: + #this action represents the opcode + iform.nominal_opcode = first.int_value + iform.nom_opcode_bits = first.nbits + iform.map = legacy_maps['map0'] + #replacing with place holder + iform.rule.actions[i] = actions.dummy_emit(first,'NOM_OPCODE') + + else: #first byte == 0x0F and we are legacy space + #check that we have at least one more byte to read + if first_naked_bits_index+1 > last_index: + genutil.die("not enough actions") + + second = iform.rule.actions[first_naked_bits_index+1] + if not second.naked_bits(): + genutil.die("expecting map/nominal opcode after 0x0F byte") + + if self.amd_enabled and second.int_value == 0x0F: #3DNow + # the nominal opcode in 3DNow is in the last action. + # FIXME: it is best to not reference directly the last action + # but rather add a meaningful field name to the action + amd3dnow_opcode_action = iform.rule.actions[-1] + iform.nominal_opcode = amd3dnow_opcode_action.int_value + iform.nom_opcode_bits = 8 + iform.map = legacy_maps['3dnow'] + iform.rule.actions[-1] = actions.dummy_emit( + amd3dnow_opcode_action,'NOM_OPCODE') + iform.rule.actions[i] = actions.dummy_emit(first,'MAP') + #the second byte that describes the map + #is not needed, remove it + iform.rule.actions.remove(second) + + elif second.int_value == 0x38 or second.int_value == 0x3A: + #check that we have at least one more byte to read + if first_naked_bits_index+2 > last_index: + genutil.die("not enough actions") + + third = iform.rule.actions[first_naked_bits_index+2] + if not third.naked_bits(): + genutil.die("expecting map/nominal opcode after 0x0F byte") + + iform.nominal_opcode = third.int_value + iform.nom_opcode_bits = third.nbits + + if second.int_value == 0x38: + iform.map = legacy_maps['map2'] + else: #0x3A + iform.map = legacy_maps['map3'] + iform.rule.actions[i+1] = actions.dummy_emit(second,'MAP') + iform.rule.actions[i+2] = actions.dummy_emit(third, + 'NOM_OPCODE') + iform.rule.actions.remove(first) + + else: + iform.nominal_opcode = second.int_value + iform.nom_opcode_bits = second.nbits + iform.map = legacy_maps['map1'] + iform.rule.actions[i] = actions.dummy_emit(first,'MAP') + iform.rule.actions[i+1] = actions.dummy_emit(second, + 'NOM_OPCODE') + + def _find_sub_list(self,all_fbs_values, fbs_values): + ''' find the the sub list: fbs_values + in the list: all_fbs_values. + + if not found return -1 + if found return the fist index of the recurrence ''' + + elems = len(fbs_values) + indices_to_scan = len(all_fbs_values) - elems + 1 + for i in range(indices_to_scan): + if fbs_values == all_fbs_values[i:i+elems]: + return i + return -1 + + + def _find_fb_occurrence(self,all_fbs_values, fbs_values): + ''' find the the sub list: fbs_values + in the list: all_fbs_values. + + if fbs_values is not a sub list to all_fbs_values + concatenate it. + + return: the first index of fbs_values occurrence + in all_fbs_values. + ''' + + if not fbs_values: + return 0 + + if not all_fbs_values: + all_fbs_values.extend(fbs_values) + return 0 + + index = self._find_sub_list(all_fbs_values,fbs_values) + if index >= 0: + # found sub list + return index + + # did not found sub list concatenate to the end + last_index = len(all_fbs_values) + all_fbs_values.extend(fbs_values) + return last_index + + + def _make_fb_values_list(self): + ''' generate a list of the values being set by the FB actions. + for each iform find the start index of the values list. + + All the field bindings get put in to a linear array. + This is finds the index in to that array. + + This is a quick compression technique for sharing trailing + subsequences. + + e.g.: iform1 sets the values: 0 1 2 (3 fields) + iform2 sets the values: 3 4 (2 fields) + iform3 sets the values: 1 2 + iform4 sets the values: 2 3 + + the ordered list of unique sequence values across + all iforms is: 0 1 2 3 4. + + start index of iform1: 0 (which picks up 0, 1 2) + start index of iform2: 3 (which picks up 3, 4) + start index of iform3: 1 (which picks up 1, 2) + start index of iform4: 2 (which picks up 2, 3) + + Note: because of ordering, if iform3 happens to show + up before iform1, they won't share iform1's + subsequence 1,2. + ''' + + fbs_list = [] + for iform in self.iform_list: + # collect all the actions that set fields + iform.fbs = iform.rule.get_all_fbs() + iform.fbs.sort(cmp=sort_field_bindings) + + # create a list of int values + fbs_values = map(lambda x: x.int_value, iform.fbs) + + #find the start index of this list of values in the general list + #and update the general list as needed + iform.fb_index = self._find_fb_occurrence(fbs_list, fbs_values) + + fbs_list = map(lambda x: str(x), fbs_list) + return fbs_list + + + def _make_field_bindings_pattern(self,iform): + ''' create the string that represents the field bindings pattern. ''' + + bind_actions = [] + for action in iform.rule.actions: + if action.type == 'nt': + pass + elif action.type == 'FB': + bind_actions.append(action.field_name) + elif action.type == 'emit': + if action.emit_type == 'numeric' and action.field_name: + bind_actions.append(action.field_name) + else: + pass + else: + genutil.die("unexpected action type: %s" % action.type) + + fb_ptrn = '' + if bind_actions: + fb_ptrn = ', '.join(sorted(bind_actions)) + iform.fb_ptrn = fb_ptrn + + def _make_emit_pattern(self,iform): + ''' create the string that represents the action for the emit phase. + using this string we will classify all + the emit actions into patterns + ''' + + emit_pattern = [] + + for action in iform.rule.actions: + if action.type == 'emit': + emit_pattern.append("emit %s nbits=%d" % (action.field_name, + action.nbits)) + elif action.type == 'nt': + emit_pattern.append(str(action)) + elif action.type == 'FB': + # FB are not used in emit phase so we do not factor them + # in to the string that represents the pattern + pass + else: + genutil.die("unexpected action type: %s" % action.type) + + iform.emit_actions = ', '.join(emit_pattern) + + def _make_bind_pattern(self,iform): + ''' create the string that represents the field bindings pattern. ''' + + bind_ptrn = [ str(iform.rule.conditions) ] + for action in iform.rule.actions: + if action.type == 'nt': + bind_ptrn.append(str(action)) + + iform.bind_ptrn = '' + if bind_ptrn: + iform.bind_ptrn = ', '.join(bind_ptrn) + + def _print_log(self): + print "---- encoder log ----" + for i,iform in enumerate(self.iform_list): + print "%d\n" % i + print "IFORM: %s" % str(iform) + print "iform index: %d" % iform.rule.iform_id + bind_index = iform.bind_func_index + bind_fo = self.fb_ptrs_fo_list[bind_index] + print "BIND function: %d, %s" % (bind_index, + bind_fo.function_name) + emit_index = iform.emit_func_index + emit_fo = self.emit_ptrs_fo_list[emit_index] + print "EMIT function: %d, %s" % (emit_index, + emit_fo.function_name) + + print "NOM_OPCODE: %d" % iform.nominal_opcode + print "MAP: %s" % iform.map + fbs_values = map(lambda x: x.int_value, iform.fbs) + print "FB values: %s" % fbs_values + print "\n\n" + print "-"*20 + + def work(self): # main entry point + ''' + Each instruction has + 1) conditions (iclass, user registers, user inputs) and + + 2) actions. 3 types: + 2a) field bindings, + 2b) nonterminals, + 2c) bit-emit of operand fields + (hard-coded or from NT output)). + + fos = function output object (plural) + + generate the following: + 1) list of emit patterns fos (2c) + 2) list of field bindings patterns fos (2a) + 3) list of all field bindings values (values from prev step) + 4) max number of emit patterns + 5) max number of field binding patterns + 6) max number of field bindings values + 7) list of groups fos (see explanation in instructions_group_t) + + ''' + + for iform in self.iform_list: + self._identify_map_and_nominal_opcode(iform) + self._make_field_bindings_pattern(iform) + self._make_emit_pattern(iform) + #see explanation about bind patterns in instructions_group_t + self._make_bind_pattern(iform) + + self._verify_naked_bits_in_unique_pattern() + + self.fb_values_list = self._make_fb_values_list() # step 3 + self.fb_values_table_size = len(self.fb_values_list) + + self.emit_ptrs_fo_list = self._make_emit_pattern_fos() + self.max_emit_ptrns = len(self.emit_ptrs_fo_list) + if self.max_emit_ptrns > max_in_byte: + # we are using uint8to hold the number of patterns, + # we need to make sure we don't exceeds + error = "total number of emit patterns(%d) exceeds 8 bits" + genutil.die(error % self.max_emit_ptrns) + + self.instruction_groups = instructions_group_t(self.iarray, + self.logs_dir) + + self.fb_ptrs_fo_list = self._make_fb_pattern_fos() + self.max_fb_ptrns = len(self.fb_ptrs_fo_list) + if self.max_fb_ptrns > max_in_byte: + # we are using uint8to hold the number of patterns, + # we need to make sure we don't exceeds + error = "total number of field binding patterns(%d) exceeds 8 bits" + genutil.die(error % self.max_fb_ptrns) + + if verbosity.vencode(): + self._print_log() + + + + + + + + + + + + + + diff --git a/pysrc/metaenum.py b/pysrc/metaenum.py new file mode 100755 index 0000000..b160e8a --- /dev/null +++ b/pysrc/metaenum.py @@ -0,0 +1,154 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# Enumeration support +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# subprocess requires python 2.4 (replaces all os.popen() ) or later +import os, sys, re, types +import enumer + +################################################################################### + + +class metaenum_t(object): + """This class is for reading in prefab enumeration files and + generating the corresponding enumeration by calling the enumer.py + module.""" + + comment_pattern = re.compile(r'[#].*$') + doxygen_comment_pattern = re.compile(r'//[/!]<.*') + + def __init__(self, enum_fn, gendir='.'): + """The inputs are an enumeration specification file and an + output directory.""" + self.cplusplus=False + self.enum_fn = enum_fn # input file + self.gendir = gendir + self.tuples = None # list [enumer.enumer_value_t] + self.cfn = None + self.hfn = None + self.density = '' + self.namespace = None + self.type_name = None + self.prefix = None + self.stream_ifdef = None + self.proto_prefix='' + self.extra_header=None # might be a list + + self.read_file() + + def read_file(self): + """Read in an existing enumeration file name, and build our + internal enumer structure. Return a tuple with the consumed data.""" + stream_ifdef = '' + lines = file(self.enum_fn).readlines() + simple_tuples = [] + density = 'automatic' + namespace = None + proto_prefix = '' + extra_header = [] + cplusplus = False + for line in lines: + nline = metaenum_t.comment_pattern.sub('',line).strip() + if len(nline) == 0: + continue + wrds = nline.split() + if wrds[0] == 'cplusplus': + cplusplus = True + elif wrds[0] == 'namespace': + namespace = wrds[1] + elif wrds[0] == 'hfn': + hfn = wrds[1] + elif wrds[0] == 'cfn': + cfn = wrds[1] + elif wrds[0] == 'density': + density = wrds[1] + elif wrds[0] == 'prefix': + prefix = wrds[1] + elif wrds[0] == 'typename': + typename = wrds[1] + elif wrds[0] == 'stream_ifdef': + stream_ifdef = wrds[1] + elif wrds[0] == 'proto_prefix': + proto_prefix = wrds[1] + elif wrds[0] == 'extra_header': + extra_header.append(wrds[1]) + else: + token = wrds[0] + comment = None + value = None + if len(wrds) > 1: + if metaenum_t.doxygen_comment_pattern.match(wrds[1]): + comment = ' '.join(wrds[1:]) + else: + value = wrds[1] + if len(wrds) > 2: + comment = ' '.join(wrds[2:]) + simple_tuples.append( (token, value, comment) ) + + self.tuples = [] + for token,value,comment in simple_tuples: + self.tuples.append(enumer.enumer_value_t(token,value,comment)) + + self.cfn = cfn + self.hfn = hfn + self.density = density + self.namespace = namespace + self.type_name = typename + self.prefix = prefix + self.stream_ifdef = stream_ifdef + self.proto_prefix= proto_prefix + self.extra_header= extra_header + self.cplusplus = cplusplus + + def run_enumer(self): + e = enumer.enumer_t(self.type_name, self.prefix, self.tuples, + self.cfn, self.hfn, + self.gendir, + self.namespace, + self.stream_ifdef, + cplusplus = self.cplusplus, + proto_prefix = self.proto_prefix, + extra_header=self.extra_header, + density=self.density) + e.emit() + self.src_full_file_name = e.cf.full_file_name + self.hdr_full_file_name = e.hf.full_file_name + + +def _test_meta_enum(): + m = metaenum_t("datafiles/xed-machine-modes-enum.txt", "obj") + m.run_enumer() + +if __name__ == '__main__': + args = len(sys.argv) + if args == 1: + sys.stderr.write("TESTING %s\n" % sys.argv[0]) + _test_meta_enum() + elif args == 3: + odir = sys.argv[1] + enum_file = sys.argv[2] + m = metaenum_t(enum_file, odir) + m.run_enumer() + sys.exit(0) + else: + sys.stderr.write("Usage: %s odir enumfile\n" % sys.argv[0]) + sys.exit(1) + diff --git a/pysrc/nt_func_gen.py b/pysrc/nt_func_gen.py new file mode 100755 index 0000000..95b52ce --- /dev/null +++ b/pysrc/nt_func_gen.py @@ -0,0 +1,354 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import refine_regs +import codegen +import genutil +import os +import copy +import constraint_vec_gen +import collections +import func_gen +import types +import actions + + +_xed_reg_invalid = 'XED_REG_INVALID' +# those operand are very wide but the real values they may have are few +# specifying here the valid values for the operands and the number bits +# needed to represent each one +_valid_width = {'BRDISP_WIDTH':[8, 16, 32], + 'DISP_WIDTH':[0, 8, 16, 32, 64], + 'IMM_WIDTH':[8, 16, 32, 64], + } +_width_bits = {'BRDISP_WIDTH':6, + 'DISP_WIDTH':7, + 'IMM_WIDTH':7, + } + +_vexpfx_vals = [0xc4, 0xc5, 0x62] +_vexpfx_bits = 8 + +''' +the tables for this nt are too complex to be generated using hash functions +and look up tables. +they are generated in the old style (if statement) +''' +_complicated_nt = ['SIB_REQUIRED_ENCODE','VMODRM_MOD_ENCODE', 'REX_PREFIX_ENC', + 'PREFIX_ENC','VEX_TYPE_ENC'] + +def get_complicated_nt(): + return _complicated_nt + +class nt_function_gen_t(object): + def __init__ (self,enc_config, storage_fields): + self.nonterminals = enc_config.nonterminals + self.decoder_ntlufs = enc_config.decoder_ntlufs + self.decoder_nonterminals = enc_config.decoder_nonterminals + self.storage_fields = storage_fields + self.functions = [] + self.operand_lu_fos = [] + + self.vec_gen_log = open( + os.path.join(enc_config.gendir,'nt_function_log.txt'), + 'w') + + regs_file = enc_config.files.regs_input_file + self.reg2int, max_gprs_bits = self._gen_regs_dict(regs_file) + self.state_space,self.ops_width = self._gen_state_space(max_gprs_bits) + + def _is_reg_type(self,field_name): + ''' check if the field name represents a reg type ''' + + if field_name not in self.storage_fields: + return False + ctype = self.storage_fields[field_name].ctype + return ctype == 'xed_reg_enum_t' + + def _cond_is_UIMM0_1(self,cond): + ''' check whether the condition is UIMM0=1. + die if the operand is UIMM0 but the value is different than 1''' + if cond.field_name == 'UIMM0': + if cond.rvalue.value == '1': + return True + else: + #the operand is UIMM0 but the value is not 1 + err= ('not expecting UIMM0 will have any other constraint '+ + 'other than UIMM0=1') + genutil.die(err) + return False + + def _replace_UIMM0_1_cond(self): + ''' if the condition is UIMM0=1 we replace it with UIMM0_1=1 + UIMM0_1 represent the accessor that compares the value + of UIMM0 to 1.''' + return 'UIMM0_1' + + def _build_constraint(self, nonterminal): + ''' + build a dict that represents the values that the operands can have. + e.g. + for the constraint EASZ=3 MODE!=3 + the cdict is {EASZ:[3],MODE:[0,1,2]} + ''' + + for rule in nonterminal.rules: + constraints = {} + for cond in rule.conditions.and_conditions: + key = cond.field_name + if cond.equals: + if cond.rvalue.null(): + constraints[key] = [self.reg2int[_xed_reg_invalid]] + elif cond.rvalue.any_valid(): + #will be gathered later + continue + else: + if self._cond_is_UIMM0_1(cond): + key = self._replace_UIMM0_1_cond() + val = cond.rvalue.value + if self._is_reg_type(key): + constraints[key] = [self.reg2int[val]] + else: + constraints[key] = [genutil.make_numeric(val)] + else: + #we have != condition, we need to calculate all the + #possible values based on the width of the field and remove + #the the unwanted value. + #need to deep copy since we modify the list, and we want + #to preserve the original + all_vals = copy.deepcopy(self.state_space[key]) + val = genutil.make_numeric(cond.rvalue.value) + all_vals.remove(val) + constraints[key] = all_vals + rule.cdict = constraints + + def _encoder_preferred(self, rules): + ''' returns the rule that has the attribute enc_prefered ''' + + for rule in rules: + if rule.enc_preferred: + return rule + return [] + + def _unite_rules(self,nonterminal): + ''' removing rules with identical constraints. + if more than one rule has that same constraint then one of them must + be marked as encoder preferred. + + bucketing the rules, each bin represents unique constraint. + we go over each bin, if it has more than one rule, + we look for the attribute enc_preferred ''' + + rules_bin = [] + for rule in nonterminal.rules: + found = False + for bin in rules_bin: + if bin[0].cdict == rule.cdict: + bin.append(rule) + found = True + break + if not found: + rules_bin.append([rule]) + + rules = [] + for bin in rules_bin: + if len(bin) > 1: + preferred_rule = self._encoder_preferred(bin) + if preferred_rule: + rules.append(preferred_rule) + else: + err = "in nt %s several rules has the constraint: %s\n" + err += "one of them must be marked as encoder preferred\n" + genutil.die(err % (nonterminal.name,bin[0].conditions)) + else: + rules.extend(bin) + return rules + + def _gen_ntluf(self,nonterminal): + '''create the constraint dictionary and call the function generator''' + + self._build_constraint(nonterminal) + rules = self._unite_rules(nonterminal) + cvg = constraint_vec_gen.constraint_vec_gen_t(self.state_space, + self.ops_width, rules, + nonterminal.name, + nonterminal.otherwise, + self.vec_gen_log) + + + #FIXME: temporary hack, the ild_phash is generic and does not aware + #whether it handles decoder or encoder. + #currently we need to know this, need it till we finish the iform + #encoding + if nonterminal.is_ntluf(): + cvg.ntluf = True + else: + cvg.nt = True + cvg.work() + + raw_name = nonterminal.name + + if nonterminal.is_ntluf(): + func_name = "%s_%s" % ("xed_encode_ntluf",raw_name) + else: + func_name = "%s_%s_%s" % ("xed_encode_nonterminal",raw_name,"BIND") + + function_gen = func_gen.func_gen_t(cvg,func_name) + #this builds the hash tables + fos, operand_lu_fo = function_gen.gen_function() + return fos, operand_lu_fo + + def _add_op_lu_fo(self,operand_lu_fo): + ''' check if the function already exists in the functions list. + if exists do nothing + if not add it to the list of all the functions ''' + if operand_lu_fo == None: + return + fname = operand_lu_fo.function_name + for fo in self.operand_lu_fos: + if fname == fo.function_name: + return + self.operand_lu_fos.append(operand_lu_fo) + + def _gen_default_action(self,nts): + ''' add to to each nonterminal the default action that should be taken + in case the no rule was satisfied ''' + + for nt in nts: + if nt.otherwise == 'error': + err_fb = 'ERROR=XED_ERROR_GENERAL_ERROR' + nt.default_action = actions.action_t(err_fb) + else: + #creating return action which return nothing + nt.default_action = actions.gen_return_action('') + + def gen_nt_functions(self): + nonterminals = (self.nonterminals.values() + + self.decoder_nonterminals.values() + + self.decoder_ntlufs.values()) + + for nt in nonterminals: + if nt.name in _complicated_nt: + continue + + fos, operand_lu_fo = self._gen_ntluf(nt) + self.functions.extend(fos) + self._add_op_lu_fo(operand_lu_fo) + + self.vec_gen_log.close() + return self.functions, self.operand_lu_fos + + def _check_duplications(self,regs): + ''' n^2 loop which verifies that each reg exists only once. ''' + + for reg in regs: + count = 0 + for r in regs: + if reg == r: + count += 1 + if count > 1: + genutil.die("reg %s defined more than once" % reg) + + + def _gen_regs_dict(self,regs_file): + ''' creates a dictionary of reg->int_value + this imitates the reg_enum_t that is created in the generator ''' + + f = genutil.base_open_file(regs_file,"r","registers input") + lines = f.readlines() + # remove comments and blank lines + # regs_list is a list of reg_info_t's + regs_list = refine_regs.refine_regs_input(lines) + + #sort the regs by their groups + reg_list_enumer_vals = refine_regs.rearrange_regs(regs_list) + + #we do not need to the PSEUDO regs since + #they are not in use by the encoder + tmp = filter(lambda x: not x.in_comment('PSEUDO'), reg_list_enumer_vals) + regs = map(lambda x: x.name, tmp) + + + #put XED_REG_INVLAID in the beginning + regs.remove('INVALID') + ordered_regs = ['INVALID'] + ordered_regs.extend(regs) + + #add XEG_REG_ prefix + full_reg_name = map(lambda x: 'XED_REG_' + x, ordered_regs) + + self._check_duplications(full_reg_name) + reg2int = {} + for i,reg in enumerate(full_reg_name): + reg2int[reg] = i + + max_reg = len(regs_list) - 1 + import math + + #calculate how many bits we need to represent + #the max int value of the regs + bits_width = int(math.floor(math.log(max_reg,2))) + 1 + return reg2int, bits_width + + def _gen_state_space(self, max_gprs_bits): + ''' max_gprs_bits is the number of bits needed to represent + all the registers that are generated by xed (xed_reg_enum_t), + calculated in _gen_regs_dict + + generating two dictionaries + op_space: mapping from operand to its possible values + op_width: mapping from operand to the number of bits needed + to represent it ''' + op_space = {} + op_width = {} + for field in self.storage_fields: + if self.storage_fields[field].ctype == 'xed_reg_enum_t': + #do not specifying the space of the regs since it is enormous + #do not want any one to use it + op_width[field] = max_gprs_bits + else: + if 'WIDTH' in field: + if field in _valid_width: + op_space[field] = _valid_width[field] + op_width[field] = _width_bits[field] + else: + #this field is in use by the encoder + continue + elif 'VEXPFX_OP' == field: + op_space[field] = _vexpfx_vals + op_width[field] = _vexpfx_bits + elif field in ['DISP','BRDISP','UIMM0']: + # those operands are not used by the encoders nonterminals + # they are very wide and specifying the range of valid + # values for them is not needed and chokes python + # FIXME: could add a column to the filed data file for this + pass + else: + bits = self.storage_fields[field].bitwidth + op_space[field] = range(2**bits) + op_width[field] = bits + + # adding artificial operands + op_space['UIMM0_1'] = [0,1] + op_width['UIMM0_1'] = 1 + return op_space,op_width + + + diff --git a/pysrc/operand_bitvec.py b/pysrc/operand_bitvec.py new file mode 100755 index 0000000..d6c9cd1 --- /dev/null +++ b/pysrc/operand_bitvec.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +""" +Build a bit vector based on the operand names +""" +################################################################################ +import os, sys, types, re +import codegen, genutil + +def build_operand_bitvector(operand_names): + """Build a bit vector in C of the operand names. Return the lines + of the typedef. Also return a dictionary of the operand names, + and the bit positions & masks to be used for building up the + initialization.""" + lines = [] + dct = {} + chunk_size = 32 + #n_elements = (len(operand_names)+(chunk_size-1)) / chunk_size + n_elements = 4 + lines.append("typedef union {") + lines.append(" xed_uint%d_t i[%d];" % (chunk_size,n_elements)) # must be first + lines.append(" struct {") + for i,n in enumerate(operand_names): + # figure out which chunk_size chunk it is in, and what offset in that chunk + dct[n] = ( "XED_OPERAND_%s" % (n), i, i/chunk_size, i % chunk_size, 1<<(i%chunk_size) ) + cmt = "%02d:%02d" % (i/chunk_size,i%chunk_size) + s = " xed_uint%d_t x_%s : 1; /* %s */" % (chunk_size,n,cmt) + lines.append(s) + #nelem = (i+chunk_size-1)/chunk_size + nelem = 4 + lines.append(" } s;") + lines.append("} xed_operand_bitvec_t;") + return (lines, dct, nelem) + +def build_init(operand_names, dct, nelem): + """Given a list of operand names and a dictory build by + build_operand_bitvector, return an data initialization string""" + values = [0] * nelem + for o in operand_names: + try: + (xed_operand, biti, chunki, pos_in_chunk, mask) = dct[o] + except: + genutil.die("Could not find %s in operand names" % (o)) + values[chunki] |= mask + t = [] + for v in values: + t.append("%s" %(hex(v))) + s = "XED_BIT_PAIR( %s )" % ",".join(t) + return s + diff --git a/pysrc/operand_storage.py b/pysrc/operand_storage.py new file mode 100755 index 0000000..a5ba43e --- /dev/null +++ b/pysrc/operand_storage.py @@ -0,0 +1,529 @@ +#!/usr/bin/env python +# -*- python -*- +################################################################################ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os, sys, types, re +import codegen +import genutil +import ildutil +import math + + +class operand_field_t(object): + def __init__(self, + name, + aggtype, + ctype, + bitwidth, + default_visibility=None, + default_initializer=None, + xprint='NOPRINT', + internal_or_public="INTERNAL", + dio="DO", + eio="EO",): + + self.name = name + self.aggtype = aggtype + self.ctype = ctype + self.bitwidth = int(bitwidth) + self.default_visibility = default_visibility + self.xprint = xprint + self.internal_or_public = internal_or_public + self.dio = dio + self.eio = eio + + if self.eio in ['EI','EO']: + pass + else: + err = "Bad Encoder IO value: %s -- need one of {EI,EO}" + genutil.die(err % self.eio) + + if self.dio in ['DI','DO','DS']: + pass + else: + err = "Bad decoder IO value: %s -- need one of {DI,DO,DS}" + genutil.die(err % self.eio) + + if self.eio == 'EI': + self.encoder_input = True + else: + self.encoder_input = False + + if self.dio == 'DS': + self.decoder_skip = True + else: + self.decoder_skip = False + + #NOTE: this next field is only used if initialize_each_field is True. + self.default_initializer = default_initializer + self.is_enum = 'enum' in self.ctype + + # this is the C type that will be used in the operand storage struct. + self.storage_type = None + + #if True using bit fields + self.compressed = False + + def print_field(self): + if self.xprint == 'PRINT': + return True + return False + +def cmp_operands_name(a,b): + if a.name > b.name: + return 1 + if a.name < b.name: + return -1 + return 0 + +def cmp_operands(a,b): + ''' comparing the operands on based on their bit width + larger width first. + if width are the same compare the names, lower name first ''' + + w1 = a.bitwidth + w2 = b.bitwidth + if w1 > w2: + return -1 + if w1 < w2: + return 1 + return cmp_operands_name(a,b) + + +class operands_storage_t(object): + """This is where we build up the storage for the fields that hold + the operand values. + """ + + def __init__(self,lines,compress_operands=False): + #a dict of operand name to operand_field_t + self.operand_fields = self._read_storage_fields(lines) + + self.compressed = compress_operands + # the prefix of the accessor function + self.xed_accessor_fn_pfx = ildutil.xed_strings['op_accessor'] + + #list of bin, each bin is operands + #used for squeezing operands with a few bits to one 32 bit variable + self.bins = [] + + + def _read_storage_fields(self,lines): + ''' Return a dictionary of operand_field_t objects + indexed by field name ''' + + comment_pattern = re.compile(r'[#].*$') + operand_types = {} + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + if len(wrds) != 9: + genutil.die("Bad number of tokens on line: " + line) + # aggtype is "SCALAR" + (name, aggtype, ctype, width, default_visibility, + xprint, internal_or_public, dio, eio) = wrds + if name in operand_types: + genutil.die("Duplicate name %s in input-fields file." % (name)) + + if aggtype != 'SCALAR': + err = ("type different than SCALAR is not" + + " supported in: %s" % (line)) + genutil.die(err) + + if ctype == 'xed_reg_enum_t': + default_initializer = 'XED_REG_INVALID' + elif ctype == 'xed_iclass_enum_t': + default_initializer = 'XED_ICLASS_INVALID' + else: + default_initializer = '0' + operand_types[name] = operand_field_t(name, aggtype, + ctype, width, + default_visibility, + default_initializer, + xprint, + internal_or_public, + dio, + eio,) + return operand_types + + def get_operand(self,opname): + return self.operand_fields[opname] + + def get_operands(self): + return self.operand_fields + + def decoder_skip(self,operand): + return self.operand_fields[operand].decoder_skip + + def get_ctype(self,operand): + return self.operand_fields[operand].ctype + + def get_storage_type(self,operand): + return self.operand_fields[operand].storage_type + + def _gen_op_getter_fo(self,opname): + ''' generate the function object for the getter accessors + adding cast to the C type according to the data files(ctype)''' + inst = 'd' + fname = get_op_getter_fn(opname) + ret_type = self.get_ctype(opname) + fo = codegen.function_object_t(fname, + return_type=ret_type, + static=True, + inline=True) + fo.add_arg('const xed_decoded_inst_t* %s' % inst) + op = opname.lower() + fo.add_code_eol('return (%s)%s->_operands.%s' % (ret_type,inst, op)) + return fo + + def _gen_op_setter_fo(self,opname): + ''' generate the function object for the setter accessors + adding cast to the C type according to the data files(ctype)''' + inst = 'd' + opval = 'opval' + fname = get_op_setter_fn(opname) + fo = codegen.function_object_t(fname, + return_type='void', + static=True, + inline=True) + fo.add_arg('xed_decoded_inst_t* %s' % inst) + fo.add_arg('%s %s' % (self.get_ctype(opname),opval)) + op = opname.lower() + type = self.get_storage_type(opname) + fo.add_code_eol('%s->_operands.%s = (%s)%s' % (inst, op, type ,opval)) + return fo + + def _gen_generic_getter(self): + ''' for xed's internal usage (printing) we need to be able to + get an operand based on its index. + generating here a switch/case over the operand index to call the + correct getter function ''' + inst = 'd' + fname = 'xed3_get_generic_operand' + ret_arg = 'ret_arg' + + fo = codegen.function_object_t(fname, + return_type='void', + static=False, + inline=False) + fo.add_arg('const xed_decoded_inst_t* %s' % inst) + fo.add_arg('xed_operand_enum_t operand') + fo.add_arg('void* %s' % ret_arg) + + switch_gen = codegen.c_switch_generator_t('operand',fo) + op_names = self.operand_fields.keys() + op_names.sort() + for op in op_names: + switch_key = "XED_OPERAND_%s" % op + ctype = self.get_ctype(op) + func_getter = "%s(d)" % get_op_getter_fn(op) + code = "*((%s*)%s)=%s;" % (ctype,ret_arg,func_getter) + switch_gen.add_case(switch_key,[code]) + switch_gen.add_default(['xed_assert(0);']) + switch_gen.finish() + return fo + + def _gen_generic_setter(self): + ''' generating a switch/case over the operand index to call the + correct setter function ''' + inst = 'd' + fname = 'xed3_set_generic_operand' + in_value = 'val' + + fo = codegen.function_object_t(fname, + return_type='void', + static=False, + inline=False) + fo.add_arg('xed_decoded_inst_t* %s' % inst) + fo.add_arg('xed_operand_enum_t operand') + fo.add_arg('xed_uint32_t %s' % in_value) + + switch_gen = codegen.c_switch_generator_t('operand',fo) + op_names = self.operand_fields.keys() + op_names.sort() + for op in op_names: + switch_key = "XED_OPERAND_%s" % op + ctype = self.get_ctype(op) + func_setter = get_op_setter_fn(op) + code = "%s(%s,(%s)%s);" % (func_setter,inst,ctype,in_value) + switch_gen.add_case(switch_key,[code]) + switch_gen.add_default(['xed_assert(0);']) + switch_gen.finish() + return fo + + def dump_operand_accessors(self,agi): + + ''' Dump operand accessor to inspect the data + structure xed_operand_storage_t ''' + fo_list = [] + h_fname = get_operand_accessors_fn() + c_fname = h_fname.replace('.h', '.c') + + for opname in self.operand_fields.keys(): + getter_fo = self._gen_op_getter_fo(opname) + setter_fo = self._gen_op_setter_fo(opname) + fo_list.append(getter_fo) + fo_list.append(setter_fo) + + # generate a generic getter + generic_getter = self._gen_generic_getter() + generic_setter = self._gen_generic_setter() + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = agi.common.options.gendir + + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + h_fname, shell_file=False, + is_private=False) + + h_file.add_header(['xed-decoded-inst.h','xed-operand-storage.h']) + h_file.start() + + for fo in fo_list: + decl = fo.emit_header() + h_file.add_code(decl) + h_file.add_code(generic_getter.emit_header()) + h_file.add_code(generic_setter.emit_header()) + + + for fo in fo_list: + fo.emit_file_emitter(h_file) + + + h_file.close() + + c_file = codegen.file_emitter_t(gendir, + c_fname, shell_file=False) + c_file.add_header(h_fname) + c_file.start() + generic_getter.emit_file_emitter(c_file) + generic_setter.emit_file_emitter(c_file) + c_file.close() + + def _fix_bit_width_for_enums(self,agi): + ''' the default width of the nums is to big and wasteful. + we get the list of all values for each enum in agi + and set the bitwidth to the minimal width needed. + ''' + + # mx_bits is a mapping from enum name to the minimal number + # of bits required to represent it + max_bits_for_enum = self._gen_max_bits_per_enum(agi.all_enums) + for op in self.operand_fields.values(): + if op.ctype in max_bits_for_enum: + needed_bits = max_bits_for_enum[op.ctype] + if op.bitwidth < needed_bits: + # verify that the specified bitwidth form the data files + # is not smaller than the calculated + vals = agi.all_enums[op.ctype] + err = 'bit width for % is to small, has %d values' + genutil.die(err % (op.name,vals)) + else: + op.bitwidth = max_bits_for_enum[op.ctype] + + def _compute_type_in_storage(self): + ''' detect the minimal C type data type can be used to represent + the operand. + the accessors will cast the operand to its C type according to the + data files''' + + for op in self.operand_fields.values(): + width = op.bitwidth + if width <= 8: + op.storage_type = 'xed_uint8_t' + elif width <=16: + op.storage_type ='xed_uint16_t' + elif width <=32: + op.storage_type = 'xed_uint32_t' + elif width <=64: + op.storage_type = 'xed_uint64_t' + else: + genutil.die("unhandled width") + + def emit(self,agi): + ''' emit the date type xed_operand_storage_t''' + + filename = 'xed-operand-storage.h' + + xeddir = agi.common.options.xeddir + gendir = agi.common.options.gendir + fe = codegen.xed_file_emitter_t(xeddir, gendir, filename) + fe.headers.remove('xed-internal-header.h') + headers = ['xed-chip-enum.h', 'xed-error-enum.h', 'xed-iclass-enum.h', + 'xed-reg-enum.h','xed-operand-element-type-enum.h'] + fe.add_header(headers) + + fe.start() + + cgen = codegen.c_class_generator_t('xed_operand_storage_t', + var_prefix='') + + #compute the minimal ctype required to represent each enum + self._fix_bit_width_for_enums(agi) + + #compute the ctype of the operand ad represented in the operand storage + self._compute_type_in_storage() + + if self.compressed: + self.bins = self._compress_operands() + + operands = self.operand_fields.values() + un_compressed = filter(lambda x: x.compressed == False, operands ) + un_compressed.sort(cmp=cmp_operands) + + # first emit all the operands that does not use bit fields + for op in un_compressed: + cgen.add_var(op.name.lower(), op.storage_type, + accessors='none') + + #emit the operand with bit fields + for i,bin in enumerate(self.bins): + for op in bin.operands: + cgen.add_var(op.name.lower(), bin.storage_ctype, + bit_width=op.bitwidth, accessors='none') + + else: + operands_sorted = self.operand_fields.values() + operands_sorted.sort(cmp=cmp_operands) + for op in operands_sorted: + cgen.add_var(op.name.lower(), op.storage_type, + accessors='none') + + lines = cgen.emit_decl() + fe.writelines(lines) + + fe.close() + + def _get_num_elements_in_enum(self,values_list): + ''' return the number of elements in the enum. + is the elements does not have the x_LAST enum add it''' + has_last = False + for val in values_list: + if 'LAST' in val: + has_last = True + if has_last: + return len(values_list) + else: + return len(values_list) + 1 + + def _gen_max_bits_per_enum(self,all_enums): + ''' calculate the number of bits required to capture the each enum. + returning a dict of enum name to the number of required bits ''' + widths = {} + for (enum_name, values_list) in all_enums.items(): + num_values = self._get_num_elements_in_enum(values_list) + log2 = math.log(num_values,2) + needed_bits = int(math.ceil(log2)) + widths[enum_name]= needed_bits + # special handling for xed_error_enum_t. + # this width is hard coded since we can not capture the values + # of this enum in the generator + widths['xed_error_enum_t'] = 4 + return widths + + def _get_candidates_for_compression(self): + ''' collect all the operands that we need to compress. + the operands that we need to compress has bitwidth smaller then + their ctype can hold. ''' + + candiadtes = [] + for op in self.operand_fields.values(): + # for optimization those operands are not using bit with + # FIXME: add field to the operands for excluding hot fields + # form being compressed + #if op.name.lower() in ['error','outreg','mode']: + # continue + if op.bitwidth != 32 and op.bitwidth != 64: + candiadtes.append(op) + return candiadtes + + def _place_operand_in_bin(self,op,bins): + ''' find a bin that has place for the operand ''' + for bin in bins: + if bin.operand_fits(op): + bin.add_operand(op) + return + + #did not find any matching bin, need to create new one + bin = operands_bin_t() + bin.add_operand(op) + bins.append(bin) + return + + def _partition_to_bins(self,ops_sorted): + ''' partition all the operands in bins ''' + bins = [] + for op in ops_sorted: + self._place_operand_in_bin(op,bins) + op.compressed = True + return bins + + def _compress_operands(self): + ''' most of the operands's width are less than their c type. + in order to save space we are bin packing the operands. + each bin is 32bit width. + using First Fit Decreasing(FFD) strategy ''' + + operands = self._get_candidates_for_compression() + operands.sort(cmp=cmp_operands) + bins = self._partition_to_bins(operands) + return bins + +class operands_bin_t(object): + ''' This class represents a single bin that aggregates a list of operands + into single c struct ''' + def __init__(self): + self.operands = [] #list of operands + self.size = 0 #total width in bits + self.max_size = 32 #the max width + self.storage_ctype = 'xed_uint32_t' #the C type used for the operands + + def add_operand(self,op): + ''' adding single operand to this bin''' + self.operands.append(op) + self.size += op.bitwidth + + def operand_fits(self,operand): + ''' checks if the given operand can be inserted into this bin ''' + return operand.bitwidth + self.size <= self.max_size + +################ +# Those are global functions that are accessed for places that do not have the +# operands_storage_t type +################ +def get_operand_accessors_fn(): + return 'xed-operand-accessors.h' + +def get_op_getter_full_func(opname,strings_dict): + obj_name = strings_dict['obj_str'] + accessor = get_op_getter_fn(opname) + return '%s(%s)' % (accessor,obj_name) + +def get_op_getter_fn(opname): + xed_accessor_fn_pfx = ildutil.xed_strings['op_accessor'] + return '%s_get_%s' % (xed_accessor_fn_pfx, opname.lower()) + +def get_op_setter_fn(opname): + xed_accessor_fn_pfx = ildutil.xed_strings['op_accessor'] + return '%s_set_%s' % (xed_accessor_fn_pfx, opname.lower()) + + + diff --git a/pysrc/opmap.py b/pysrc/opmap.py new file mode 100755 index 0000000..54c3d6b --- /dev/null +++ b/pysrc/opmap.py @@ -0,0 +1,212 @@ +#!/usr/bin/env python +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys,re + +class opmap_field_t(object): + """This describes one field that makes up a concatenated sequence of bits. It has a width and can be inverted""" + def __init__(self, name, width, invert=False): + self.name = name + self.width = width + self.invert = invert + # Updated when used with other fields + self.global_bit_offset = 0 # of the rightmost bit + +class opmap_t(object): + """This generates two strings: one for decoding and one for + encoding. For decoding, I pack the bit fields in to one larger + value that can be used for register indexing. For encoding, I take + the larger value and scatter it to the various component fields""" + + def __init__(self, name): + self.index_name = name + self.fields = [] # of opmap_field_t's. MSB is on the left when created! Reversed when used. + self.total_width = 0 + self.decode_output = '' + self.encode_output = '' + + def add(self,o): + self.fields.append(o) + def activate(self): + self.number_fields() + self.emit_decoder_code() + self.emit_encoder_code() + def dump(self): + print self.index_name, " DECODER OUTPUT: ", self.decode_output + print self.index_name, " ENCODER OUTPUT: ", self.encode_output + + def number_fields(self): + self.fields.reverse() + total = 0 + for f in self.fields: + f.global_bit_offset = total + total = total + f.width + self.total_width = total + + def emit_decoder_code(self): + """Assemble the fields in to an index. The index will be used + to compute a register of some type.""" + self.decode_preamble() + for f in self.fields: + self.decode_emit_one_field(f) + self.decode_epilogue() + + def emit_encoder_code(self): + """convert a given index in to settings of the various + constituent fields for subsequent encoding.""" + self.encode_preamble() + for f in self.fields: + self.encode_emit_one_field(f) + self.encode_epilogue() + + + + def decode_preamble(self): + self.decode_output = "xed_uint32_t c=" + self.decode_first_term = True + def decode_emit_one_field(self,f): + d = {} + d['shift'] = str(f.global_bit_offset) + d['name'] = f.name + if f.invert: + c = '%(conditional_or)s (((~ov[XED_OPERAND_%(name)s]) & %(mask)s) << %(shift)s)' + d['mask'] = str((1<[A-Za-z0-9_]+)[(](?P[A-Za-z0-9_]+)[)]') + + def __init__(self, field_to_bits): + """Fields to bits is a dictionary that maps field names to bit + widths as is required to manufacture opmpa_field_t objects""" + + self.groups = {} + self.field_to_bits = field_to_bits + + + def read_line(self,line): + a = line.split() + if len(a) <= 1: + die("Not enough fields on line " + line) + m=parse_opmap_t.opmap_pattern.match(a[0]) + if not m: + die("Could not parse " + line) + (group,index) = m.group("grp","indx") + fields = a[1:] + opmap = opmap_t(index) + + for f in fields: + if ":" in f: + (name,suffix) = f.split(':') + else: + name = f + suffix = None + + invert = False + if suffix: + if suffix == 'invert': + invert=True + else: + die("Unknown suffix: " + suffix) + + try: + width = self.field_to_bits[name] + except: + die("Could not find width for field [" + name + "]") + ofield = opmap_field_t(name, width, invert=invert) + opmap.add(ofield) + opmap.activate() + if group in self.groups: + die("Overwrite attempt for group: " + group) + self.groups[group] = opmap + + def read_lines(self,lines): + for line in lines: + line = re.sub(r'#.*','',line) + line = line.strip() + if line: + self.read_line(line) + + def dump(self): + for g,v in self.groups.iteritems(): + print g, ": " + v.dump() + print "\n\n" + +if __name__ == "__main__": + o = opmap_t('regidx1') + o.add(opmap_field_t('bb',1)) # leftmost field first! + o.add(opmap_field_t('b',1)) + o.add(opmap_field_t('a',3)) + o.activate() + o.dump() + + o = opmap_t('regidx2') + o.add(opmap_field_t('bb',1)) # leftmost field first! + o.add(opmap_field_t('b',1, invert=True)) + o.add(opmap_field_t('a',3)) + o.activate() + o.dump() + + d = { 'a':3, 'b':1, 'bb':1} + p = parse_opmap_t(d) + lines = [ 'FOO(indx1) a b bb', + 'BAR(indx2) bb b a', + 'ZIP(indx3) b bb:invert a' ] + p.read_lines(lines) + p.dump() diff --git a/pysrc/opnd_types.py b/pysrc/opnd_types.py new file mode 100755 index 0000000..0ab61e7 --- /dev/null +++ b/pysrc/opnd_types.py @@ -0,0 +1,83 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re,sys,os,types +from verbosity import * +import genutil +import enum_txt_writer +import codegen + +class operand_type_t(object): + def __init__(self, + name, + dtype, + bits_per_element): + self.name = name + self.dtype = dtype + self.bits_per_element = bits_per_element + + +def read_operand_types(lines): + """ Return a dictionary of operand_type_t""" + ots = {} + for line in lines: + line = re.sub(r'#.*','',line) + line = line.strip() + if line: + (xtype, dtype, bits_per_element) = line.split() + ots[xtype] = operand_type_t(xtype,dtype,bits_per_element) + + return ots + +def write_table(agi,ots): + """Emit the xtypes enum and write the initialization table""" + + fp = codegen.xed_file_emitter_t(agi.common.options.xeddir, + agi.common.options.gendir, + 'xed-init-operand-type-mappings.c') + fp.start() + fp.add_code("const xed_operand_type_info_t xed_operand_xtype_info[] = {") + names = ots.keys() + names.sort() + names = ['INVALID'] + names + ots['INVALID'] = operand_type_t('INVALID','INVALID','0') + for n in names: + v = ots[n] + s = '/* %s */ { XED_OPERAND_ELEMENT_TYPE_%s, %s },' % (n, v.dtype, v.bits_per_element) + fp.add_code(s) + fp.add_code_eol("}") + fp.close() + return fp.full_file_name + +def write_enum(agi,ots): + """Emit the xtypes enum""" + names = ots.keys() + names.sort() + names = ['INVALID'] + names + width_enum = enum_txt_writer.enum_info_t(names, + agi.common.options.xeddir, + agi.common.options.gendir, + 'xed-operand-element-xtype', + 'xed_operand_element_xtype_enum_t', + 'XED_OPERAND_XTYPE_', cplusplus=False) + width_enum.print_enum() + width_enum.run_enumer() + + return (width_enum.src_full_file_name,width_enum.hdr_full_file_name) diff --git a/pysrc/opnds.py b/pysrc/opnds.py new file mode 100644 index 0000000..f4b74b1 --- /dev/null +++ b/pysrc/opnds.py @@ -0,0 +1,491 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +import sys +import os +import types +from verbosity import * +import genutil + + +class operand_info_t(object): + """This is one of the major classes of the program. It describes + the captured fields and lookup functions that are required for + decoding.""" + + decimal_number_pattern = re.compile(r'[0-9]+') + + operand_types = [ 'reg', 'imm', 'imm_const', 'error', + 'relbr', 'ptr', 'nt_lookup_fn', 'mem', 'xed_reset', + 'flag', 'agen' ] + + def __init__(self, + name, + type, + bits='', # typically the right hand side of an operand or '1' + rw='r', + invert=False, + lookupfn_name=None, + vis='DEFAULT', + oc2=None, + cvt=[], + xtype=None, + internal=False, + multireg=0): + + self.name = name.upper() + self.type = type # See operand_info_t.operand_types + self.xtype = xtype # the user specified type for the operand + + self.internal = internal + self.multireg = multireg + + # some operands are captured during operand processing. Those + # are called inline operands + self.inline = False + + if self.type not in operand_info_t.operand_types: + genutil.die("Unexpected type when building operand: %s" % + (str(self.type))) + + # constant or varible bits, Register names. could be empty for + # lookup functions that do not take arguments. + self.bits = bits + + # for lookup-functions this is the name of that function + self.lookupfn_name = lookupfn_name + + self.rw = rw # r,w,rw, cw (conditional write, may write) + + # ascii conversion function + self.cvt = cvt + + + # accept some shorthand. + if vis == 'SUPP': + self.visibility = 'SUPPRESSED' + elif vis == 'IMPL': + self.visibility = 'IMPLICIT' + elif vis == 'EXPL': + self.visibility = 'EXPLICIT' + else: + # The default visibililty comes from the field definitions + if ( vis == 'DEFAULT' or + vis == 'EXPLICIT' or + vis == 'IMPLICIT' or + vis == 'SUPPRESSED' ): + self.visibility = vis # DEFAULT, EXPLICIT, IMPLICIT or SUPPRESSED + else: + genutil.die("Bad visibility qualifier: " + vis) + + # size code for partial reg writes. + self.oc2 = oc2 + + # Sometimes we want the actual operand to be the logical + # inversion of the captured bit. + self.invert=invert + + # names of functions for extracting or packing these bits + # These become function pointers in the instruction table. + self.bit_extractor = None + self.bit_packer = None + + # actual index of each variable bit in the operand. + # The values point to bits in the ipattern. + self.bit_positions = [] + + # Captures require finding the rightmost bit of any group of + # letter-bits of the same name. Sometimes though, the bits captured + # are constant (as in MOD[11_]). + + # sometimes the rightmost bit is not the last in the + # bit_positions list when the bits are discontinuous. So we + # stash it here to avoid searching for the maximum value in the + # bit_positions list. + self.rightmost_bitpos = 0 + + def is_ntluf(self): + if self.type == 'nt_lookup_fn': + return True + return False + + def get_cvt(self, i): + cvt = None + try: + cvt = self.cvt[i] + except: + pass + if cvt == None: + cvt = 'INVALID' + return cvt.upper() + + def get_type_for_emit(self): + if self.type == 'nt_lookup_fn' and self.multireg >= 2: + return self.type.upper() + str(self.multireg) + return self.type.upper() + + def non_binary_fixed_number(self): + "Returns True if this operand is a decimal number" + if type(self.bits) == types.ListType: + if ( len(self.bits) == 1 and + operand_info_t.decimal_number_pattern.match(self.bits[0]) ): + return True + elif type(self.bits) == types.StringType: + if operand_info_t.decimal_number_pattern.match(self.bits): + return True + return False + + def all_bits_fixed(self): + "Return True if all bits in the operand are 1s/0s (could be mixed)" + if self.bits == None: + return False + + for b in self.bits: + #genutil.msge("\ttesting bit " + b) + if b != '1' and b != '0': + # found a non 1/0 bit--> all bits are not fixed. + #genutil.msge("\t\tall not fixed! " + b) + return False + + # all bits are 1s or 0s. + return True + + def set_implicit(self): + self.visibility = 'IMPLICIT' + def set_suppressed(self): + self.visibility = 'SUPPRESSED' + + def dump_str(self, pad=''): + s = [] + s.append(pad) + s.append("{:6}".format(self.name)) + s.append("{:9}".format(self.type)) + if self.bits: + if type(self.bits) == types.ListType: + s.append(''.join(self.bits) + " (L)") + else: + s.append('[' + self.bits + ']') + s.extend([self.rw, self.visibility]) + if self.lookupfn_name: + s.append( self.lookupfn_name) + if self.oc2: + s.append( self.oc2) + if self.xtype: + s.append( self.xtype) + for c in self.cvt: + if c and c != 'INVALID': + s.append( "TXT=%s" % (c)) + if self.multireg >= 2: + s.append("MULTIREG{}".format(self.multireg)) + + if self.bit_positions: + s.append(' bitpos: ' + ', '.join(map(str,self.bit_positions))) + + if self.invert: + s.append('invert') + return " ".join(s) + + def dump(self, pad=''): + genutil.msge( self.dump_str(pad)) + def __str__(self): + return self.dump_str() + def __eq__(self,other): + if self.name != other.name: + return False + if self.type != other.type: + return False + if self.xtype != other.xtype: + return False + if self.lookupfn_name != other.lookupfn_name: + return False + if self.invert != other.invert: + return False + if self.rw != other.rw: + return False + if self.visibility != other.visibility: + return False + if self.oc2 != other.oc2: + return False + if self.cvt != other.cvt: + return False + if self.multireg != other.multireg: + return False + if self.bits != other.bits: # FIXME: check this + return False + return True + def __hash__(self): + h = 0 + if self.name: + h = h ^ self.name.__hash__() + if self.type: + h = h ^ self.type.__hash__() + if self.xtype: + h = h ^ self.xtype.__hash__() + if self.lookupfn_name: + h = h ^ self.lookupfn_name.__hash__() + # skipping invert boolean, cvt list and bits list + h = h ^ self.multireg.__hash__() + if self.rw: + h = h ^ self.rw.__hash__() + if self.visibility: + h = h ^ self.visibility.__hash__() + if self.oc2: + h = h ^ self.oc2.__hash__() + return h + +############################################################## +colon_pattern= re.compile(r'[:]') +slash_pattern= re.compile(r'/') +error_pattern = re.compile(r'^XED_ERROR_') +oc2_pattern = re.compile(r'^[a-z][a-z0-9]*$') + +# b = longbcd +# e = longdouble +# f = float +# s = struct +# v = variable +# i = signed integer +# u = unsigned integer + +decimal_number_pattern = re.compile(r'[0-9]+') +letters_underscore_pattern = re.compile(r'^[a-z_]+$') +mem_pattern = re.compile(r'MEM[01]') +imm_token_pattern = re.compile(r'IMM[0123]') +agen_pattern = re.compile(r'AGEN') +relative_branch_pattern = re.compile(r'RELBR') +pointer_pattern = re.compile(r'PTR') +xed_reset_pattern = re.compile(r'XED_RESET') +double_parens_pattern = re.compile(r'[(][)]') +equals_pattern = re.compile(r'(?P[^!]+)=(?P.+)') +not_equals_pattern = re.compile(r'(?P[^!]+)!=(?P.+)') +az_cap_pattern = re.compile(r'[A-Z]') +enum_pattern = re.compile(r'^XED_') +reg_pattern = re.compile(r'^XED_REG_') +error_pattern = re.compile(r'^XED_ERROR_') +hex_pattern = re.compile(r'0[xX][0-9A-Fa-f]+') +multireg_pattern = re.compile(r'MULTI(?P(SOURCE|DEST))(?P[0-9]+)') +convert_pattern = re.compile(r'TXT=(?P[0-9A-Za-z_]+)') + + +def parse_one_operand(w, + default_vis='DEFAULT', + xtypes=None, + default_xtypes=None, + internal=False): + """Format examples: + name=xxxxxy:{r,w,crw,rw,rcw}[:{EXPL,IMPL,SUPP,ECOND}][:{some oc2 code}][:{some xtype code}] + name=NTLUR():{r,w,crw,rw,rcw}[:{EXPL,IMPL,SUPP,ECOND}][:{some oc2 code}][:{some xtype code}] + oc2 can be before EXPL/IMPL/SUPP. oc2 is the width code. + MEM{0,1}, PTR, RELBR, AGEN, IMM{0,1,2,3} + + xtype descibes the number of data type and width of each element. + If the xtype is omitted, xed will attempt to infer it from the oc2 code. + + ECOND is for encoder-only conditions. Completely ignored by the decoder. + + Default is read-only + + @param w: string + @param w: an operand specification string + + @rtype operand_info_t + @return a parsed operand + """ + + if vopnd(): + genutil.msge("PARSE-OPND: " + w) + + # get the r/w/rw info, if any + vis = default_vis + oc2 = None + otype = None + rw = 'r' + cvt = [] + invert = False + lookupfn_name=None + xtype = None + multireg = 0 + if colon_pattern.search(w): + chunks = w.split(':') + if vopnd(): + genutil.msge("CHUNKS [%s]" % (",".join(chunks))) + for i,c in enumerate(chunks): + if vopnd(): + genutil.msge("\tCHUNK %d %s" %( i,c)) + if i == 0: + a = c + elif i == 1: + rw = c + if vopnd(): + genutil.msge("\t\tSET rw to %s" % (rw)) + elif (i == 2 or i == 3) and (c in ['IMPL', 'SUPP', 'EXPL', 'ECOND']): + vis = c + if vopnd(): + genutil.msge("\t\tSET VIS to %s" % (vis)) + else: # FIXME: somewhat sloppy error checking on input + + multi_reg_p=multireg_pattern.match(c) + cp=convert_pattern.match(c) + + if multi_reg_p: + multireg = int(multi_reg_p.group('nreg')) + elif cp: + cvt.append(cp.group('rhs')) + elif oc2 == None and oc2_pattern.match(c): + oc2 = c + if vopnd(): + genutil.msge("\t\tSET OC2 to %s" % (oc2)) + elif oc2 and c in xtypes: + xtype = c + if vopnd(): + genutil.msge("\t\tSET xtype to %s" % (xtype)) + elif decimal_number_pattern.match(c): + genutil.die("Bad number in %s" % (w)) + else: + genutil.die( + "Bad oc2 pattern in %s when looking at %d chunk: %s " % + (w,i,c) ) + + else: + a = w + + if vis == 'ECOND': + return None + + + # From now on, use a, not w. + + if slash_pattern.search(a): + genutil.die("Bad slash in operand") + + if xtype == None: + # need to use the default xtype based on the oc2 width code + if oc2: + try: + xtype = default_xtypes[oc2.upper()] + except: + s = '' + for i,v in default_xtypes.iteritems(): + s += "\t%10s -> %10s\n" % (i,v) + genutil.die("Parsing operand [%s]. Could not find default type for %s. xtypes=%s\nTypes=%s" % (w, oc2, str(xtypes), s)) + else: + # there was no oc2 type and no xtype. probably a nonterminal + # lookup function + xtype = 'INVALID' + + # look for X=y and X!=y and bare operands like MEM0. + + eqp = equals_pattern.search(a) + neqp = not_equals_pattern.search(a) + if eqp: + (name,rhs) = eqp.group('lhs','rhs') + if vopnd(): + genutil.msge("PARSE-OPND:\t" + name + " + " + rhs) + + if double_parens_pattern.search(rhs): # NTLUF + if vopnd(): + genutil.msge("PARSE-OPND:\t nonterminal lookup function " + + name + " <- " + rhs) + # remove the parens + nt_lookup_fn = double_parens_pattern.sub('',rhs) + optype ='nt_lookup_fn' + rhs = None + lookupfn_name=nt_lookup_fn + + elif reg_pattern.match(rhs): + optype = 'reg' + elif error_pattern.match(rhs): + optype = 'error' + elif enum_pattern.match(rhs): + # for storing XED_* enum values as RHS's of operand bindings + optype = 'imm_const' + elif (not genutil.numeric(rhs)) and az_cap_pattern.search(rhs): + genutil.die("THIS SHOULD NOT HAPPEN: %s" % (rhs)) + elif letters_underscore_pattern.match(rhs): + rhs = list(rhs.replace('_','')) + optype = 'imm' + else: + rhs = hex(genutil.make_numeric(rhs)) + optype = 'imm_const' + elif neqp: + (name,rhs) = neqp.group('lhs','rhs') + if vopnd(): + genutil.msge("PARSE-OPND: (NOT EQUALS)\t" + name + " + " + rhs) + invert = True + if reg_pattern.match(rhs): + optype = 'reg' + elif az_cap_pattern.search(rhs): + genutil.die("THIS SHOULD NOT HAPPEN") + elif letters_underscore_pattern.match(rhs): + genutil.die("Cannot have a != pattern with dont-care letters") + else: + rhs = hex(genutil.make_numeric(rhs)) + optype = 'imm_const' + elif mem_pattern.search(a): # memop + name = a + optype ='imm_const' + rhs = '1' + elif imm_token_pattern.search(a): # immediate placeholder + name = a + optype ='imm_const' + rhs = '1' + elif agen_pattern.search(a): # agen + name = a + optype ='imm_const' + rhs = '1' + elif relative_branch_pattern.search(a): + name = a + optype ='imm_const' + rhs = '1' + elif pointer_pattern.search(a): + name = a + optype ='imm_const' + rhs = '1' + elif xed_reset_pattern.search(a): + # special marker that tells the traverser to restart this + # nonterminal from the current position + name = a + optype ='xed_reset' + rhs = '' + vis = 'SUPP' + elif double_parens_pattern.search(a): + if vopnd(): + genutil.msge("PARSE-OPND:\t unbound nonterminal lookup function " + + a) + # 2007-07-23 this code is not used + genutil.die("UNBOUND NTLUF!: %s" % (a)) + + else: + # macros -- these get rewritten later + if vopnd(): + genutil.msge("PARSE-OPND:\t flag-ish: " + a) + name = a + optype = 'flag' + rhs = '' + + + xop = operand_info_t(name, optype, rhs, rw=rw, invert=invert, + vis=vis, oc2=oc2, cvt=cvt, xtype=xtype, + lookupfn_name=lookupfn_name, internal=internal, + multireg=multireg) + + return xop + diff --git a/pysrc/patterns.py b/pysrc/patterns.py new file mode 100755 index 0000000..591ee87 --- /dev/null +++ b/pysrc/patterns.py @@ -0,0 +1,76 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +import re + +macro_def_pattern = \ + re.compile(r'^MACRO_DEF[ \t]*[:][ \t]*(?P[_A-Za-z0-9]+)[ \t]*$') +macro_use_pattern = \ + re.compile(r'^MACRO_USE[ \t]*[:][ \t]*(?P[_A-Za-z0-9]+)[(](?P[^)]+)[)][ \t]*$') + + +xed_reg_pattern = re.compile(r'(?PXED_REG_[A-Za-z0-9_]+)') + +nt_name_pattern = re.compile(r'^(?P[A-Za-z_0-9]+)[(][)]') +ntluf_name_pattern = re.compile(r'^(?P[A-Za-z_0-9]+)[(]OUTREG[)]') +nt_pattern = re.compile(r'^(?P[A-Za-z_0-9]+)[(][)]::') +ntluf_pattern = re.compile(r'^(?P[A-Za-z0-9_]+)\s+(?P[A-Za-z_0-9]+)[(][)]::') + +# for the decode rule, the rhs might be empty +decode_rule_pattern = re.compile(r'(?P.+)[|](?P.*)') + +comment_pattern = re.compile(r'#.*$') +leading_whitespace_pattern = re.compile(r'^\s+') +full_line_comment_pattern = re.compile(r'^\s*#') +arrow_pattern = re.compile(r'(?P.+)->(?P.+)') +curly_pattern = re.compile(r'(?P[{}])') +left_curly_pattern = re.compile(r'^[{]$') # whole line +right_curly_pattern = re.compile(r'^[}]$') # whole line + +delete_iclass_pattern = re.compile('^DELETE') +delete_iclass_full_pattern = \ + re.compile(r'^DELETE[ ]*[:][ ]*(?P[A-Za-z_0-9]+)') + +udelete_pattern = re.compile('^UDELETE') +udelete_full_pattern = \ + re.compile(r'^UDELETE[ ]*[:][ ]*(?P[A-Za-z_0-9]+)') + +iclass_pattern = re.compile(r'^ICLASS\s*[:]\s*(?P[A-Za-z0-9_]+)') +uname_pattern = re.compile(r'^UNAME\s*[:]\s*(?P[A-Za-z0-9_]+)') +ipattern_pattern = re.compile(r'^PATTERN\s*[:]\s*(?P.+)') +operand_pattern = re.compile(r'^OPERANDS\s*[:]\s*(?P.+)') +no_operand_pattern = re.compile(r'^OPERANDS\s*[:]\s*$') +equals_pattern = re.compile(r'(?P[^!]+)=(?P.+)') +not_equals_pattern = re.compile(r'(?P[^!]+)!=(?P.+)') +bit_expand_pattern = re.compile(r'(?P[a-z])/(?P\d{1,2})') +rhs_pattern = re.compile(r'[!]?=.*$') +lhs_capture_pattern = re.compile(r'(?P[A-Za-z_0-9]+)[[](?P[a-z]+)]') +lhs_capture_pattern_end = re.compile(r'(?P[A-Za-z_0-9]+)[[](?P[a-z01_]+)]$') +lhs_pattern = re.compile(r'(?P[A-Za-z_0-9]+)[!=]') +hex_pattern = re.compile(r'0[xX][0-9a-fA-F]+') +decimal_pattern = re.compile(r'^[0-9]+$') +binary_pattern = re.compile(r"^0b(?P[01_]+$)") # only 1's and 0's +old_binary_pattern = re.compile(r"B['](?P[01_]+)") # Explicit leading "B'" +bits_pattern = re.compile(r'^[10]+$') +bits_and_underscores_pattern = re.compile(r'^[10_]+$') +bits_and_letters_pattern = re.compile(r'^[10a-z]+$') +bits_and_letters_underscore_pattern = re.compile(r'^[10a-z_]+$') +sequence_pattern = re.compile(r'^SEQUENCE[ \t]+(?P[A-Za-z_0-9]+)') +encoding_template_pattern = re.compile(r'[a-z01]+') +letter_pattern = re.compile(r'^[a-z]+$') +letter_and_underscore_pattern = re.compile(r'^[a-z_]+$') +simple_number_pattern = re.compile(r'^[0-9]+$') diff --git a/pysrc/read-encfile.py b/pysrc/read-encfile.py new file mode 100755 index 0000000..0c4c993 --- /dev/null +++ b/pysrc/read-encfile.py @@ -0,0 +1,3088 @@ +#!/usr/bin/env python +# Read the encode format files +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# There are dictionaries of nonterminals and sequencers. The +# sequencers are ordered lists of nonterminals. The nonterminals +# consist of rule_t's. Each rule has conditions and actions. An +# action can be a simple bit encoding or it can be a binding of a +# value to a field. A condition contains a list of or'ed condtion_t's +# and a list of and'ed condition_t's. When all the and'ed conditions +# are satisfied and one of the or'ed conditions (if any) are +# satisfied, then the action should occur. The conditions are field +# values that are = or != to a right hand side. The right hand side +# could be a value or a nonterminal (NTLUF really). Also the field +# name could be bound to some bits that are used in the action, using +# square brackets after the name. + + + +import re +import sys +import os +import types +import optparse +import stat +import copy + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + #msg("Trying %s" % (target_dir)) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +mbuild_install_path = os.path.join(os.path.dirname(sys.argv[0]), + '..', '..', 'mbuild') + +if not os.path.exists(mbuild_install_path): + mbuild_install_path = find_dir('mbuild') +sys.path= [mbuild_install_path] + sys.path +try: + import mbuild +except: + + sys.stderr.write("\nERROR(read-encfile.py): Could not find mbuild." + + " Should be a sibling of the xed2 directory.\n\n") + sys.exit(1) + +xed2_src_path = os.path.join(os.path.dirname(sys.argv[0])) +if not os.path.exists(xed2_src_path): + xed2_src_path = find_dir('xed2') +sys.path= [xed2_src_path] + sys.path +sys.path= [ os.path.join(xed2_src_path,'pysrc') ] + sys.path + +try: + import codegen + from codegen import * + from genutil import * + from scatter import * + from verbosity import * + import slash_expand + import operand_storage + import nt_func_gen + import func_gen + +except: + sys.stderr.write("\nERROR(read-encfile.py): Could not find " + + "the xed directory for python imports.\n\n") + sys.exit(1) + +import actions +import ins_emit +import encutil +from patterns import * + +storage_fields = {} +def outreg(): + return operand_storage.get_op_getter_full_func('outreg', + encutil.enc_strings) +def error_operand(): + return operand_storage.get_op_getter_full_func('error',encutil.enc_strings) + +xed_encoder_request = "xed_encoder_request_t" + +output_file_emitters = [] + +def _vmsgb(s,b=''): + if vencode(): + mbuild.msgb(s,b) + +def no_underscores(s): + v = s.replace('_','') # remove underscores + return v + +def make_writable(fn): + """Make the file or directory readable/writable/executable by me""" + _rwx_by_me = stat.S_IWUSR| stat.S_IRUSR|stat.S_IXUSR + os.chmod(fn, _rwx_by_me) + +def remove_file(fn): + """Remove a file if it exists.""" + if os.path.exists(fn): + _vmsgb("Removing ", fn) + make_writable(fn) + os.unlink(fn) + +class blot_t(object): + """A blot_t is a fragment of a decoder pattern""" + def __init__(self,type=None): + self.type = type # 'bits', 'letters', 'nt', "od" (operand decider) + self.nt = None # name of a nonterminal + self.value = None # integer representing this blot_t's value + self.length = 0 # number of bits for this blot_t + self.letters = None # sequence of substitution letters for this blot. All must be the same letter + self.field_name = None # name of the operand storage field that has the values for this blot-t + self.field_offset = 0 # offset within the field + self.od_equals = None + + def make_action_string(self): + """ + @rtype: string or None + @returns: string if the blot is something we want to make in to an action + """ + if vblot(): + msgb("Making action for blot", str(self) ) + if self.type == 'bits': + binary = ''.join(decimal_to_binary(self.value)) + if vblot(): + msgb("CONVERT", "%s <-- %s" % ( binary, str(self))) + blen = len(binary) + if blen < self.length: + # pad binary on the left with 0's until it is self.length bits long + need_zeros = self.length - blen + #msgerr("Padding with %d zeros" % need_zeros) + binary = "%s%s" % ('0'*need_zeros , binary) + blen = len(binary) + if blen > self.length: + die("bit length problem in %s --- %s" % (str(self), binary)) + if self.field_name: + return "%s[0b%s]" % (self.field_name,binary) + else: + return "0b%s" % binary + elif self.type == 'letters': + return "%s[%s]" % (self.field_name,self.letters) + elif self.type == 'od': + if self.od_equals == False: + #return "%s!=0x%x" % (self.field_name, self.value) #EXPERIMENT 2007-08-07 + if vignoreod(): + msgerr("Ignoring OD != relationships in actions: %s" % str(self)) + return None + return "%s=0x%x" % (self.field_name, self.value) + elif self.type == 'nt': + return "%s()" % self.nt + else: + die("Unhandled type: %s" % self.type) + + def __str__(self): + s = [] + if self.type: + s.append("%8s" % self.type) + else: + s.append("%8s" % "no-type") + if self.nt: + s.append("nt: %s" % self.nt) + if self.field_name: + s.append("field_name: %s" % self.field_name) + + if self.od_equals != None: + if self.od_equals: + v = '=' + else: + v = '!=' + s.append(v) + if self.type == 'letters': + s.append( "".join(self.letters) ) + if self.value != None: + s.append("0x%x" % self.value) # print as HEX + s.append("(raw %s)" % self.value) + if self.nt == None and self.od_equals == None: + s.append("length: %d" % self.length) + s.append("field_offset: %d" % self.field_offset) + return ' '.join(s) + +class operand_t(object): + """These are main ISA (decode) operands being used for encode + conditions. They are either individual tokens or X=y bindings. The + tokens or RHS of bindings can have qualifiers separated by colons: + (1) r/w/rw/cr/crcw/rcw/cw, (2) EXPL, IMPL, SUPP or ECOND, (3) + length-code. The EXPL/IMPL/SUPP/ECOND is optional as is the length + code. Memops must have the length code.""" + + convert_pattern = re.compile(r'TXT=(?P[0-9A-Za-z_]+)') + + def __init__(self,s): + pieces=s.split(':') + op_or_binding = pieces[0] + self.lencode = '?' + self.vis = None + explicit_vis = None + self.rw = '?' + self.type = None # 'token', 'binding', 'ntluf' + if len(pieces) >= 2: + nxt= pieces[1] + if nxt in [ 'IMPL', 'SUPP','EXPL', 'ECOND']: + explicit_vis = nxt + else: + self.rw = pieces[1] + if len(pieces) >= 3: + for p in pieces[2:]: + cp=operand_t.convert_pattern.match(p) + if cp: + cvt = cp.group('rhs') # ignored + elif p in [ 'IMPL', 'SUPP', 'EXPL', 'ECOND']: + explicit_vis = p + elif self.lencode == '?': + self.lencode = p + else: + _vmsgb("Ignoring [%s] from %s" % (p,s)) + #die("Unhandled operand: %s" % s) + + self.value = None + self.ntluf = False + ap = equals_pattern.match(op_or_binding) + if ap: # binding + (self.var,self.value) = ap.group('lhs','rhs') + ntluf_match = nt_name_pattern.match(self.value) + if ntluf_match: + self.value = ntluf_match.group('ntname') + self.ntluf = True + self.type = 'ntluf' + else: + self.type = 'binding' + else: # operand (MEM/IMM/DISP/etc.) + self.var = op_or_binding + self.type = 'token' + + if explicit_vis: + self.vis = explicit_vis + else: + default_vis = storage_fields[self.var].default_visibility + if default_vis == 'SUPPRESSED': + self.vis = 'SUPP' + elif default_vis == 'EXPLICIT': + self.vis = 'EXPL' + elif default_vis == 'ECOND': + self.vis = 'ECOND' + else: + die("unhandled default visibility: %s for %s" % (default_vis, self.var)) + + + + def make_condition(self): + """ + @rtype: condition_t or None + @return: list of conditions based on this operand """ + # ignore suppressed operands in encode conditions + if self.vis == 'SUPP': + return None + + # make s, a string from which we manufacture a condition_t + if self.type == 'binding': + if letter_pattern.match(self.value): + # associate the field with some letters + s = "%s[%s]=*" % (self.var, self.value) + else: + s = "%s=%s" % (self.var, self.value) + elif self.type == 'token': + s = "%s=1" % (self.var) # FIXME need to specify memop widths + elif self.type == 'ntluf': + s = "%s=%s()" % (self.var,self.value) + else: + die("Unhandled condition: %s" % str(self)) + #msgerr("MAKE COND %s" % s) + c = condition_t(s) + + #msgerr("XCOND type: %s var: %s lencode: %s" % (self.type, self.var, str(self.lencode))) + # FIXME: THIS IS A DISGUSTING HACK + if self.type == 'token' and self.var == 'MEM0': + # add a secondary condition for checking the width of the memop. + # + # NOTE: this MEM_WIDTH is not emitted! It is used in + # xed_encoder_request_t::memop_compatible() + c2 = condition_t('MEM_WIDTH',self.lencode) # MEM_WIDTH + #msgerr("\tRETURNING LIST WITH MEM_WIDTH") + return [c, c2] + return [c] + + def __str__(self): + if self.vis == 'EXPL': + pvis = '' + else: + pvis = ":%s" % self.vis + + if self.lencode == '?': + plen = '' + else: + plen = ":%s" % self.lencode + + if self.rw == '?': + prw = '' + else: + prw = ":%s" % self.rw + + if self.value: + if self.ntluf: + parens = '()' + else: + parens = '' + return "%s=%s%s%s%s%s" % ( self.var, self.value, parens, prw, plen, pvis) + return "%s%s%s%s" % ( self.var, prw, plen, pvis) + + +class rvalue_t(object): + """The right hand side of an operand decider equation. It could be + a value, a NTLUF, a * or an @. + For thing that are bits * means any value. + A @ is shorthand for ==XED_REG_INVALID""" + def __init__(self, s): + self.string = s + m = nt_name_pattern.search(s) + if m: + self.nt = True + self.value = m.group('ntname') + else: + self.nt = False + if decimal_pattern.match(s) or binary_pattern.match(s): + #_vmsgb("MAKING NUMERIC FOR %s" %(s)) + self.value = str(make_numeric(s)) + else: + #_vmsgb("AVOIDING NUMERIC FOR %s" %(s)) + self.value = s + + def nonterminal(self): + """Returns True if this rvalue is a nonterminal name""" + return self.nt + + def null(self): + if self.value == '@': + return True + return False + def any_valid(self): + if self.value == '*': + return True + return False + def __str__(self): + s = self.value + if self.nt: + s += '()' + return s + + +class condition_t(object): + """ xxx[bits]=yyyy or xxx=yyy or xxx!=yyyy. bits can be x/n where + n is a repeat count. Can also be an 'otherwise' clause that is + the final action for a nonterminal if no other rule applies. + """ + def __init__(self,s,lencode=None): + #_vmsgb("examining %s" % s) + self.string = s + self.bits = None # bound bits + self.rvalue = None + self.equals = None + self.lencode = lencode # for memory operands + + b = bit_expand_pattern.search(s) + if b: + expanded = b.group('bitname') * int(b.group('count')) + ss = bit_expand_pattern.sub(expanded,s) + else: + ss = s + rhs = None + e= equals_pattern.search(ss) + if e: + #_vmsgb("examining %s --- EQUALS" % s) + raw_left_side = e.group('lhs') + lhs = lhs_capture_pattern.search(raw_left_side) + self.equals = True + rhs = e.group('rhs') + self.rvalue = rvalue_t(rhs) + #_vmsgb("examining %s --- EQUALS rhs = %s" % (s,str(self.rvalue))) + + else: + ne = not_equals_pattern.search(ss) + if ne: + raw_left_side = ne.group('lhs') + lhs = lhs_capture_pattern.search(raw_left_side) + self.equals = False + self.rvalue = rvalue_t(ne.group('rhs')) + else: + # no equals or not-equals... just a binding. assume "=*" + raw_left_side = ss + #msgerr("TOKEN OR BINDING %s" % (raw_left_side)) + + lhs = lhs_capture_pattern.search(raw_left_side) + self.equals = True + self.rvalue = rvalue_t('*') + + # the lhs is set if we capture bits for an encode action + + if lhs: + self.field_name = lhs.group('name') + self.bits = lhs.group('bits') + else: + #_vmsgb("examining %s --- NO LHS" % (s)) + self.field_name = raw_left_side + if self.is_reg_type() and self.rvalue.any_valid(): + die("Not supporting 'any value' (*) for reg type in: %s" % s) + if self.is_reg_type() and self.equals == False: + die("Not supporting non-equal sign for reg type in: %s" % s) + + # Some bit bindings are done like "SIMM=iiiiiiii" instead + # of "MOD[mm]=*". We must handle them as well. Modify the captured rvalue + if rhs and self.equals: + rhs_short = no_underscores(rhs) + if letter_pattern.match(rhs_short): + #msgerr("LATE LETTER BINDING %s %s" % (raw_left_side, str(self.rvalue))) + self.bits = rhs_short + del self.rvalue + self.rvalue = rvalue_t('*') + return + + #msgerr("NON BINDING %s" % (s)) # FIXME: what reaches here? + + + def contains(self, s): + if self.field_name == s: + return True + return False + + def capture_info(self): + # FIXME: could locally bind bit fields in capture region to + # avoid redundant calls to xes.operands(). + return ( operand_storage.get_op_getter_full_func(self.field_name, + encutil.enc_strings), + self.bits ) + + def is_bit_capture(self): + """Binding an OD to some bits""" + if self.bits != None: + return True + return False + + def is_otherwise(self): + """Return True if this condition is an 'otherwise' final + condition.""" + if self.field_name == 'otherwise': + return True + return False + + def is_reg_type(self): + if self.field_name not in storage_fields: + return False + ctype = storage_fields[self.field_name].ctype + return ctype == 'xed_reg_enum_t' + + def __str__(self): + s = [ self.field_name ] + if self.memory_condition(): # MEM_WIDTH + s.append(" (MEMOP %s)" % self.lencode) + if self.bits: + s.append( '[%s]' % (self.bits)) + if self.equals: + s.append( '=' ) + else: + s.append('!=') + s.append(str(self.rvalue)) + return ''.join(s) + + def memory_condition(self): # MEM_WIDTH + if self.lencode != None: + return True + return False + + def emit_code(self): + #msgerr("CONDEMIT " + str(self)) + if self.is_otherwise(): + return "1" + + if self.equals: + equals_string = '==' + else: + equals_string = '!=' + + #FIXME: get read off this old accessor + op_accessor = operand_storage.get_op_getter_full_func(self.field_name, + encutil.enc_strings) + + if self.memory_condition(): # MEM_WIDTH + s = 'xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_%s)' % (self.lencode.upper()) + elif self.rvalue.nonterminal(): + s = 'xed_encode_ntluf_%s(xes,%s)' % (self.rvalue.value,op_accessor) + elif self.rvalue.any_valid(): + if storage_fields[self.field_name].ctype == 'xed_reg_enum_t': + # FOO=* is the same as FOO!=XED_REG_INVALID. So we + # invert the equals sign here. + if self.equals: + any_equals = "!=" + else: + any_equals = "==" + s = "(%s %s XED_REG_INVALID)" % (op_accessor,any_equals) + else: + s = '1' + + elif self.rvalue.null(): + s = "(%s %s XED_REG_INVALID)" % (op_accessor,equals_string) + else: # normal bound value test + if self.rvalue.value == 'XED_REG_ERROR': + s = '0' + else: + #msgerr("CONDEMIT2 " + str(self) + " -> " + self.rvalue.value) + s = "(%s %s %s)" % (op_accessor,equals_string, + self.rvalue.value) + return s + + +class conditions_t(object): + """Two lists of condition_t's. One gets ANDed together and one gets + ORed together. The OR-output gets ANDed with the rest of the AND + terms.""" + def __init__(self): + self.and_conditions = [] + def contains(self,s): + for c in self.and_conditions: + if c.contains(s): + return True + return False + + def and_cond(self, c): + if type(c) == types.StringType: + nc = condition_t(c) + else: + nc = c + self.and_conditions.append(nc) + + def has_otherwise(self): + for a in self.and_conditions: + if a.is_otherwise(): + return True + return False + + def __str__(self): + s = [] + for a in self.and_conditions: + s.append(str(a)) + s.append(' ') + return ''.join(s) + + + + + def _captures_from_list(self, clist): + """ + @type clist: list of condition_t + @param clist: list of condition_t + + Return a list of tuples (fieldname, bits) for use by code + generation (emit actions), by searching the conditions to see + which ones are captures""" + if vcapture(): + msgb("CAPTURE COLLECTION USING:\n\t%s\n" % "\n\t".join(map(str,clist))) + full_captures = filter(lambda(x): x.is_bit_capture(), clist) + captures = map(lambda(x): x.capture_info(), full_captures) + return captures + + def compute_field_capture_list(self): + """Study the conditions and return a list of tuples + (fieldname, bits) for use by code-emit actions, by searching + the conditions to see which ones are captures""" + + captures = self._captures_from_list(self.and_conditions) + return captures + + def field_names_from_list(self,clist): + """Return a tuple of list of field names and list of NTS""" + field_names = [] + nt_names = [] + for cond in clist: + if cond.field_name: + field_names.append(cond.field_name) + if cond.rvalue and cond.rvalue.nonterminal(): + nt_names.append(cond.rvalue.value) + + return (field_names, nt_names) + + def get_field_names(self): + """Return a tuple of list of field names and list of NTS""" + and_field_names = self.field_names_from_list(self.and_conditions) + return ( and_field_names[0] , and_field_names[1]) + + def emit_code(self): + if len(self.and_conditions) == 1: + if self.and_conditions[0].is_otherwise(): + return [ 'conditions_satisfied = 1;' ] + + # conditions_satisfied = f1 && f2 && f3 + # + # if conditions are operand deciders we just do the test. + # if conditions are NTLUFs then we must see if the name is in + # the set defined by the NTLUF. For example, BASE0=ArAX(). If + # BASE0 is rAX then we are and the corresponding subexpression + # should be True. + + s = ['conditions_satisfied = ' ] + emitted = False + if len(self.and_conditions) == 0: + # no conditions. that's okay. encoder's job is simple in this case... + s.append('1') + emitted = True + elif len(self.and_conditions) == 1 and self.and_conditions[0].field_name == 'ENCODER_PREFERRED': + s.append('1') + emitted = True + else: + first_and = True + for and_cond in self.and_conditions: + if and_cond.field_name == 'ENCODER_PREFERRED': + continue + try: + t = and_cond.emit_code() + if t != '1': + if first_and: + first_and = False + else: + s.append( ' &&\n\t\t ') + emitted = True + s.append( t ) + except: + die("Could not emit code for condition %s of %s" % ( str(and_cond), str(self))) + if not emitted: + s.append('1') + + s.append(';') + return [ ''.join(s) ] + + + + +class iform_builder_t(object): + def __init__(self): + self.iforms = {} + def remember_iforms(self,ntname): + if ntname not in self.iforms: + self.iforms[ntname] = True + def _build(self): + self.cgen = c_class_generator_t("xed_encoder_iforms_t", var_prefix="x_") + for v in self.iforms.iterkeys(): + self.cgen.add_var(v, 'xed_uint32_t', accessors='none') + def emit_header(self): + self._build() + return self.cgen.emit_decl() + + +iform_builder = iform_builder_t() # FIXME GLOBAL + +class rule_t(object): + """The encoder conditions -> actions. These are stored in nonterminals.""" + def __init__(self, conditions, action_list, nt): + """ + @type conditions: conditions_t + @param conditions: a conditions_t object specifying the encode conditions + + @type action_list: list of strings/action_t + @param action_list: list of actions can string or action_t obj. + + @type nt: string + @param nt: the nt which this rule is belong to + """ + _vmsgb("MAKING RULE", "%s - > %s" % (str(conditions), str(action_list))) + self.default = False #indicates whether this rule is a default rule + self.nt = nt + self.index = 0 #index is used to identify the correct emit order + self.conditions = self.handle_enc_preferred(conditions) + self.actions = [] + + for action in action_list: + if type(action) == types.StringType: + self.actions.append(actions.action_t(action)) + else: + self.actions.append(action) + + def __str__(self): + s = [ str(self.conditions) , " ->\t" ] + first = True + for a in self.actions: + if first: + first=False + else: + s.append(" \t") + s.append(str(a)) + return ''.join(s) + + def handle_enc_preferred(self,conditions): + ''' remove the ENCODER_PREFERRED constraint and replace it with + an attribute ''' + for cond in conditions.and_conditions: + if cond.field_name == "ENCODER_PREFERRED": + self.enc_preferred = True + conditions.and_conditions.remove(cond) + + else: + self.enc_preferred = False + return conditions + + def compute_field_capture_list(self): + """Look at the conditions and return a list of tuples + (fieldname, bits) for use by code generation, by searching the + conditions to see which one s are captures""" + + # 2009-02-08: using the bind-phase test conditions is wrong, + # as we do not need to test all the bindings. + + return self.conditions.compute_field_capture_list() + + def prepare_value_for_emit(self, a): + """@return: (length-in-bits, value-as-hex)""" + if a.emit_type == 'numeric': + v = hex(a.int_value) + return (a.nbits, v) # return v with the leading 0x + s = a.value + if hex_pattern.match(s): + return ((len(s)-2)*4, s) #hex nibbles - 0x -> bytes + s_short = no_underscores(s) + if bits_pattern.match(s_short): # ones and zeros + return (len(s_short), hex(int(s_short,2))) + die("prepare_value_for_emit: Unhandled value [%s] for rule: [%s]" %(s,str(self))) + + def uses_bit_vector(self): + """For encoding multiple prefixes, we need to stash multiple values in the IFORM. This is the key.""" + for a in self.actions: + if a.is_field_binding(): + if a.field_name == 'NO_RETURN': # FIXME: check value ==1? + return True + return False + + def has_nothing_action(self): + for a in self.actions: + if a.is_nothing(): + return True + return False + + def has_error_action(self): + for a in self.actions: + if a.is_error(): + return True + elif a.is_field_binding() and a.field_name == 'ERROR': + return True + return False + + def has_emit_action(self): + for a in self.actions: + if a.is_emit_action(): + return True + return False + def has_nonterminal_action(self): + for a in self.actions: + if a.is_nonterminal(): + return True + return False + + def has_naked_bit_action(self): + for a in self.actions: + if a.naked_bits(): + return True + return False + + + def has_no_return_action(self): + for a in self.actions: + if a.is_field_binding(): + # for repeating prefixes, we have the NO_RETURN field. + if a.field_name == 'NO_RETURN': # FIXME: check value ==1? + return True; + return False + + def has_otherwise_rule(self): + if self.conditions.has_otherwise(): + return True + return False + + + + def get_nt_in_cond_list(self): + #returns the condition with nt, if exists + nts = [] + for cond in self.conditions.and_conditions: + rvalue = cond.rvalue + if rvalue.nonterminal(): + nts.append(cond) + + if len(nts) == 0: + return None + if len(nts) == 1: + return nts[0] + error = ("the rule %s has more than one nt in the" + + "condition list, we do not support it currently") % str(self) + die(error) + + def emit_isa_rule(self, ith_rule, group): + ''' emit code for INSTRUCTION's rule: + 1. conditions. + 2. set of the encoders iform index. + 3. call the field binding pattern function to set values to flieds. + 4. nonterminal action type. + + + ''' + lines = [] + # 1. + lines.extend( self.conditions.emit_code() ) + lines.append( "if (conditions_satisfied) {") + lines.append( " okay=1;") + + # 2. + obj_name = encutil.enc_strings['obj_str'] + set_iform = 'xed_encoder_request_set_iform_index' + code = '%s(%s,iform_ids[iclass_index][%d])' + code = code % (set_iform,obj_name,ith_rule) + lines.append(' %s;' % code) + + # 3. + get_fb_ptrn = (' fb_ptrn_function = '+ + 'xed_encoder_get_fb_ptrn(%s);' % obj_name ) + lines.append(get_fb_ptrn) + #call function that sets the values to the fileid + lines.append(' (*fb_ptrn_function)(%s);' % obj_name) + + # 4. + for a in self.actions: + if a.is_nonterminal(): + lines += a.emit_code('BIND') + + lines.append( " if (okay) return 1;") + lines.append( "}") + return lines + + def emit_rule_bind(self, ith_rule, nt_name, ntluf): + lines = [] + # + # emit code for the conditions and if the conditions are true, do the action + # + lines.extend( self.conditions.emit_code() ) + lines.append( "if (conditions_satisfied) {") + lines.append( " okay=1;") # 2007-07-03 start okay over again... + obj_name = encutil.enc_strings['obj_str'] + + do_return = True + use_bit_vector = self.uses_bit_vector() + has_nothing_action = self.has_nothing_action() + has_error_action = self.has_error_action() + has_nonterminal_action = self.has_nonterminal_action() + has_emit_action = self.has_emit_action() + + # NESTED FUNCTION! + def emit_code_bind_sub(a,lines, do_return): + #msgerr("Codegen for action %s" % str(a)) + if a.is_field_binding(): + # for repeating prefixes, we have the NO_RETURN field. + if a.field_name == 'NO_RETURN': # FIXME: could check bound value == 1. + do_return = False + lines.extend( a.emit_code('BIND') ) + return do_return + + + # first do the non nonterminals + for a in self.actions: + if not a.is_nonterminal(): + do_return = emit_code_bind_sub(a, lines, do_return) + + # do the nonterminals after everything else + for a in self.actions: + if a.is_nonterminal(): + do_return = emit_code_bind_sub(a, lines, do_return) + + #here we are setting the enc iform ordinal + if (has_emit_action or has_nonterminal_action) and \ + not has_error_action: + # We do not set the iform for the "nothing" actions. + if not has_nothing_action: + if use_bit_vector: + code = 'xed_encoder_request_iforms(%s)->x_%s |=(1<<%d)' + code = code % (obj_name,nt_name,ith_rule) + lines.append( ' %s;' % code) + else: + code = 'xed_encoder_request_iforms(%s)->x_%s=%d' + code = code % (obj_name,nt_name,ith_rule) + lines.append( ' %s;' % code) + iform_builder.remember_iforms(nt_name) + + if do_return: + # 2007-07-03 I added the condtional return to allow + # checking other encode options in the event that a + # sub-nonterminal (in this case SIMMz) tanks a partially made "BIND" decision. + lines.append( " if (okay) return 1;") + + lines.append( "}") + return lines + + def emit_rule_emit(self, ith_rule_arg, nt_name, captures): + """Return a list of lines of code for the nonterminal function. + + @type ith_rule_arg: integer + @param ith_rule_arg: number of the iform for which we are emitting code. + + @type ntname: string + @param ntname: name of the nonterm + + @type captures: list + @param captures: list of tuples (c-string,bits) (optional) + """ + lines = [] + # emit code for the conditions and if the conditions are true, do the action + + use_bit_vector = self.uses_bit_vector() + has_error_action = self.has_error_action() + has_nothing_action = self.has_nothing_action() + has_no_return_action = self.has_no_return_action() + has_otherwise_rule = self.has_otherwise_rule() + + #complicated_nt are nonterminals that can not be auto generated using + #hash function and look uptables due to thier complexity + #so we generete them in the old if statement structure + complicated_nt = nt_func_gen.get_complicated_nt() + + # the 'INSTRUCTIONS' and the complicated nts emit iform are + # using the old ordering mechnism + # all other nts are using the new attribute index to set the order + ith_rule = ith_rule_arg + if nt_name != 'INSTRUCTIONS' and nt_name not in complicated_nt: + ith_rule = self.index + has_otherwise_rule = self.default + + if veemit(): + msgb("EEMIT", "%d %s %s" % (ith_rule, nt_name, self.__str__())) + + if has_no_return_action: + cond_else = '/* no return */ ' + else: + cond_else = '/* %d */ ' % (ith_rule) + + + if has_otherwise_rule: + # 2007-07-23: otherwise rules always fire in emit. There + # is no "else" for the otherwise rule. It is a catch-all. + lines.append( "if (1) { /*otherwise*/") + elif has_nothing_action: + # Some rules have 'nothing' actions that serve as epsilon accepts. + lines.append( "%sif (1) { /* nothing */" % (cond_else)) + for a in self.actions: + if not a.is_nothing(): + die("Nothing action mixed with other actions") + elif has_error_action: + # + # do not check the iform on error actions -- just ignore + # them. They are caught in the "BIND" step. + return [] + + elif use_bit_vector: + lines.append( "%sif (iform&(1<<%d)) {" % (cond_else,ith_rule)) + else: + lines.append( "%sif (iform==%d) {" % (cond_else,ith_rule)) + do_return = True + + for a in self.actions: + if veemit(): + msgb("Codegen for action", str(a)) + + if a.is_field_binding(): + # for repeating prefixes, we have the NO_RETURN field. + if a.field_name == 'NO_RETURN': # FIXME: check value ==1? + do_return = False + continue + + if a.is_nonterminal(): + if veemit(): + msgb("EEMIT NT ACTION", str(a)) + t = a.emit_code('EMIT') # EMIT for NTs + if veemit(): + for x in t: + msgb("NT EMIT", x) + lines.extend( t ) + + elif a.is_emit_action(): + # emit actions require knowledge of all the conditions + # which have the field bindings so we emit them here. + if captures: + list_of_tuples = captures + else: + list_of_tuples = self.compute_field_capture_list() + + if vtuples(): + msgb("TUPLES", (" ,".join(map(str, list_of_tuples)))) + if len(list_of_tuples) == 0 or a.emit_type == 'numeric': + # no substitutions required + (length, s) = self.prepare_value_for_emit(a) + if veemit(): + msgb("SIMPLE EMIT", "bits=%d value=%s" % (length, s)) + else: + (length,s) = scatter_gen( a.value, list_of_tuples) + #msgerr("SCATTERGEN %s %s -> %s %s" % (str(a.value), str(list_of_tuples), length, s)) + t = " xed_encoder_request_encode_emit(xes,%s,%s);" % (length,s) + if veemit(): + msgb("EMITTING" , t) + lines.append(t) + + if do_return: + #lines.append( " if (okay && %s != XED_ERROR_NONE) okay=0;" % (error_operand())) + lines.append( " if (%s != XED_ERROR_NONE) okay=0;" % (error_operand())) + #lines.append( " if (okay) return 1;") + lines.append( " return okay;") + lines.append( "}") # close iform + return lines + + def emit_rule(self, bind_or_emit, ith_rule, nt_name, captures=None): + """Return a list of lines of code for the nonterminal + function. + + @type bind_or_emit: string + @param bind_or_emit: 'BIND', 'EMIT' or 'NTLUF' + """ + if bind_or_emit == 'NTLUF': + ntluf = True + else: + ntluf = False + + if bind_or_emit == 'BIND' or bind_or_emit == 'NTLUF': + return self.emit_rule_bind(ith_rule, nt_name, ntluf) + elif bind_or_emit == 'EMIT': + return self.emit_rule_emit(ith_rule, nt_name,captures) + else: + die("Need BIND or EMIT") + + def get_all_fbs(self): + ''' collect all the actions that sets fields ''' + fbs = [] + for action in self.actions: + if action.is_field_binding(): + fbs.append(action) + if action.is_emit_action() and action.emit_type == 'numeric': + if action.field_name: + fbs.append(action) + return fbs + + def get_all_emits(self): + ''' return a list of all emit type actions ''' + emits = [] + for action in self.actions: + if action.is_emit_action(): + emits.append(action) + return emits + + def get_all_nts(self): + ''' return a list of all nonterminal type actions ''' + nts = [] + for action in self.actions: + if action.is_nonterminal(): + nts.append(action) + return nts + +class iform_t(object): + """One form of an instruction""" + def __init__(self, iclass, enc_conditions, enc_actions, modal_patterns, uname=None): + self.iclass = iclass + self.uname = uname + self.enc_conditions = enc_conditions # [ operand_t ] + self.enc_actions = enc_actions # [ blot_t ] + self.modal_patterns = modal_patterns # [ string ] + self.rule = self.make_rule() + + #the emit phase action pattern + self.emit_actions = None + + #the FB actions pattern + self.fb_ptrn = None + + + def make_operand_name_list(self): + """Make an ordered list of operand storage field names that + drives encode operand order checking. """ + operand_names = [] + for opnd in self.enc_conditions: + if voperand2(): + msg( "EOLIST iclass %s opnd %s vis %s" % (self.iclass, opnd.var, opnd.vis)) + if opnd.vis == 'SUPP': + continue + if opnd.vis == 'ECOND': + continue + if self._check_encoder_input(opnd.var): + operand_names.append(opnd.var) + # 2007-07-05 We do not need to add MEM_WIDTH, since that does + # not affect operand order. It is checked for memops by + # encode. + return operand_names + + + def compute_binding_strings_for_emit(self): + """Gather up *all* the conditions (suppressed or not) and + include them as possible canditates for supplying bits for the + encoder.""" + + captures = [] + for opnd in self.enc_conditions: # each is an operand_t + if opnd.type == 'binding': + if letter_and_underscore_pattern.match(opnd.value): + captures.append((opnd.var, no_underscores(opnd.value))) + else: + pass + #msge("SKIPPING BINDING " + str(opnd)) + + # add the C decoration to the field name for emitting code. + decorated_captures = [] + for (f,b) in captures: + decorated_captures.append((operand_storage.get_op_getter_fn(f),b)) + return decorated_captures + + def _check_encoder_input(self,name): + """Return True for things that are storage field encoder inputs""" + global storage_fields + if name in storage_fields and storage_fields[name].encoder_input: + return True + return False + + def find_encoder_inputs(self): + """Return a set of encoder input field names""" + s = set() + ns = set() + for mp in self.modal_patterns: + if self._check_encoder_input(mp): + s.add(mp) + + for op in self.enc_conditions: + # The encoder ignores SUPP operands. + if op.vis == 'SUPP': + continue + if op.type == 'token' or op.type == 'binding' or op.type == 'ntluf': + if self._check_encoder_input(op.var): + s.add(op.var) + if op.lencode != '?': + s.add('MEM_WIDTH') + if op.ntluf: + ns.add(op.value) + return (s,ns) + + def make_rule(self): + """Return a rule_t based on the conditions and action_list.""" + if vrule(): + msgb("MAKE RULE","for %s" % str(self)) + action_list = [] # [ string ] + for blot in self.enc_actions: + a = blot.make_action_string() + if a: + action_list.append(a) + + cond = conditions_t() + for mp in self.modal_patterns: + if vrule(): + msgb("Adding MODAL_PATTERN", mp) + c = condition_t(mp) + cond.and_cond(c) + + for opnd in self.enc_conditions: + # some conditions we ignore: like for SUPP registers... + if vrule(): + msge("OPERAND: %s" % (str(opnd))) + c = opnd.make_condition() + if c: + if vrule(): + msge("\t MADE CONDITION") + for subc in c: + if vrule(): + msge("\t\tANDCOND %s" % str(subc)) + cond.and_cond(subc) + else: + if vrule(): + msge("\t SKIPPING OPERAND in the AND CONDITIONS") + #here we are handling only instructions. + #Do not need to specify the nt name since the instructions have + #their own emit function and this nt name is not used + rule = rule_t(cond,action_list, None) + self._remove_overlapping_actions(rule.actions) + return rule + + + def _remove_overlapping_actions(self, action_list): + ''' for some actions the generated code looks exactly the same. + for example: + action1: MOD=0 + action2: MOD[0b00] + + the generated code for both of them in the BIND phase is the same + and for action1 we do nothing in the EMIT phase. + + we are itereting over all the field binding to see if we have + overlapping emit action. + + modifying to input action_list + ''' + + emit_actions = filter(lambda x: x.type == 'emit', action_list) + fb_actions = filter(lambda x: x.type == 'FB', action_list) + + #iterate to find overlapping actions + action_to_remove = [] + for fb in fb_actions: + for emit in emit_actions: + if fb.field_name.lower() == emit.field_name and \ + emit.emit_type == 'numeric': + if fb.int_value == emit.int_value: + # overlapping actions, recored this action + # and remove later + action_to_remove.append(fb) + else: + err = "FB and emit action for %s has different values" + genutil.die(err % fb.field_name) + + #remove the overlapping actions + for action in action_to_remove: + action_list.remove(action) + + def __str__(self): + s = [] + s.append("ICLASS: %s" % self.iclass) + s.append("CONDITIONS:") + for c in self.enc_conditions: + s.append("\t%s" % str(c)) + s.append( "ACTIONS:") + for a in self.enc_actions: + s.append("\t%s" % str(a)) + return '\n'.join(s) + +def rule_tuple_sort(a,b): + (a1,a2) = a + (b1,b2) = b + if a1 > b1: + return 1 + elif a1 < b1: + return -1 + return 0 + +class nonterminal_t(object): + def __init__(self, name, rettype=None): + """ + The return type is for the NLTUFs only. + """ + self.name = name + self.rettype = rettype # if non None, then this is a NTLUF + self.rules = [] + #FIXME: this will be used in the future + #self.otherwise = actions.action_t('error=XED_ERROR_GENERAL_ERROR') + self.otherwise = [actions.gen_return_action('0')] + + def _default_rule(self): + ''' return a rule_t object, where the conditions are: 'otherewise' + and the actions are taken from the otherwise attribute + ''' + + conds = conditions_t() + conds.and_cond('otherwise') + rule = rule_t(conds,self.otherwise,self.name) + rule.default = True + return rule + + def is_ntluf(self): + if self.rettype: + return True + return False + + def add(self,rule): + self.rules.append(rule) + def __str__(self): + s = [ self.name , "()::\n" ] + for r in self.rules: + s.extend(["\t" , str(r) , "\n"]) + return ''.join(s) + + def add_simple_rule(self, cond, action): + """ + @type cond: string + @param cond: condition + @type action: string + @param action: simple action + """ + conditions = conditions_t() + conditions.and_cond(cond) + actions = [ action ] + r = rule_t(conditions, actions) + self.rules.append(r) + + def multiple_otherwise_rules(self): + c = 0 + for r in self.rules: + if r.has_otherwise_rule(): + c = c + 1 + if c > 1: + return True + return False + + def sort_for_size(self): + tups = [] + # PERF: want the 'nothing' bindings to occur before the error + # bindings because the errors are less frequent. (Only one + # "nothing" emit will occur and "error" actions do not show up + # in the "emit" phase.) + for rule in self.rules: + if rule.has_otherwise_rule(): + weight = 99999 # make it last + elif rule.has_nothing_action(): + weight = 99997 + elif rule.has_error_action(): + weight = 99998 + else: + weight = len(rule.actions) # try to get shortest form first... + _vmsgb("RULE WEIGHT %d" % (weight), str(rule)) + tups.append((weight,rule)) + tups.sort(cmp=rule_tuple_sort) + newrules = [] + for (x,y) in tups: + newrules.append(y) + self.rules = newrules + + def create_function(self, bind_or_emit): + if self.is_ntluf(): # bind_or_emit should be 'NTLUF' + fname = 'xed_encode_ntluf_%s' % self.name + else: + fname = 'xed_encode_nonterminal_%s_%s' % (self.name, bind_or_emit) + if vntname(): + msgb("NTNAME", self.name) + fo = function_object_t(fname,"xed_uint_t") + fo.add_arg("%s* xes" % xed_encoder_request) + if self.is_ntluf(): + fo.add_arg("xed_reg_enum_t arg_reg") # bind this to OUTREG below + fo.add_comment(self.__str__()) + fo.add_code_eol("xed_uint_t okay=1") + if bind_or_emit == 'BIND' or bind_or_emit == 'NTLUF': + fo.add_code_eol( "xed_uint_t conditions_satisfied=0" ) + + has_emit_action = False + if bind_or_emit == 'EMIT': + for r in self.rules: + if r.has_emit_action(): + has_emit_action = True + break + + has_nonterminal_action = False + if bind_or_emit == 'EMIT': + for r in self.rules: + if r.has_nonterminal_action(): + has_nonterminal_action = True + break + + # FIXME: PERF using OUTREG to hold arg_reg is the easiest way + # to not change any of the condition code generation stuff. I + # could easily optimize this later. 2007-04-10 + + nt_name = self.name + + if self.is_ntluf(): + fo.add_code_eol( "%s = arg_reg" % (outreg())) + + # setup or read the IFORM variable if we are binding or emitting. + if bind_or_emit == 'BIND' or bind_or_emit == 'NTLUF': + if len(self.rules)>0: + if self.rules[0].uses_bit_vector(): + fo.add_code_eol( "xed_encoder_request_iforms(xes)->x_%s=0" % (nt_name) ) + iform_builder.remember_iforms(nt_name) + + else: # EMIT + if has_emit_action or has_nonterminal_action: + fo.add_code_eol( "unsigned int iform = xed_encoder_request_iforms(xes)->x_%s" % (nt_name) ) + iform_builder.remember_iforms(nt_name) + else: + # nothing to emit, so skip this... + fo.add_code_eol('return 1') + fo.add_code_eol('(void) okay') + fo.add_code_eol('(void) xes') + return fo + + #_vmsgb("EMITTING RULES FOR", nt_name) + + emitted_nothing_action=False + for i,rule in enumerate(self.rules): + #_vmsgb("EMITTING RULE %d" % (i+1)) + emitr = True + if bind_or_emit == 'EMIT' and rule.has_nothing_action(): + if emitted_nothing_action: + emitr = False + emitted_nothing_action = True + if emitr: + lines = rule.emit_rule(bind_or_emit,i+1, nt_name) + fo.add_lines(lines) + default_rule = self._default_rule() + lines = default_rule.emit_rule(bind_or_emit,0, nt_name) + fo.add_lines(lines) + + fo.add_code('return 0; /*pacify the compiler*/') + fo.add_code_eol('(void) okay') + fo.add_code_eol('(void) xes') + if bind_or_emit == 'EMIT': + fo.add_code_eol('(void) iform') + + if bind_or_emit == 'BIND' or bind_or_emit == 'NTLUF': + fo.add_code_eol("(void) conditions_satisfied") + return fo + +class sequencer_t(object): + def __init__(self, name): + self.name = name + self.nonterminals = [] + def add(self,nt): + t = nt_name_pattern.search(nt) + if t: + self.nonterminals.append(t.group('ntname')) + else: + self.nonterminals.append(nt) + def __str__(self): + s = ["SEQUENCE " , self.name , "\n"] + for nt in self.nonterminals: + s.extend(["\t" , str(nt) , "()\n"]) + return ''.join(s) + def create_function(self,sequences): + fname = 'xed_encode_nonterminal_' + self.name + lst = [] + for x in self.nonterminals: + # FIXME 2007-06-29 Mark Charney: This looks odd + if x in sequences: + lst.append("xed_encode_nonterminal_%s" % x) + else: + lst.append("xed_encode_nonterminal_%s" % x) + + arg ='xes' + fo = function_call_sequence_conditional(fname,lst,arg) + fo.add_arg('%s* xes' % xed_encoder_request) + return fo + + +def group_bits_and_letter_runs(s): + """ + @type s: string + @param s: string of the form [01a-z]+ + + @rtype: list of strings + @return: list of binary bit strings and distinct letter runs + """ + out = [] + run = None + last_letter = None + last_was_number = False + # remove underscores from s + for i in list(s.replace('_','')): + if i=='0' or i=='1': + if last_was_number: + run += i + else: + if run: + out.append(run) # end last run + run = i + last_was_number = True + last_letter = None + + else: # i is a letter + + if last_letter and last_letter == i: + run += i + else: + if run: + out.append(run) # end last run + run = i + last_was_number = False + last_letter = i + if run: + out.append(run) + return out + + +class encoder_input_files_t(object): + def __init__(self, options): + self.xeddir = options.xeddir + self.gendir = options.gendir + self.storage_fields_file = options.input_fields + self.regs_input_file = options.input_regs + self.decoder_input_files = options.enc_dec_patterns + self.encoder_input_files = options.enc_patterns + self.state_bits_file = options.input_state + self.instructions_file = options.isa_input_file + + # dict of operand_order_t indexed by special keys stored in iform.operand_order_key + self.all_operand_name_list_dict = None + + + def input_file(self,s): + """Join the xeddir and the datafiles dir to s""" + return os.path.join(self.xeddir,'datafiles',s) + +class operand_order_t(object): + def __init__(self,n,lst): + self.n = n # index in to the encode_order array + self.lst = lst # list of nonsuppressed operands + +class encoder_configuration_t(object): + # decode: ipatterns -> operands + # encode: conditions -> actions + + # normally ipatterns become actions. + # normally operands become conditions. + # however, + # some ipatterns become conditions + # and some operands become actions. + # + # and finally, some operands get dropped entirely. + + def __init__(self, encoder_input_files, amd_enabled=True): + self.amd_enabled = amd_enabled + self.files = encoder_input_files + self.gendir = self.files.gendir + self.xeddir = self.files.xeddir + + + global storage_fields + lines = file(self.files.storage_fields_file) + operands_storage = operand_storage.operands_storage_t(lines) + storage_fields = operands_storage.get_operands() + + self.state_bits = None + + self.sequences = {} + self.nonterminals = {} + + self.decoder_nonterminals = {} + self.decoder_ntlufs = {} + + self.functions = [] + + # the main ISA decode rules are stored here before conversion + # to the encode rules + self.iarray = {} # dictionary by iclass of [ iform_t ] + + self.deleted_instructions = {} # by iclass + self.deleted_unames = {} # by uname + + cmkdir(self.gendir) + + def dump_output_file_names(self): + global output_file_emitters + ofn = os.path.join(self.gendir,"ENCGEN-OUTPUT-FILES.txt") + o = open(ofn,"w") + for fe in output_file_emitters: + o.write(fe.full_file_name + "\n") + o.close() + + def parse_decode_rule(self, conds,actions ,line, nt_name): + # conds -- rhs, from an encode perspective (decode operands) + # actions -- lhs, from an encode perspective (decode patterns) + + # move some special actions to the conditions + new_actions = [] + for a in actions: # decode patterns + if veparse(): + msgb("parse_decode_rule actions", str(a)) + q = lhs_pattern.match(a) + if q: + lhs_a = q.group('name') + if lhs_a in storage_fields and storage_fields[lhs_a].encoder_input == True: + if veparse(): + msgb("CVT TO ENCODER CONDITION", lhs_a) + conds.append(a) + continue + opcap = lhs_capture_pattern_end.match(a) + if opcap: + synth_cap = "%s=%s" % (opcap.group('name'), opcap.group('bits')) + conds.append( synth_cap ) + if veparse(): + msge("SYNTH CONDITION FOR " + a + " --> " + synth_cap ) + new_actions.append(a) + continue + if veparse(): + msge("NEWACTION " + a) + new_actions.append(a) + del actions + + # Move some special encode conditions to the encode + # actions if they are not encoder inputs. This solves + # a problem with encoding IMM0SIGNED on SIMMz() + # nonterminals. + new_conds = [] + for c in conds: # were decode operands (rhs) + if veparse(): + msgb("parse_decode_rule conditions", str(c)) + if c.find('=') == -1: + trimmed_cond = c + else: + ep = equals_pattern.match(c) # catches "=", but not "!=" + if ep: + trimmed_cond = ep.group('lhs') + else: + die("Bad condition: %s" % c) + if veparse(): + msgb("TESTING COND", "%s --> %s" % (c, trimmed_cond)) + keep_in_conds = True + try: + if storage_fields[trimmed_cond].encoder_input == False: + if veparse(): + msgb("DROPPING COND", c) + keep_in_conds = False # 2007-08-01 + except: + pass + + # if we have the constraint: OUTREG=some_nt() and it is not the + # single constraint we want to move + # the nt: some_nt() to the actions side. + # e.g. the constraint: MODE=3 OUTREG=GPRv_64() -> nothing + # becomes: MODE=3 -> GPRv_64() + if trimmed_cond == 'OUTREG': + nt = nt_name_pattern.match(c.split('=')[1]) + if nt and len(conds) > 1: + c = "%s(OUTREG)" % nt.group('ntname') + keep_in_conds = False + + if keep_in_conds: + new_conds.append(c) + else: + if veparse(): + msge("COND->ACTION " + c) # FIXME: REMOVEME + new_actions.append(c) + conds = new_conds + + # signal it is okay if there is no action + if len(new_actions) == 0: + new_actions.append('nothing') + + if len(conds) == 0: + conds = ['otherwise'] + + if len(conds) > 0: + conditions = conditions_t() + for c in conds: + #msge("COND " + c) # FIXME: REMOVEME + xr = xed_reg_pattern.match(c) # FIXME: not general enough + if xr: + conditions.and_cond("OUTREG=%s" % (xr.group('regname'))) + else: + conditions.and_cond(c) + # only add a rule if we have conditions for it! + rule = rule_t(conditions, new_actions, nt_name) + return rule + else: + _vmsgb("DROP DECODE LINE (NO eCONDS)", "%s\nin NT: %s" %(line,nt_name)) + return None + + + def parse_decode_lines(self, lines): + """ Read the flat decoder files (not the ISA file). + + Return a tuple: + ( dict of nonterminals, dict of nonterminal lookup functions ) + + This parses the so-called flat format with the vertical + bar used for all the non-instruction tables. + + For decode the semantics are: + preconditions | dec-actions + However for encode, the semantics change to: + enc-actions | conditions + + And we must take some of the "enc-actions" and add them to the preconditions. + These include the actions associated with: MODE,SMODE,EOSZ,EASZ + """ + nts = {} + ntlufs = {} + + while len(lines) > 0: + line = lines.pop(0) + #msge("LINEOUT:" + line) + line = comment_pattern.sub("",line) + line = leading_whitespace_pattern.sub("",line) + line = line.rstrip() + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + + p = ntluf_pattern.match(line) + if p: + nt_name = p.group('ntname') + ret_type = p.group('rettype') + # create a new nonterminal to use + nt = nonterminal_t(nt_name, ret_type) + ntlufs[nt_name] = nt + continue + + p = nt_pattern.match(line) + if p: + nt_name = p.group('ntname') + + # create a new nonterminal to use + nt = nonterminal_t(nt_name) + nts[nt_name] = nt + continue + + p = decode_rule_pattern.match(line) + if p: + conds = p.group('cond').split() # rhs, from an encode perspective (decode operands) + actions = p.group('action').split() # lhs, from a encode perspective (decode patterns) + rule = self.parse_decode_rule(conds,actions,line,nt.name) + if rule: + nt.add(rule) + if nt.multiple_otherwise_rules(): + die("Multiple otherwise rules in %s -- noninvertible" % (nt_name)) + continue + + die("Unhandled line: %s" % line) + + return (nts, ntlufs) + + def parse_encode_lines(self,lines): + """ + Returns a tuple of two dictionaries: (1) a dictionary of + sequencer_t's and (2) a dictionary of nonterminal_t's + """ + nts = {} # nonterminals_t's + ntlufs = {} # nonterminals_t's + seqs = {} # sequencer_t's + while len(lines) > 0: + line = lines.pop(0) + line = comment_pattern.sub("",line) + line = leading_whitespace_pattern.sub("",line) + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + c = curly_pattern.search(line) + if c: + line = re.sub("{", " { ", line) + line = re.sub("}", " } ", line) + + sequence = sequence_pattern.match(line) + if sequence: + seq = sequencer_t(sequence.group('seqname')) + seqs[seq.name] = seq + #msg("SEQ MATCH %s" % seq.name) + nt = None + continue + + p = ntluf_pattern.match(line) + if p: + nt_name = p.group('ntname') + ret_type = p.group('rettype') + # create a new nonterminal to use + nt = nonterminal_t(nt_name, ret_type) + ntlufs[nt_name] = nt + seq = None + continue + + m = nt_pattern.match(line) + if m: + nt_name = m.group('ntname') + if nt_name in nts: + nt = nts[nt_name] + else: + nt = nonterminal_t(nt_name) + nts[nt_name] = nt + seq = None + continue + a = arrow_pattern.match(line) + if a: + conds = a.group('cond').split() + actns = a.group('action').split() + #msg("ARROW" + str(conds) + "=>" + str(actions)) + conditions = conditions_t() + for c in conds: + conditions.and_cond(c) + rule = rule_t(conditions, actns, nt_name) + if seq: + seq.add(rule) + else: + # we do not need the rules otherwise->error/nothing in the + # new encoding structure (hash tables). + # instead we are holding this info in a matching attribute + if rule.conditions.and_conditions[0].is_otherwise(): + if rule.actions[0].is_nothing(): + nt.otherwise = [actions.gen_return_action('1')] + elif rule.actions[0].is_error(): + nt.otherwise = [actions.gen_return_action('0')] + else: + nt.otherwise = map(lambda(x): actions.action_t(x), + actns) + # in case we have valid action for the otherwise + # rule we should finish it with returnning 1 + # which is "not an error" + nt.otherwise.append(actions.gen_return_action('1')) + else: + nt.add(rule) + else: + for nt in line.split(): + seq.add(nt) + return (seqs,nts,ntlufs) + + def parse_state_bits(self,lines): + d = [] + state_input_pattern = re.compile(r'(?P[^\s]+)\s+(?P.*)') + while len(lines) > 0: + line = lines.pop(0) + line = comment_pattern.sub("",line) + line = leading_whitespace_pattern.sub("",line) + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + p = state_input_pattern.search(line) + if p: + #_vmsgb(p.group('key'), p.group('value')) + #d[p.group('key')] = p.group('value') + s = r'\b' + p.group('key') + r'\b' + pattern = re.compile(s) + d.append( (pattern, p.group('value')) ) + else: + die("Bad state line: %s" % line) + return d + + def expand_state_bits_one_line(self,line): + new_line = line + for k,v in self.state_bits: + new_line = k.sub(v,new_line) + return new_line + + def expand_state_bits(self,lines): + new_lines = [] + # n^2 algorithm + for line in lines: + new_line = line + for k,v in self.state_bits: + new_line = k.sub(v,new_line) + new_lines.append(new_line) + return new_lines + + def update(self,seqs,nts,ntlufs): + """Update the sequences and nonterminals dictionaries""" + self.sequences.update(seqs) + self.nonterminals.update(nts) + self.decoder_ntlufs.update(ntlufs) + + def read_encoder_files(self): + + for f in self.files.encoder_input_files: + lines = file(f).readlines() + lines = self.expand_state_bits(lines) + (seqs,nts,ntlufs) = self.parse_encode_lines(lines) + del lines + self.update(seqs,nts,ntlufs) + + + def reorder_encoder_rules(self,nts): + """reorder rules so that any rules with ENCODER_PREFERRED is first + """ + for nt in nts.itervalues(): + first_rules = [] + rest_of_the_rules = [] + for r in nt.rules: + if r.conditions.contains("ENCODER_PREFERRED"): + first_rules.append(r) + else: + rest_of_the_rules.append(r) + nt.rules = first_rules + rest_of_the_rules + + + ################################################## + + + def make_nt(self,ntname): + blot = blot_t('nt') + blot.nt = ntname + return blot + + def make_hex(self,s,field_name=None): + """ + @param s: string with a 2 nibble hex number + @rtype: blot_t + @return: blot containing the integer value + """ + blot = blot_t('bits') + blot.value = int(s,16) + blot.length = 8 + blot.field_name = field_name + return blot + def make_binary(self,s,field_name=None): + """ + @param s: string with a binary number + @rtype: blot_t + @return: blot containing the integer value + """ + blot = blot_t('bits') + if re.search(r'^0b',s): + s = re.sub('0b','',s) + s = re.sub('_','',s) + blot.value = int(s,2) + blot.length = len(s) + blot.original_bits = s # FIXME: 2007-04-20 + blot.field_name = field_name + return blot + + def make_bits_and_letters(self,s, field_name=None): + """ + @type s: string + @param s: string of letters or binary digits representing the blot_t + @type field_name: string + @param field_name: name of the storage field (optional) + + @rtype: list of blot_t's + @return: list of blot_t's + """ + #_vmsgb("MBAL","%s" % s) + blots = [] + bit_offset_in_field = 0 + runs = group_bits_and_letter_runs(s) + _vmsgb("RUNS\t",str(runs)) + for r in runs: + #_vmsgb("\t",str(r)) + if len(r) == 0: + die("Bad run in " + str(s)) + blot = blot_t() + if r[0] == '0' or r[0] == '1': + blot.type = 'bits' + blot.value = int(r,2) + else: + blot.type = 'letters' + blot.letters = r + blot.length = len(r) + blot.field_name = field_name + blot.field_offset = bit_offset_in_field + bit_offset_in_field += blot.length + blots.append(blot) + return blots + def make_decider_blot(self, lhs,rhs,equals): + blot = blot_t('od') + blot.field_name = lhs + rhs = re.sub(r':.*','',rhs) + blot.value = make_numeric(rhs,"%s %s %s" % (str(lhs),str(equals),str(rhs))) + blot.od_equals = equals + return blot + + def make_decode_patterns(self,s): + """ return one or more subpatterns of type. + + Sometimes we specify an decode pattern like MOD[mm] or + MOD[11_]. The 2nd part of the return tuple is a list of the + implied decode operands such as MOD=mm or MOD=11_. + + @rtype: tuple + @returns: (list of blot_t's representing patterns,\ + a list of tuples of field bindings) + """ + decode_patterns = [] + field_bindings = [] + while 1: + nt = nt_name_pattern.match(s) + if nt: + decode_patterns.append(self.make_nt(nt.group('ntname'))) + break + opcap = lhs_capture_pattern_end.match(s) + if opcap: + # MOD[mm] REG[0b000] + bits = opcap.group('bits') + field_name = opcap.group('name') + if binary_pattern.match(bits): + decode_patterns.append(self.make_binary(bits, field_name)) + elif hex_pattern.match(bits): + decode_patterns.append(self.make_hex(bits, field_name)) + elif letter_pattern.match(bits): + o = self.make_bits_and_letters( bits, field_name) + decode_patterns.extend(o) + else: + genutil.die("Unrecognaized pattern '%s' for %s" % bits, s) + field_bindings.append( opcap.group('name','bits') ) + break + if hex_pattern.match(s): + decode_patterns.append(self.make_hex(s)) + break + s_nounder = no_underscores(s) + if binary_pattern.match(s_nounder): + decode_patterns.append(self.make_binary(s_nounder)) + break + if bits_and_letters_pattern.match(s_nounder): + decode_patterns.extend(self.make_bits_and_letters(s_nounder)) + break + if letter_pattern.match(s_nounder): + decode_patterns.extend(self.make_bits_and_letters(s_nounder)) + break + equals = equals_pattern.match(s) + if equals: + (lhs,rhs) = equals.group('lhs','rhs') + decode_patterns.append(self.make_decider_blot(lhs,rhs,equals=True)) + break + not_equals = not_equals_pattern.match(s) + if not_equals: + (lhs,rhs) = not_equals.group('lhs','rhs') + decode_patterns.append(self.make_decider_blot(lhs,rhs,equals=False)) + break + + die("Could not process decode pattern %s" % s) + + return (decode_patterns, field_bindings) + + def parse_one_decode_rule(self, iclass, operand_str, pattern_str): + """Read the decoder rule from the main ISA file and package it + up for encoding. Flipping things around as necessary. + + @type operand_str: string + @param operand_str: decode operands + + @type pattern_str: string + @param pattern_str: decode pattern (bits, nts, ods, etc.) + + @rtype: tuple + @return: (list operands/conditions as operand_t's, \ + list patterns/actions as blot_t's \ + list of modal patterns strings that should become condition_t objs) + """ + # We move the special_attributes from the decode operands to + # the encode actions because they are not relevant at this + # point in the processing. + + # decode patterns are the encode actions: hex bytes or binary + # strings to emit, or reverse-operand-deciders. (Things that + # were ODs for decode now are binding actions for encode). + + + # parse up the patterns and collect some extra bindings that + # become decode-operands (encode-conditions). + # + # Some of the decode patterns (encode actions) need to become + # encode conditions. We move some decode patterns to encode + # actions here by storing them in the list of modal_patterns + + global storage_fields + patterns = [] + + # The extra_bindings_list is a list of implied bindings deduced + # from the decode pattern, for things like MOD[mm] (etc.) that do + # field captures in the pattern. We use them to create + # new (decode) operands (which then become encode conditions). + extra_bindings = [] + + # Decode patterns that do not become encode actions, instead + # they become encode conditions. (This stuff that was on the + # LHS in decode-land stays on the LHS in encode land.) These + # are the fields that are listed as "EI" (encoder inputs) in + # the "fields description" file. + modal_patterns = [] + + for p in pattern_str.split(): # the decode-patterns or encode-actions + p_short = rhs_pattern.sub('', p) # grab the lhs + if (p_short in storage_fields and + storage_fields[p_short].encoder_input): + if voperand(): + msgb("MODAL PATTERN", p_short) + modal_patterns.append(p) + continue + + if p_short in storage_fields and p == 'BCRC=1': + # FIXME: 2016-01-28: MJC: HACK TO ENCODE ROUNDC/SAE CONTRAINTS + if 'SAE' in pattern_str: + modal_patterns.append("SAE!=0") + else: + modal_patterns.append("ROUNDC!=0") + + # The pattern_list is a list of blot_t's covering the + # pattern. The extra_bindings_list is a list of + # implied bindings deduced from the decode patterns. + ## + # The extra bindings are for MOD[mm] (etc.) that do + # field captures in the pattern. We use them to create + # new operands. + _vmsgb("MAKING DECODE PATTERNS", str(p)) + (pattern_list, extra_bindings_list) = self.make_decode_patterns(p) + s = [] + for p in pattern_list: + s.append(str(p)) + _vmsgb("PATTERN LIST", ", ".join(s)) + _vmsgb("EXTRABINDING LIST", str(extra_bindings_list)) + patterns.extend(pattern_list) + extra_bindings.extend(extra_bindings_list) + + # Decode operands are type:rw:[lencode|SUPP|IMPL|EXPL|ECOND] + # where type could be X=y or MEM0. Decode operands become + # encode conditions. + + # Collect up the decode operands. Some of them get converted + # in to extra encode actions. + operands = [] + extra_actions = [] + for x in operand_str.split(): # the encode conditions (decode operands) + x_short = rhs_pattern.sub('', x) # grab the lhs + + # Some "operands" are really side effects of decode. They + # are also side effects of encode and so we move them to + # the list of actions. + + if voperand(): + msgb("ENCODER FIELD CHECK", x_short) + special = False + try: + # Move some decode operands (the ones that are not + # encoder inputs) to the extra encode actions. + if storage_fields[x_short].encoder_input == False: + if voperand(): + msgb("ENCODER OUTPUT FIELD", x_short) + special = True + except: + pass + + if special: + if voperand(): + msgb("SPECIAL ATTRIBUTE", x) + extra_actions.append(x) + else: + if voperand(): + msgb("MAKING A DECODE-OPERAND/ENC-ACTION FROM", x) + operands.append(operand_t(x)) + + # Some of the decode-patterns (encode-actions) really become + # encoder-conditions as well. They are modal or inputs to + # encoding. The modal_patterns skip the operands step and can + # be made right in to condition_t objects. + + # Add the extra encode conditions (decode-operands) implied + # from the instruction decode patterns (MOD[mm] etc.). We + # ignore the ones for constant bindings! + for (field_name,value) in extra_bindings: + if genutil.numeric(value): + #msgerr("IGNORING %s %s" % (field_name, value)) + pass # we ignore things that are just bits at this point. + else: + extra_operand = operand_t("%s=%s:SUPP" % (field_name, value)) + _vmsgb("EXTRA BINDING", "%s=%s:SUPP" % (field_name, value)) + operands.append(extra_operand) + + # Add the extra actions (from the special attributes) -- + # things that were part of the decode operands as side-effects + # but are really side-effects of encode too. + for raw_action in extra_actions: + okay = False + equals = equals_pattern.match(raw_action) + if equals: + (lhs,rhs) = equals.group('lhs','rhs') + new_blot = self.make_decider_blot(lhs,rhs,equals=True) + okay = True + not_equals = not_equals_pattern.match(raw_action) + if not_equals: + (lhs,rhs) = equals.group('lhs','rhs') + new_blot = self.make_decider_blot(lhs,rhs,equals=False) + okay = True + if not okay: + die("Bad extra action: %s" % raw_action) + #msgerr("NEW BLOT: %s" % str(new_blot)) + patterns.append(new_blot) + + + + # return: (decode-operands are encode-conditions, + # decode-patterns are encode-actions [blot_t], + # modal-patterns that become encode-conditions [string]) + + #msgerr("OPERANDS %s" % ' '.join(map(str,operands))) + return (operands, patterns, modal_patterns) + + def print_iclass_info(self,iclass, operands, ipattern, conditions, + actions, modal_patterns): + msg(iclass + ':\t' + operands + '->' + ipattern) + msg( "CONDITIONS:") + for c in conditions: + msg("\t" + str(c) ) + msg("ACTIONS:") + for a in actions: + msg("\t" + str(a)) + msg("MODAL PATTERNS:") + for a in modal_patterns: + msg("\t" + str(a)) + + def finalize_decode_conversion(self,iclass, operands, ipattern, uname=None): + if ipattern == None: + die("No ipattern for iclass %s and operands: %s" % + (str(iclass), operands )) + if iclass == None: + die("No iclass for " + operands) + # the encode conditions are the decode operands (as [ operand_t ]) + # the encode actions are the decode patterns (as [ blot_t ]) + (conditions, actions, modal_patterns) = \ + self.parse_one_decode_rule(iclass, operands, ipattern) + if vfinalize(): + self.print_iclass_info(iclass, operands, ipattern, conditions, + actions, modal_patterns) + # FIXME do something with the operand/conditions and patterns/actions + iform = iform_t(iclass, conditions, actions, modal_patterns, uname) + + if 'VEXVALID=2' in ipattern: # EVEX + # FIXME: 2016-01-28: MJC: hack. 1st check patterns w/ ROUNDC/SAE. + # (See other instance of BCRC=1 in this file) + if 'BCRC=1' in ipattern: + iform.priority = 0 + else: + iform.priority = 2 + elif 'VEXVALID=3' in ipattern: # XOP + iform.priority = 3 + elif 'VEXVALID=4' in ipattern: # KNC + iform.priority = 3 + else: # EVERYTHING ELSE + iform.priority = 1 + + try: + self.iarray[iclass].append ( iform ) + except: + self.iarray[iclass] = [ iform ] + + def read_decoder_instruction_file(self): + """Taking a slightly different tack with the ISA file because + it is so large. Processing each line as we encounter it rather + than buffering up the whole file. Also, just storing the parts + I need. """ + continuation_pattern = re.compile(r'\\$') + _vmsgb("READING",self.files.instructions_file) + lines = file(self.files.instructions_file).readlines() + lines = process_continuations(lines) + nts = {} + nt = None + iclass = None + uname = None + unamed = None + ipattern = None + started = False + while len(lines) > 0: + line = lines.pop(0) + line = comment_pattern.sub("",line) + #line = leading_whitespace_pattern.sub("",line) + line=line.strip() + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + #_vmsgb("INPUT", line) + + if udelete_pattern.search(line): + m = udelete_full_pattern.search(line) + unamed = m.group('uname') + _vmsgb("REGISTER BAD UNAME", unamed) + self.deleted_unames[unamed] = True + continue + + if delete_iclass_pattern.search(line): + m = delete_iclass_full_pattern.search(line) + iclass = m.group('iclass') + self.deleted_instructions[iclass] = True + continue + + + line = self.expand_state_bits_one_line(line) + p = nt_pattern.match(line) + if p: + nt_name = p.group('ntname') + if nt_name in nts: + nt = nts[nt_name] + else: + nt = nonterminal_t(nt_name) + nts[nt_name] = nt + continue + + if left_curly_pattern.match(line): + if started: + die("Nested instructions") + started = True + iclass = None + uname = None + continue + + if right_curly_pattern.match(line): + if not started: + die("Mis-nested instructions") + started = False + iclass = None + uname = None + continue + ic = iclass_pattern.match(line) + if ic: + iclass = ic.group('iclass') + continue + + un = uname_pattern.match(line) + if un: + uname = un.group('uname') + continue + + ip = ipattern_pattern.match(line) + if ip: + ipattern = ip.group('ipattern') + continue + + if no_operand_pattern.match(line): + self.finalize_decode_conversion(iclass,'', + ipattern, uname) + continue + + op = operand_pattern.match(line) + if op: + operands = op.group('operands') + self.finalize_decode_conversion(iclass, operands, + ipattern, uname) + continue + + return + + + def remove_deleted(self): + bad = self.deleted_unames.keys() + _vmsgb("BAD UNAMES", str(bad)) + for ic,v in self.iarray.iteritems(): + x1 = len(v) + l = [] + for i in v: + if i.uname not in bad: + l.append(i) + else: + _vmsgb("PRE-DELETING IFORMS", "%s %s" % (ic, i.uname)) + x2 = len(l) + if x1 != x2: + _vmsgb("DELETING IFORMS", "%s %d -> %d" % (ic,x1,x2)) + self.iarray[ic]=l + + for k in self.deleted_instructions.keys(): + if k in self.iarray: + _vmsgb("DELETING", k) + del self.iarray[k] + + def add_iform_indices(self): + ''' add iform's index to all iforms. + flatten all the iforms to a single list ''' + + all_iforms_list = [] + i = 0 + for iforms in self.iarray.itervalues(): + for iform in iforms: + iform.rule.iform_id = i + all_iforms_list.append(iform) + i += 1 + self.total_iforms = i + return all_iforms_list + + def read_decoder_files(self): + """Read the flat decoder input files and 'invert' them. Build + two dictionaries: the NTLUFs and the NTs""" + + # read the main ISA tables + self.read_decoder_instruction_file() # read_isa_ + self.all_iforms = self.add_iform_indices() + self.remove_deleted() + + # Read the other decoder format tables. + nts = {} + ntlufs = {} + for f in self.files.decoder_input_files: + lines = file(f).readlines() + lines = self.expand_state_bits(lines) + (some_nts, some_ntlufs) = self.parse_decode_lines(lines) # read_flat_ + nts.update(some_nts) + ntlufs.update(some_ntlufs) + del lines + + # reorder rules so that any rules with ENCODER_PREFERRED is first + self.reorder_encoder_rules(nts) + self.reorder_encoder_rules(ntlufs) + if vread(): + msgb("NONTERMINALS") + for nt in nts.itervalues(): + msg( str(nt)) + msgb("NTLUFS") + for ntluf in ntlufs.itervalues(): + msg( str(ntluf)) + _vmsgb("DONE","\n\n") + + self.decoder_nonterminals.update(nts) + self.decoder_ntlufs.update(ntlufs) + + def make_isa_encode_group(self, group_index,ins_group): + """Make the function object for encoding one group. + + @rtype: function_object_t + @returns: an encoder function object that encodes group + """ + if vencode(): + msgb("ENCODING GROUP", " %s -- %s" % (group_index, bind_or_emit)) + fname = "xed_encode_group_%d" % (group_index) + fo = function_object_t(fname,'xed_bool_t') + fo.add_arg("%s* xes" % xed_encoder_request) + fo.add_code_eol( "xed_bool_t okay=1") + fo.add_code_eol( "xed_bool_t conditions_satisfied=0" ) + fo.add_code_eol( "xed_ptrn_func_ptr_t fb_ptrn_function" ) + + iform_ids_table = ins_group.get_iform_ids_table() + iclasses_number = len(ins_group.get_iclasses()) + iforms_number = len(ins_group.iforms) + table_type = 'static const xed_uint16_t ' + table_decl = 'iform_ids[%d][%d] = {' % (iclasses_number, + iforms_number) + table = table_type + table_decl + fo.add_code(table) + for line in iform_ids_table: + fo.add_code(line) + fo.add_code_eol('}') + + get_iclass_index = 'xed_encoder_get_iclasses_index_in_group' + obj_name = encutil.enc_strings['obj_str'] + code = 'xed_uint8_t iclass_index = %s(%s)' % (get_iclass_index,obj_name) + fo.add_code_eol(code) + # FIXME: 2014-04-17: copy to sorted_iforms still sorts ins_group.iforms + sorted_iforms = ins_group.iforms + sorted_iforms.sort(cmp=ins_emit.cmp_iform_len) + for i,iform in enumerate(sorted_iforms): + # FIXME:2007-07-05 emit the iform.operand_order check of + # the xed_encode_order[][] array + + # emit code that checks the operand order + + # made special operand orders for 0 1 and 2 + # operands. store the dictionary of operand orders, + # look up the list. If there are zero entries, no + # memcmp is needed. If there is one entry, replace the + # memcmp with an equality check. If there are two + # operands, replace the memcmp with two equality + # tests. Otherwise use the memcmp. + + # FIXME 2007-09-11 use the static count of the values of + # the number of operands rather than looking it up in + # xed_encode_order_limit. Save many array derefs per + # encode. 2014-04-15: xed_encode_order_limit[] does not + # currently show up in the generated code so the above + # fixme is moot. + + + + try: + operand_order =\ + self.all_operand_name_list_dict[iform.operand_order_key] + except: + operand_order = None + cond1 = None + nopnd = None + optimized = False + if operand_order: + nopnd = len(operand_order.lst) + if 0: + msge("OPNDORDER for group %d is (%d) %s " % ( + group_index, + nopnd, + str(operand_order.lst))) + cond1 = "xes->_n_operand_order == %d" % (nopnd) + if nopnd==0: + optimized = True + fo.add_code("if (%s) {" % (cond1)) + elif nopnd ==1: + optimized = True + cond2 = "xes->_operand_order[0] == XED_OPERAND_%s" + cond2 = cond2 % (operand_order.lst[0]) + fo.add_code("if (%s && %s) {" % (cond1,cond2)) + elif nopnd ==2: + optimized = True + cond2 = "xes->_operand_order[0] == XED_OPERAND_%s" + cond2 = cond2 % (operand_order.lst[0]) + cond3 = "xes->_operand_order[1] == XED_OPERAND_%s" + cond3 = cond3 % (operand_order.lst[1]) + fo.add_code("if (%s && %s && %s) {" % (cond1,cond2,cond3)) + + memcmp_type = 'xed_uint8_t' + if not optimized: + if cond1 == None: + cond1 = "xed_encode_order_limit[%d]==xes->_n_operand_order" + cond1 = cond1 % (iform.operand_order) + if nopnd == None: + cond2 = "memcmp(xed_encode_order[%d], "+\ + "xes->_operand_order, "+\ + "sizeof(%s)*xed_encode_order_limit[%d])==0" + cond2 = cond2 % (iform.operand_order, memcmp_type, + iform.operand_order) + else: + cond2 = "memcmp(xed_encode_order[%d], "+\ + "xes->_operand_order, sizeof(%s)*%d)==0" + cond2 = cond2 % (iform.operand_order, memcmp_type, nopnd) + + fo.add_code("if (%s && %s) {" % (cond1, cond2)) + if viform(): + msgb("IFORM", str(iform)) + + # For binding, this emits code that sets + # conditions_satisfied based on some long expression and + # then tests it and sets some operand storage fields. For + # emitting, it checks the iform and emits bits. + captures = None + lines = iform.rule.emit_isa_rule(i,ins_group) + fo.add_lines(lines) + + fo.add_code(' }') + + + fo.add_code_eol('return 0') + fo.add_code_eol("(void) okay") + fo.add_code_eol("(void) conditions_satisfied") + fo.add_code_eol("(void) xes") + return fo + + def emit_encode_function_table_init(self): + ''' emit the functions that inits encoders look up tables. ''' + global output_file_emitters + func_name = "xed_init_encode_table" + fo = function_object_t(func_name,"void") + init_table = [] + template = " xed_enc_iclass2group[XED_ICLASS_%s] = %d;" + + iclass2group = self.ins_groups.get_iclass2group() + for iclass,group_index in iclass2group.items(): + code = template % (iclass.upper(),group_index) + init_table.append(code) + + template = " xed_enc_iclass2index_in_group[XED_ICLASS_%s] = %d;" + iclass2index_in_group = self.ins_groups.get_iclass2index_in_group() + for iclass,index in iclass2index_in_group.items(): + code = template % (iclass.upper(),index) + init_table.append(code) + fo.add_lines(init_table) + filename = 'xed-encoder-init.c' + fe = xed_file_emitter_t(self.xeddir, self.gendir, + filename, shell_file=False) + fe.add_header("xed-encoder.h") # FIXME confusing file name. + fe.start() + fo.emit_file_emitter(fe) + fe.close() + output_file_emitters.append(fe) + + def make_isa_encode_functions(self, iarray): + # each iarray dictionary entry is a list: of iform_t objects + + ins_code_gen = ins_emit.instruction_codegen_t(self.all_iforms, + self.iarray, + self.gendir, + self.amd_enabled) + ins_code_gen.work() + ins_code_gen.get_values(self) + + i=0 + group_fos = [] + for group in self.ins_groups.get_groups(): + if vencfunc(): + msgb("=== ENCODING FUNCTION %d for %s niforms=%d ===" % + ( i, iclass, len(iforms_list))) + #generate the function object for the group bind function + fo = self.make_isa_encode_group(i,group) + group_fos.append(fo) + i += 1 + + self.group_fos = group_fos + + def emit_iforms(self): + global output_file_emitters + s = iform_builder.emit_header() # FIXME GLOBAL + filename = 'xed-encoder-iforms.h' + fe = xed_file_emitter_t(self.xeddir, self.gendir, filename, shell_file=False) + fe.headers.remove('xed-internal-header.h') + fe.add_header("xed-types.h") + fe.start() + fe.write(s) + fe.close() + output_file_emitters.append(fe) + + def find_nt_by_name(self,nt_name): + # returns nonterminal_t object that represents the nt name + if nt_name in self.nonterminals: + return self.nonterminals[nt_name] + elif nt_name in self.decoder_nonterminals: + return self.decoder_nonterminals[nt_name] + elif nt_name in self.decoder_ntlufs: + return self.decoder_ntlufs[nt_name] + + die('could not find nt object for nt name %s\n' % nt_name) + + def replace_outreg(self,cond_nt,conds_list): + '''cond_nt: the condition with nt + cond_list: list of conditions that replaces the nt + + if the field name of cond_nt is different than OUTREG, + replace the field name OUTREG in the conds_list ''' + + if cond_nt.field_name == 'OUTREG': + return + for c in conds_list: + if c.field_name == 'OUTREG': + c.field_name = cond_nt.field_name + + def inline_nt(self,rule,cond_nt,dfile): + ''' merges the conditions & actions in rule with the + conditions & actions in the cond_nt, returns a list of merged rules + + rule: is a rule with nt in the conds list (called UPPER) + cond_nt: is the condition with the nt that we want to + inline (called N()) ''' + + nt = self.find_nt_by_name(cond_nt.rvalue.value) + dfile.write("working rule:\n %s\n" % str(rule)) + dfile.write("inlining rule: %s\n" % str(nt)) + + #remove the nt from the conds list + rule.conditions.and_conditions.remove(cond_nt) + + inlined_rules = [] + #add all the rules from N() to UPPER rule + for r in nt.rules: + #copying the conditions & actions + #since we are going to modify them later + conds = copy.deepcopy(r.conditions.and_conditions) + actions = copy.deepcopy(r.actions) + + #replace field name OUTREG in the cond_nt with the original + #field name in the rule + self.replace_outreg(cond_nt,conds) + + if conds[0].is_otherwise() and actions: + if actions[0].is_nothing() or actions[0].is_error(): + # for otherwise -> nothing/error we do nothing. + # if we have not succeeded to satisfy the lower nt ( N() ) + # the UPPER rule will simply be rejected, + # and we will continue to try satisfy the next rule. + continue + else: + err = ("otherwise condition may get only error or"+ + "nothing actions in NT: " + nt.name) + die(err) + + new_upper_rule = copy.deepcopy(rule) + new_upper_rule.conditions.and_conditions.extend(conds) + + if actions and actions[0].is_error(): + #if we have error action in the canonical nt take it as + #the only action and do not append it to other actions + new_upper_rule.actions = actions + elif actions and actions[0].is_nothing(): + #appending nothing actions does not have any affect + pass + elif new_upper_rule.actions and new_upper_rule.actions[0].is_nothing(): + new_upper_rule.actions = actions + else: + upper_actions = new_upper_rule.actions + new_upper_rule.actions = actions + new_upper_rule.actions.extend(upper_actions) + dfile.write("new rule %s\n" % str(new_upper_rule)) + inlined_rules.append(new_upper_rule) + return inlined_rules + + def inline_conditions(self,nt_map,dfile): + '''we are going to inline all the nt in the condition list + example: + the rule(lets call it UPPER): + A=1 BASE=N() -> X=0 + the nt N() is: + OUTREG=EAX -> Z=1 + OUTREG=RAX -> Z=2 + the inlined rule are: + A=1 BASE=EAX -> X=0 Z=1 + A=1 BASE=RAX -> X=0 Z=2 + + nt_map is a map of nt name to nonterminal_t ''' + + for nt_name in nt_map: + nt = nt_map[nt_name] + rules_with_nt = [] + dfile.write('nt: %s\n' % nt_name) + for rule in nt.rules: + cond_nt = rule.get_nt_in_cond_list() + if cond_nt: + #collect all the rules with nt + rules_with_nt.append(rule) + + #we have a nt in the condtion list + #create new inlined ruels + inlined_rules = self.inline_nt(rule,cond_nt,dfile) + nt.rules.extend(inlined_rules) + + #now delete all the rules with nt in the condition list + for rule in rules_with_nt: + nt.rules.remove(rule) + + def run(self): + # this is the main loop + + # read the state bits + f = self.files.state_bits_file + lines = file(f).readlines() + self.state_bits = self.parse_state_bits(lines) + del lines + + # writes self.sequences and self.nonterminals + self.read_encoder_files() + # writes self.deocoder_nonterminals and self.decoder_ntlufs + self.read_decoder_files() + + if vdumpinput(): + self.dump() + + ## inline all the nt in the conditions section + dfile = open(mbuild.join(self.gendir,'inline_nt.txt'),'w') + self.inline_conditions(self.nonterminals,dfile) + self.inline_conditions(self.decoder_ntlufs,dfile) + dfile.close() + + self.make_sequence_functions() + + f_gen = nt_func_gen.nt_function_gen_t(self,storage_fields) + fos, operand_lu_fos = f_gen.gen_nt_functions() + self.emit_lu_functions(operand_lu_fos) + self.functions.extend(fos) + + self.make_nonterminal_functions(self.nonterminals) + self.make_nonterminal_functions(self.decoder_ntlufs) + self.make_nonterminal_functions(self.decoder_nonterminals) + + self.make_encode_order_tables()# FIXME too early? + # emit the per instruction bind & emit functions + self.make_isa_encode_functions(self.iarray) + self.emit_group_encode_functions() + + self.emit_lu_tables() + self.emit_encoder_iform_table() + # write the dispatch table initialization function + self.emit_encode_function_table_init() + + self.emit_function_bodies_and_header_numbered() + + self.emit_iforms() + + def look_for_encoder_inputs(self): + encoder_inputs_by_iclass = {} # dictionary mapping iclass -> set of field names + encoder_nts_by_iclass = {} # dictionary mapping iclass -> set of nt names + for iclass,iform_list in self.iarray.iteritems(): + encoder_field_inputs = set() + encoder_nts = set() + for iform in iform_list: + (field_set,nt_set) = iform.find_encoder_inputs() + #msg("FIELDS: %s" % ' '.join(field_set)) + #msg( "NTS: %s" % ' '.join(nt_set)) + encoder_field_inputs |= field_set + encoder_nts |= nt_set + #msg("FIELDS: %s" % ' '.join(encoder_field_inputs)) + #msg( "NTS: %s" % ' '.join(encoder_nts)) + encoder_inputs_by_iclass[iclass] = encoder_field_inputs + encoder_nts_by_iclass[iclass] = encoder_nts + + for iclass in encoder_inputs_by_iclass.keys(): + fld_set = encoder_inputs_by_iclass[iclass] + nt_set = encoder_nts_by_iclass[iclass] + if vinputs(): + msg("EINPUTS: %15s FIELDS: %s \tNTS: %s" % + (iclass, ", ".join(fld_set), ", ".join(nt_set))) + + def make_encode_order_tables(self): + global output_file_emitters + self.all_operand_name_list_dict = self._collect_ordered_operands() + (init_order_fo,max_entries, max_operands) = \ + self._emit_operand_order_array(self.all_operand_name_list_dict) + filename = 'xed-encoder-order-init.c' + fe = xed_file_emitter_t(self.xeddir, self.gendir,filename, + shell_file=False) + fe.start() + init_order_fo.emit_file_emitter(fe) + fe.close() + self.max_operand_order_entries = max_entries + self.max_operand_order_operands = max_operands + output_file_emitters.append(fe) + + + def emit_encode_defines(self): + global output_file_emitters + filename = 'xed-encoder-gen-defs.h' + fe = xed_file_emitter_t(self.xeddir, self.gendir, filename, shell_file=False) + fe.headers.remove('xed-internal-header.h') + fe.start() + fe.write("#define XED_ENCODE_ORDER_MAX_ENTRIES %d\n" % + self.max_operand_order_entries) + fe.write("#define XED_ENCODE_ORDER_MAX_OPERANDS %d\n" % + self.max_operand_order_operands) + fe.write("#define XED_ENCODE_MAX_FB_PATTERNS %d\n" % + self.max_fb_ptrns) + fe.write("#define XED_ENCODE_MAX_EMIT_PATTERNS %d\n" % + self.max_emit_ptrns) + fe.write("#define XED_ENCODE_FB_VALUES_TABLE_SIZE %d\n" % + self.fb_values_table_size) + fe.write("#define XED_ENCODE_MAX_IFORMS %d\n" % self.total_iforms) + fe.write("#define XED_ENC_GROUPS %d\n" % + self.ins_groups.num_groups()) + fe.close() + output_file_emitters.append(fe) + + def _collect_ordered_operands(self): + """Return a dictionary of ordered operand name lists that + include just the encoder inputs. We denote the key to index + this dictionary in each iform as iform.operand_order""" + + all_operand_name_list_dict = {} + for iclass,iform_list in self.iarray.iteritems(): + for niform,iform in enumerate(iform_list): + ordered_operand_name_list = iform.make_operand_name_list() + key = "-".join(ordered_operand_name_list) + if key in all_operand_name_list_dict: + n = all_operand_name_list_dict[key].n + else: + n = len(all_operand_name_list_dict) + all_operand_name_list_dict[key] = operand_order_t(n, + ordered_operand_name_list) + iform.operand_order = n + iform.operand_order_key = key + _vmsgb("TOTAL ENCODE OPERAND SEQUENCES: %d" % (len(all_operand_name_list_dict))) + + if vopseq(): + for iclass,iform_list in self.iarray.iteritems(): + for niform,iform in enumerate(iform_list): + msg("OPSEQ: %20s-%03d: %s" % + (iclass, niform+1, + ", ".join(all_operand_name_list_dict[iform.operand_order_key].lst))) + return all_operand_name_list_dict + + def _emit_operand_order_array(self, all_operand_name_list_dict): + """Return a function that initializes the encode order array""" + fname = "xed_init_encoder_order" + fo = function_object_t(fname, 'void') + operands = 0 # columns + entries = 0 # rows + for oo in all_operand_name_list_dict.itervalues(): # stringkeys -> operand_order_t's + for j,o in enumerate(oo.lst): + fo.add_code_eol("xed_encode_order[%d][%d]=XED_OPERAND_%s" % (oo.n,j,o)) + t = len(oo.lst) + fo.add_code_eol("xed_encode_order_limit[%d]=%d" % (oo.n,t)) + + if entries < oo.n+1: + entries = oo.n+1 + if operands < t: + operands = t + return (fo, entries, operands) + + def dump(self): + msgb("NONTERMINALS") + for nt in self.nonterminals.itervalues(): + msg(str(nt)) + msgb("SEQUENCERS") + for s in self.sequences.itervalues(): + msg(str(s)) + + def make_sequence_functions(self): + # we pass in the list of known sequences so that we know to + # call the right kind of function from the sequence function + # we are creating. + for s in self.sequences.itervalues(): + fo = s.create_function(self.sequences) + self.functions.append(fo) + + def make_nonterminal_functions(self, nts): + """For each nonterminal, we create two versions if it is not a + NTLUF. One version does the required bindings. The other + version emits the required bytes""" + + for nt in nts.itervalues(): + _vmsgb("SORTING FOR SIZE", nt.name) + nt.sort_for_size() + if nt.is_ntluf(): + if nt.name in nt_func_gen.get_complicated_nt(): + fo = nt.create_function(bind_or_emit='NTLUF') + self.functions.append(fo) + else: + if nt.name in nt_func_gen.get_complicated_nt(): + fo = nt.create_function(bind_or_emit='BIND') + self.functions.append(fo) + fo = nt.create_function(bind_or_emit='EMIT') + self.functions.append(fo) + + def emit_function_headers(self,fname_prefix,fo_list): + global output_file_emitters + filename = fname_prefix + '.h' + gendir = os.path.join(self.gendir, 'include-private') + fe = xed_file_emitter_t(self.xeddir, gendir, + filename, shell_file=False) + fe.start() + for fo in fo_list: + s = fo.emit_header() + fe.write(s) + fe.close() + output_file_emitters.append(fe) + + def emit_function_bodies_and_header(self,fname_prefix,headers,fo_list): + global output_file_emitters + filename = fname_prefix+ '.c' + fe = xed_file_emitter_t(self.xeddir, self.gendir, + filename, shell_file=False) + fe.add_header(headers) + fe.start() + for fo in fo_list: + s = fo.emit() + fe.write(s) + fe.close() + self.emit_function_headers(fname_prefix,fo_list) + output_file_emitters.append(fe) + + def emit_function_bodies_and_header_numbered(self): + filename_prefix = 'xed-encoder' + + headers = ['xed-encode-private.h', 'xed-enc-operand-lu.h', + 'xed-operand-accessors.h'] + fe_list = emit_function_list(self.functions, + filename_prefix, + self.xeddir, + self.gendir, + os.path.join(self.gendir, 'include-private'), + other_headers=headers) + if 0: + # move the generated header file to the private generated headers + efile = os.path.join(self.gendir, 'include-private', 'xed-encoder.h') + remove_file(efile) + os.rename(os.path.join(self.gendir, 'xed-encoder.h'), efile) + output_file_emitters.extend(fe_list) + + def emit_lu_functions(self, fos): + ''' emit the list of lookup functions ''' + filename_prefix = 'xed-enc-operand-lu' + headers = ["xed-encode.h", "xed-operand-accessors.h"] + self.emit_function_bodies_and_header(filename_prefix,headers,fos) + + def _emit_functions_lu_table(self,fe, type, values, table_name, + size_def, per_line=1): + table_def = "const %s %s[%s] = {" % (type,table_name,size_def) + fe.write(table_def) + indent = ' '*12 + fe.write(indent) + for i,val in enumerate(values): + if i % per_line == 0: + fe.write('\n%s' % indent) + fe.write("%s," % val) + fe.write('\n};\n') + + def emit_lu_tables(self): + '''emit the function pointers tables ''' + + filename_prefix = 'xed-enc-patterns' + headers = ['xed-encode.h','xed-encoder.h','xed-operand-accessors.h'] + fos = self.fb_ptrs_fo_list + self.emit_ptrs_fo_list + self.emit_function_bodies_and_header(filename_prefix,headers,fos) + + h_filename = "%s.h" % filename_prefix + filename = 'xed-encoder-pattern-lu.c' + fe = xed_file_emitter_t(self.xeddir, self.gendir, + filename, shell_file=False) + headers = [h_filename, 'xed-encoder-gen-defs.h', 'xed-encoder.h', + 'xed-enc-groups.h'] + fe.add_header(headers) + fe.start() + + f_names = map(lambda x: x.function_name, self.fb_ptrs_fo_list) + self._emit_functions_lu_table(fe, 'xed_ptrn_func_ptr_t', + f_names, 'xed_encode_fb_lu_table', + 'XED_ENCODE_MAX_FB_PATTERNS') + fe.write('\n\n\n') + f_names = map(lambda x: x.function_name, self.emit_ptrs_fo_list) + self._emit_functions_lu_table(fe, 'xed_ptrn_func_ptr_t', + f_names, 'xed_encode_emit_lu_table', + 'XED_ENCODE_MAX_EMIT_PATTERNS') + + fe.write('\n\n\n') + self._emit_functions_lu_table(fe,'xed_uint8_t', + self.fb_values_list, + 'xed_encode_fb_values_table', + 'XED_ENCODE_FB_VALUES_TABLE_SIZE',20) + + fe.write('\n\n\n') + f_names = map(lambda x: x.function_name, self.group_fos) + self._emit_functions_lu_table(fe,'xed_encode_function_pointer_t', + f_names, 'xed_encode_groups', + 'XED_ENC_GROUPS') + + + fe.close() + output_file_emitters.append(fe) + + + + + def emit_encoder_iform_table(self): + filename = 'xed-encoder-iforms-init.c' + fe = xed_file_emitter_t(self.xeddir, self.gendir, + filename, shell_file=False) + fe.add_header('xed-ild.h') + fe.start() + + ptrn = "/*(%4d)%20s*/ {%4d, %4d, %4s," +\ + " XED_STATIC_CAST(xed_uint8_t,%15s), %4d}" + iform_definitions = [] + for iform in self.all_iforms:#iforms: + iform_init = ptrn % (iform.rule.iform_id, + iform.iclass, + iform.bind_func_index, + iform.emit_func_index, + hex(iform.nominal_opcode), + iform.map, + iform.fb_index) + iform_definitions.append(iform_init) + + self._emit_functions_lu_table(fe, 'xed_encoder_iform_t', + iform_definitions, 'xed_encode_iform_db', + 'XED_ENCODE_MAX_IFORMS') + + + + fe.close() + output_file_emitters.append(fe) + + + def emit_group_encode_functions(self): + filename_prefix = 'xed-enc-groups' + + headers = ['xed-encode-private.h', 'xed-enc-operand-lu.h', + 'xed-operand-accessors.h','xed-encoder.h'] + + self.emit_function_bodies_and_header(filename_prefix,headers, + self.group_fos) + +############################################################################## +def setup_arg_parser(): + arg_parser = optparse.OptionParser() + + arg_parser.add_option('--gendir', + action='store', dest='gendir', default='obj', + help='Directory for generated files') + arg_parser.add_option('--xeddir', + action='store', dest='xeddir', default='.', + help='Directory for generated files') + + arg_parser.add_option('--input-fields', + action='store', dest='input_fields', default='', + help='Operand storage description input file') + arg_parser.add_option('--input-state', + action='store', dest='input_state', default='xed-state-bits.txt', + help='state input file') + arg_parser.add_option('--input-regs', + action='store', dest='input_regs', default='', + help='Encoder regs file') + arg_parser.add_option('--enc-patterns', + action='append', dest='enc_patterns', default=[], + help='Encoder input files') + arg_parser.add_option('--enc-dec-patterns', + action='append', dest='enc_dec_patterns', default=[], + help='Decoder input files used by the encoder') + arg_parser.add_option('--isa', + action='store', dest='isa_input_file', default='', + help='Read structured input file containing the ISA INSTRUCTIONS() nonterminal') + arg_parser.add_option('--no-amd', + action='store_false', dest='amd_enabled', default=True, + help='Omit AMD instructions') + arg_parser.add_option('--verbosity', '-v', + action='append', dest='verbosity', default=[], + help='list of verbosity tokens, repeatable.') + return arg_parser + + +if __name__ == '__main__': + arg_parser = setup_arg_parser() + (options, args ) = arg_parser.parse_args() + set_verbosity_options(options.verbosity) + enc_inputs = encoder_input_files_t(options) + enc = encoder_configuration_t(enc_inputs, options.amd_enabled) + enc.run() + enc.look_for_encoder_inputs() # exploratory stuff + enc.emit_encode_defines() # final stuff after all tables are sized + enc.dump_output_file_names() + sys.exit(0) diff --git a/pysrc/read_xed_db.py b/pysrc/read_xed_db.py new file mode 100755 index 0000000..a92904a --- /dev/null +++ b/pysrc/read_xed_db.py @@ -0,0 +1,478 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import re +import collections +import patterns +import slash_expand +import genutil +import opnd_types +import opnds + +def die(s): + sys.stdout.write("ERROR: {0}\n".format(s)) + sys.exit(1) +def msgb(b,s=''): + sys.stdout.write("[{0}] {1}\n".format(b,s)) + +class inst_t(object): + def __init__(self): + pass + + +class width_info_t(object): + def __init__(self, name, dtype, widths): + """ a name and a list of widths, 8, 16,32, and 64b""" + self.name = name.upper() + self.dtype = dtype + self.widths = widths + +completely_numeric = re.compile(r'^[0-9]+$') # only numbers + +def _is_bits(val): + """Return a number if the value is in explicit bits form: + [0-9]+bits, or None""" + global completely_numeric + length = len(val) + if length > 4: + if val[-4:] == "bits": + number_string = val[0:-4] + if completely_numeric.match(number_string): + return number_string + return None + + + + +class xed_reader_t(object): + def __init__(self, + state_bits_filename, + instructions_filename, + widths_filename, + element_types_filename): + + self.xtypes = self._gen_xtypes(element_types_filename) + self.widths_dict = self._gen_widths(widths_filename) + + self.state_bits = self._parse_state_bits(state_bits_filename) + self.deleted_unames = {} + self.deleted_instructions = {} + self.recs = self._process_lines(instructions_filename) + self._find_opcodes() + self._fix_real_opcode() + self._generate_explicit_operands() + self._parse_operands() + + + def _refine_widths_input(self,lines): + """Return a list of width_info_t. Skip comments and blank lines""" + comment_pattern = re.compile(r'#.*$') + widths_list = [] + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + ntokens = len(wrds) + if ntokens == 3: + (name, dtype, all_width) = wrds + width8 = all_width + width16 = all_width + width32 = all_width + width64 = all_width + elif ntokens == 5: + width8='0' + (name, dtype, width16, width32, width64) = wrds + else: + die("Bad number of tokens on line: " + line) + + # convert from bytes to bits, unless in explicit bits form "b'[0-9]+" + bit_widths = [] + for val in [width8, width16, width32, width64]: + number_string = _is_bits(val) + if number_string: + bit_widths.append(number_string) + else: + bit_widths.append(str(int(val)*8)) + widths_list.append(width_info_t(name, dtype, bit_widths)) + return widths_list + + def _gen_widths(self, fn): + lines = file(fn).readlines() + widths_list = self._refine_widths_input(lines) + + # sets the default data type for each width + widths_dict = {} + for w in widths_list: + widths_dict[w.name] = w.dtype + return widths_dict + + def _gen_xtypes(self, fn): + lines = file(fn).readlines() + xtypes_dict = opnd_types.read_operand_types(lines) + return set(xtypes_dict.keys()) + + + def _compute_explicit_operands(self,v): + # all operands + v.operand_list = v.operands.split() + # just the explicit ones + expl_operand_list = [] + + + for opnd in v.operand_list: + stg = None + vis = None + opname = None + if re.search(r'^[^:]*=',opnd): + pieces = opnd.split(':') + for i,p in enumerate(pieces): + if i == 0: + if '=' in p: + stg,opname = p.split('=') + elif p in ['IMPL', 'SUPP', 'EXPL', 'ECOND']: + vis = p + elif opnd.startswith('IMM0') or opnd.startswith('MEM0') or opnd.startswith('IMM1'): + pieces = opnd.split(':') + opname = pieces[0] + for i,p in enumerate(pieces): + if i>0 and p in ['IMPL', 'SUPP', 'EXPL', 'ECOND']: + vis = p + if opname and vis not in ['IMPL', 'SUPP', 'ECOND']: + expl_operand_list.append(re.sub(r'[()]*','',opname)) + return expl_operand_list + + + def _generate_explicit_operands(self): + for v in self.recs: + if not hasattr(v,'iform'): + v.iform='' + v.explicit_operands = self._compute_explicit_operands(v) + + def _parse_operands(self): + '''set v.parsed_operands with list of operand_info_t objects (see opnds.py).''' + for v in self.recs: + v.parsed_operands = [] + for op_str in v.operand_list: + #op is an operand_info_t object + op = opnds.parse_one_operand(op_str, + 'DEFAULT', + self.xtypes, + self.widths_dict) + v.parsed_operands.append(op) + #print "OPERAND: {}".format(op) + + + def _fix_real_opcode(self): + for v in self.recs: + if not hasattr(v,'real_opcode'): + v.real_opcode='Y' + + + def _find_opcodes(self): + '''augment the records with information found by parsing the pattern''' + + map_pattern = re.compile(r'MAP=(?P[0-6])') + vex_prefix = re.compile(r'VEX_PREFIX=(?P[0-9])') + rep_prefix = re.compile(r'REP=(?P[0-3])') + osz_prefix = re.compile(r'OSZ=(?P[01])') + no_prefix = re.compile(r'REP=0 OSZ=0') + rexw_prefix = re.compile(r'REXW=(?P[01])') + reg_required = re.compile(r'REG[[](?P[b01]+)]') + mod_required = re.compile(r'MOD[[](?P[b01]+)]') + mod_mem_required = re.compile(r'MOD!=3') + rm_required = re.compile(r'RM[[](?P[b01]+)]') + mode_pattern = re.compile(r' MODE=(?P[012]+)') + not64_pattern = re.compile(r' MODE!=2') + + for v in self.recs: + + if not hasattr(v,'isa_set'): + v.isa_set = v.extension + + v.undocumented = False + if hasattr(v,'comment'): + if 'UNDOC' in v.comment: + v.undocumented = True + + pattern = v.pattern.split() + p0 = pattern[0] + v.map = 0 + v.space = 'legacy' + if p0 in ['0x0F']: + if pattern[1] == '0x38': + v.map = 2 + opcode = pattern[2] + elif pattern[1] == '0x3A': + v.map = 3 + opcode = pattern[2] + else: + v.map = 1 + opcode = pattern[1] + elif p0 == 'VEXVALID=1': + v.space = 'vex' + opcode = pattern[1] + elif p0 == 'VEXVALID=2': + v.space = 'evex' + opcode = pattern[1] + elif p0 == 'VEXVALID=4': #KNC + v.space = 'evex.u0' + opcode = pattern[1] + elif p0 == 'VEXVALID=3': + v.space = 'xop' + opcode = pattern[1] + else: + opcode = p0 + v.opcode = opcode + v.partial_opcode = False + + mp = map_pattern.search(v.pattern) + if mp: + v.map = int(mp.group('map')) + + v.no_prefixes_allowed = False + if no_prefix.search(v.pattern): + v.no_prefixes_allowed = True + + v.osz_required = False + osz = osz_prefix.search(v.pattern) + if osz: + if osz.group('prefix') == '1': + v.osz_required = True + + v.f2_required = False + v.f3_required = False + rep = rep_prefix.search(v.pattern) + if rep: + if rep.group('prefix') == '2': + v.f2_required = True + elif rep.group('prefix') == '3': + v.f3_required = True + + if v.space in ['evex','vex', 'xop']: + vexp = vex_prefix.search(v.pattern) + if vexp: + if vexp.group('prefix') == '0': + v.no_prefixes_allowed = True + elif vexp.group('prefix') == '1': + v.osz_required = True + elif vexp.group('prefix') == '2': + v.f2_required = True + elif vexp.group('prefix') == '3': + v.f3_required = True + + + v.rexw_prefix = "unspecified" + rexw = rexw_prefix.search(v.pattern) + if rexw: + v.rexw_prefix = rexw.group('rexw') # 0 or 1 + + v.reg_required = 'unspecified' + reg = reg_required.search(v.pattern) + if reg: + v.reg_required = genutil.make_numeric(reg.group('reg')) + + v.rm_required = 'unspecified' + rm = rm_required.search(v.pattern) + if rm: + v.rm_required = genutil.make_numeric(rm.group('rm')) + + v.mod_required = 'unspecified' + mod = mod_required.search(v.pattern) + if mod: + v.mod_required = genutil.make_numeric(mod.group('mod')) + mod = mod_mem_required.search(v.pattern) + if mod: + v.mod_required = '00/01/10' + + # 16/32/64b mode restrictions + v.mode_restriction = 'unspecified' + if not64_pattern.search(v.pattern): + v.mode_restriction = 'not64' + else: + mode = mode_pattern.search(v.pattern) + if mode: + v.mode_restriction = int(mode.group('mode')) + + v.scalar = False + if hasattr(v,'attributes'): + v.attributes = v.attributes.upper() + if 'SCALAR' in v.attributes: + v.scalar = True + + + if opcode.startswith('0x'): + nopcode = int(opcode,16) + elif opcode.startswith('0b'): + # partial opcode.. 5 bits, shifted + nopcode = genutil.make_numeric(opcode) << 3 + v.partial_opcode = True + + v.upper_nibble = int(nopcode/16) + v.lower_nibble = nopcode & 0xF + + + def _parse_state_bits(self,f): + lines = file(f).readlines() + d = [] + state_input_pattern = re.compile(r'(?P[^\s]+)\s+(?P.*)') + while len(lines) > 0: + line = lines.pop(0) + line = patterns.comment_pattern.sub("",line) + line = patterns.leading_whitespace_pattern.sub("",line) + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + p = state_input_pattern.search(line) + if p: + s = r'\b' + p.group('key') + r'\b' + pattern = re.compile(s) + d.append( (pattern, p.group('value')) ) + else: + die("Bad state line: %s" % line) + return d + + def _expand_state_bits_one_line(self,line): + new_line = line + for k,v in self.state_bits: + new_line = k.sub(v,new_line) + return new_line + def _process_lines(self,fn): + r = self._process_input_lines(fn) + + r = self._expand_compound_values(r) + return r + + def _expand_compound_value(self, in_rec): + """ v is dictionary of lists. return a list of those with one element per list""" + if len(in_rec['OPERANDS']) != len(in_rec['PATTERN']): + die("Mismatched number of patterns and operands lines") + x = len(in_rec['PATTERN']) + res = [] + for i in range(0,x): + d = inst_t() + for k,v in in_rec.iteritems(): + if len(v) == 1: + setattr(d,k.lower(),v[0]) + else: + if i >= len(v): + die("k = {0} v = {1}".format(k,v)) + setattr(d,k.lower(),v[i]) + res.append(d) + + return res + + def _delist(self,in_rec): + """The valies in the record are lists. Remove the lists since they are + all now singletons """ + n = inst_t() + for k,v in in_rec.iteritems(): + setattr(n,k.lower(),v[0]) + return n + + def _expand_compound_values(self,r): + n = [] + for v in r: + if len(v['OPERANDS']) > 1 or len(v['PATTERN']) > 1: + t = self._expand_compound_value(v) + n.extend(t) + else: + n.append(self._delist(v)) + return n + + def _process_input_lines(self,fn): + """We'll still have multiple pattern/operands/iform lines after reading this. + Stores each record in a list of dictionaries. Each dictionary has key-value pairs + and the value is always a list""" + + started = False + recs = [] + nt_name = "Unknown" + i = 0 + for line in file(fn): + i = i + 1 + if i > 500: + sys.stdout.write(".") + sys.stdout.flush() + i = 0 + line = patterns.comment_pattern.sub("",line) + line=line.strip() + if line == '': + continue + line = slash_expand.expand_all_slashes(line) + + if patterns.udelete_pattern.search(line): + m = patterns.udelete_full_pattern.search(line) + unamed = m.group('uname') + self.deleted_unames[unamed] = True + continue + + if patterns.delete_iclass_pattern.search(line): + m = pattersn.delete_iclass_full_pattern.search(line) + iclass = m.group('iclass') + self.deleted_instructions[iclass] = True + continue + + line = self._expand_state_bits_one_line(line) + + p = patterns.nt_pattern.match(line) + if p: + nt_name = p.group('ntname') + continue + + + if patterns.left_curly_pattern.match(line): + if started: + die("Nested instructions") + started = True + d = collections.defaultdict(list) + d['NTNAME'].append(nt_name) + continue + + if patterns.right_curly_pattern.match(line): + if not started: + die("Mis-nested instructions") + started = False + recs.append(d) + continue + + if started: + key, value = line.split(":",1) + key = key.strip() + value = value.strip() + if key == 'IFORM': + # fill in missing iforms with empty strings + x = len(d['PATTERN']) - 1 + y = len(d['IFORM']) + # if we have more patterns than iforms, add some + # blank iforms + while y < x: + d['IFORM'].append('') + y = y + 1 + + d[key].append(value) + + else: + die("Unexpected: [{0}]".format(line)) + sys.stdout.write("\n") + return recs + diff --git a/pysrc/refine_regs.py b/pysrc/refine_regs.py new file mode 100644 index 0000000..9adc4b4 --- /dev/null +++ b/pysrc/refine_regs.py @@ -0,0 +1,190 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +from patterns import * +from genutil import * +import enumer + +# $$ reg_info_t + +class reg_info_t(object): + def __init__(self, name, type, width, + max_enclosing_reg, + ordinal, + hreg=False, + max_enclosing_reg_32=None, + display_str=None): + self.name = name.upper() + if display_str: + self.display_str = display_str + else: + self.display_str = self.name + self.type = type.upper() + self.width = width + self.max_enclosing_reg = max_enclosing_reg + self.max_enclosing_reg_32 = max_enclosing_reg_32 + self.ordinal = ordinal + self.hreg = hreg # the AH,BH,CH,DH registers + if self.type == 'GPR': + if self.hreg: + self.rtype = self.type + str(self.width) + self.hreg + else: + self.rtype = self.type + str(self.width) + else: + self.rtype = self.type + + +def refine_regs_input(lines): + """Return a list of reg_info_t. Skip comments and blank lines""" + global comment_pattern + all_ri = [] + reg_width_dict = {} + for line in lines: + pline = comment_pattern.sub('',line).strip() + if pline == '': + continue + wrds = pline.split() + n = len(wrds) + # if there are only 3 fields, duplicate the first field as the 4th field + if n == 3: + n = 4 + first = wrds[0] + wrds.append(first) + if n == 6 and (wrds[5] not in [ 'h', '-']): + die("regs-read: Illegal final token on line: " + line) + if n < 4 or n > 7: + die("regs-read: Bad number of tokens on line: " + line) + name = wrds[0] + rtype = wrds[1] + width = wrds[2] + max_enclosing_reg = wrds[3] + max_enclosing_reg_32 = None + if '/' in max_enclosing_reg: + (max_enclosing_reg, max_enclosing_reg_32) = max_enclosing_reg.split('/') + + ordinal = 0 + if n >= 5: + ordinal = int(wrds[4]) + hreg = None + if n >= 6: + hreg = wrds[5] + if hreg != 'h': + hreg = None + # 7th operand is a display string to replace the name in the enumerations + display_str = None + if n >= 7: + display_str = wrds[6] + + ri = reg_info_t(name, + rtype, + width, + max_enclosing_reg, + ordinal, + hreg, + max_enclosing_reg_32, + display_str) + all_ri.append(ri) + + # CR/DR regs have slashes in the width for 32/64b mode. They + # are not relevant for the register enclosing computation that + # this code is facilitating. + if width == 'NA': + # the pseudo registers use NA as their width. We do not + # care about the enclosing register computation for them. + short_width = '1' + elif '/' in width: + short_width = re.sub(r'/.*','',width) + else: + short_width = width + + iw = int(short_width) + if name in reg_width_dict: + if reg_width_dict[name] < iw: + reg_width_dict[name] = iw + else: + reg_width_dict[name] = iw + + regs_name_list = [] + regs_dict = {} + + for ri in all_ri: + # add name to list to preserve original order + if ri.name not in regs_dict: + regs_dict[ri.name] = ri + regs_name_list.append(ri.name) + elif regs_dict[ri.name].width < ri.width: # replace narrower + regs_dict[ri.name] = ri + else: + old_enclosing = regs_dict[ri.name].max_enclosing_reg + a = reg_width_dict[old_enclosing] + b = reg_width_dict[ri.max_enclosing_reg] + print "LER: Comparing {} and {} for {}".format(old_enclosing, + ri.max_enclosing_reg, + ri.name) + if a < b: + # take the wider enclosing registers + print "\ttaking new wider version" + regs_dict[ri.name] = ri + + # return a list resembling the original order + regs_list = [] + for nm in regs_name_list: + regs_list.append(regs_dict[nm]) + + return regs_list + +def _reg_cmp(a,b): + if a.ordinal < b.ordinal: + return -1 + elif a.ordinal > b.ordinal: + return 1 + return 0 + +def rearrange_regs(regs_list): + """Return a list of enumer.enumer_values_t objects to be passed to + enum_txt_writer""" + groups = uniqueify(map(lambda(x) : x.rtype, regs_list)) + msgb("RGROUPS", str(groups)) + enumvals = [] + for g in groups: + k = filter(lambda(x): x.rtype == g, regs_list) + k.sort(cmp=_reg_cmp) + first = '%s_FIRST' % (g) + last = '%s_LAST' % (g) + + # first + enumvals.append(enumer.enumer_value_t(k[0].name, + display_str=k[0].display_str)) + enumvals.append(enumer.enumer_value_t(first, + value=k[0].name, + doxygen='//< PSEUDO')) + + # everything in the middle + if len(k) > 1: + enumvals.extend( + map(lambda(x) : enumer.enumer_value_t(x.name, + display_str=x.display_str), k[1:])) + #last + enumvals.append(enumer.enumer_value_t(last, + value=k[-1].name, + doxygen='// +# Code generation support: emitting files, emitting functions, etc. +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +import re +import genutil + +slash2_macro_pattern = re.compile(r'(?P[a-z])[/](?P[0-9]+)') + +def expand_all_slashes(s): + global slash2_macro_pattern + a = s + m = slash2_macro_pattern.search(a) + while m: + n = int(m.group('number')) + if n > 99: + genutil.die("Hit a very large number %d when explanding slash patterns in [%s]" %( n, s)) + new = n * m.group('letter') + old = '%s/%s' % ( m.group('letter'), m.group('number') ) + #print "old %s -> new %s" % (old,new) + a = a.replace(old,new,1) + m = slash2_macro_pattern.search(a) + return a diff --git a/pysrc/tup2int.py b/pysrc/tup2int.py new file mode 100644 index 0000000..1454e1d --- /dev/null +++ b/pysrc/tup2int.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +def tuple2int(t, cnames, op_widths_dict): + """Convert list of values in the input parameter t to a hash key by + shifting and adding (OR'ing really) the values together. Must + factor in the max width of each field. The max width of each + component comes from the cnames and op_widths_dict parameters). + """ + res = 0 + bit_shift = 0 + for i,byte in enumerate(t): + opwidth = op_widths_dict[cnames[i]] + res += byte << bit_shift + bit_shift += opwidth + return res diff --git a/pysrc/verbosity.py b/pysrc/verbosity.py new file mode 100644 index 0000000..c41b1b6 --- /dev/null +++ b/pysrc/verbosity.py @@ -0,0 +1,139 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +_verbosity_options = [] +def set_verbosity_options(options): + global _verbosity_options + _verbosity_options = options + + +def vflag(): + return 'flag' in _verbosity_options +def vnext(): + return 'next' in _verbosity_options +def vrearrange(): + return 'rearrange' in _verbosity_options +def vmacro(): + return 'macro' in _verbosity_options +def vreadyscan(): + return 'readyscan' in _verbosity_options +def vbitgroup(): + return 'bitgroup' in _verbosity_options +def vextract(): + return 'extract' in _verbosity_options +def vstack(): + return 'stack' in _verbosity_options +def vgraph_res(): + return 'graph_res' in _verbosity_options +def varraygen(): + return 'arraygen' in _verbosity_options +def viform(): + return 'iform' in _verbosity_options +def viclass(): + return 'iclass' in _verbosity_options +def vattr(): + return 'attribute' in _verbosity_options +def vopnd(): + return 'opnd' in _verbosity_options +def vlookup(): + return 'lookup' in _verbosity_options +def vopvis(): + return 'opvis' in _verbosity_options +def vcapture(): + return 'capture' in _verbosity_options +def vcapture1(): + return 'capture1' in _verbosity_options +def vcapture2(): + return 'capture2' in _verbosity_options +def vcapturefunc(): + return 'capture' in _verbosity_options +def vbind(): + return 'bind' in _verbosity_options +def vod(): + return 'od' in _verbosity_options +def vtrace(): + return 'trace' in _verbosity_options +def vparse(): + return 'parse' in _verbosity_options +def vpart(): + return 'partition' in _verbosity_options +def vbuild(): + return 'build' in _verbosity_options +def vmerge(): + return 'merge' in _verbosity_options + +def verb1(): + return '1' in _verbosity_options +def verb2(): + return '2' in _verbosity_options +def verb3(): + return '3' in _verbosity_options +def verb4(): + return '4' in _verbosity_options +def verb5(): + return '5' in _verbosity_options +def verb6(): + return '6' in _verbosity_options +def verb7(): + return '7' in _verbosity_options + +def vencfunc(): + return 'encfunc' in _verbosity_options +def vencode(): + return 'encode' in _verbosity_options +def vntname(): + return 'ntname' in _verbosity_options +def vtestingcond(): + return 'testingcond' in _verbosity_options +def vclassify(): + return 'classify' in _verbosity_options +def veparse(): + return 'eparse' in _verbosity_options +def veemit(): + return 'eemit' in _verbosity_options +def vignoreod(): + return 'ignoreod' in _verbosity_options +def vtuples(): + return 'tuples' in _verbosity_options +def vdumpinput(): + return 'dumpinput' in _verbosity_options +def vfinalize(): + return 'finalize' in _verbosity_options +def vopseq(): + return 'opseq' in _verbosity_options +def voperand(): + return 'operand' in _verbosity_options +def voperand2(): + return 'operand2' in _verbosity_options +def vinputs(): + return 'inputs' in _verbosity_options +def vread(): + return 'read' in _verbosity_options +def vcapture(): + return 'capture' in _verbosity_options +def vrule(): + return 'rule' in _verbosity_options +def vaction(): + return 'action' in _verbosity_options +def vblot(): + return 'blot' in _verbosity_options + +def vild(): + return 'ild' in _verbosity_options +def vfuncgen(): + return 'funcgen' in _verbosity_options diff --git a/pysrc/xed3_nt.py b/pysrc/xed3_nt.py new file mode 100755 index 0000000..56147f4 --- /dev/null +++ b/pysrc/xed3_nt.py @@ -0,0 +1,795 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import genutil +import ildutil +import ild_nt +import ild_cdict +import mbuild +import codegen +import ild_phash +import os +import ild_codegen +import operand_storage +import verbosity +import tup2int + +_xed3_ops_type = 'xed3_operands_struct_t*' +_xed3_ops_header = 'xed3-operands-struct.h' +_key_ctype = 'xed_uint32_t' +_xed3_err_op = 'error' +_xed3_gen_error = 'XED_ERROR_GENERAL_ERROR' +_xed_reg_error_val = 'XED_ERROR_BAD_REGISTER' +_xed_no_err_val = 'XED_ERROR_NONE' +_xed_op_type = 'xed_operand_values_t' +_xed3_opstruct_type = 'xed3_operands_struct_t' + +def _vlog(f,s): + if verbosity.vcapture(): + f.write(s) + +#FIXME: this is not used currently, but it would be nice +#to have a special error enum with more specific error reasons +#instead of just XED_ERROR_GENERAL_ERROR +#for example for each NT we can create a separate error value +def _nt_2_xed3_err_enum(nt_name): + return 'XED3_ERROR_%s' % nt_name.upper() + +#This is not used currently. +#I was going to use it for decoding the operands: for each +#operand enum value call the corresponding NT function, +#but it turned out to be better to generate chain capture functions +#for each operands combination +def dump_nt_enum_2_capture_fptr(agi, fname): + """Dump mapping nt_enum -> nt_capture_fptr + """ + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = mbuild.join(agi.common.options.gendir,'include-private') + + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + fname, shell_file=False, + is_private=True) + h_file.add_header('xed-lookup-functions.h') + h_file.add_header(_xed3_nt_capture_header) + h_file.start() + lu_name = 'xed3_nt_2_capture' + + xed3_capture_f_t = 'xed3_capture_function_t' + + fptr_typedef = 'typedef void(*%s)(%s*);' % (xed3_capture_f_t, + ildutil.xed3_decoded_inst_t) + + fptr_typedef = 'typedef void(*%s)(xed_decoded_inst_t*);' % xed3_capture_f_t + + h_file.add_code(fptr_typedef) + + h_file.add_code(('static %s ' % xed3_capture_f_t) +\ + '%s[XED_NONTERMINAL_LAST] = {' % lu_name) + nonterminals = agi.nonterminal_dict.keys() + + invalid_line = '/*XED_NONTERMINAL_INVALID*/ (%s)0,' % xed3_capture_f_t + h_file.add_code(invalid_line) + for nt_name in agi.xed3_nt_enum_val_map.values(): + enum_val = 'XED_NONTERMINAL_%s' % nt_name.upper() + if _skip_nt(nt_name): + fn = '0' + else: + fn = get_xed3_nt_capture_fn(nt_name) + h_file.add_code('/*%s*/ (%s)%s,'% (enum_val, xed3_capture_f_t, fn)) + h_file.add_code('};') + h_file.close() + + +def get_ii_constraints(ii, state_space, constraints): + """ + sets constraints[xed_operand_name][xed_operand_val] = True + + xed_operandname and xed_operand_val correspond to operands + encountered in ii (both operand deciders and constant prebindings) + """ + #set constraints that come from operands deciders + ild_nt.add_op_deciders(ii.ipattern, state_space, constraints) + #set constraints that come from prebindings + for name,binding in ii.prebindings.items(): + if binding.is_constant(): + if name not in constraints: + constraints[name] = {} + val = int(binding.get_value(), 2) + constraints[name][val] = True + +def _get_all_cnames(gi): + """ + Returns a set of all constraints used by a given gi + (generator_info - represents a single NT) + """ + cnames = [] + for rule in gi.parser_output.instructions: + cnames.extend(rule.xed3_constraints.keys()) + return set(cnames) + +def _gen_cdict(agi, nt_name, all_state_space): + """ + Creates a ild_cdict.constraint_dict_t corresponding to NT + defined by gi. + """ + gi = agi.generator_dict[nt_name] + options = agi.common.options + + state_space = {} + for opname in all_state_space: + state_space[opname] = all_state_space[opname].keys() + + + cdict_list = [] + + for rule in gi.parser_output.instructions: + rule.xed3_constraints = {} + get_ii_constraints(rule, state_space, rule.xed3_constraints) + + cnames = _get_all_cnames(gi) + + for rule in gi.parser_output.instructions: + cdict = ild_cdict.constraint_dict_t( + cnames, + rule.xed3_constraints, + all_state_space, + rule) + cdict_list.append(cdict) + msg = "cdict conflict in NT %s\n" % nt_name + united_dict = ild_cdict.constraint_dict_t.unite_dicts( + cdict_list, + msg, + cnames) + return united_dict + + +def get_xed3_member_name(xed2_opname): + """ + This is not used currently. + When we have a struct for operands instead of _operands array + this can be used to get struct member name from operand + """ + return xed2_opname.lower() + +_xed3_capture_fn_pfx = 'xed3_capture' + +def get_xed3_nt_capture_fn(nt_name): + """ + Return a xed3 capture function name for a given NT name. + """ + return '%s_nt_%s' % (_xed3_capture_fn_pfx, nt_name) + +def get_xed3_capture_chain_fn(nt_names, is_ntluf=False): + """ + Return a xed3 chain capture function name from a given list of + NT names. + is_ntluf==True for operands chain functions. + """ + suffix = '_'.join(nt_names) + if is_ntluf: + suffix = 'ntluf_%s' % suffix + return '%s_chain_%s' % (_xed3_capture_fn_pfx, suffix) + +def _add_cgen_key_lines(fo, + nt_name, + gi, + all_ops_widths, + key_str='key', + inst='d'): + """ + Add C code to compute the key from constraints' values. + """ + fo.add_code_eol('%s %s = 0' % (_key_ctype, key_str)) + cdict = gi.xed3_cdict + bit_shift = 0 + for i,cname in enumerate(cdict.cnames): + #eosz_set=True indicates that current value of EOSZ is correct + #in the _operands array and we can take it from there. + #Otherwise we would have to use special eosz computing functions + #the same way as we do in ILD. + #eosz_set=True here because we are doing dynamic decoding + #and have processed the NTs that come before the current NT. + access_str = ild_codegen.emit_ild_access_call(cname, inst, + eoasz_set=True) + + #constraints might have 1,2 or 3 bit widths + #and we allocate bits in the key vector appropriately + #e.g REXB operand gets only 1 bit in the key + #and RM gets 3 bits + shift_val = ('(%s)' % bit_shift) + bit_shift += all_ops_widths[cname] + fo.add_code_eol('%s += (%s) << (%s)' % (key_str,access_str, shift_val)) + +def _get_pattern_nts(rule): + """ + Return a list of NT names present in given rule. + """ + nt_names = [] + for bt in rule.ipattern.bits: + if bt.is_nonterminal(): + nt_name = bt.nonterminal_name() + nt_names.append(nt_name) + return nt_names + +def _is_error_rule(rule): + for op in rule.operands: + if op.type == 'error': + return True + return False + +def _add_capture_nt_call(fo, nt_name, inst='d', indent=0): + capture_fn = get_xed3_nt_capture_fn(nt_name) + indent = ' ' * indent + fo.add_code_eol('%s%s(%s)' % (indent, capture_fn, inst)) + +def _add_op_assign_stmt(fo, opname, opval, inst='d', op=None, + indent=0): + if op: + fo.add_code('/* op.type=%s */' % op.type) + setter_fn = operand_storage.get_op_setter_fn(opname) + set_stmt = '%s(%s, %s)' %(setter_fn, inst, opval) + indentstr = ' ' * indent + fo.add_code_eol(indentstr + set_stmt) + +def _is_reg_error_op(op): + return op.bits in ['XED_REG_ERROR'] + +def _add_nt_rhs_assignments(fo, nt_name, gi, rule, inst='d'): + #fo.add_code("/* %s */" % rule) + + #first if it's error, we set general_error and quit + if _is_error_rule(rule): + _add_op_assign_stmt(fo, _xed3_err_op, _xed3_gen_error, + inst, indent=1) + return + + #now check if there are NT calls in pattern, we need to call them first + pattern_nts = _get_pattern_nts(rule) + for nt_name in pattern_nts: + _add_capture_nt_call(fo, nt_name, inst, indent=1) + + #now let's do the RHS - for each operand assign value + #FIXME: if we assign ERROR_REG or INVALID_REG set also error? + for op in rule.operands: + if op.name == 'ENCODER_PREFERRED': + #skip encoder preferred + continue + if op.type == 'imm': + #skip prebindings + continue + if op.type == 'nt_lookup_fn': + #NT as RHS, we call its capturing function + #and then assign op.name to OUTREG + _add_capture_nt_call(fo, op.lookupfn_name, inst, indent=1) + #now copy the outreg to op.name (unless it is outreg too!) + if op.name != 'OUTREG': + getter_fn = operand_storage.get_op_getter_fn('outreg') + outreg_expr = '%s(%s)' % (getter_fn, inst) + _add_op_assign_stmt(fo, op.name, outreg_expr, inst, indent=1) + + else: #assignment of an operand to a constant + _add_op_assign_stmt(fo, op.name, op.bits, inst, indent=1) + if _is_reg_error_op(op): + _add_op_assign_stmt(fo, _xed3_err_op, + _xed_reg_error_val, inst, indent=1) + fo.add_code('/*pacify the compiler */') + fo.add_code_eol('(void)%s' % inst) + +def _add_case_lines(fo, nt_name, gi, rule, inst='d'): + _add_nt_rhs_assignments(fo, nt_name, gi, rule, inst=inst) + fo.add_code_eol(' break') + +def _add_switchcase_lines(fo, + nt_name, + gi, + all_ops_widths, + key_str='key', + inst='d'): + cdict = gi.xed3_cdict + fo.add_code('switch(%s) {' %key_str) + + int2key = {} + key2int = {} + for key in cdict.tuple2rule.keys(): + keyval = tup2int.tuple2int(key, cdict.cnames, all_ops_widths) + #This checks for a nasty conflict that should never happen: + #when two different tuple keys have the same integer value. + #This conflict can happen when bit widths of all constraints are + #bigger than 32 bit (key is uint32 currently). + #In general such error will be caught by C compiler when we try + #to build a key and shift more than 32 bits. + #Checking here too just to be sure. + #FIXME: add an assertion to constraint_dict_t constructor to check + #for that? + #FIXME: this doesn't really checks for integer overflow, because + #python autmatically extends int32 if it overflows to int64. + #Need better checking. + if keyval in int2key: + msg = [] + msg.append('CDICT TUPLE VALUE CONFLICT in nt %s !!!!' % nt_name) + msg.append('keyval %s' % keyval) + msg.append('key1 %s, key2 %s' % (key, int2key[keyval])) + msg.append('cdict %s') + msg = '\n'.join(msg) + ildutil.ild_err(msg) + int2key[keyval] = key + key2int[key] = keyval + + covered_rules = set() + + #we want cases sorted by value - prettier + for keyval in sorted(int2key.keys()): + key = int2key[keyval] + rule = cdict.tuple2rule[key] + if rule in covered_rules: + continue + covered_rules.add(rule) + keys = cdict.get_all_keys_by_val(rule) + for key in keys: + #FIXME: move tuple2int to ild_cdict? + keyval = key2int[key] + fo.add_code('case %s: /*%s -> %s*/' %(keyval, key, rule)) + _add_case_lines(fo, nt_name, gi, rule) + fo.add_code('default:') + if gi.parser_output.otherwise_ok: + fo.add_code('/* otherwise_ok */') + else: + #FIXME: temporary using general error, later + #define more specific error enum + #errval = _nt_2_xed3_err_enum(nt_name) + errval = 'XED_ERROR_GENERAL_ERROR' + _add_op_assign_stmt(fo, _xed3_err_op, errval, + inst, indent=1) + fo.add_code_eol(' break') + fo.add_code('}') + + +def gen_capture_fo(agi, nt_name, all_ops_widths): + """ + Generate xed3 capturing function for a given NT name. + """ + gi = agi.generator_dict[nt_name] + cdict = gi.xed3_cdict + fname = get_xed3_nt_capture_fn(nt_name) + inst = 'd' + keystr = 'key' + fo = fo = codegen.function_object_t(fname, + return_type='void', + static=True, + inline=True) + fo.add_arg(ildutil.xed3_decoded_inst_t + '* %s' % inst) + if len(cdict.cnames) > 0: + _add_cgen_key_lines(fo, nt_name, gi, all_ops_widths, keystr, inst) + fo.add_code('/* now switch code..*/') + _add_switchcase_lines(fo, nt_name, gi, all_ops_widths, keystr, inst) + else: + rule = cdict.rule + _add_nt_rhs_assignments(fo, nt_name, gi, rule) + return fo + +#FIXME: not used currently. +#Will be nice to use it and have different types for different members, +#especially for registers. 9debugging and overall tidy code) +def _gen_xed3_op_struct(agi, hfn): + """ + Dump xed3_oprands_struct_t definition + """ + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = mbuild.join(agi.common.options.gendir) + + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + hfn, shell_file=False, + is_private=False) + h_file.add_header('xed-operand-storage.h') + h_file.start() + + + typedef_s = 'typedef struct xed3_operands_struct_s {' + h_file.add_code(typedef_s) + + for op_name in agi.xed3_operand_names: + h_file.add_code('%s %s;'% (_xed_op_type, op_name.lower())) + h_file.add_code('} %s;' %_xed3_opstruct_type) + h_file.close() + +def _get_op_nt_names_from_ii(ii): + nt_names = [] + for op in ii.operands: + if op.type == 'nt_lookup_fn': + nt_names.append(op.name + '_' + op.lookupfn_name) + elif op.type == 'imm_const': + suffix = '_const%s' % op.bits + nt_names.append(op.name + suffix) + elif op.type == 'reg': + suffix = '_%s' % op.bits + nt_names.append(op.name + suffix) + return nt_names + +def _get_nt_names_from_ii(ii): + """ + @param ii - instruction_info_t + @return list of NT names in ii's pattern + """ + nt_names = [] + for bt in ii.ipattern.bits: + if bt.is_nonterminal(): + name = bt.nonterminal_name() + if not name: + ildutil.ild_err('Failed to get NT name in %s for %s' % (ii,bt)) + nt_names.append(name) + return nt_names + +def _gen_ntluf_capture_chain_fo(nt_names, ii): + """ + Given a list of OP_NAME_NT_NAME strings(nt_names), generate a function + object (function_object_t) + that calls corresponding xed3 NT capturing functions. + Each such function captures everything that xed2 decode graph would + capture for a given pattern with operands that have nt_lokkupfns. + The difference between this function and _gen_capture_chain_fo + is that this function creates chain capturing functions for + operand decoding - assigns the REG[0,1] operands, etc. + """ + fname = get_xed3_capture_chain_fn(nt_names, is_ntluf=True) + inst = 'd' + fo = fo = codegen.function_object_t(fname, + return_type=_xed3_chain_return_t, + static=True, + inline=True) + fo.add_arg(ildutil.xed3_decoded_inst_t + '* %s' % inst) + + for op in ii.operands: + if op.type == 'nt_lookup_fn': + nt_name = op.lookupfn_name + capture_fn = get_xed3_nt_capture_fn(nt_name) + capture_stmt = '%s(%s)' % (capture_fn, inst) + fo.add_code_eol(capture_stmt) + #if we have NTLUF functions, we need to assign OUTREG + getter_fn = operand_storage.get_op_getter_fn('outreg') + outreg_expr = '%s(%s)' % (getter_fn, inst) + fo.add_code('/*opname %s */' % op.name) + _add_op_assign_stmt(fo, op.name, outreg_expr, inst) + #now check if we have errors in current NT + #we don't need to check if there was a reg_error because + #we assign error operand inside the called nt_capture function + #if there was a reg_error + getter_fn = operand_storage.get_op_getter_fn(_xed3_err_op) + errval = '%s(%s)' % (getter_fn, inst) + fo.add_code('if (%s) {' % errval) + fo.add_code_eol('return %s' % errval) + fo.add_code('}') + elif op.type in ['imm_const', 'reg']: + opval = op.bits + _add_op_assign_stmt(fo, op.name, opval, inst) + + + fo.add_code_eol('return %s' % _xed_no_err_val) + return fo + +def _gen_capture_chain_fo(nt_names, fname=None): + """ + Given a list of NT names, generate a function object (function_object_t) + that calls corresponding xed3 NT capturing functions. + Each such function captures everything that xed2 decode graph would + capture for a given pattern with NTs (nt_names) in it. + """ + if not fname: + fname = get_xed3_capture_chain_fn(nt_names) + inst = 'd' + fo = fo = codegen.function_object_t(fname, + return_type=_xed3_chain_return_t, + static=True, + inline=True) + fo.add_arg(ildutil.xed3_decoded_inst_t + '* %s' % inst) + + for name in nt_names: + capture_fn = get_xed3_nt_capture_fn(name) + capture_stmt = '%s(%s)' % (capture_fn, inst) + fo.add_code_eol(capture_stmt) + #now check if we have errors in current NT + getter_fn = operand_storage.get_op_getter_fn(_xed3_err_op) + errval = '%s(%s)' % (getter_fn, inst) + fo.add_code('if (%s) {' % errval) + fo.add_code_eol('return %s' % errval) + fo.add_code('}') + + fo.add_code_eol('return %s' % _xed_no_err_val) + return fo + +_xed3_chain_header = 'xed3-chain-capture.h' +_xed3_op_chain_header = 'xed3-op-chain-capture.h' +_xed3_chain_lu_header = 'xed3-chain-capture-lu.h' +_xed3_op_chain_lu_header = 'xed3-op-chain-capture-lu.h' +_xed3_nt_capture_header = 'xed3-nt-capture.h' +_xed3_capture_lu_header = 'xed3-nt-capture-lu.h' +_xed3_empty_capture_func = 'xed3_capture_nt_nop' +_xed3_chain_return_t = 'xed_error_enum_t' +_xed3_dynamic_part1_header = 'xed3-dynamic-part1-capture.h' + + +def _gen_empty_capture_fo(is_ntluf=False): + """ + Generate capture function that does nothing. + For patterns without NTs. + """ + inst = 'd' + if is_ntluf: + fname = '%s_ntluf' % _xed3_empty_capture_func + else: + fname = _xed3_empty_capture_func + fo = fo = codegen.function_object_t(fname, + return_type=_xed3_chain_return_t, + static=True, + inline=True) + fo.add_arg(ildutil.xed3_decoded_inst_t + '* %s' % inst) + fo.add_code_eol('(void)%s' % inst) + fo.add_code_eol('return %s' % _xed_no_err_val) + return fo + +def _dump_op_capture_chain_fo_lu(agi, patterns): + """ + Creates chain capturing functions for operands - for each pattern, + dumps those functions definitions, dumps a mapping + from inum(xed_inst_t index) to those functions. + """ + fn_2_fo = {} + inum_2_fn = {} + nop_fo = _gen_empty_capture_fo(is_ntluf=True) + fn_2_fo[nop_fo.function_name] = nop_fo + for ptrn in patterns: + ii = ptrn.ii + nt_names = _get_op_nt_names_from_ii(ii) + if len(nt_names) == 0: + #if no NTs we use empty capturing function + fn = nop_fo.function_name + else: + fn = get_xed3_capture_chain_fn(nt_names, is_ntluf=True) + if fn not in fn_2_fo: + fo = _gen_ntluf_capture_chain_fo(nt_names, ii) + fn_2_fo[fn] = fo + inum_2_fn[ii.inum] = (fn, ii.operands) + + + #dump chain functions + headers = [_xed3_nt_capture_header] + ild_codegen.dump_flist_2_header(agi, + _xed3_op_chain_header, + headers, + fn_2_fo.values(), + is_private=True) + + lu_size = max(inum_2_fn.keys()) + 1 + + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = mbuild.join(agi.common.options.gendir,'include-private') + + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + _xed3_op_chain_lu_header, shell_file=False, + is_private=True) + h_file.add_header(_xed3_op_chain_header) + h_file.start() + lu_name = 'xed3_op_chain_fptr_lu' + xed3_op_chain_f_t = 'xed3_op_chain_function_t' + + fptr_typedef = 'typedef %s(*%s)(%s*);' % (_xed3_chain_return_t, + xed3_op_chain_f_t, + ildutil.xed3_decoded_inst_t) + + h_file.add_code(fptr_typedef) + + h_file.add_code(('static %s ' % xed3_op_chain_f_t) +\ + '%s[%s] = {' % (lu_name, lu_size)) + + empty_line = '/*NO PATTERN*/ (%s)0,' % xed3_op_chain_f_t + + for inum in range(0, lu_size): + if inum in inum_2_fn: + (fn, oplist) = inum_2_fn[inum] + op_str = '\n'.join([str(op) for op in oplist]) + entry_str = '/*%s inum=%s*/ %s,' % (op_str,inum, fn) + else: + entry_str = empty_line + h_file.add_code(entry_str) + h_file.add_code('};') + h_file.close() + + +def _dump_capture_chain_fo_lu(agi, patterns): + """ + Creates chain capturing functions - for each pattern, + dumps those functions definitions, dumps a mapping + from inum(xed_inst_t index) to those functions. + """ + fn_2_fo = {} + inum_2_fn = {} + + nop_fo = _gen_empty_capture_fo() + fn_2_fo[nop_fo.function_name] = nop_fo + for ptrn in patterns: + ii = ptrn.ii + nt_names = _get_nt_names_from_ii(ii) + if len(nt_names) == 0: + #if no NTs we use empty capturing function + fn = nop_fo.function_name + else: + fn = get_xed3_capture_chain_fn(nt_names) + if fn not in fn_2_fo: + fo = _gen_capture_chain_fo(nt_names) + fn_2_fo[fn] = fo + inum_2_fn[ii.inum] = (fn, ptrn.ptrn) + + + #dump chain functions + headers = [_xed3_nt_capture_header] + ild_codegen.dump_flist_2_header(agi, + _xed3_chain_header, + headers, + fn_2_fo.values(), + is_private=True) + + lu_size = max(inum_2_fn.keys()) + 1 + + xeddir = os.path.abspath(agi.common.options.xeddir) + gendir = mbuild.join(agi.common.options.gendir,'include-private') + + h_file = codegen.xed_file_emitter_t(xeddir,gendir, + _xed3_chain_lu_header, shell_file=False, + is_private=True) + h_file.add_header(_xed3_chain_header) + h_file.start() + lu_name = 'xed3_chain_fptr_lu' + xed3_chain_f_t = 'xed3_chain_function_t' + + fptr_typedef = 'typedef %s(*%s)(%s*);' % (_xed3_chain_return_t, + xed3_chain_f_t, + ildutil.xed3_decoded_inst_t) + + h_file.add_code(fptr_typedef) + + h_file.add_code(('static %s ' % xed3_chain_f_t) +\ + '%s[%s] = {' % (lu_name, lu_size)) + + empty_line = '/*NO PATTERN*/ (%s)0,' % xed3_chain_f_t + + for inum in range(0, lu_size): + if inum in inum_2_fn: + (fn, ptrn_str) = inum_2_fn[inum] + entry_str = '/*\n%s\ninum=%s*/ %s,' % (ptrn_str, inum,fn) + else: + entry_str = empty_line + h_file.add_code(entry_str) + h_file.add_code('};') + h_file.close() + +def _dump_dynamic_part1_f(agi): + """ + Dumps the xed3_dynamic_decode_part1 function that captures all the + NTs in the spine that come before INSTRUCTIONS NT. + """ + fo = _gen_dynamic_part1_fo(agi) + #dump the function + headers = [_xed3_nt_capture_header] + ild_codegen.dump_flist_2_header(agi, + _xed3_dynamic_part1_header, + headers, + [fo], + is_private=True) + +#things that are covered by ILD and static decoding +#FIXME: is there a better way to determine them instead of just +#hardcoding their names? +_nts_to_skip = ['PREFIXES', 'ISA'] +_spine_nt_name = 'ISA' +_dynamic_part1_fn = 'xed3_dynamic_decode_part1' + +def _skip_nt(nt_name): + """ + Return True if there is no need to generate a capturing + function for a given NT name. + """ + return (nt_name in _nts_to_skip or + 'INSTRUCTIONS' in nt_name or + 'SPLITTER' in nt_name) + +def _gen_dynamic_part1_fo(agi): + """ + Generate the xed3_dynamic_decode_part1 function that + captures all the NTs that come before INSTRUCTIONS. + The generated function should be called after ILD and before + static decoding. + """ + gi = agi.generator_dict[_spine_nt_name] + if len(gi.parser_output.instructions) != 1: + ildutil.ild_err("Failed to gen dynamic part1 function!\n" + + "Unexpected number of rules in %s NT: %s" % + (_spine_nt_name, len(gi.parser_output.instructions))) + rule = gi.parser_output.instructions[0] + nt_names = _get_nt_names_from_ii(rule) + + #filter NTs that we want to skip + nt_names = filter(lambda(x): not _skip_nt(x), nt_names) + fo = _gen_capture_chain_fo(nt_names, fname=_dynamic_part1_fn) + return fo + + + +def work(agi, all_state_space, all_ops_widths, patterns): + """ + Main entry point of the module. + For each NT generate a capturing function. + Then for each sequence of NTs in patterns generate a + chain capturing function that would call single capturing functions + for each NT. + Then for each combination of operands generate operands chain captuirng + function. + Also generate lookup tables to obtain those chain capturing functions + from inum (xed_inst_t index). + """ + gendir = ild_gendir = agi.common.options.gendir + logfn = mbuild.join(gendir, 'xed3_nt_cdicts.txt') + log_f = open(logfn, 'w') + + #generate NT capturing functions + capture_fn_list = [] + for nt_name in agi.nonterminal_dict.keys(): + #skip non terminals that we don't want to capture: + #PREFIXES, AVX_SPLITTER, *ISA, etc. + if _skip_nt(nt_name): + continue + + _vlog(log_f,'processing %s\n' % nt_name) + #create a constraint_dict_t for each NT + nt_cdict = _gen_cdict(agi, nt_name, all_state_space) + _vlog(log_f,'NT:%s:\n%s\n' % (nt_name, nt_cdict)) + gi = agi.generator_dict[nt_name] + gi.xed3_cdict = nt_cdict #just for transporting + #create a function_object_t for the NT + fo = gen_capture_fo(agi, nt_name, all_ops_widths) + gi.xed3_capture_fo = fo + capture_fn_list.append(fo) + _vlog(log_f,fo.emit()) + + #dump NT capturing functions + headers = [operand_storage.get_operand_accessors_fn(), ildutil.ild_header] + ild_codegen.dump_flist_2_header(agi, + _xed3_nt_capture_header, + headers, + capture_fn_list, + is_private=True) + + #in each pattern we have a number of NTs, + #now that we have a capturing function for each NT + #we can create a create a function that would call + #needed capturing functions for each pattern. + #Also dump lookup tables from inum(xed_inst_t index) to + #chain capturing functions + _dump_capture_chain_fo_lu(agi, patterns) + + #do the same for operands of each xed_inst_t + _dump_op_capture_chain_fo_lu(agi, patterns) + + #create chain capturing functions for the NTs that come from + #spine, before the INSTRUCTIONS NT + _dump_dynamic_part1_f(agi) + + log_f.close() + + + + + diff --git a/pysrc/xedhash.py b/pysrc/xedhash.py new file mode 100644 index 0000000..b34110a --- /dev/null +++ b/pysrc/xedhash.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import collections + +#The idea is to have different algorithms for finding hash +#functions. So far we use only FKS and it seems to work well enough. +class hash_fun_interface_t(object): + def _raise_error(self): + raise NotImplementedError("Hash function not implemented.") + def apply(self, x): + self._raise_error() + def emit_cexpr(self, key_str): + self.raise_error() + def __str__(self): + self._raise_error() + def kind(self): + self._raise_error() + +def is_perfect(keylist, hash_f): + "Does each input map to a different bucket? If so, it is perfect.""" + bucket = set() + for x in keylist: + hash_val = hash_f.apply(x) + if hash_val in bucket: + # collision! ka-boom + return None + else: + bucket.add(hash_val) + return bucket + +def _measure_bucket_max(table, maxbin): + """check for buckets that are too large (_l1_bucket_max)""" + okay = True + max_bucket = 0 + bad_buckets = 0 + for k, vl in table.iteritems(): + lvl = len(vl) + if lvl >= maxbin: + if lvl > max_bucket: + max_bucket = lvl + bad_buckets = bad_buckets + 1 + okay = False + return okay + +def is_well_distributed(keylist, hash_f, maxbin): + """populate the buckets and see if any are too big""" + table = collections.defaultdict(list) + for t,x in keylist.iteritems(): + hash_val = hash_f.apply(x) + table[hash_val].append(t) + + okay = _measure_bucket_max(table, maxbin) + return okay diff --git a/scripts/apply_legal_header.py b/scripts/apply_legal_header.py new file mode 100755 index 0000000..8749b3c --- /dev/null +++ b/scripts/apply_legal_header.py @@ -0,0 +1,173 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import sys, os, re +from stat import * + +def get_mode(fn): + "get the mode of the file named fn, suitable for os.chmod() or open() calls" + mode = os.stat(fn)[ST_MODE] + cmode = S_IMODE(mode) + return cmode + +def replace_original_with_new_file(file,newfile): + "Replace file with newfile" + # os.system(" mv -f %s %s" % ( newfile, file)) + os.unlink(file) + os.rename(newfile,file) + +def remove_existing_header(contents): + "remove existing legal header, if any" + retval = [] + skipping = False + start_pattern = re.compile(r"^(/[*]BEGIN_LEGAL)|(#BEGIN_LEGAL)") + stop_pattern = re.compile(r"^[ ]*(END_LEGAL[ ]?[*]/)|(#[ ]*END_LEGAL)") + for line in contents: + if start_pattern.match(line): + skipping = True + if skipping == False: + retval.append(line) + if stop_pattern.match(line): + skipping = False + return retval + +def prepend_script_comment(header): + "Apply script comment marker to each line" + retval = [] + for line in header: + retval.append( "#" + line ) + return retval + +def apply_header_to_source_file(header, file): + "apply header to file using C++ comment style" + f = open(file,"r") + mode = get_mode(file) + contents = f.readlines() + f.close() + trimmed_contents = remove_existing_header(contents) + newfile = file + ".new" + o = open(newfile,"w") + o.write("/*BEGIN_LEGAL \n") + o.writelines(header) + o.write("END_LEGAL */\n") + o.writelines(trimmed_contents) + o.close() + os.chmod(newfile,mode) + replace_original_with_new_file(file,newfile) + +# FIXME: this will flag files that have multiline C-style comments +# with -*- in them even though the splitter will not look for the +# comment properly + +def shell_script(lines): + """return true if the lines are the start of shell script or + something that needs a mode comment at the top""" + + first = "" + second = "" + if len(lines) > 0: + first = lines[0]; + if len(lines) > 1: + second = lines[1]; + + if re.match("#!",first): + #print "\t\t First script test true" + return True + if re.search("-\*-",first) or re.search("-\*-",second): + #print "\t\t Second script test true" + return True + return False + +def split_script(lines): + "Return a tuple of (header, body) for shell scripts, based on an input line list" + header = [] + body = [] + + f = lines.pop(0) + while re.match("#",f) or re.search("-\*-",f): + header.append(f) + f = lines.pop(0) + + # tack on the first non matching line from the above loop + body.append(f); + body.extend(lines); + return (header,body) + +def write_script_header(o,lines): + "Write the file header for a script" + o.write("#BEGIN_LEGAL\n") + o.writelines(lines) + o.write("#END_LEGAL\n") + +def apply_header_to_data_file(header, file): + "apply header to file using script comment style" + f = open(file,"r") + mode = get_mode(file) + #print "file: " + file + " mode: " + "%o" % mode + contents = f.readlines() + f.close() + trimmed_contents = remove_existing_header(contents) + newfile = file + ".new" + o = open(newfile,"w") + augmented_header = prepend_script_comment(header) + if shell_script(trimmed_contents): + (script_header, script_body) = split_script(trimmed_contents) + o.writelines(script_header) + write_script_header(o, augmented_header) + o.writelines(script_body) + else: + write_script_header(o,augmented_header) + o.writelines(trimmed_contents) + o.close() + os.chmod(newfile,mode) + replace_original_with_new_file(file,newfile) + +#################################################################### +### MAIN +#################################################################### +if __name__ == '__main__': + if len(sys.argv) < 4: + print "Usage " + sys.argv[0] + " [-s|-t] legal-header file-name [file-name...]\n" + sys.exit(1) + + type = sys.argv[1] + header_file = sys.argv[2] + if not os.path.exists(header_file): + print "Could not find header file: [%s]\n" % (header_file) + sys.exit(1) + + files_to_tag = sys.argv[3:] + f = open(header_file,"r") + header = f.readlines() + f.close() + + sources = files_to_tag + + if type in [ '-c', "-s"]: + for file in sources: + if re.search(".svn",file) == None and re.search(".new$",file) == None: + apply_header_to_source_file(header, file.strip()) + elif type in ['-d', "-t"]: + for file in sources: + if re.search(".svn",file) == None and re.search(".new$",file) == None: + apply_header_to_data_file(header, file.strip()) + else: + print "2nd argument must be -s or -t\n" + sys.exit(1) diff --git a/scripts/elf_sizes.py b/scripts/elf_sizes.py new file mode 100755 index 0000000..97ce2a2 --- /dev/null +++ b/scripts/elf_sizes.py @@ -0,0 +1,172 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import subprocess +import find_dir +sys.path.append(find_dir.find_dir('mbuild')) +import mbuild + +def _warn(s): + sys.stderr.write("ERROR:" + s + "\n") +def _die(s): + _warn(s) + sys.exit(1) + +def _run_cmd(cmd, die_on_errors=True): + try: + sub = subprocess.Popen(cmd, + shell=True, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT) + lines = sub.stdout.readlines() + sub.wait() + return (sub.returncode, lines) + except OSError, e: + msg = "Execution failed for:" + str( cmd) + ".\nResult is " + str(e) + if die_on_errors: + _die(msg) + else: + return (1,[msg]) + + +def _run_readelf_sections(fn,die_on_errors): + cmd = 'readelf -S ' + fn + (retval, output) = _run_cmd(cmd, die_on_errors) + if retval: + for line in output: + line = line.strip() + _warn(line) + return None + return output + +def _find_key(line): + key = None + if line.find('.text') != -1: + key='text' + if line.find('.rodata') != -1: + key='rodata' + if line.find('.data') != -1: + key='data' + if line.find('.bss') != -1: + key='bss' + return key + +def _read32(fn,die_on_errors): + output = _run_readelf_sections(fn,die_on_errors) + if not output: + return None + key = None + data = {} + for line in output: + line = line.strip() + key = _find_key(line) + if key: + chunks = line.split() + # unexpected input happens + try: + x = int(chunks[5],16) + except: + x = 0 # just don't die for now + data[key] = x + return data + + +def _read64(fn,die_on_errors): + output = _run_readelf_sections(fn,die_on_errors) + if not output: + return None + # in 64b the size is on the next line after the key is located. + key = None + data = {} + for line in output: + line = line.strip() + if key: + chunks = line.split() + # unexpected input happens + try: + x = int(chunks[0],16) + except: + x = 0 # just don't die for now + data[key] = x + key = _find_key(line) + + return data + +def print_table(data): + python27 = mbuild.check_python_version(2,7) + fmt_str27 = "{0:10s} {1:10,d} Bytes {2:5.2f} MB {3:10.2f}%" + fmt_str = "%10s %10d Bytes %5.2f MB %10.2f%%" + keys = data.keys() + keys.sort() + + total = 0 + for k in keys: + total = total + data[k] + + for k in keys: + try: # avoid div/0 + pct = 100.0 * data[k] / total + except: + pct = 0 + mb = data[k]/1024.0/1024.0 + if python27: + print fmt_str27.format(k,data[k],mb,pct) + else: + print fmt_str % (k,data[k],mb,pct) + + mb = total/1024.0/1024.0 + if python27: + print fmt_str27.format('total', total, mb, 100) + else: + print fmt_str % ('total', total, mb, 100) + + +def _find_mode(fn,die_on_errors): + cmd = 'readelf -h ' + fn + (retval, header) = _run_cmd(cmd, die_on_errors) + mode = 0 + if retval == 0: + for line in header: + if 'Class:' in line: + if 'ELF32' in line: + mode=32 + break + elif 'ELF64' in line: + mode=64 + break + return mode + +def work(fn,die_on_errors=True): + mode = _find_mode(fn,die_on_errors) + if mode == 64: + return _read64(fn,die_on_errors) + elif mode == 32: + return _read32(fn,die_on_errors) + return None + +if __name__ == '__main__': + if len(sys.argv) != 2: + _die("Need one arg") + fn = sys.argv[1] + d = work(fn) + if d: + print_table(d) diff --git a/scripts/external_libs.py b/scripts/external_libs.py new file mode 100644 index 0000000..eeb94e2 --- /dev/null +++ b/scripts/external_libs.py @@ -0,0 +1,117 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import re +import os +import sys +import mbuild +import copy + +def _grab_ldd_libraries(lines): + files = [] + okay = True + for line in lines: + t=line.strip().split() + pieces = len(t) + if pieces == 0: + continue + if pieces == 2: + files.append(t[-2]) + elif pieces == 4: + if re.search('not found',line): + print "\n\nWARNING: SKIPPING MISSING LIBRARY: [%s]\n\n" % \ + (t[0]) + else: + files.append(t[-2]) + elif pieces == 3 and t[-2] == '=>': + # missing library + print "\n\nWARNING: SKIPPING MISSING LIBRARY: [%s]\n\n" % \ + (line.strip()) + else: + print "Unrecognized ldd line: [%s]" % line.strip() + okay = False + files = map(os.path.abspath,files) + return (okay, files) + +def _file_to_avoid(env,x): + avoid_libraries = [ 'ld-linux', 'linux-vdso'] + if 'copy_libc' in env: + if env['copy_libc']==False: + avoid_libraries.append('libc') + for av in avoid_libraries: + if re.search(av, x): + return True + return False + +def _add_to_ld_library_path(env,paths): + new_pth=':'.join(paths) + if 'LD_LIBRARY_PATH' in os.environ: + new_pth = new_pth + ":" + os.environ['LD_LIBRARY_PATH'] + mbuild.msgb("SET LD_LIBRARY_PATH", new_pth) + os.environ['LD_LIBRARY_PATH'] = new_pth + +def copy_system_libraries(env, kitdir, files, extra_ld_library_paths=[]): + """copy system libraries to kit on Linux systems. Return True on success.""" + + # Make a temporary environment for running ldd that includes any required + # LD_LIBRARY_PATH additions. + osenv = None + if extra_ld_library_paths: + osenv = copy.deepcopy(os.environ) + s = None + if 'LD_LIBRARY_PATH' in osenv: + s = osenv['LD_LIBRARY_PATH'] + osenv['LD_LIBRARY_PATH'] = ":".join(extra_ld_library_paths) + if s: + osenv['LD_LIBRARY_PATH'] += ":" + s + + okay = True + if env.on_linux() or env.on_freebsd(): + system_libraries = set() + for binary_executable in files: + if os.path.exists(binary_executable): + (retval, lines, stderr) = mbuild.run_command( + "ldd {}".format( binary_executable), + osenv=osenv) + for line in lines: + line = line.rstrip() + print "\t%s"%(line) + if retval != 0: # error handling + if len(lines) >= 1: + if lines[0].find("not a dynamic executable") != -1: + continue + elif lines[0].find("not a dynamic ELF executable") != -1: + continue + mbuild.warn("Could not run ldd on [%s]" % binary_executable) + return False + if env.on_freebsd(): + lines = lines[1:] + ldd_okay, files = _grab_ldd_libraries(lines) + if not ldd_okay: + okay = False + for lib in files: + if not _file_to_avoid(env,lib): + system_libraries.add(lib) + + for slib in system_libraries: + mbuild.msgb("TO COPY", slib) + for slib in system_libraries: + mbuild.copy_file(src=slib, tgt=kitdir) + return okay diff --git a/scripts/find_dir.py b/scripts/find_dir.py new file mode 100755 index 0000000..8ad6e19 --- /dev/null +++ b/scripts/find_dir.py @@ -0,0 +1,38 @@ +#! /usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys + +def find_dir(d,required=True): + idir = os.getcwd() + last_idir = '' + while idir != last_idir: + mfile = os.path.join(idir,d) + if os.path.exists(mfile): + break + last_idir = idir + idir = os.path.dirname(idir) + if not os.path.exists(mfile): + if required: + print "Could not find %s file, looking upwards"% (mfile) + sys.exit(1) + return None + return mfile diff --git a/scripts/perftest.py b/scripts/perftest.py new file mode 100755 index 0000000..af87c41 --- /dev/null +++ b/scripts/perftest.py @@ -0,0 +1,148 @@ +#!/usr/bin/env python +#-*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +import os +import sys +import argparse +import textwrap +import find_dir +import math + +sys.path.append(find_dir.find_dir('mbuild')) +import mbuild + +def graph_it(lst): + import numpy as np + import matplotlib.pyplot as plt + + plt.plot(lst) + plt.show() + +def variance(cpd): + cpd_avg = sum(cpd)/len(cpd) + s = 0.0 + for x in cpd: + d = (x-cpd_avg) + s += d*d + return s/(len(cpd)-1) +def standard_deviation(cpd): + return math.sqrt(variance(cpd)) + + +def work(args): + print "Testing performance..." + + if not os.path.exists(args.input): + mbuild.warn("Performance test input binary not found: {}".format(args.input)) + return 2 + if not os.path.exists(args.xed): + mbuild.warn("Performance test executable binary not found: {}".format(args.xed)) + return 2 + + s = args.xed + ' -v 0 -i ' + args.input + cpd = [] + + print "Skipping {} samples...".format(args.skip) + for sample in range(0,args.skip): + (status, stdout, stderr) = mbuild.run_command(s) + + print "Running {} tests...".format(args.samples) + for sample in range(0,args.samples): + (status, stdout, stderr) = mbuild.run_command(s) + found=False + if status == 0 and stdout: + for line in stdout: + if '#Total cycles/instruction DECODE' in line: + chunks = line.strip().split() + cpd_one = float(chunks[-1]) + found = True + if status and stdout: + print "Error messages from sample {0:d}:".format(sample) + for line in stdout: + print " ",line, + if found: + cpd.append(cpd_one) + + if len(cpd) == args.samples: + + expected = 450.0 # cycles / decode + + cpd_min = min(cpd) + cpd_max = max(cpd) + cpd_avg = sum(cpd)/len(cpd) + print textwrap.fill("Samples: " + + ", ".join(map(lambda x: "{0:6.2f}".format(x),cpd)), + subsequent_indent = " ") + + print "Minimum: {0:6.2f}".format(cpd_min) + print "Average: {0:6.2f}".format(cpd_avg) + print "Maximum: {0:6.2f}".format(cpd_max) + print "Range : {0:6.2f}".format(cpd_max-cpd_min) + print "Stddev : {0:6.2f}".format(standard_deviation(cpd)) + + + if cpd_avg > expected: + s = ["PERFORMANCE DEGREDATION: "] + s.append("Observed {0:.2f} vs Expected {1:.2f}".format( + cpd_avg, expected)) + print "".join(s) + return 1 # error + print "Success. Average less than {0:.2f}".format(expected) + + if args.graph: + graph_it(cpd) + return 0 # success + print "MISSING SAMPLES" + return 2 + +def setup(defaults): + parser = argparse.ArgumentParser(description='XED Performance testing.') + parser.add_argument("--xed", help='input XED executable', + default=defaults.xed) + parser.add_argument("--input", help='input test file name', + default=defaults.input) + parser.add_argument("--graph", help='graph the samples', + action="store_true", + default=defaults.graph) + parser.add_argument("--samples", help='number of samples', + type=int, default=defaults.samples) + parser.add_argument("--skip", help='number of samples to skip', + type=int, default=defaults.skip) + args = parser.parse_args() + return args + +class args_t: + pass + +def mkargs(): + args = args_t() + args.xed = 'obj/examples/xed' + args.input = '/usr/bin/emacs24-x' + args.graph = False + args.samples=10 + args.skip=12 + return args + +if __name__ == "__main__": + defaults = mkargs() + args = setup(defaults) + r = work(args) + sys.exit(r) + diff --git a/src/xed-agen.c b/src/xed-agen.c new file mode 100644 index 0000000..6399050 --- /dev/null +++ b/src/xed-agen.c @@ -0,0 +1,149 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-agen.c +#include "xed-agen.h" +#include "xed-decoded-inst-api.h" + +static xed_register_callback_fn_t register_callback = 0; +static xed_segment_base_callback_fn_t segment_callback = 0; + +void xed_agen_register_callback(xed_register_callback_fn_t register_fn, + xed_segment_base_callback_fn_t segment_fn) { + register_callback = register_fn; + segment_callback = segment_fn; +} + +xed_error_enum_t xed_agen(xed_decoded_inst_t* xedd, + unsigned int memop_index, + void* context, + xed_uint64_t* out_address) { + xed_uint64_t out = 0; + // Normal memops: BASE+INDEX*SCALE+DISPLACMENT + xed_uint64_t base_value = 0; + xed_uint64_t index_value = 0; + xed_uint64_t segment_base = 0; + xed_uint64_t scale = 0; + xed_int64_t displacement = 0; + xed_operand_values_t* xedv = 0; + xed_uint32_t addr_width = 0; + xed_uint32_t opnd_width = 0; + xed_bool_t real_mode = 0; + xed_bool_t error=0; + xed_reg_enum_t base_reg = XED_REG_INVALID; + xed_reg_enum_t seg_reg = XED_REG_INVALID; + xed_attribute_enum_t attr; + + if (xedd == 0) + return XED_ERROR_GENERAL_ERROR; + if (memop_index != 0 && memop_index != 1) + return XED_ERROR_BAD_MEMOP_INDEX; + if (register_callback == 0) + return XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED; + if (segment_callback == 0) + return XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED; + + + xedv = xed_decoded_inst_operands(xedd); + + addr_width = xed_operand_values_get_effective_address_width(xedv); + + //16,32,64 + opnd_width = xed_operand_values_get_effective_operand_width(xedv); + real_mode = xed_operand_values_get_real_mode(xedv); + + base_reg = xed_decoded_inst_get_base_reg(xedd,memop_index); + if (base_reg != XED_REG_INVALID) + base_value = (*register_callback)(base_reg, context, &error); + if (error) + return XED_ERROR_CALLBACK_PROBLEM; + + if (memop_index == 1) + attr = XED_ATTRIBUTE_STACKPUSH1; + else + attr = XED_ATTRIBUTE_STACKPUSH0; + if (xed_decoded_inst_get_attribute(xedd,attr)) { + base_value = base_value - (opnd_width>>3); + } + + seg_reg = xed_decoded_inst_get_seg_reg(xedd,memop_index); + if (seg_reg != XED_REG_INVALID) { + if (real_mode) { + // selectors are values in real mode + segment_base = (*register_callback)(seg_reg, context, &error); + segment_base <<= 4; + } + else { + segment_base = (*segment_callback)(seg_reg, context, &error); + } + if (error) + return XED_ERROR_CALLBACK_PROBLEM; + } + + if (memop_index == 0) { + xed_reg_enum_t index_reg; + index_reg = xed_decoded_inst_get_index_reg(xedd,memop_index); + if (index_reg != XED_REG_INVALID) { + index_value = (*register_callback)(index_reg, context, &error); + if (error) + return XED_ERROR_CALLBACK_PROBLEM; + + scale = xed_decoded_inst_get_scale(xedd,0); + } + displacement = xed_decoded_inst_get_memory_displacement(xedd,0); + } + + if (addr_width == 64) { + xed_int64_t base64 = base_value; + xed_int64_t index64 = index_value; + xed_int64_t disp64 = displacement; + xed_int64_t ea64 = base64 + index64 * scale + disp64; + xed_int64_t lin64 = segment_base + ea64; + out = lin64; + } + else if (addr_width == 32) { + xed_int32_t base32 = base_value; + xed_int32_t index32 = index_value; + xed_int32_t disp32 = displacement; + xed_int32_t ea32 = base32 + index32 * scale + disp32; + xed_int32_t lin32 = segment_base + ea32; + out = lin32; + // FIXME: big real mode! + } + else if (addr_width == 16) { + xed_int16_t base16 = base_value; + xed_int16_t index16 = index_value; + xed_int16_t disp16 = displacement; + xed_int16_t ea16 = base16 + index16 * scale + disp16; + xed_int32_t lin32 = segment_base + ea16; + if (real_mode) { + xed_uint32_t masked20 = lin32 & 0x000FFFFF; + out = masked20; + } + else + out = lin32; + } + + // RIP-rel 32b -- 67 prefixed rip-rel stuff in 64b mode. FIXME + + if (out_address) + *out_address = out; + else + return XED_ERROR_NO_OUTPUT_POINTER; + return XED_ERROR_NONE; +} + diff --git a/src/xed-chip-features.c b/src/xed-chip-features.c new file mode 100644 index 0000000..66b5a5f --- /dev/null +++ b/src/xed-chip-features.c @@ -0,0 +1,82 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-internal-header.h" +#include "xed-chip-features.h" +#include "xed-chip-features-private.h" // for xed_test_chip_features() +#include "xed-chip-features-table.h" +void +xed_get_chip_features(xed_chip_features_t* p, xed_chip_enum_t chip) +{ + if (p) + { + if (chip < XED_CHIP_LAST) + { + p->f[0] = xed_chip_features[chip][0]; + p->f[1] = xed_chip_features[chip][1]; + p->f[2] = xed_chip_features[chip][2]; + p->f[3] = xed_chip_features[chip][3]; + } + else + { + p->f[0] = 0; + p->f[1] = 0; + p->f[2] = 0; + p->f[3] = 0; + } + } +} + + +static XED_INLINE void +set_bit(xed_uint64_t* p, + xed_uint64_t bitnum, + xed_bool_t value) +{ + const xed_uint64_t one = 1; + // turn off the existing bit in *p + const xed_uint64_t q = *p & ~(one<f+n, f-(64*n), present); + } +} + +xed_bool_t +xed_test_chip_features(xed_chip_features_t* p, + xed_isa_set_enum_t isa_set) +{ + const xed_uint64_t one = 1; + const unsigned int n = XED_CAST(unsigned int,isa_set) / 64; + const unsigned int r = XED_CAST(unsigned int,isa_set) - (64*n); + if (p->f[n] & (one< XED_ISA_SET_INVALID && + isaset < XED_ISA_SET_LAST && + i < XED_MAX_CPUID_BITS_PER_ISA_SET) + { + return xed_isa_set_to_cpuid_mapping[isaset][i]; + } + return XED_CPUID_BIT_INVALID; +} + +xed_int_t xed_get_cpuid_rec(xed_cpuid_bit_enum_t cpuid_bit, xed_cpuid_rec_t* cpuid_rec) +{ + if (cpuid_bit > XED_CPUID_BIT_INVALID && + cpuid_bit < XED_CPUID_BIT_LAST) + { + xed_assert(cpuid_rec!=0); + *cpuid_rec = xed_cpuid_info[cpuid_bit]; + return 1; + } + return 0; +} + diff --git a/src/xed-decode.c b/src/xed-decode.c new file mode 100644 index 0000000..5869f4a --- /dev/null +++ b/src/xed-decode.c @@ -0,0 +1,414 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decode.c + +//////////////////////////////////////////////////////////////////////////// +// This file contains the public interface to the decoder. Related code for +// decoded instructions is in xed-decoded-inst.cpp and xed-decode-impl.cpp +//////////////////////////////////////////////////////////////////////////// +#include "xed-decode.h" // external interface to decoder +#include "xed-error-enum.h" +#include "xed-decoded-inst.h" +#include "xed-operand-storage.h" +#include "xed-tables-extern.h" +#include "xed-internal-header.h" +#include "xed-isa-set.h" +#include "xed-ild-private.h" +#include "xed3-static-decode.h" +#include "xed3-dynamic-decode.h" +#include "xed3-dynamic-part1-capture.h" //FIXME fix filename +#include "xed-chip-features.h" +#include "xed-chip-features-private.h" // for xed_test_chip_features() +#include "xed-chip-modes.h" + +////////////////////////////////////////////////////////////////////////////// + +#if defined(XED_ILD_CHECK) +#include "xed-ild.h" +#include +#include +#include + +#define XED_ILD_CMP_BUFLEN 1024 +#define XED_ILD_CHECK_MAX_ERR 1 + +static void xedex_derror(const char* s) { + //we want to assert after XED_ILD_CHECK_MAX_ERR divergences + static unsigned int err_count = 0; + printf("\n[XED_ILD_CHECK_ERROR] %s\n",s); + err_count++; + if (err_count == XED_ILD_CHECK_MAX_ERR) { + exit(1); + } +} + +static void xed_print_hex_line(char* buf, const xed_uint8_t* array, + const int length, const int buflen) { + const xed_bool_t uppercase=0; + int n = length; + int i=0; + if (length == 0) + n = XED_MAX_INSTRUCTION_BYTES; + assert(buflen >= (2*n+1)); /* including null */ + for( i=0 ; i< n; i++) { + buf[2*i+0] = xed_to_ascii_hex_nibble(array[i]>>4, uppercase); + buf[2*i+1] = xed_to_ascii_hex_nibble(array[i]&0xF, uppercase); + } + buf[2*i]=0; +} + +static void print_hex_line(const xed_uint8_t* p, unsigned int length) { + char buf[XED_ILD_CMP_BUFLEN]; + unsigned int lim = XED_ILD_CMP_BUFLEN/2; + if (length < lim) + lim = length; + xed_print_hex_line(buf,p, lim, XED_ILD_CMP_BUFLEN); + printf("%s\n", buf); +} + +static void xed_ild_inst_dump(const xed_decoded_inst_t* p, char* buf, int buflen) { + char* t=buf; + int blen = buflen; + blen = xed_strncpy(t, "ILD INST:\n", blen); + t = buf + xed_strlen(buf); + xed_operand_values_print_short( xed_decoded_inst_operands_const(p), t, blen); +} + +static void xed_ild_error(const xed_decoded_inst_t* xedd, + const xed_decoded_inst_t* ild) { + char buf[XED_ILD_CMP_BUFLEN] = {0}; + xed_uint_t xed2_length = xed_decoded_inst_get_length(xedd); + xed_decoded_inst_dump(xedd, buf, XED_ILD_CMP_BUFLEN); + printf("xedd:\n%s\n", buf); + print_hex_line(xedd->_byte_array._dec, xed2_length); + xed_ild_inst_dump(ild, buf, XED_ILD_CMP_BUFLEN); + printf("ild:\n%s\n", buf); + print_hex_line(ild->_byte_array._dec, xed2_length); + xedex_derror("ILD CMP FAILURE"); +} + +static void xed_ild_cmp_member(xed_uint_t xed2_res, xed_uint_t ild_res, + const char* format_str, const xed_decoded_inst_t* xedd, + const xed_decoded_inst_t* ild) { + if (ild_res != xed2_res) { + printf(format_str, xed2_res, ild_res); + xed_ild_error(xedd, ild); + } +} + +static void xed_ild_cmp(const xed_decoded_inst_t* xedd, + const xed_decoded_inst_t* ild) { + xed_uint_t ild_res = 0; + xed_uint_t xed2_res = 0; + + /*FIXME: automate it somehow?*/ + + /* check all relevant information */ + ild_res = xed_decoded_inst_get_length(ild); + xed2_res = xed_decoded_inst_get_length(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "ILD length differs! xed2_length=%d ild_length=%d\n", xedd, ild); + + + ild_res = xed3_operand_get_asz(ild); + xed2_res = xed3_operand_get_asz(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "ASZ differs! xed2_asz=%d ild_asz=%d\n", xedd, ild); + + + ild_res = xed3_operand_get_prefix66(ild); + xed2_res = xed3_operand_get_prefix66(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "PREFIX66 differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + ild_res = xed3_operand_get_rep(ild); + xed2_res = xed3_operand_get_rep(xedd); + if ((ild_res == 1 && xed2_res != 2) || + (ild_res == 0 && xed2_res == 2)) { + printf("F2 differs! xed2_rep=%d ild_rep=%d\n", + xed2_res, ild_res); + xed_ild_error(xedd, ild); + } + + ild_res = xed3_operand_get_lock(ild); + xed2_res = xed3_operand_get_lock(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "LOCK differs! xed2_lock=%d ild_lock=%d\n", xedd, ild); + + ild_res = xed3_operand_get_seg_ovd(ild); + xed2_res = xed3_operand_get_seg_ovd(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "SEG_OVD differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + /* HINT is reassigned sometimes, so we cannot compare it after + * ILD + */ + /* + ild_res = xed3_operand_get_hint(ild); + xed2_res = xed3_operand_get_hint(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "HINT differs! xed2_res=%d ild_res=%d\n", xedd, ild); + */ + + if (xed3_operand_get_modrm(xedd)) { + ild_res = xed3_operand_get_mod(ild); + xed2_res = xed3_operand_get_mod(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "MOD differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + ild_res = xed3_operand_get_reg(ild); + xed2_res = xed3_operand_get_reg(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "REG differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + ild_res = xed_ild_get_rm(ild); + xed2_res = xed3_operand_get_rm(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "RM differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + } + + ild_res = xed3_operand_get_sibscale(ild); + xed2_res = xed3_operand_get_sibscale(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "SIBSCALE differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + ild_res = xed3_operand_get_sibindex(ild); + xed2_res = xed3_operand_get_sibindex(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "SIBINDEX differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + ild_res = xed3_operand_get_sibbase(ild); + xed2_res = xed3_operand_get_sibbase(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "SIBBASE differs! xed2_res=%d ild_res=%d\n", xedd, ild); + + /*FIXME: VEX operands ? */ + + /* displacement width in xed2 has some problems ... + ild_res = ild->disp_bytes; + xed2_res = xed_decoded_inst_get_memory_displacement_width(xedd,0) + + xed_decoded_inst_get_branch_displacement_width(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "disp_bytes differs! xed2_disp_bytes=%d ild_disp_bytes=%d\n", + xedd, ild); + */ + + /* immediate is tricky since there is implicit IMM0 operand + ild_res = ild->imm_bytes + ild->imm1_bytes; + xed2_res = xed_decoded_inst_get_immediate_width(xedd); + xed_ild_cmp_member(xed2_res, ild_res, + "imm_bytes differs! xed2_imm_bytes=%d ild_imm_bytes=%d\n", xedd, ild); + */ +} + + +static void xed3_static_decode_cmp(const xed_decoded_inst_t* xedd, + xed_decoded_inst_t* ild) { + + if (ild->_inst != xedd->_inst) { + xed_uint32_t xed2_idx = + (xed_uint32_t)(xedd->_inst - &xed_inst_table[0]); + xed_uint32_t xed3_idx = + (xed_uint32_t)(ild->_inst - &xed_inst_table[0]); + printf("_inst differs! xed2_idx=%d xed3_idx=%d\n", + xed2_idx, xed3_idx); + xed_ild_error(xedd, ild); + } +} + + +static void check_ild(const xed_decoded_inst_t* xedd, + const xed_uint8_t* itext) { +#if defined(XED_ILD_CHECK_VERBOSE) + static unsigned int inst_count = 0; +#endif + + xed_decoded_inst_t ild_data; + + xed_decoded_inst_zero(&ild_data); + + xed3_operand_set_mode(&ild_data, xed3_operand_get_mode(xedd)); + + xed_ild_decode(&ild_data, itext, XED_MAX_INSTRUCTION_BYTES); + xed_ild_cmp(xedd, &ild_data); + + xed3_dynamic_decode_part1(&ild_data); + xed3_static_decode(&ild_data); + xed3_static_decode_cmp(xedd, &ild_data); + xed3_dynamic_decode_part2(&ild_data); + xed3_decode_operands(&ild_data); + + +#if defined(XED_ILD_CHECK_VERBOSE) + inst_count++; + printf("[XED_ILD_CHECK_LOG] #instructions = %d\n", inst_count); +#endif +} + +#endif // XED_ILD_CHECK + +////////////////////////////////////////////////////////////////////////////// + + + +#if defined(XED_AVX) +static void check_avx2_gathers(xed_decoded_inst_t* xds) { + // the 3 regs (dest, mask and index) cannot be the same. + if (xed3_operand_get_index(xds) == xed3_operand_get_reg1(xds) || + xed3_operand_get_index(xds) == xed3_operand_get_reg0(xds) || + xed3_operand_get_reg0(xds) == xed3_operand_get_reg1(xds) ) + { + xed3_operand_set_error(xds,XED_ERROR_GATHER_REGS); + } +} +# if defined(XED_SUPPORTS_AVX512) +static void check_avx512_gathers(xed_decoded_inst_t* xds) { + // index cannot be same as dest on avx512 gathers + if ( xed3_operand_get_index(xds) == xed3_operand_get_reg0(xds)) + xed3_operand_set_error(xds,XED_ERROR_GATHER_REGS); + +} +#endif +#endif + +static XED_INLINE void +xed_decode_finalize_operand_storage_fields(xed_decoded_inst_t* xds) +{ + // if something is found to be in-error, you must set xed3_operand_get_error(xds)! + + if (xed3_operand_get_lock(xds) && !xed_decoded_inst_get_attribute(xds,XED_ATTRIBUTE_LOCKED)) { + // operation cannot take a LOCK prefix, but one was found. + xed3_operand_set_error(xds,XED_ERROR_BAD_LOCK_PREFIX); + return; + } + + /* We only keep real reps, MPX reps, HLE reps. Refining reps can just + mess up subsequent encodes if the iclass or operands get changed by + the user. */ + +#if 0 // FIXME: DO NOT COMMIT + if (xed3_operand_get_rep(xds) && + !xed_decoded_inst_get_attribute(xds,XED_ATTRIBUTE_REP)) + { + if (!xed_decoded_inst_has_mpx_prefix(xds) && + !xed_decoded_inst_is_xrelease(xds) && + !xed_decoded_inst_is_xacquire(xds) ) + { + xed3_operand_set_rep(xds,0); // clear refining REP + } + } +#endif + +#if defined(XED_AVX) + if (xed_decoded_inst_get_attribute(xds, XED_ATTRIBUTE_GATHER)) + { + if (xed_decoded_inst_get_extension(xds) == XED_EXTENSION_AVX2GATHER) + check_avx2_gathers(xds); +# if defined(XED_SUPPORTS_AVX512) + else if (xed_decoded_inst_get_attribute(xds, XED_ATTRIBUTE_MASKOP_EVEX)) + check_avx512_gathers(xds); +# endif // XED_SUPPORTS_AVX512 + } +#endif // XED_AVX + +#if defined(XED_MPX) + // BNDLDX/BNDSTX disallow RIP-relative operation in 64b mode. + // + // FIXME: Expressing this in the grammar causes the NOP hashtable to be + // too big. + if (xed_decoded_inst_get_attribute(xds, XED_ATTRIBUTE_NO_RIP_REL)) + if (xed3_operand_get_rm(xds) == 5 && xed3_operand_get_mod(xds) == 0) + if (xed3_operand_get_mode(xds)==2) // 64b mode + xed3_operand_set_error(xds,XED_ERROR_GENERAL_ERROR); +#endif +} + + + + +xed_error_enum_t +xed_decode_with_features(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes, + xed_chip_features_t* features) +{ + xed_error_enum_t error; + xed_chip_enum_t chip = xed_decoded_inst_get_input_chip(xedd); + + set_chip_modes(xedd, chip, features); + xedd->_byte_array._dec = itext; + + /* max_bytes says ILD how many bytes it can read */ + xed3_operand_set_max_bytes(xedd, bytes); + + /* Do the instruction length decode*/ + xed_instruction_length_decode(xedd); + + /* check ILD-specific decoding errors */ + if (xed3_operand_get_error(xedd)) + return xed3_operand_get_error(xedd); + + /* part1 is all the Nts that come before the INSTRUCTIONS NT (OSZ, ASZ + * nonterminals)*/ + xed3_dynamic_decode_part1(xedd); + if (xed3_operand_get_error(xedd)) + return xed3_operand_get_error(xedd); + + /* lookup the xed_inst_t */ + xed3_static_decode(xedd); + + if (xed_decoded_inst_get_iform_enum(xedd) == XED_IFORM_INVALID) + return XED_ERROR_GENERAL_ERROR; + + /* capture all the Nts that come in patterns */ + xed3_dynamic_decode_part2(xedd); + if (xed3_operand_get_error(xedd)) + return xed3_operand_get_error(xedd); + + /* capture the operands */ + xed3_decode_operands(xedd); + if (xed3_operand_get_error(xedd)) + return xed3_operand_get_error(xedd); + + xed_decode_finalize_operand_storage_fields(xedd); + + error = xed3_operand_get_error(xedd); + if (error == XED_ERROR_NONE) { + if (chip != XED_CHIP_INVALID) { + if (!xed_decoded_inst_valid_for_chip(xedd, chip)) { + return XED_ERROR_INVALID_FOR_CHIP; + } + } + if (features) { + const xed_isa_set_enum_t isa_set = xed_decoded_inst_get_isa_set(xedd); + if (!xed_test_chip_features(features, isa_set)) { + return XED_ERROR_INVALID_FOR_CHIP; + } + } + } + return error; +} + +xed_error_enum_t +xed_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes) +{ + return xed_decode_with_features(xedd, itext, bytes, 0); +} diff --git a/src/xed-decoded-init.c b/src/xed-decoded-init.c new file mode 100644 index 0000000..77923c7 --- /dev/null +++ b/src/xed-decoded-init.c @@ -0,0 +1,54 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-internal-header.h" +#include "xed-decoded-inst.h" +#include "xed-operand-values-interface.h" +#include // memset + +/* INITIALIZATION */ + +XED_DLL_EXPORT void +xed_decoded_inst_zero_set_mode(xed_decoded_inst_t* p, + const xed_state_t* dstate) +{ + memset(p, 0, sizeof(xed_decoded_inst_t)); + xed_operand_values_set_mode(p,dstate); +} + +XED_DLL_EXPORT void +xed_decoded_inst_zero(xed_decoded_inst_t* p) { + memset(p, 0, sizeof(xed_decoded_inst_t)); +} + +XED_DLL_EXPORT void +xed_decoded_inst_zero_keep_mode_from_operands( + xed_decoded_inst_t* p, + const xed_operand_values_t* operands) +{ + xed_operand_values_init_keep_mode(p, operands); + p->_decoded_length = 0; + p->_inst = 0; +} + +XED_DLL_EXPORT void +xed_decoded_inst_zero_keep_mode(xed_decoded_inst_t* p) { + xed_decoded_inst_zero_keep_mode_from_operands(p, p); +} + + diff --git a/src/xed-decoded-inst.c b/src/xed-decoded-inst.c new file mode 100644 index 0000000..ea77647 --- /dev/null +++ b/src/xed-decoded-inst.c @@ -0,0 +1,951 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-internal-header.h" +#include "xed-decoded-inst.h" +#include "xed-decoded-inst-api.h" +#include "xed-decoded-inst-private.h" +#include "xed-util.h" +#include "xed-operand-values-interface.h" +#include "xed-reg-class.h" +#include "xed-isa-set.h" +#include "xed-ild.h" + +xed_reg_enum_t xed_decoded_inst_get_reg(const xed_decoded_inst_t* p, + xed_operand_enum_t reg_operand) { + + switch(reg_operand) { + case XED_OPERAND_REG0: return xed3_operand_get_reg0(p); + case XED_OPERAND_REG1: return xed3_operand_get_reg1(p); + case XED_OPERAND_REG2: return xed3_operand_get_reg2(p); + case XED_OPERAND_REG3: return xed3_operand_get_reg3(p); + case XED_OPERAND_REG4: return xed3_operand_get_reg4(p); + case XED_OPERAND_REG5: return xed3_operand_get_reg5(p); + case XED_OPERAND_REG6: return xed3_operand_get_reg6(p); + case XED_OPERAND_REG7: return xed3_operand_get_reg7(p); + case XED_OPERAND_REG8: return xed3_operand_get_reg8(p); + case XED_OPERAND_BASE0: return xed3_operand_get_base0(p); + case XED_OPERAND_BASE1: return xed3_operand_get_base1(p); + case XED_OPERAND_SEG0: return xed3_operand_get_seg0(p); + case XED_OPERAND_SEG1: return xed3_operand_get_seg1(p); + case XED_OPERAND_INDEX: return xed3_operand_get_index(p); + default: + return XED_REG_INVALID; + } + +} + + +xed_uint32_t +xed_decoded_inst_get_attribute(const xed_decoded_inst_t* p, + xed_attribute_enum_t attr) +{ + xed_assert(p->_inst != 0); + return xed_inst_get_attribute(p->_inst, attr); +} + +xed_attributes_t +xed_decoded_inst_get_attributes(const xed_decoded_inst_t* p) +{ + xed_assert(p->_inst != 0); + return xed_inst_get_attributes(p->_inst); +} + +/* xrelease is valid when we have: + 1: F3 (REP) prefix AND + 2: (a) xchg inst. OR + (b) lock prefix OR + (c) mov mem,reg or mov mem,imm where reg is a normal register. + + ** cmpxchg16b inst. is special and can not have xacquire +*/ +xed_uint32_t +xed_decoded_inst_is_xrelease(const xed_decoded_inst_t* p){ + xed_iclass_enum_t iclass; + const xed_operand_values_t* ov; + xed_uint32_t rel_able = + xed_decoded_inst_get_attribute(p,XED_ATTRIBUTE_HLE_REL_ABLE); + + if (rel_able){ + ov = xed_decoded_inst_operands_const(p); + if (xed_operand_values_has_rep_prefix(ov)){ + iclass = xed_decoded_inst_get_iclass(p); + if (xed_operand_values_get_atomic(ov) || iclass == XED_ICLASS_MOV){ + //mov instruction do not need the lock prefix + return 1; + } + } + } + return 0; +} + +/* xacquire is valid when we have: + 1: F2 (REPNE) prefix + 2: xchg inst. OR lock prefix + ** cmpxchg16b inst. is special and can not have xacquire +*/ +xed_uint32_t +xed_decoded_inst_is_xacquire(const xed_decoded_inst_t* p){ + const xed_operand_values_t* ov; + xed_uint32_t acq_able = + xed_decoded_inst_get_attribute(p,XED_ATTRIBUTE_HLE_ACQ_ABLE); + + if (acq_able){ + ov = xed_decoded_inst_operands_const(p); + if (xed_operand_values_has_repne_prefix(ov)){ + return xed_operand_values_get_atomic(ov); + } + } + return 0; +} + +xed_uint32_t +xed_decoded_inst_has_mpx_prefix(const xed_decoded_inst_t* p){ + const xed_operand_values_t* ov; + xed_uint32_t mpx_able = xed_decoded_inst_get_attribute(p, + XED_ATTRIBUTE_MPX_PREFIX_ABLE); + if (mpx_able){ + ov = xed_decoded_inst_operands_const(p); + if (xed_operand_values_has_repne_prefix(ov)){ + return 1; + } + } + return 0; +} + +xed_uint8_t +xed_decoded_inst_get_modrm(const xed_decoded_inst_t* p) +{ + return xed3_operand_get_modrm_byte(p); +} + +///////////////////////////////////////////////////////////////////////// +xed_int32_t +xed_decoded_inst_get_branch_displacement(const xed_decoded_inst_t* p) { + return xed_operand_values_get_branch_displacement_int32(p); +} +xed_uint_t +xed_decoded_inst_get_branch_displacement_width(const xed_decoded_inst_t* p) { + return xed3_operand_get_brdisp_width(p)/8; +} +xed_uint_t +xed_decoded_inst_get_branch_displacement_width_bits(const xed_decoded_inst_t* p) { + return xed3_operand_get_brdisp_width(p); +} +///////////////////////////////////////////////////////////////////////// + + +xed_uint64_t +xed_decoded_inst_get_unsigned_immediate(const xed_decoded_inst_t* p) { + return xed_operand_values_get_immediate_uint64(p); +} +xed_int32_t +xed_decoded_inst_get_signed_immediate(const xed_decoded_inst_t* p) { + xed_int64_t y = xed_operand_values_get_immediate_int64(p); + return XED_STATIC_CAST(xed_int32_t,y); +} +xed_uint_t +xed_decoded_inst_get_immediate_width(const xed_decoded_inst_t* p) { + return xed3_operand_get_imm_width(p)/8; +} +xed_uint_t +xed_decoded_inst_get_immediate_width_bits(const xed_decoded_inst_t* p) { + return xed3_operand_get_imm_width(p); +} + +xed_uint_t +xed_decoded_inst_get_immediate_is_signed(const xed_decoded_inst_t* p) { + //return xed_operand_values_get_immediate_is_signed(p); + return xed3_operand_get_imm0signed(p); +} + + +///////////////////////////////////////////////////////////////////////// + +xed_int64_t +xed_decoded_inst_get_memory_displacement(const xed_decoded_inst_t* p, + unsigned int mem_idx) +{ + if (xed_operand_values_has_memory_displacement(p)) + { + switch(mem_idx) + { + case 0: + return xed_operand_values_get_memory_displacement_int64(p); + + case 1: + return 0; + + default: + xed_assert(mem_idx == 0 || mem_idx == 1); + } + } + return 0; +} +xed_uint_t +xed_decoded_inst_get_memory_displacement_width(const xed_decoded_inst_t* p, + unsigned int mem_idx) +{ + return xed_decoded_inst_get_memory_displacement_width_bits(p,mem_idx)/8; +} +xed_uint_t +xed_decoded_inst_get_memory_displacement_width_bits( + const xed_decoded_inst_t* p, + unsigned int mem_idx) +{ + + if (xed_operand_values_has_memory_displacement(p)) + { + switch(mem_idx) { + case 0: + return xed_operand_values_get_memory_displacement_length_bits(p); + case 1: + return 0; + + default: + xed_assert(mem_idx == 0 || mem_idx == 1); + } + } + return 0; +} + +xed_reg_enum_t xed_decoded_inst_get_seg_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx) { + switch(mem_idx) { + case 0: return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_seg0(p)); + case 1: return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_seg1(p)); + default: xed_assert(mem_idx == 0 || mem_idx == 1); + } + return XED_REG_INVALID; +} +xed_reg_enum_t xed_decoded_inst_get_base_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx) { + switch(mem_idx) { + case 0: return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_base0(p)); + case 1: return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_base1(p)); + default: xed_assert(mem_idx == 0 || mem_idx == 1); + } + return XED_REG_INVALID; +} +xed_reg_enum_t xed_decoded_inst_get_index_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx) { + switch(mem_idx) { + case 0: return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_index(p)); + case 1: return XED_REG_INVALID; + default: xed_assert(mem_idx == 0 || mem_idx == 1); + } + return XED_REG_INVALID; +} +xed_uint_t xed_decoded_inst_get_scale(const xed_decoded_inst_t* p, + unsigned int mem_idx) { + switch(mem_idx) { + case 0: return xed3_operand_get_scale(p); + case 1: return 1; + default: xed_assert(mem_idx == 0 || mem_idx == 1); + } + return XED_REG_INVALID; +} + +xed_bool_t xed_decoded_inst_mem_read(const xed_decoded_inst_t* p, + unsigned int mem_idx) { + const xed_inst_t* inst = p->_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const xed_uint32_t i = xed_decoded_inst_get_find_memop(p,memop_idx); + const xed_operand_t* o = xed_inst_operand(inst,i); + const xed_operand_width_enum_t width = xed_operand_width(o); + xed_uint32_t bits; + + if ( width == XED_OPERAND_WIDTH_SSZ || + width == XED_OPERAND_WIDTH_SPW || + width == XED_OPERAND_WIDTH_SPW2 || + width == XED_OPERAND_WIDTH_SPW3 || + width == XED_OPERAND_WIDTH_SPW8 ) { + bits=xed_operand_values_get_stack_address_width( + xed_decoded_inst_operands_const(p)); + } + else { + bits=xed_operand_values_get_effective_address_width( + xed_decoded_inst_operands_const(p)); + } + return bits; +} + + +static XED_INLINE unsigned int +xed_decoded_inst_get_operand_width_bits(const xed_decoded_inst_t* p, + const xed_operand_t* o ) { + const xed_operand_width_enum_t width = xed_operand_width(o); + unsigned int bits=0; + if (width == XED_OPERAND_WIDTH_SSZ) { + bits=xed_operand_values_get_stack_address_width( + xed_decoded_inst_operands_const(p)); + } + else if (width == XED_OPERAND_WIDTH_ASZ) { + bits=xed_operand_values_get_effective_address_width( + xed_decoded_inst_operands_const(p)); + } + else { + const xed_uint32_t eosz = xed3_operand_get_eosz(p); + xed_assert(width < XED_OPERAND_WIDTH_LAST); + xed_assert(eosz <= 3); + bits = xed_width_bits[width][eosz]; + } + return bits; +} + + +static xed_uint32_t +xed_decoded_inst_compute_variable_width(const xed_decoded_inst_t* p, + const xed_operand_t* o) { + const xed_uint32_t nelem = xed3_operand_get_nelem(p); + const xed_uint32_t element_size = xed3_operand_get_element_size(p); + return nelem*element_size; + (void)o; // pacify compiler +} + + +unsigned int +xed_decoded_inst_compute_memory_operand_length(const xed_decoded_inst_t* p, + unsigned int memop_idx) { + const xed_inst_t* inst = p->_inst; + const unsigned int i = xed_decoded_inst_get_find_memop(p, memop_idx); + const xed_operand_t* o = xed_inst_operand(inst,i); + xed_uint32_t bits = xed_decoded_inst_get_operand_width_bits(p,o); + if (bits) + return bits>>3; + bits = xed_decoded_inst_compute_variable_width(p,o); + return bits>>3; +} + +// returns bytes +unsigned int +xed_decoded_inst_get_memory_operand_length(const xed_decoded_inst_t* p, + unsigned int memop_idx) +{ + if (xed_decoded_inst_number_of_memory_operands(p) > memop_idx) + return xed_decoded_inst_compute_memory_operand_length(p,memop_idx); + return 0; +} + +static xed_uint32_t +xed_decoded_inst_operand_length_bits_register( + const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + xed_uint32_t mode = 0; + xed_uint_t idx = 0; // default for 16b and 32b + const xed_inst_t* inst = p->_inst; + const xed_operand_t* o = xed_inst_operand(inst,operand_index); + xed_operand_enum_t op_name = xed_operand_name(o); + + xed_reg_enum_t r; + + /* some registers have a special width specified */ + const xed_operand_width_enum_t width = xed_operand_width(o); + if (width != XED_OPERAND_WIDTH_INVALID) + return xed_decoded_inst_get_operand_width_bits(p,o); + + r = xed_decoded_inst_get_reg(p,op_name); + mode = xed_decoded_inst_get_machine_mode_bits(p); + if (mode == 64) + idx = 1; + return xed_reg_width_bits[r][idx]; +} + + +unsigned int +xed_decoded_inst_operand_length_bits( + const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + const xed_inst_t* inst = p->_inst; + const unsigned int noperands = xed_inst_noperands(inst); + const xed_operand_t* o = xed_inst_operand(inst,operand_index); + xed_operand_enum_t op_name; + xed_uint32_t len; + if (noperands <= operand_index) + return 0; + + + op_name = xed_operand_name(o); + if (xed_operand_template_is_register(o)) { + len= xed_decoded_inst_operand_length_bits_register( p,operand_index); + return len; + } + else if (op_name == XED_OPERAND_AGEN) { + len=xed_operand_values_get_effective_address_width( + xed_decoded_inst_operands_const(p)); + + return len; + } + // MEM0, MEM1,PTR, IMM0, IMM1, and RELBR use the width codes now. + // use the "scalable" width codes from the operand template. + + len = xed_decoded_inst_get_operand_width_bits(p,o); + if (len) + return len; + + // variable width stuff must compute it based on nelem * element_size + len = xed_decoded_inst_compute_variable_width(p,o); + return len; +} + +unsigned int xed_decoded_inst_operand_length(const xed_decoded_inst_t* p, + unsigned int operand_index) { + unsigned int bits = xed_decoded_inst_operand_length_bits(p, operand_index); + return bits >> 3; +} + + + +/*******************************************************************/ + +// The number of elements in the operand +unsigned int xed_decoded_inst_operand_elements(const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + unsigned int nelem = 1; + const xed_inst_t* inst = p->_inst; + const unsigned int noperands = xed_inst_noperands(inst); + const xed_operand_t* o = xed_inst_operand(inst,operand_index); + xed_operand_width_enum_t width; + xed_operand_element_xtype_enum_t xtype; + const xed_operand_type_info_t* q; + + if ( operand_index >= noperands ) + return 0; + + width = xed_operand_width(o); + if ( width >= XED_OPERAND_WIDTH_LAST) + return 0; + + xtype = xed_operand_xtype(o); + if ( xtype >= XED_OPERAND_XTYPE_LAST) + return 0; + + q = xed_operand_xtype_info+xtype; + if (q->bits_per_element) { + const xed_uint_t bits = + xed_decoded_inst_operand_length_bits(p, operand_index); + + nelem = bits / q->bits_per_element; + } + else if (q->dtype == XED_OPERAND_ELEMENT_TYPE_STRUCT) { + nelem = 1; + } + else if (q->dtype == XED_OPERAND_ELEMENT_TYPE_VARIABLE) { + nelem = xed3_operand_get_nelem(p); + } + else { // XED_OPERAND_ELEMENT_TYPE_INT, XED_OPERAND_ELEMENT_TYPE_UINT + nelem = 1; + } + + return nelem; +} + +unsigned int +xed_decoded_inst_operand_element_size_bits( + const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + + unsigned int element_size = 0; + const xed_inst_t* inst = p->_inst; + const xed_operand_t* o = xed_inst_operand(inst,operand_index); + //const xed_operand_enum_t op_name = xed_operand_name(o); + //const xed_reg_enum_t reg = xed_decoded_inst_get_reg(p, op_name); + const xed_operand_element_xtype_enum_t xtype = xed_operand_xtype(o); + const xed_operand_type_info_t* q; + if ( xtype >= XED_OPERAND_XTYPE_LAST) + return 0; + + q = xed_operand_xtype_info+xtype; + if (q->bits_per_element) { + element_size = q->bits_per_element; + } + else if ( q->dtype == XED_OPERAND_ELEMENT_TYPE_STRUCT || + q->dtype == XED_OPERAND_ELEMENT_TYPE_INT || + q->dtype == XED_OPERAND_ELEMENT_TYPE_UINT ) { + element_size = xed_decoded_inst_operand_length_bits(p, operand_index); + } + else if (q->dtype == XED_OPERAND_ELEMENT_TYPE_VARIABLE) { + element_size = xed3_operand_get_element_size(p); + } + else if (xed_operand_template_is_register(o)) { + return xed_decoded_inst_operand_length_bits_register(p, operand_index); + } + else { + // catch all + xed_assert(0); + } + return element_size; +} + +xed_operand_element_type_enum_t +xed_decoded_inst_operand_element_type(const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + xed_operand_element_type_enum_t dtype = XED_OPERAND_ELEMENT_TYPE_INVALID; + const xed_inst_t* inst = p->_inst; + const unsigned int noperands = xed_inst_noperands(inst); + const xed_operand_t* o = xed_inst_operand(inst,operand_index); + xed_operand_width_enum_t width; + xed_operand_element_xtype_enum_t xtype; + if ( operand_index >= noperands ) + return dtype; + + width = xed_operand_width(o); + if ( width >= XED_OPERAND_WIDTH_LAST) + return dtype; + + xtype = xed_operand_xtype(o); + if ( xtype < XED_OPERAND_XTYPE_LAST) { + + const xed_operand_type_info_t* q = xed_operand_xtype_info+xtype; + dtype = q->dtype; + /* This is a catch case for the register NTs that do not have + type codes. It is not 100% accurate */ + if (dtype == XED_OPERAND_ELEMENT_TYPE_INVALID) + return XED_OPERAND_ELEMENT_TYPE_INT; + else if (dtype == XED_OPERAND_ELEMENT_TYPE_VARIABLE) + dtype = XED_STATIC_CAST(xed_operand_element_type_enum_t, + xed3_operand_get_type(p)); + } + return dtype; +} + +/*******************************************************************/ + + +xed_bool_t +xed_decoded_inst_uses_rflags(const xed_decoded_inst_t* q) +{ + const xed_simple_flag_t* p = xed_decoded_inst_get_rflags_info(q); + if (p && xed_simple_flag_get_nflags(p) > 0 ) + return 1; + return 0; +} + + +static xed_uint8_t +xed_decoded_inst__compute_masked_immediate( const xed_decoded_inst_t* p) +{ + xed_uint8_t imm_byte; + xed_uint8_t masked_imm_byte; + xed_uint8_t mask = 0x1F; + if (xed_operand_values_get_effective_operand_width(p) == 64) + mask = 0x3F; + xed_assert(xed3_operand_get_imm_width(p) == 8); + imm_byte = xed3_operand_get_uimm0(p); + masked_imm_byte = imm_byte & mask; + return masked_imm_byte; +} + +const xed_simple_flag_t* +xed_decoded_inst_get_rflags_info(const xed_decoded_inst_t* q) +{ + xed_uint32_t complex_simple_index; + const xed_complex_flag_t* p; + + // no flags + const xed_inst_t* inst = xed_decoded_inst_inst(q); + xed_uint32_t t_index = inst->_flag_info_index; + if(t_index == 0) + return 0; + + // simple + + if (inst->_flag_complex==0) + return xed_flags_simple_table+t_index; + + // complex + + complex_simple_index=0; + p = xed_flags_complex_table + t_index; + if (p->check_rep) + { + if (xed_operand_values_has_real_rep(q)) + complex_simple_index = p->cases[XED_FLAG_CASE_HAS_REP]; + else + complex_simple_index = p->cases[XED_FLAG_CASE_NO_REP]; + } + else if (p->check_imm) + { + xed_uint8_t masked_imm_byte = + xed_decoded_inst__compute_masked_immediate(q); + + if (masked_imm_byte == 0) + complex_simple_index = p->cases[XED_FLAG_CASE_IMMED_ZERO]; + else if (masked_imm_byte == 1) + complex_simple_index = p->cases[XED_FLAG_CASE_IMMED_ONE]; + else + complex_simple_index = p->cases[XED_FLAG_CASE_IMMED_OTHER]; + } + else + xed_assert(0); + + if (complex_simple_index == 0) + return 0; + return xed_flags_simple_table+complex_simple_index; +} + +xed_bool_t +xed_decoded_inst_is_prefetch(const xed_decoded_inst_t* p) +{ + return xed_decoded_inst_get_attribute(p, XED_ATTRIBUTE_PREFETCH); +} + +xed_uint_t +xed_decoded_inst_number_of_memory_operands(const xed_decoded_inst_t* p) { + return (xed3_operand_get_mem0(p) + + xed3_operand_get_mem1(p) + xed3_operand_get_agen(p)); +} + + + + +////////////////////////////////////////////////////////////////////////// +// Modifying decoded instructions before re-encoding + + +void xed_decoded_inst_set_scale(xed_decoded_inst_t* p, xed_uint_t scale) { + xed3_operand_set_scale(p,scale); +} +void xed_decoded_inst_set_memory_displacement(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bytes) { + xed_operand_values_set_memory_displacement(p, disp, length_bytes); +} +void xed_decoded_inst_set_branch_displacement(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bytes) { + xed_operand_values_set_branch_displacement(p, disp, length_bytes); +} + +void xed_decoded_inst_set_immediate_signed(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bytes) { + xed_operand_values_set_immediate_signed(p, x,length_bytes); +} +void xed_decoded_inst_set_immediate_unsigned(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bytes) { + xed_operand_values_set_immediate_unsigned(p, x,length_bytes); +} + +//////// + +void xed_decoded_inst_set_memory_displacement_bits(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bits) { + xed_operand_values_set_memory_displacement_bits(p, disp, length_bits); +} +void xed_decoded_inst_set_branch_displacement_bits(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bits) { + xed_operand_values_set_branch_displacement_bits(p, disp, length_bits); +} + +void xed_decoded_inst_set_immediate_signed_bits(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bits) { + xed_operand_values_set_immediate_signed_bits(p, x,length_bits); +} +void xed_decoded_inst_set_immediate_unsigned_bits(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bits) { + xed_operand_values_set_immediate_unsigned_bits(p, x,length_bits); +} + + +//////////////////////////////////////////////////////////////////////////// + + +xed_uint32_t xed_decoded_inst_get_operand_width(const xed_decoded_inst_t* p) { + if (xed_decoded_inst_get_attribute(p, XED_ATTRIBUTE_BYTEOP)) + return 8; + return xed_operand_values_get_effective_operand_width(p); +} + + + +xed_bool_t +xed_decoded_inst_valid_for_chip(xed_decoded_inst_t const* const p, + xed_chip_enum_t chip) +{ + xed_isa_set_enum_t isa_set; + + isa_set = xed_decoded_inst_get_isa_set( p); + return xed_isa_set_is_valid_for_chip(isa_set, chip); +} + +xed_uint_t +xed_decoded_inst_vector_length_bits(xed_decoded_inst_t const* const p) +{ + xed_uint_t vl_bits=0; +#if defined(XED_AVX) + xed_uint_t vl_encoded; + // only valid for VEX, EVEX (and XOP) instructions. + if (xed3_operand_get_vexvalid(p) == 0) + return 0; + + /* vl_encoded 0=128,1=256,2=512*/ + vl_encoded = xed3_operand_get_vl(p); + + /* 0->128, 1->256, 2->512 */ + vl_bits = 1 << (vl_encoded+7); +#endif + return vl_bits; + (void)p; // pacify (msvs) compiler for noavx builds +} + +xed_bool_t +xed_decoded_inst_masked_vector_operation(xed_decoded_inst_t* p) +{ + // pre-evex masked operations + xed_uint32_t maskop = + xed_decoded_inst_get_attribute(p, XED_ATTRIBUTE_MASKOP); + if (maskop) + return 1; + // if evex, and not k0, and not mask-as-control, then report it as a + // masked operation. Evex operations that mask-as-control are a + // different kind of masked operation. + + if (xed_decoded_inst_get_attribute(p, XED_ATTRIBUTE_MASKOP_EVEX) && + !xed_decoded_inst_get_attribute(p, XED_ATTRIBUTE_MASK_AS_CONTROL)) + { + const xed_uint_t write_mask_operand = 1; + const xed_operand_t* op = xed_inst_operand(p->_inst, write_mask_operand); + xed_operand_enum_t op_name = xed_operand_name(op); + if (op_name == XED_OPERAND_REG0 || op_name == XED_OPERAND_REG1) { + xed_reg_enum_t r = xed_decoded_inst_get_reg(p, op_name); + if (xed_reg_class(r) == XED_REG_CLASS_MASK) { + if (r != XED_REG_K0) + return 1; + } + } + } + + return 0; +} + + + +xed_uint_t +xed_decoded_inst_get_nprefixes(xed_decoded_inst_t* p) { + return xed3_operand_get_nprefixes(p); +} + +xed_bool_t xed_decoded_inst_masking(const xed_decoded_inst_t* p) { +#if defined(XED_SUPPORTS_AVX512) || defined(XED_SUPPORTS_KNC) + if (xed3_operand_get_mask(p) != 0) + return 1; +#endif + return 0; + (void)p; //pacify compiler +} +xed_bool_t xed_decoded_inst_merging(const xed_decoded_inst_t* p) { +#if defined(XED_SUPPORTS_AVX512) || defined(XED_SUPPORTS_KNC) + if (xed3_operand_get_mask(p) != 0) +# if defined(XED_SUPPORTS_AVX512) + if (xed3_operand_get_zeroing(p) == 0) + return 1; +# elif defined(XED_SUPPORTS_KNC) + return 1; +# endif +#endif + return 0; + (void)p; //pacify compiler +} +xed_bool_t xed_decoded_inst_zeroing(const xed_decoded_inst_t* p) { +#if defined(XED_SUPPORTS_AVX512) + if (xed3_operand_get_mask(p) != 0) + if (xed3_operand_get_zeroing(p) == 1) + return 1; +#endif + return 0; + (void)p; //pacify compiler +} + +xed_operand_action_enum_t +xed_decoded_inst_operand_action(const xed_decoded_inst_t* p, + unsigned int operand_index) +{ + + /* For the 0th operand, exept for stores: + RW W <<< SDM/XED notion + =========================================== + aaa=0 merging r w w + aaa=0 zeroing n/a n/a + aaa!=0 merging r cw r cw <<< This one requires special handling + aaa!=0 zeroing r w w + + */ + const xed_inst_t* xi = xed_decoded_inst_inst(p); + const xed_operand_t* op = xed_inst_operand(xi,operand_index); + xed_operand_action_enum_t rw = xed_operand_rw(op); + + if (operand_index == 0) + { + if (xed_decoded_inst_masking(p) && xed_decoded_inst_merging(p)) + { + if (rw == XED_OPERAND_ACTION_RW) + return XED_OPERAND_ACTION_RCW; + //need to filter out stores which do NOT read memory when merging. + if (rw == XED_OPERAND_ACTION_W) + { + const xed_operand_t* zero_op = xed_inst_operand(xi,0); + if (xed_operand_name(zero_op) == XED_OPERAND_MEM0) + return XED_OPERAND_ACTION_CW; + // reflect dest register input dependence when merging + return XED_OPERAND_ACTION_RCW; + } + + } + } + + return rw; +} + diff --git a/src/xed-disas.c b/src/xed-disas.c new file mode 100644 index 0000000..f0b67c4 --- /dev/null +++ b/src/xed-disas.c @@ -0,0 +1,1519 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas.c + + +//////////////////////////////////////////////////////////////////////////// +#include "xed-internal-header.h" +#include "xed-decoded-inst.h" +#include "xed-decoded-inst-api.h" +#include "xed-decoded-inst-private.h" + +#include "xed-disas.h" +#include "xed-disas-private.h" +#include "xed-util.h" +#include "xed-util-private.h" +#include "xed-format-options.h" +#include "xed-reg-class.h" + +#include "xed-operand-ctype-enum.h" +#include "xed-operand-ctype-map.h" +#include "xed-init-pointer-names.h" +#include "xed-print-info.h" +#include "xed-convert-table-init.h" //generated +#include "xed-isa-set.h" +#include "xed-ild.h" + +#include // memset +#define XED_HEX_BUFLEN 200 + +int +xed_get_symbolic_disassembly(xed_print_info_t* pi, + xed_uint64_t address, + char* buffer, + xed_uint_t buffer_length, + xed_uint64_t* offset) + +{ + // use the common registered version of the callback if non is supplied + // by the user. + xed_disassembly_callback_fn_t fn = 0; + if (pi->disassembly_callback) + fn = pi->disassembly_callback; + + if (fn) { + int r = (*fn)(address, + buffer, + buffer_length, + offset, + pi->context); + return r; + } + return 0; +} + + +//////////////////////////////////////////////////// + + +static xed_bool_t stringop_memop(const xed_decoded_inst_t* p, + const xed_operand_t* o) { + xed_bool_t stringop = (xed_decoded_inst_get_category(p) == + XED_CATEGORY_STRINGOP); + if (stringop) { + xed_operand_enum_t op_name = xed_operand_name(o); + if (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1) + return 1; + } + return 0; +} + +static xed_bool_t xed_decoded_inst_explicit_memop(const xed_decoded_inst_t* p) { + const xed_inst_t* inst = p->_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i_inst; + const unsigned int noperands = xed_inst_noperands(inst); + unsigned int i; + for( i=0;i",blen); + for( i=0;i0) + blen = xed_strncat(buf, " ",blen); + (void) xed_flag_action_print(fa,tbuf,XED_HEX_BUFLEN); + blen = xed_strncat(buf, tbuf,blen); + + } + blen = xed_strncat(buf,"",blen); + } + return blen; +} + + + + +static void xed_pi_strcat(xed_print_info_t* pi, + char const* str) +{ + pi->blen = xed_strncat(pi->buf, str, pi->blen); +} + + + +static void xed_prefixes(xed_print_info_t* pi, + char const* prefix) +{ + if (pi->emitted == 0 && pi->format_options.xml_a) + xed_pi_strcat(pi,""); + if (pi->emitted) + xed_pi_strcat(pi," "); + xed_pi_strcat(pi,prefix); + pi->emitted=1; +} + + +static void +xed_decoded_inst_dump_common(xed_print_info_t* pi) +{ + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(pi->p); + + int long_mode = xed_operand_values_get_long_mode(ov); + const xed_uint32_t dmode = xed_decoded_inst_get_machine_mode_bits(pi->p); + int dmode16 = (dmode == 16); + int dmode32 = (dmode == 32); + + if (xed_decoded_inst_has_mpx_prefix(pi->p)) + xed_prefixes(pi,"bnd"); + if (xed_decoded_inst_is_xacquire(pi->p)) + xed_prefixes(pi,"xacquire"); + if (xed_decoded_inst_is_xrelease(pi->p)) + xed_prefixes(pi,"xrelease"); + if (xed_operand_values_has_lock_prefix(ov)) + xed_prefixes(pi,"lock"); + if (xed_operand_values_has_real_rep(ov)) { + if (xed_operand_values_has_rep_prefix(ov)) + xed_prefixes(pi,"rep"); + if (xed_operand_values_has_repne_prefix(ov)) + xed_prefixes(pi,"repne"); + } + else if (xed_operand_values_branch_not_taken_hint(ov)) + xed_prefixes(pi,"hint-not-taken"); + else if (xed_operand_values_branch_taken_hint(ov)) + xed_prefixes(pi,"hint-taken"); + + if (xed_operand_values_has_address_size_prefix(ov)) { + if (xed_decoded_inst_explicit_memop(pi->p) == 0) { + if (long_mode || dmode16) + xed_prefixes(pi,"addr32"); + else + xed_prefixes(pi,"addr16"); + } + } + if (xed_operand_values_has_operand_size_prefix(ov)) { + if (xed_decoded_inst_explicit_operand(pi->p) == 0) { + if (long_mode || dmode32) + xed_prefixes(pi,"data16"); + else + xed_prefixes(pi,"data32"); + } + } + if (pi->emitted && pi->format_options.xml_a) + xed_pi_strcat(pi,""); + if (pi->emitted) + xed_pi_strcat(pi," "); + + // reset the spacing-is-required indicator after handling prefixes + pi->emitted = 0; +} + + +static const char* instruction_name_att(const xed_decoded_inst_t* p) + +{ + xed_iform_enum_t iform = xed_decoded_inst_get_iform_enum(p); + return xed_iform_to_iclass_string_att(iform); +} + +static const char* instruction_name_intel(const xed_decoded_inst_t* p) +{ + xed_iform_enum_t iform = xed_decoded_inst_get_iform_enum(p); + return xed_iform_to_iclass_string_intel(iform); +} + + +/////////////////////////////////////////////////////////////////////////////// +static int xed_print_cvt(const xed_decoded_inst_t* p, + char* buf, + int blen, + xed_operand_convert_enum_t cvt) { + // 32bit var is enough since the only operand wider than 32b disp/imm + // and we are not decorating those + xed_uint_t opvalue; + xed_operand_enum_t index_operand = xed_convert_table[cvt].opnd; + xed3_get_generic_operand(p,index_operand,&opvalue); + if (opvalue < xed_convert_table[cvt].limit) { + const char* s = xed_convert_table[cvt].table_name[ opvalue ]; + blen = xed_strncat(buf,s,blen); + } + else + blen = xed_strncat(buf,"BADCVT",blen); + return blen; +} + +static int xml_tag(char* buf, int blen, char const* tag, xed_uint_t value) { + char tbuf[XED_HEX_BUFLEN]; + + blen = xed_strncat(buf,"<",blen); + blen = xed_strncat(buf,tag,blen); + blen = xed_strncat(buf," bits=\"",blen); + + xed_sprintf_uint32(tbuf, value, XED_HEX_BUFLEN); + blen = xed_strncat(buf,tbuf,blen); + + blen = xed_strncat(buf,"\">",blen); + return blen; +} + +static void xml_tag_pi(xed_print_info_t* pi, + char const* tag, + xed_uint_t value) +{ + pi->blen = xml_tag(pi->buf, pi->blen, tag, value); +} + + +static void xed_operand_spacer(xed_print_info_t* pi) { + if (pi->emitted) { + pi->blen = xed_strncat(pi->buf,", ",pi->blen); + } +} + + +static void print_seg_prefix_for_suppressed_operands( + xed_print_info_t* pi, + const xed_operand_values_t* ov, + const xed_operand_t* op) +{ + int i; + xed_operand_enum_t op_name = xed_operand_name(op); + /* suppressed memops with nondefault segments get their segment printed */ + const xed_operand_enum_t names[] = { XED_OPERAND_MEM0,XED_OPERAND_MEM1}; + for(i=0;i<2;i++) { + if (op_name == names[i]) { + if (xed_operand_values_using_default_segment(ov, i) == 0) { + xed_reg_enum_t seg = XED_REG_INVALID; + xed_operand_spacer(pi); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + switch(i) + { + case 0: seg = xed3_operand_get_seg0(ov); break; + case 1: seg = xed3_operand_get_seg1(ov); break; + } + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + pi->emitted = 1; + } + } + } +} + +static void +xed_print_operand_decorations( + xed_print_info_t* pi, + xed_operand_t const* const op) +{ + xed_uint32_t cvt_idx = op->_cvt_idx; + + if (cvt_idx && cvt_idx < XED_MAX_CONVERT_PATTERNS) { + int i; + for( i=0; iblen = xed_print_cvt(pi->p, pi->buf, pi->blen, v); + } + } +} + + +static void +xml_reg_prefix(xed_print_info_t* pi, xed_reg_enum_t reg) +{ + if (pi->format_options.xml_a) + xml_tag_pi(pi, + "REG", + xed_get_register_width_bits(reg)); +} + +static void +xml_reg_suffix(xed_print_info_t* pi) +{ + if (pi->format_options.xml_a) + pi->blen = xed_strncat(pi->buf,"",pi->blen); +} + +static void +print_reg(xed_print_info_t* pi, + xed_reg_enum_t reg) +{ + char const* s; + + if (pi->syntax == XED_SYNTAX_ATT) + xed_pi_strcat(pi,"%"); + + if (reg == XED_REG_ST0 && pi->implicit) + s = "st"; + else + s = xed_reg_enum_t2str(reg); + + pi->blen = xed_strncat_lower(pi->buf, s, pi->blen); +} + +static void +print_reg_xml(xed_print_info_t* pi, + xed_reg_enum_t reg) +{ + xml_reg_prefix(pi,reg); + print_reg(pi,reg); + xml_reg_suffix(pi); +} + + +#if defined(XED_SUPPORTS_AVX512) +static xed_uint_t +operand_is_writemask( + xed_operand_t const* const op) +{ + + xed_operand_enum_t op_name = xed_operand_name(op); + // for memops dests, writemask is REG0. + // for reg-dest instr, writemask is REG1. + if (op_name == XED_OPERAND_REG1 || op_name == XED_OPERAND_REG0) + if (xed_operand_nonterminal_name(op) == XED_NONTERMINAL_MASK1) + return 1; + + return 0; +} + +static void +print_decoration(xed_print_info_t* pi, + xed_uint_t indx) +{ + xed_inst_t const* xi = xed_decoded_inst_inst(pi->p); + xed_operand_t const* const kop = xed_inst_operand(xi,indx); + xed_print_operand_decorations(pi, kop); +} + + + +static xed_reg_enum_t +printing_writemasked_operand( + xed_print_info_t* pi) +{ + // return XED_REG_INVALID if next operand is not a writemask + // else return the XED_REG_K0...K7 if it is a writemask. + // (We treat k0 as a write mask, but it won't get printed) + + // write masked operand must be first + if (pi->operand_indx > 0) + return XED_REG_INVALID; + else + { + xed_inst_t const* xi = xed_decoded_inst_inst(pi->p); + xed_uint_t noperands = xed_inst_noperands(xi); + + // we have another operand + xed_uint_t nxt_opnd = pi->operand_indx + 1; + if (nxt_opnd < noperands) + { + xed_operand_t const* const op = xed_inst_operand(xi,nxt_opnd); + if (operand_is_writemask(op)) + { + xed_operand_enum_t op_name = xed_operand_name(op); + xed_reg_enum_t reg; + xed3_get_generic_operand(pi->p,op_name,®); + return reg; + } + + } + } + return XED_REG_INVALID; +} + +static void +print_write_mask_reg( + xed_print_info_t* pi, + xed_reg_enum_t writemask) +{ + // print the write mask if not k0 + if (writemask != XED_REG_K0) + { + pi->blen = xed_strncat(pi->buf,"{",pi->blen); + print_reg(pi,writemask); + pi->blen = xed_strncat(pi->buf,"}",pi->blen); + + // write mask operand might have decorations. print them. + print_decoration(pi, pi->operand_indx + 1); + } +} +#endif // XED_SUPPORTS_AVX512 + + +static void +print_write_mask_generic( + xed_print_info_t* pi) +{ +#if defined(XED_SUPPORTS_AVX512) + if (pi->format_options.write_mask_curly_k0) + { + xed_reg_enum_t writemask; + writemask = printing_writemasked_operand(pi); + if (writemask != XED_REG_INVALID) + { + print_write_mask_reg(pi, writemask); + // tell operand loop to skip emitting write mask operand on + // next iteration (for any write mask reg, k0 or otherwise) + pi->skip_operand = 1; + } + } +#endif + (void) pi; +} + + +static void +print_reg_writemask( + xed_print_info_t* pi, + xed_reg_enum_t reg) +{ + xml_reg_prefix(pi,reg); + print_reg(pi,reg); +#if defined(XED_SUPPORTS_AVX512) + print_write_mask_generic(pi); +#endif + xml_reg_suffix(pi); +} + +#define XED_SYMBOL_LEN 512 + +static const xed_bool_t print_address=1; +static const xed_bool_t no_print_address=0; +static const xed_bool_t branch_displacement=0; +static const xed_bool_t memory_displacement=1; + +static void +print_rel_sym(xed_print_info_t* pi, + xed_bool_t arg_print_address, + xed_bool_t arg_memory_displacement) +{ + xed_int64_t disp; + xed_uint64_t instruction_length = xed_decoded_inst_get_length(pi->p); + xed_uint64_t pc = pi->runtime_address + instruction_length; + xed_uint64_t effective_addr; + xed_bool_t long_mode, symbolic; + xed_uint_t bits_to_print; + char symbol[XED_SYMBOL_LEN]; + xed_uint64_t offset; + const xed_bool_t leading_zeros = 0; + + if (arg_memory_displacement) + disp = xed_decoded_inst_get_memory_displacement(pi->p,0); //first memop only + else + disp = xed_decoded_inst_get_branch_displacement(pi->p); + + long_mode = xed_operand_values_get_long_mode( + xed_decoded_inst_operands_const(pi->p)); + + bits_to_print = long_mode ? 8*8 :4*8; + + effective_addr = (xed_uint64_t) ((xed_int64_t)pc + disp); + + symbolic = xed_get_symbolic_disassembly(pi, + effective_addr, + symbol, + XED_SYMBOL_LEN, + &offset); + + if (arg_print_address) // print the numeric address + { + if (symbolic==0 || + pi->format_options.hex_address_before_symbolic_name) + { + xed_pi_strcat(pi,"0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + effective_addr, + bits_to_print, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + } + + if (symbolic) + { + if (pi->format_options.xml_a) + xed_pi_strcat(pi," <"); + else + xed_pi_strcat(pi," <"); + + xed_pi_strcat(pi,symbol); + if (offset) + { + xed_pi_strcat(pi,"+0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + offset, + bits_to_print, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + if (pi->format_options.xml_a) + xed_pi_strcat(pi," >"); + else + xed_pi_strcat(pi,">"); + } +} + +static void +print_relbr(xed_print_info_t* pi) +{ + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + print_rel_sym(pi,print_address, branch_displacement); + + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); +} + +static void xed_print_operand( xed_print_info_t* pi ) +{ + const xed_inst_t* xi = xed_decoded_inst_inst(pi->p); + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(pi->p); + const xed_operand_t* op = xed_inst_operand(xi,pi->operand_indx); + xed_operand_enum_t op_name = xed_operand_name(op); + const xed_bool_t leading_zeros = 0; + + if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) { + if (stringop_memop(pi->p,op)) { + /* allow a fall through to print the memop for stringops to + * match dumpbin */ + } + else { + print_seg_prefix_for_suppressed_operands(pi, ov, op); + return; + } + } + + // for mangling name of x87 implicit operand + pi->implicit = (xed_operand_operand_visibility(op) == XED_OPVIS_IMPLICIT); + + xed_operand_spacer(pi); + pi->emitted = 1; + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + switch(xed_operand_name(op)) { + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: { + xed_bool_t no_base_index = 0; + xed_reg_enum_t base = xed3_operand_get_base0(pi->p); + xed_reg_enum_t seg = xed3_operand_get_seg0(pi->p); + xed_reg_enum_t index = xed3_operand_get_index(pi->p); + + xed_int64_t disp = + xed_operand_values_get_memory_displacement_int64(ov); + unsigned int disp_bits = + xed_operand_values_get_memory_displacement_length_bits(ov); + + xed_bits_t scale = xed3_operand_get_scale(pi->p); + xed_bool_t started = 0; + xed_uint_t bytes = + xed_decoded_inst_operand_length_bits(pi->p, pi->operand_indx)>>3; + if (pi->format_options.xml_a) { + if (xed_operand_name(op) == XED_OPERAND_AGEN) + xed_pi_strcat(pi,""); + else + xml_tag_pi(pi, "MEM", bytes << 3); + } + + if (xed_operand_name(op) != XED_OPERAND_AGEN) + pi->blen = xed_strncat_lower( + pi->buf, + xed_decoded_inst_print_ptr_size(bytes), + pi->blen); + + xed_pi_strcat(pi,"ptr "); + if (seg != XED_REG_INVALID && + !xed_operand_values_using_default_segment(ov, 0)) + { + if (xed_operand_name(op) != XED_OPERAND_AGEN) { + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + pi->blen = xed_strncat(pi->buf,":",pi->blen); + } + } + + xed_pi_strcat(pi,"["); + if (base != XED_REG_INVALID) { + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(base), + pi->blen); + started = 1; + } + + if (index != XED_REG_INVALID) + { +#if defined(XED_MPX) + if (xed_decoded_inst_get_attribute( + pi->p, + XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + { + // MPX BNDLDX/BNDSTX instr are unusual in that they use + // the index reg as distinct operand. + + pi->extra_index_operand = index; + } + else // normal path +#endif + { + if (started) + xed_pi_strcat(pi,"+"); + started = 1; + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(index), + pi->blen); + + if (scale != 1 || pi->format_options.omit_unit_scale==0) { + xed_pi_strcat(pi,"*"); + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), + XED_STATIC_CAST(xed_uint_t,scale), + pi->blen); + } + } + } + + no_base_index = (base == XED_REG_INVALID) && + (index == XED_REG_INVALID); + + if (xed_operand_values_has_memory_displacement(ov)) + { + if (disp_bits && (disp || no_base_index)) + { + xed_uint_t negative = (disp < 0) ? 1 : 0; + if (started) + { + if (negative) + { + xed_pi_strcat(pi,"-"); + disp = - disp; + } + else + xed_pi_strcat(pi,"+"); + } + xed_pi_strcat(pi,"0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + disp_bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + } + xed_pi_strcat(pi,"]"); + + print_write_mask_generic(pi); + if (base == XED_REG_RIP && xed_operand_values_has_memory_displacement(ov)) + print_rel_sym(pi,no_print_address, memory_displacement); + + + if (pi->format_options.xml_a) { + if (xed_operand_name(op) == XED_OPERAND_AGEN) + xed_pi_strcat(pi,""); + else + xed_pi_strcat(pi,""); + } + break; + } + + case XED_OPERAND_MEM1: { + xed_reg_enum_t base = xed3_operand_get_base1(pi->p); + xed_reg_enum_t seg = xed3_operand_get_seg1(pi->p); + xed_uint_t bytes = + xed_decoded_inst_operand_length_bits(pi->p, pi->operand_indx)>>3; + + if (pi->format_options.xml_a) + xml_tag_pi(pi, "MEM", bytes << 3); + + pi->blen = xed_strncat_lower(pi->buf, + xed_decoded_inst_print_ptr_size(bytes), + pi->blen); + + xed_pi_strcat(pi,"ptr "); + + if (seg != XED_REG_INVALID && + !xed_operand_values_using_default_segment(ov, 1)) + { + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + xed_pi_strcat(pi,":"); + } + xed_pi_strcat(pi,"["); + if (base != XED_REG_INVALID) + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(base), + pi->blen); + xed_pi_strcat(pi,"]"); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + break; + } + case XED_OPERAND_IMM0: { + unsigned int bits = xed3_operand_get_imm_width(pi->p); + if (pi->format_options.xml_a) + xml_tag_pi(pi, "IMM", bits); + + if ( xed3_operand_get_imm0signed(pi->p) && + pi->format_options.no_sign_extend_signed_immediates == 0 ) + { + xed_int32_t disp; + bits = xed_decoded_inst_get_operand_width(pi->p); + disp = XED_STATIC_CAST(xed_int32_t, + xed_operand_values_get_immediate_int64(ov)); + xed_pi_strcat(pi,"0x"); + + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + else { + xed_uint64_t disp = xed_operand_values_get_immediate_uint64(ov); + xed_pi_strcat(pi,"0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + break; + } + case XED_OPERAND_IMM1: { // The ENTER instruction + xed_uint64_t disp = xed3_operand_get_uimm1(pi->p); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + xed_pi_strcat(pi,"0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + 8, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + break; + } + + case XED_OPERAND_PTR: { + unsigned int disp =(unsigned int) + xed_operand_values_get_branch_displacement_int32(ov); + + xed_bool_t long_mode = xed_operand_values_get_long_mode( + xed_decoded_inst_operands_const(pi->p)); + + xed_uint_t bits_to_print = long_mode ? 8*8 :4*8; + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + xed_pi_strcat(pi,"0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits_to_print, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + break; + + } + case XED_OPERAND_RELBR: + print_relbr(pi); + break; + + default: { + xed_operand_ctype_enum_t ctype = xed_operand_get_ctype(op_name); + switch(ctype) { + case XED_OPERAND_CTYPE_XED_BITS_T: { + xed_bits_t b; + xed3_get_generic_operand(pi->p,op_name,&b); + + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), + XED_STATIC_CAST(xed_uint_t,b), + pi->blen); + break; + } + case XED_OPERAND_CTYPE_XED_UINT8_T: { + xed_uint32_t b; + xed3_get_generic_operand(pi->p,op_name,&b); + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), b, pi->blen); + + break; + } + case XED_OPERAND_CTYPE_XED_ERROR_ENUM_T: { + /* THIS DOES NOT HAPPEN */ + xed_pi_strcat(pi,"NDY"); + break; + } + case XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T: { + /* THIS DOES NOT HAPPEN */ + xed_iclass_enum_t b = xed3_operand_get_iclass(pi->p); + xed_pi_strcat(pi,xed_iclass_enum_t2str(b)); + break; + } + case XED_OPERAND_CTYPE_XED_REG_ENUM_T: { + /* THIS ONE IS IMPORTANT -- IT PRINTS THE REGISTERS */ + xed_reg_enum_t reg; + xed3_get_generic_operand(pi->p,op_name,®); + print_reg_writemask(pi,reg); + break; + } + + default: + xed_pi_strcat(pi, "NOT HANDLING CTYPE "); + xed_pi_strcat(pi, xed_operand_ctype_enum_t2str(ctype)); + xed_assert(0); + } // inner switch + } // default case of outer switch + } // outer switch + + + xed_print_operand_decorations(pi, op); + + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); +} + + +static void +setup_print_info(xed_print_info_t* pi) +{ + // init the internal fields + pi->emitted = 0; + pi->operand_indx = 0; + pi->skip_operand = 0; + pi->implicit = 0; + pi->extra_index_operand = XED_REG_INVALID; + + pi->buf[0]=0; /* allow use of strcat for everything */ + + if (pi->format_options_valid==0) { + // grab the defaults. + pi->format_options_valid = 1; + pi->format_options = xed_format_options; + } +} + +//exported +void xed_init_print_info(xed_print_info_t* pi) +{ + memset(pi, 0, sizeof(xed_print_info_t)); + pi->syntax = XED_SYNTAX_INTEL; +} + + +static xed_bool_t +xed_decoded_inst_dump_intel_format_internal(xed_print_info_t* pi) +{ + unsigned int i; + unsigned int noperands; + const char* instruction_name=0 ; + const xed_inst_t* xi = xed_decoded_inst_inst(pi->p); + + if (!xi) + return 0; + + setup_print_info(pi); + + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + xed_decoded_inst_dump_common(pi); + + instruction_name = instruction_name_intel(pi->p); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + pi->blen = xed_strncat_lower(pi->buf, instruction_name, pi->blen); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + + xed_pi_strcat(pi," "); + + /* print the operands */ + noperands = xed_inst_noperands(xi); + for( i=0;iskip_operand) + { + pi->skip_operand = 0; + } + else + { + pi->operand_indx=i; + xed_print_operand(pi); + } + } + + if (pi->extra_index_operand != XED_REG_INVALID) { + xed_operand_spacer(pi); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + print_reg_xml(pi,pi->extra_index_operand); + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + } + + + if (pi->format_options.xml_f) + pi->blen = xml_print_flags(pi->p, pi->buf, pi->blen); + + if (pi->format_options.xml_a) + xed_pi_strcat(pi,""); + return 1; +} + + + +static xed_bool_t +xed_decoded_inst_dump_att_format_internal( + xed_print_info_t* pi) +{ + int i,j,intel_way, noperands; + const int leading_zeros=0; + const xed_inst_t* xi = xed_decoded_inst_inst(pi->p); + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(pi->p); + const char* instruction_name = 0; + const char* suffix = 0; + + if (!xi) + return 0; + + setup_print_info(pi); + xed_decoded_inst_dump_common(pi); + + instruction_name = instruction_name_att(pi->p); + pi->blen = xed_strncat_lower(pi->buf, instruction_name, pi->blen); + suffix = instruction_suffix_att(pi->p); + if (suffix) { + xed_pi_strcat(pi,suffix); + } + + xed_pi_strcat(pi," "); + noperands = xed_inst_noperands(xi); + intel_way = 0; + if (xed_inst_get_attribute(xi, XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION)) + intel_way = 1; + +#if defined(XED_MPX) + if (xed_decoded_inst_get_attribute( + pi->p, + XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + { + + for( j=0;jp); + xed_pi_strcat(pi,"%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(indx), + pi->blen); + + pi->emitted=1; + } // case + default: + break; // ignore everything else + + } // switch + } //for + } +#endif + + for( j=0;jimplicit = (xed_operand_operand_visibility(op) == XED_OPVIS_IMPLICIT); + + pi->operand_indx=i; // use the Intel numbering +#if defined(XED_SUPPORTS_AVX512) + if (pi->format_options.write_mask_curly_k0 && + operand_is_writemask(op)) + { + continue; + } +#endif + + if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) { + if (stringop_memop(pi->p,op)) { + /* print the memop */ + } + else { + /* suppressed memops with nondefault segments get their + * segment printed */ + if (xed_operand_name(op) == XED_OPERAND_MEM0) { + if (xed_operand_values_using_default_segment(ov, 0) == 0) { + xed_reg_enum_t seg = xed3_operand_get_seg0(pi->p); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + xed_pi_strcat(pi,":"); + pi->emitted=1; + } + } + else if (xed_operand_name(op) == XED_OPERAND_MEM1) { + if (xed_operand_values_using_default_segment(ov, 1) == 0) { + xed_reg_enum_t seg = xed3_operand_get_seg1(pi->p); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + xed_pi_strcat(pi, ":"); + pi->emitted=1; + } + } + continue; + } + } + + if (pi->emitted) + xed_pi_strcat(pi,", "); + pi->emitted=1; + + switch(xed_operand_name(op)) { + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: { + xed_reg_enum_t base = xed3_operand_get_base0(pi->p); + xed_reg_enum_t seg = xed3_operand_get_seg0(pi->p); + xed_reg_enum_t index = xed3_operand_get_index(pi->p); + xed_int64_t disp = + xed_operand_values_get_memory_displacement_int64(ov); + unsigned int disp_bits = + xed_operand_values_get_memory_displacement_length_bits(ov); + + xed_bits_t scale = xed3_operand_get_scale(pi->p); + + if (seg != XED_REG_INVALID && + !xed_operand_values_using_default_segment(ov, 0)) + { + if (xed_operand_name(op) != XED_OPERAND_AGEN) { + xed_pi_strcat(pi,"%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + xed_pi_strcat(pi,":"); + } + } + if (xed_operand_values_has_memory_displacement(ov)) + { + if (disp_bits && disp) { + if (disp<0) { + if ( (base != XED_REG_INVALID) || + (index != XED_REG_INVALID) ) { + xed_pi_strcat(pi,"-"); + disp = - disp; + } + } + xed_pi_strcat(pi,"0x"); + pi->blen = + xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + disp_bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + } + + if (base != XED_REG_INVALID || index != XED_REG_INVALID) + xed_pi_strcat(pi,"("); + if (base != XED_REG_INVALID) { + xed_pi_strcat(pi,"%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(base), + pi->blen); + } + if (index != XED_REG_INVALID) + { +#if defined(XED_MPX) + if (xed_decoded_inst_get_attribute( + pi->p, + XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + { + // MPX BNDLDX/BNDSTX instr are unusual in that they use + // the index reg as distinct operand. + + // HANDLED ABOVE! + } + else +#endif + { + xed_pi_strcat(pi,",%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(index), + pi->blen); + xed_pi_strcat(pi,","); + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), + XED_STATIC_CAST(xed_uint_t,scale), + pi->blen); + } + } + if (base != XED_REG_INVALID || index != XED_REG_INVALID) + xed_pi_strcat(pi,")"); + + print_write_mask_generic(pi); + if (base == XED_REG_RIP && xed_operand_values_has_memory_displacement(ov)) + print_rel_sym(pi,no_print_address, memory_displacement); + + break; + } + + case XED_OPERAND_MEM1: { + xed_reg_enum_t base = xed3_operand_get_base1(pi->p); + xed_reg_enum_t seg = xed3_operand_get_seg1(pi->p); + if (seg != XED_REG_INVALID && + !xed_operand_values_using_default_segment(ov, 1)) + { + xed_pi_strcat(pi,"%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(seg), + pi->blen); + xed_pi_strcat(pi,":"); + } + + if (base != XED_REG_INVALID) { + xed_pi_strcat(pi,"(%"); + pi->blen = xed_strncat_lower(pi->buf, + xed_reg_enum_t2str(base), + pi->blen); + xed_pi_strcat(pi,")"); + } + break; + } + case XED_OPERAND_IMM0: { + if ( xed3_operand_get_imm0signed(pi->p) && + pi->format_options.no_sign_extend_signed_immediates == 0 ) + { + unsigned int bits = xed_decoded_inst_get_operand_width(pi->p); + xed_int32_t disp = XED_STATIC_CAST(xed_int32_t, + xed_operand_values_get_immediate_int64(ov)); + xed_pi_strcat(pi,"$0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + else { + unsigned int bits = xed3_operand_get_imm_width(pi->p); + xed_uint64_t disp =xed_operand_values_get_immediate_uint64(ov); + xed_pi_strcat(pi,"$0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + } + break; + } + case XED_OPERAND_IMM1: { // The ENTER instruction + xed_uint64_t disp = xed3_operand_get_uimm1(pi->p); + xed_pi_strcat(pi,"$0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + 8, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + break; + } + + case XED_OPERAND_PTR: { + unsigned int disp = + xed_decoded_inst_get_branch_displacement(pi->p); + xed_bool_t long_mode = + xed_operand_values_get_long_mode( + xed_decoded_inst_operands_const(pi->p)); + + xed_uint_t bits_to_print = long_mode ? 8*8 :4*8; + xed_pi_strcat(pi,"$0x"); + pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf), + disp, + bits_to_print, + leading_zeros, + pi->blen, + pi->format_options.lowercase_hex); + break; + } + + case XED_OPERAND_RELBR: + print_relbr(pi); + break; + + default: { + xed_operand_ctype_enum_t ctype = xed_operand_get_ctype(op_name); + switch(ctype) { + case XED_OPERAND_CTYPE_XED_BITS_T: { + xed_bits_t b; + xed3_get_generic_operand(pi->p,op_name,&b); + + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), + XED_STATIC_CAST(xed_uint_t,b), + pi->blen); + break; + } + case XED_OPERAND_CTYPE_XED_UINT8_T: { + xed_uint32_t b; + xed3_get_generic_operand(pi->p,op_name,&b); + pi->blen = xed_itoa(pi->buf+xed_strlen(pi->buf), + b, + pi->blen); + break; + } + case XED_OPERAND_CTYPE_XED_ERROR_ENUM_T: { + /* DOES NOT OCCUR */ + xed_pi_strcat(pi,"NDY"); + break; + } + case XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T: { + /* DOES NOT OCCUR */ + xed_iclass_enum_t b = xed3_operand_get_iclass(pi->p); + pi->blen = xed_strncat_lower(pi->buf, + xed_iclass_enum_t2str(b), + pi->blen); + break; + } + case XED_OPERAND_CTYPE_XED_REG_ENUM_T: { + /* THIS IS IMPORTANT - THIS IS WHERE REGISTERS GET + * PRINTED */ + xed_reg_enum_t reg; + xed3_get_generic_operand(pi->p,op_name,®); + print_reg_writemask(pi, reg); + break; + } + + default: + xed_pi_strcat(pi,"NOT HANDLING CTYPE "); + xed_pi_strcat(pi, xed_operand_ctype_enum_t2str(ctype)); + xed_assert(0); + } + } + } + xed_print_operand_decorations(pi, op); + } /* for operands */ + + + return 1; +} + + +//////////////////////////////////////////////////////////////////////////// +static xed_bool_t +validate_print_info(xed_print_info_t* pi) +{ + if (pi->p == 0) + return 1; // fail + if (pi->buf == 0) + return 1; // fail + if (pi->blen < 16) + return 1; // fail + return 0; +} + + +xed_bool_t +xed_format_context(xed_syntax_enum_t syntax, + const xed_decoded_inst_t* xedd, + char* out_buffer, + int buffer_len, + xed_uint64_t runtime_instruction_address, + void* context, + xed_disassembly_callback_fn_t symbolic_callback) +{ + xed_print_info_t pi; + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = buffer_len; + pi.buf = out_buffer; + + // passed back to symbolic disassembly function + pi.context = context; + pi.disassembly_callback = symbolic_callback; + + pi.runtime_address = runtime_instruction_address; + pi.syntax = syntax; + pi.format_options_valid = 0; // use defaults + pi.buf[0]=0; //allow use of strcat + return xed_format_generic(&pi); +} + + +// preferred interface (fewer parameters, most flexible) + +xed_bool_t xed_format_generic( xed_print_info_t* pi ) +{ + if (validate_print_info(pi)) + return 0; + + if (pi->syntax == XED_SYNTAX_INTEL) + return xed_decoded_inst_dump_intel_format_internal(pi); + else if (pi->syntax == XED_SYNTAX_ATT) + return xed_decoded_inst_dump_att_format_internal(pi); + else if (pi->syntax == XED_SYNTAX_XED) + return xed_decoded_inst_dump_xed_format(pi->p, + pi->buf, + pi->blen, + pi->runtime_address); + return 0; +} diff --git a/src/xed-enc-dec.c b/src/xed-enc-dec.c new file mode 100644 index 0000000..8fedcc7 --- /dev/null +++ b/src/xed-enc-dec.c @@ -0,0 +1,57 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode.c + +//////////////////////////////////////////////////////////////////////////// +// This file contains the public interface to the encoder. +//////////////////////////////////////////////////////////////////////////// +#include "xed-internal-header.h" +#include "xed-encode-private.h" +#include "xed-operand-accessors.h" + +void xed_encoder_request_init_from_decode(xed_decoded_inst_t* d) { + // copy the non-suppressed operands to the encode order array + const xed_inst_t* inst = d->_inst; + const xed_uint_t noperands = xed_inst_noperands(inst); + xed_uint_t i, eops=0; + for( i=0;i_operand_order[eops++] = xed_operand_name(o); + } + } + d->_n_operand_order=eops; + + // the decoder does not set the iclass field + xed3_operand_set_iclass(d,xed_decoded_inst_get_iclass(d)); + + if (xed3_operand_get_mem0(d)) + xed_decoded_inst_cache_memory_operand_length(d); + + + xed3_operand_set_rex(d,0); + xed3_operand_set_rexb(d,0); + xed3_operand_set_rexr(d,0); + xed3_operand_set_rexw(d,0); + xed3_operand_set_rexx(d,0); + xed3_operand_set_norex(d,0); + xed3_operand_set_needrex(d,0); + xed3_operand_set_osz(d,0); +} diff --git a/src/xed-encode-isa-functions.c b/src/xed-encode-isa-functions.c new file mode 100644 index 0000000..c66d709 --- /dev/null +++ b/src/xed-encode-isa-functions.c @@ -0,0 +1,71 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode-isa-functions.c +/// + +//////////////////////////////////////////////////////////////////////////// +// This file contains the public interface to the encoder. +//////////////////////////////////////////////////////////////////////////// +#include "xed-encode.h" +#include "xed-encode-private.h" +#include "xed-encode-isa-functions.h" +#include "xed-tables-extern.h" +#include "xed-operand-accessors.h" + + + +// FIXME: I could generate these 3 functions: + +static xed_bool_t +xed_encode_nonterminal_INSTRUCTIONS(xed_encoder_request_t* r) +{ + xed_iclass_enum_t iclass; + + // bind function sets the encoding iform index + xed_encode_function_pointer_t bind_func; + + iclass = xed_encoder_request_get_iclass(r); + bind_func = xed_encoder_get_group_encoding_function(iclass); + if (bind_func) { + xed_bool_t okay = (*bind_func)(r); + return okay; + } + return 0; +} + +// These are called during the encoding sequence to look up the right +// encoder functions specific to an iclass. + +xed_bool_t +xed_encode_nonterminal_INSTRUCTIONS_BIND(xed_encoder_request_t* xes) +{ + return xed_encode_nonterminal_INSTRUCTIONS(xes); +} +xed_bool_t +xed_encode_nonterminal_INSTRUCTIONS_EMIT(xed_encoder_request_t* xes) +{ + xed_ptrn_func_ptr_t emit_ptrn_function; + + emit_ptrn_function = xed_encoder_get_emit_ptrn(xes); + (*emit_ptrn_function)(xes); + return 1; + //FIXME: use this in the future + //return xed3_operand_get_error(xes); +} + + diff --git a/src/xed-encode.c b/src/xed-encode.c new file mode 100644 index 0000000..3f114e4 --- /dev/null +++ b/src/xed-encode.c @@ -0,0 +1,548 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode.c + +//////////////////////////////////////////////////////////////////////////// +// This file contains the public interface to the encoder. +//////////////////////////////////////////////////////////////////////////// +#include "xed-internal-header.h" +#include "xed-encode-private.h" +#include "xed-operand-accessors.h" + +#include "xed-encoder.h" // a generated file of prototypes + +//FIXME just need one proto from the above file: xed_bool_t +//xed_encode_nonterminal_ISA_ENCODE(xed_encoder_request_t& xes); + + +const xed_operand_values_t* +xed_encoder_request_operands_const(const xed_encoder_request_t* p) { + return p; +} +xed_operand_values_t* +xed_encoder_request_operands(xed_encoder_request_t* p) { + return p; +} + +// Emitting the legacy map bytes. +// Need to convert from xed_ild_map_enum_t to the actual bytes. +// called from generated code (in OBJDIR/xed-enc-patterns.c) +void xed_encoder_request_emit_legacy_map(xed_encoder_request_t* q) +{ + xed_uint8_t bits; + xed_uint16_t value; + xed_ild_map_enum_t map; + map = XED_STATIC_CAST(xed_ild_map_enum_t,xed_encoder_get_map(q)); + + switch(map) { + case XED_ILD_MAP0: + return; + + case XED_ILD_MAP1: + value = 0x0F; + bits = 8; + break; + + case XED_ILD_MAP2: + value = 0x380F; //need to convert big to little endian + bits = 16; + break; + + case XED_ILD_MAP3: + value = 0x3A0F; //need to convert big to little endian + bits = 16; + break; + + case XED_ILD_MAPAMD: + value = 0x0F0F; + bits = 16; + break; + + default: + xed3_operand_set_error(q,XED_ERROR_GENERAL_ERROR); + return; + + } + xed_encoder_request_emit_bytes(q,bits,value); +} + +void xed_encoder_request_emit_bytes(xed_encoder_request_t* q, + const xed_uint8_t bits, + const xed_uint64_t value){ + + xed_uint32_t byte_offset; + xed_uint8_t* p; + xed_uint32_t bit_offset = xed_encoder_request_bit_offset(q); + + //verify that we are aligned on byte + xed_assert((bit_offset & 7) == 0); + if ( bit_offset + bits > 8 * xed_encoder_request_ilen(q)) { + xed3_operand_set_error(q,XED_ERROR_BUFFER_TOO_SHORT); + return; + } + + byte_offset = bit_offset >> 3; + + xed_encoder_request_update_bit_offset(q, bits); + p = q->_byte_array._enc+byte_offset; + + switch(bits){ + case 8: + *p = XED_STATIC_CAST(xed_uint8_t,value); + break; + case 16: + *XED_REINTERPRET_CAST(xed_uint16_t*,p) = + XED_STATIC_CAST(xed_uint16_t,value); + break; + case 32: + *XED_REINTERPRET_CAST(xed_uint32_t*,p)= + XED_STATIC_CAST(xed_uint32_t,value); + break; + case 64: + *XED_REINTERPRET_CAST(xed_uint64_t*,p)= value; + break; + default: + xed_assert(0); + } + return; +} + + +void xed_encoder_request_encode_emit(xed_encoder_request_t* q, + const unsigned int bits, + const xed_uint64_t value) { + xed_uint32_t nbits; + xed_uint32_t byte_offset; + xed_uint32_t bit_in_byte; + xed_uint32_t processed_bits; + xed_uint32_t t_bit_offset = xed_encoder_request_bit_offset(q); + if ( t_bit_offset + bits > 8 * xed_encoder_request_ilen(q)) { + xed3_operand_set_error(q,XED_ERROR_BUFFER_TOO_SHORT); + return; + } + + nbits = bits; + byte_offset = t_bit_offset >> 3; + bit_in_byte = t_bit_offset & 7; + processed_bits = 0; + + // looking for multiples of 8 on the input and when we are at natural + // byte boundaries in the output. + if ((bits&7) == 0 && bit_in_byte == 0) { + xed_uint8_t* p; + //int shift; + + // the value to encode is a multiple of 8 bits and the current bit + // pointer is aligned on an 8b boundary, then we can jam in the + // bytes efficiently using 8/16/32/64b stores. + xed_encoder_request_update_bit_offset(q, bits); + p = q->_byte_array._enc+byte_offset; + + switch(bits) { + case 8: + *p = XED_STATIC_CAST(xed_uint8_t,value); + break; + case 16: + *XED_REINTERPRET_CAST(xed_uint16_t*,p) = XED_STATIC_CAST(xed_uint16_t,value); + break; + case 32: + *XED_REINTERPRET_CAST(xed_uint32_t*,p)= XED_STATIC_CAST(xed_uint32_t,value); + break; + case 64: + *XED_REINTERPRET_CAST(xed_uint64_t*,p)= value; + break; + default: + xed_assert(0); + } + return; + } + + // for inputs that are not multiples of 8-bits: + while (nbits > 0) { + xed_uint64_t tvalue; // value we'll shift to get to the right bits + xed_uint32_t tbits; // # of bits we are taking in this iteraation + xed_uint32_t bits_remaining_in_byte = 8 - bit_in_byte; + + + if (bits_remaining_in_byte >= nbits) { + // What's left fits in the current byte. + tbits = nbits; + nbits = 0; + tvalue = value; + } + else { + xed_uint32_t vshift; + + // we have more bits than fit in what remains of this + // byte. split it up and take just what remains in this byte. + tbits = bits_remaining_in_byte; + nbits = nbits - tbits; + vshift = bits - processed_bits - tbits; + tvalue = value >> vshift; + processed_bits += tbits; + } + + if (tbits == 8) + q->_byte_array._enc[byte_offset] = XED_STATIC_CAST(xed_uint8_t,tvalue); + else { + xed_uint64_t mask; + xed_uint32_t shift; + + // we will be OR'ing bits in to this byte so it had better + // start off as zero. + if (bit_in_byte == 0) + q->_byte_array._enc[byte_offset] = 0; + + mask = (1<_byte_array._enc[byte_offset] |= XED_STATIC_CAST(xed_uint8_t,(tvalue & mask) << shift); + } + byte_offset++; + bit_in_byte = 0; + } + xed_encoder_request_update_bit_offset(q,bits); +} + + + +xed_bool_t +xed_encoder_request__memop_compatible(const xed_encoder_request_t* p, + xed_operand_width_enum_t operand_width) { + // return 1 if the memop specified in the operand storage is + // compatible with the argument operand_width. + xed_uint16_t operand_width_bytes; + xed_uint16_t request_width_bytes = xed3_operand_get_mem_width(p); + + // figure out the width, in bytes, of the specified operand + xed_uint8_t eosz = xed3_operand_get_eosz(p); + xed_assert(operand_width < XED_OPERAND_WIDTH_LAST); + xed_assert(eosz < 4); + operand_width_bytes = xed_width_bits[operand_width][eosz]>>3; + //variable sized stuff we punt on the width + if (operand_width_bytes == 0 || operand_width_bytes == request_width_bytes) + return 1; + return 0; +} + + +void xed_encoder_request_zero_set_mode(xed_encoder_request_t* p, + const xed_state_t* dstate) { + memset(p, 0, sizeof(xed_encoder_request_t)); + xed_operand_values_set_mode(p,dstate); +} + +void xed_encoder_request_zero(xed_encoder_request_t* p) { + memset(p, 0, sizeof(xed_encoder_request_t)); +} + +xed_iclass_enum_t +xed_encoder_request_get_iclass( const xed_encoder_request_t* p) +{ + return XED_STATIC_CAST(xed_iclass_enum_t,xed3_operand_get_iclass(p)); +} +void xed_encoder_request_set_iclass( xed_encoder_request_t* p, + xed_iclass_enum_t iclass) { + xed3_operand_set_iclass(p,iclass); +} +void xed_encoder_request_set_repne(xed_encoder_request_t* p) { + xed3_operand_set_rep(p,2); +} +void xed_encoder_request_set_rep(xed_encoder_request_t* p) { + xed3_operand_set_rep(p,3); +} +void xed_encoder_request_clear_rep(xed_encoder_request_t* p) { + xed3_operand_set_rep(p,0); +} + + +void +xed_encoder_request_set_effective_operand_width( xed_encoder_request_t* p, + xed_uint_t width_bits) { + switch(width_bits) { + // x87 memops use the width. + case 8: xed3_operand_set_eosz(p,0); break; + + case 16: xed3_operand_set_eosz(p,1); break; + case 32: xed3_operand_set_eosz(p,2); break; + case 64: xed3_operand_set_eosz(p,3); break; + default: + xed_assert( width_bits == 8 || + width_bits == 16 || + width_bits == 32 || + width_bits == 64 ); + break; + } +} +void +xed_encoder_request_set_effective_address_size( xed_encoder_request_t* p, + xed_uint_t width_bits) { + switch(width_bits) { + case 16: xed3_operand_set_easz(p,1); break; + case 32: xed3_operand_set_easz(p,2); break; + case 64: xed3_operand_set_easz(p,3); break; + default: + xed_assert( width_bits == 16 || + width_bits == 32 || + width_bits == 64 ); + break; + } +} + +void xed_encoder_request_set_branch_displacement(xed_encoder_request_t* p, + xed_int32_t brdisp, + xed_uint_t nbytes) { + xed_operand_values_set_branch_displacement(p, brdisp, nbytes); +} + +void xed_encoder_request_set_relbr(xed_encoder_request_t* p) { + xed3_operand_set_relbr(p,1); +} +void xed_encoder_request_set_ptr(xed_encoder_request_t* p) { + xed3_operand_set_ptr(p,1); +} + +void xed_encoder_request_set_memory_displacement(xed_encoder_request_t* p, + xed_int64_t memdisp, + xed_uint_t nbytes) { + xed_operand_values_set_memory_displacement(p, memdisp, nbytes); +} + +void xed_encoder_request_set_uimm0(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbytes) { + xed_operand_values_set_immediate_unsigned(p, uimm, nbytes); + xed3_operand_set_imm0(p,1); +} + +void xed_encoder_request_set_uimm0_bits(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbits) { + xed_operand_values_set_immediate_unsigned_bits(p, uimm, nbits); + xed3_operand_set_imm0(p,1); +} +void xed_encoder_request_set_uimm1(xed_encoder_request_t* p, + xed_uint8_t uimm) { + xed3_operand_set_imm1(p,1); + xed3_operand_set_uimm1(p,uimm); +} + +void xed_encoder_request_set_simm(xed_encoder_request_t* p, + xed_int32_t simm, + xed_uint_t nbytes) { + + xed_operand_values_set_immediate_signed(p, simm, nbytes); + xed3_operand_set_imm0(p,1); +} + +void xed_encoder_request_set_agen(xed_encoder_request_t* p) { + xed3_operand_set_agen(p,1); +} +void xed_encoder_request_set_mem0(xed_encoder_request_t* p) { + xed3_operand_set_mem0(p,1); +} +void xed_encoder_request_set_mem1(xed_encoder_request_t* p) { + xed3_operand_set_mem1(p,1); +} +void xed_encoder_request_set_memory_operand_length(xed_encoder_request_t* p, + xed_uint_t nbytes) { + xed3_operand_set_mem_width(p,nbytes); +} +void xed_encoder_request_set_seg0(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg) { + xed3_operand_set_seg0(p,seg_reg); +} +void xed_encoder_request_set_seg1(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg) { + xed3_operand_set_seg1(p,seg_reg); +} +void xed_encoder_request_set_base0(xed_encoder_request_t* p, + xed_reg_enum_t base_reg) { + xed3_operand_set_base0(p,base_reg); +} +void xed_encoder_request_set_base1(xed_encoder_request_t* p, + xed_reg_enum_t base_reg) { + xed3_operand_set_base1(p,base_reg); +} +void xed_encoder_request_set_index(xed_encoder_request_t* p, + xed_reg_enum_t index_reg) { + xed3_operand_set_index(p,index_reg); +} +void xed_encoder_request_set_scale(xed_encoder_request_t* p, + xed_uint_t scale) { + xed3_operand_set_scale(p,scale); +} + +void xed_encoder_request_set_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index, + xed_operand_enum_t name) { + xed_assert(operand_index < XED_ENCODE_ORDER_MAX_OPERANDS); + p->_operand_order[operand_index] = name; + + /* track the maximum number of operands */ + if (operand_index+1 > p->_n_operand_order) + p->_n_operand_order = operand_index + 1; +} + +xed_operand_enum_t +xed_encoder_request_get_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index) { + xed_assert(operand_index < XED_ENCODE_ORDER_MAX_OPERANDS && + operand_index < p->_n_operand_order); + return XED_STATIC_CAST(xed_operand_enum_t,p->_operand_order[operand_index]); +} + + +void xed_encoder_request_zero_operand_order(xed_encoder_request_t* p) { + p->_n_operand_order = 0; +} + +void xed_encoder_request_set_reg(xed_encoder_request_t* p, + xed_operand_enum_t operand, + xed_reg_enum_t reg) { + xed_assert(operand < XED_OPERAND_LAST); + xed_operand_values_set_operand_reg(p,operand,reg); +} + +void +xed_encode_request_print(const xed_encoder_request_t* p, + char* buf, + xed_uint_t buflen) { + char* t; + xed_uint_t i; + xed_uint_t blen = buflen; + if (buflen < 1000) { + (void)xed_strncpy(buf, + "Buffer passed to xed_encode_request_print is " + "too short. Try 1000 bytes", + buflen); + return; + } + blen = xed_strncpy(buf, + xed_iclass_enum_t2str(xed_encoder_request_get_iclass(p)), + blen); + blen = xed_strncat(buf, " ",blen); + t = buf + xed_strlen(buf); + xed_operand_values_print_short( p, t, blen); + blen = buflen - xed_strlen(buf); + + if (p->_n_operand_order) { + blen = xed_strncat(buf,"\nOPERAND ORDER: ",blen); + for(i=0;i_n_operand_order;i++) { + const char* s = xed_operand_enum_t2str(XED_STATIC_CAST(xed_operand_enum_t,p->_operand_order[i])); + blen = xed_strncat(buf, s, blen); + blen = xed_strncat(buf, " ", blen); + } + } + (void) xed_strncat(buf, "\n", blen); +} + + +////////////////////////////////////////////////////////////////////////////////////////////// +//FIXME: I am not fond of this fixed table, since it is a testament to +//how difficult it is to encode instructions. One day, I'll make this +//use the XED encoding engine. +#define XED_MAX_FIXED_NOPS 9 +static const xed_uint8_t xed_nop_array[XED_MAX_FIXED_NOPS][XED_MAX_FIXED_NOPS] = { + /*1B*/ { 0x90 }, + /*2B*/ { 0x66, 0x90}, + /*3B*/ { 0x0F, 0x1F, 0x00}, + /*4B*/ { 0x0F, 0x1F, 0x40, 0x00}, + /*5B*/ { 0x0F, 0x1F, 0x44, 0x00, 0x00}, + /*6B*/ { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00}, + /*7B*/ { 0x0F, 0x1F, 0x80, 0x00, 0x00,0x00, 0x00}, + /*8B*/ { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00,0x00, 0x00}, + /*9B*/ { 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00,0x00, 0x00}, +}; + +XED_DLL_EXPORT xed_error_enum_t +xed_encode_nop(xed_uint8_t* array, + const unsigned int ilen) +{ + if (ilen >= 1 && ilen <= XED_MAX_FIXED_NOPS) { + // subtract one from the requested length to get the array index. + memcpy(array, xed_nop_array[ilen-1], ilen); + return XED_ERROR_NONE; + } + return XED_ERROR_GENERAL_ERROR; +} + + +static void xed_encode_precondition(xed_encoder_request_t* r) { + /* If the base is RIP, then we help the encoder users by adjusting or + * supplying a memory displacement. It must be 4B, even if it is zero. + * + * This ignores the case of a 2B displacement. No one should do that as + * it is not legal in 64b mode. + */ + xed_int64_t t; + if (xed3_operand_get_base0(r)==XED_REG_RIP) { + if (xed3_operand_get_disp_width(r) == 0) { + xed3_operand_set_disp_width(r,32); + xed3_operand_set_disp(r,0); + } + else if (xed3_operand_get_disp_width(r) == 8) { + xed3_operand_set_disp_width(r,32); + /* sign extend the current value to 64b and then pick off the + * correct part of it */ + t = xed3_operand_get_disp(r); + xed_operand_values_set_memory_displacement_bits(r, + t, 32); + } + } +} + +XED_DLL_EXPORT xed_error_enum_t xed_encode(xed_encoder_request_t* r, + xed_uint8_t* array, + const unsigned int ilen, + unsigned int* olen) { + xed_iclass_enum_t iclass = xed_encoder_request_get_iclass(r); + if (iclass != XED_ICLASS_INVALID && + iclass < XED_ICLASS_LAST && + ilen > 0 && + array != 0) + { + xed_bool_t okay; + xed_encoder_vars_t xev; + r->_byte_array._enc = array; + + // FIRST THING: set up the ephemeral storage for the encoder + xed_encoder_request_set_encoder_vars(r,&xev); + + xed_encoder_request_set_ilen(r,ilen); + xed_encode_precondition(r); + okay = xed_encode_nonterminal_ISA_ENCODE(r); + + if (okay) { + xed_uint32_t t_bit_offset = xed_encoder_request_bit_offset(r); + xed_assert((t_bit_offset & 7) == 0); // no partial bytes + *olen = (t_bit_offset >> 3); // offset points to the 1st bit of next byte + xed_assert(ilen >= *olen); + xed_encoder_request_vars_remove(r); + return XED_ERROR_NONE; + } + xed_encoder_request_vars_remove(r); + if (xed3_operand_get_error(r) != XED_ERROR_NONE) + return xed3_operand_get_error(r); + return XED_ERROR_GENERAL_ERROR; + } + return XED_ERROR_GENERAL_ERROR; +} + + + + diff --git a/src/xed-encoder-hl.c b/src/xed-encoder-hl.c new file mode 100644 index 0000000..65e1a16 --- /dev/null +++ b/src/xed-encoder-hl.c @@ -0,0 +1,177 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encoder-hl.c + +#include "xed-encoder-hl.h" +#include "xed-reg-class-enum.h" +#include "xed-reg-class.h" +#include "xed-operand-accessors.h" + +/// convert a #xed_encoder_instruction_t to a #xed_encoder_request_t for encoding +xed_bool_t xed_convert_to_encoder_request(xed_encoder_request_t* out, + xed_encoder_instruction_t* in) { + + /* this is basically what the encoder language example code does but in + * a more uniform way. */ + xed_uint_t real_operands = 0; + xed_uint_t i=0; + xed_uint_t memops = 0; + xed_uint_t regs = 0; + xed_encoder_request_zero_set_mode(out, &(in->mode)); + xed_encoder_request_set_iclass(out, in->iclass ); + if (in->effective_operand_width) + xed_encoder_request_set_effective_operand_width(out, in->effective_operand_width); + if (in->effective_address_width) + xed_encoder_request_set_effective_address_size(out, in->effective_address_width); + + if (in->prefixes.s.rep) + xed_encoder_request_set_rep(out); + if (in->prefixes.s.repne) + xed_encoder_request_set_repne(out); +#if 0 // FIXME + if (in->prefixes.s.br_hint_taken) + xed_encoder_request_set_hint_taken(out); + if (in->prefixes.s.br_hint_not_taken) + xed_encoder_request_set_hint_not_taken(out); +#endif + + + for(; i< in->noperands ; i++ ) { + xed_encoder_operand_t* op = in->operands + i; + switch(op->type) { + case XED_ENCODER_OPERAND_TYPE_PTR: + xed_encoder_request_set_branch_displacement(out, + op->u.brdisp, + op->width_bits/8); //FIXME: bits interface + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_PTR); + xed_encoder_request_set_ptr(out); + real_operands++; + break; + + case XED_ENCODER_OPERAND_TYPE_BRDISP: + xed_encoder_request_set_branch_displacement(out, + op->u.brdisp, + op->width_bits/8); //FIXME: bits interface + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_RELBR); + xed_encoder_request_set_relbr(out); + real_operands++; + break; + + case XED_ENCODER_OPERAND_TYPE_SEG0: + xed_encoder_request_set_seg0(out, op->u.reg); + break; + + case XED_ENCODER_OPERAND_TYPE_SEG1: + xed_encoder_request_set_seg1(out, op->u.reg); + break; + + case XED_ENCODER_OPERAND_TYPE_REG: { + xed_operand_enum_t r = XED_STATIC_CAST(xed_operand_enum_t,XED_OPERAND_REG0 + regs); + xed_encoder_request_set_reg(out, r, op->u.reg); + xed_encoder_request_set_operand_order(out, real_operands, r); + real_operands++; + regs++; + break; + } + + + case XED_ENCODER_OPERAND_TYPE_IMM0: + + xed_encoder_request_set_uimm0_bits(out, + op->u.imm0, + op->width_bits); + xed_encoder_request_set_operand_order(out, real_operands , XED_OPERAND_IMM0); + real_operands++; + break; + + case XED_ENCODER_OPERAND_TYPE_SIMM0: + /* the max width of a signed immediate is 32b. */ + xed_encoder_request_set_simm(out, + XED_STATIC_CAST(xed_int32_t,op->u.imm0), + op->width_bits/8); //FIXME: bits interface + xed_encoder_request_set_operand_order(out, real_operands , XED_OPERAND_IMM0); + real_operands++; + break; + + case XED_ENCODER_OPERAND_TYPE_IMM1: + xed_encoder_request_set_uimm1(out, op->u.imm1); + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_IMM1); + real_operands++; + break; + + case XED_ENCODER_OPERAND_TYPE_OTHER: + xed3_set_generic_operand(out, op->u.s.operand_name, op->u.s.value); + //xed_encoder_request_set_operand_order(out, real_operands, op->u.s.operand_name); + //real_operands++; + //FIXME: What is this ??? + xed_assert(0); + break; + + case XED_ENCODER_OPERAND_TYPE_MEM: + { + xed_reg_class_enum_t rc = xed_gpr_reg_class(op->u.mem.base); + xed_reg_class_enum_t rci = xed_gpr_reg_class(op->u.mem.index); + if (rc == XED_REG_CLASS_GPR32 || rci == XED_REG_CLASS_GPR32) + xed_encoder_request_set_effective_address_size(out, 32); + if (rc == XED_REG_CLASS_GPR16 || rci == XED_REG_CLASS_GPR16) + xed_encoder_request_set_effective_address_size(out, 16); + } + + if (in->iclass == XED_ICLASS_LEA) { + xed_encoder_request_set_agen(out); + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_AGEN); + } + else if (memops == 0) { + xed_encoder_request_set_mem0(out); + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_MEM0); + } + else { + xed_encoder_request_set_mem1(out); + xed_encoder_request_set_operand_order(out, real_operands, XED_OPERAND_MEM1); + } + real_operands++; + + if (memops == 0) { + xed_encoder_request_set_base0(out, op->u.mem.base); + xed_encoder_request_set_index(out, op->u.mem.index); + xed_encoder_request_set_scale(out, op->u.mem.scale); + xed_encoder_request_set_seg0(out, op->u.mem.seg); + } + else { + xed_encoder_request_set_base1(out, op->u.mem.base); + xed_encoder_request_set_seg1(out, op->u.mem.seg); + } + + xed_encoder_request_set_memory_operand_length(out, op->width_bits>>3 ); // CVT TO BYTES -- FIXME make bits interface + + if (op->u.mem.disp.displacement_bits) + xed_encoder_request_set_memory_displacement(out, + op->u.mem.disp.displacement, + op->u.mem.disp.displacement_bits/8); //FIXME: make bits interface + + memops++; + break; + case XED_ENCODER_OPERAND_TYPE_INVALID: + default: + return 0; + } + } + + return 1; +} + diff --git a/src/xed-flags.c b/src/xed-flags.c new file mode 100644 index 0000000..3c33746 --- /dev/null +++ b/src/xed-flags.c @@ -0,0 +1,227 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flags.cpp +/// +#include "xed-flags.h" +#include "xed-flags-private.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-tables-extern.h" +#include //memset + +xed_bool_t +xed_flag_set_is_subset_of(const xed_flag_set_t* p, const xed_flag_set_t* other) +{ + xed_uint32_t conj = p->flat & other->flat; + return (conj == p->flat); +} + + +int xed_flag_set_print(const xed_flag_set_t* p, char* buf, int buflen) { + int blen = buflen; + *buf = 0; // start w/null terminated + if (p->s.of) { blen = xed_strncat(buf, "of ",blen);} + if (p->s.sf) { blen = xed_strncat(buf, "sf ",blen);} + if (p->s.zf) { blen = xed_strncat(buf, "zf ",blen);} + if (p->s.af) { blen = xed_strncat(buf, "af ",blen);} + if (p->s.pf) { blen = xed_strncat(buf, "pf ",blen);} + if (p->s.cf) { blen = xed_strncat(buf, "cf ",blen);} + if (p->s.df) { blen = xed_strncat(buf, "df ",blen);} + if (p->s.vif) { blen = xed_strncat(buf, "vif ",blen);} + if (p->s.iopl) { blen = xed_strncat(buf, "iopl ",blen);} + if (p->s._if) { blen = xed_strncat(buf, "if ",blen);} + if (p->s.ac) { blen = xed_strncat(buf, "ac ",blen);} + if (p->s.vm) { blen = xed_strncat(buf, "vm ",blen);} + if (p->s.rf) { blen = xed_strncat(buf, "rf ",blen);} + if (p->s.nt) { blen = xed_strncat(buf, "nt ",blen);} + if (p->s.tf) { blen = xed_strncat(buf, "tf ",blen);} + if (p->s.id) { blen = xed_strncat(buf, "id ",blen);} + if (p->s.vip) { blen = xed_strncat(buf, "vip ",blen);} + if (p->s.fc0) { blen = xed_strncat(buf, "fc0 ",blen);} + if (p->s.fc1) { blen = xed_strncat(buf, "fc1 ",blen);} + if (p->s.fc2) { blen = xed_strncat(buf, "fc2 ",blen);} + if (p->s.fc3) { blen = xed_strncat(buf, "fc3 ",blen);} + return blen; +} + + + +/// @name Flag accessors +//@{ + +/// get the name of the flag +xed_flag_enum_t +xed_flag_action_get_flag_name(const xed_flag_action_t* p) { + return p->flag; +} + +/// return the action +xed_flag_action_enum_t +xed_flag_action_get_action(const xed_flag_action_t* p, unsigned int i) { + return p->action; + (void)i; // pacify compiler warnings +} + +/// returns 1 if the specified action is invalid. Only the 2nd flag might +/// be invalid. +xed_bool_t +xed_flag_action_action_invalid(const xed_flag_action_enum_t a) { + return (a == XED_FLAG_ACTION_INVALID); +} + +/// print the flag & actions +int xed_flag_action_print(const xed_flag_action_t* p, char* buf, int buflen) { + int blen = buflen; + blen = xed_strncpy(buf, xed_flag_enum_t2str(p->flag),blen); + if (p->action != XED_FLAG_ACTION_INVALID) { + blen = xed_strncat(buf, "-",blen); + blen = xed_strncat(buf, xed_flag_action_enum_t2str(p->action), blen); + } + return blen; +} + +/// returns 1 if either action is a read +xed_bool_t +xed_flag_action_read_flag(const xed_flag_action_t* p ) { + return xed_flag_action_read_action(p->action); +} + +/// returns 1 if either action is a write +xed_bool_t +xed_flag_action_writes_flag(const xed_flag_action_t* p) { + return xed_flag_action_write_action(p->action); +} + + +/// test to see if the specific action is a read +xed_bool_t +xed_flag_action_read_action( xed_flag_action_enum_t a) { + return (a == XED_FLAG_ACTION_tst); +} + +/// test to see if a specific action is a write +xed_bool_t +xed_flag_action_write_action( xed_flag_action_enum_t a) { + switch(a) { + case XED_FLAG_ACTION_mod: + case XED_FLAG_ACTION_0: + case XED_FLAG_ACTION_1: + case XED_FLAG_ACTION_ah: + case XED_FLAG_ACTION_pop: + case XED_FLAG_ACTION_u: + return 1; + default: + return 0; + } +} +//@} + +//////////////////////////////////////////////////////////////////////////// + + +/// @name Accessing the flags +//@{ +/// returns the number of flag-actions +unsigned int +xed_simple_flag_get_nflags(const xed_simple_flag_t* p) { + return p->nflags; +} + +/// return union of bits for read flags +const xed_flag_set_t* +xed_simple_flag_get_read_flag_set(const xed_simple_flag_t* p) { + return &(p->read); +} + +/// return union of bits for written flags +const xed_flag_set_t* +xed_simple_flag_get_written_flag_set(const xed_simple_flag_t* p) { + return &(p->written); +} + +/// return union of bits for undefined flags +const xed_flag_set_t* +xed_simple_flag_get_undefined_flag_set(const xed_simple_flag_t* p) { + return &(p->undefined); +} + +xed_bool_t xed_simple_flag_get_may_write(const xed_simple_flag_t* p) { + return p->may_write; +} + +xed_bool_t xed_simple_flag_get_must_write(const xed_simple_flag_t* p) { + return p->must_write; +} + + +/// return the specific flag-action +const xed_flag_action_t* +xed_simple_flag_get_flag_action(const xed_simple_flag_t* p, unsigned int i) { + xed_assert(i < p->nflags); + return xed_flag_action_table + p->fa_index+i; +} + +/// boolean test to see if flags are read, scans the flags +xed_bool_t +xed_simple_flag_reads_flags(const xed_simple_flag_t* p) { + int i; + for( i=0;inflags ;i++) + if ( xed_flag_action_read_flag(xed_flag_action_table + p->fa_index+i) ) + return 1; + return 0; +} + +/// boolean test to see if flags are written, scans the flags +xed_bool_t xed_simple_flag_writes_flags(const xed_simple_flag_t* p) { + int i; + for( i=0;inflags ;i++) + if ( xed_flag_action_writes_flag(xed_flag_action_table +p->fa_index+i)) + return 1; + return 0; +} +/// print the flags +int xed_simple_flag_print(const xed_simple_flag_t* p, char* buf, + int buflen) +{ + unsigned int i,n; + char tbuf[100]; + int blen = buflen; + if (xed_simple_flag_get_may_write(p)) + blen = xed_strncat(buf, "MAY-WRITE ",blen); + if (xed_simple_flag_get_must_write(p)) + blen = xed_strncat(buf, "MUST-WRITE ",blen); + n = p->nflags; + for( i=0;iread, tbuf,100); + blen = xed_strncat(buf,tbuf,blen); + blen = xed_strncat(buf,"\n\tFlags written: ",blen); + (void) xed_flag_set_print(&p->written, tbuf, 100); + blen = xed_strncat(buf,tbuf,blen); + return blen; +} +//@} + + diff --git a/src/xed-iform-map.c b/src/xed-iform-map.c new file mode 100644 index 0000000..2b728e5 --- /dev/null +++ b/src/xed-iform-map.c @@ -0,0 +1,89 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iform-map.c + +#include "xed-internal-header.h" +#include "xed-decoded-inst.h" +#include "xed-iform-map.h" +//////////////////////////////////////////////////////////////////////////// + +const xed_iform_info_t* xed_iform_map(xed_iform_enum_t iform) { + + if (iform < XED_IFORM_LAST) { + const xed_iform_info_t* p = xed_iform_db + iform; + return p; + } + return 0; +} + +xed_uint32_t xed_iform_max_per_iclass(xed_iclass_enum_t iclass) { + + xed_assert(iclass < XED_ICLASS_LAST); + return xed_iform_max_per_iclass_table[iclass]; +} + + +xed_uint32_t xed_iform_first_per_iclass(xed_iclass_enum_t iclass) { + + xed_assert(iclass < XED_ICLASS_LAST); + return xed_iform_first_per_iclass_table[iclass]; +} + +xed_category_enum_t xed_iform_to_category(xed_iform_enum_t iform) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) + return (xed_category_enum_t) ii->category; + return XED_CATEGORY_INVALID; +} +xed_extension_enum_t xed_iform_to_extension(xed_iform_enum_t iform) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) + return (xed_extension_enum_t)ii->extension; + return XED_EXTENSION_INVALID; +} + +xed_isa_set_enum_t xed_iform_to_isa_set(xed_iform_enum_t iform) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) + return (xed_isa_set_enum_t)ii->isa_set; + return XED_ISA_SET_INVALID; +} + + +char const* xed_iform_to_iclass_string(xed_iform_enum_t iform, int att) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) { + if (ii->string_table_idx) { + char const* p = 0; + xed_assert(ii->string_table_idx + att < XED_ICLASS_NAME_STR_MAX); + p = xed_iclass_string[ii->string_table_idx + att]; + if (p) + return p; + } + return xed_iclass_enum_t2str( ii->iclass ); + } + return "unknown"; +} + +char const* xed_iform_to_iclass_string_att(xed_iform_enum_t iform) { + return xed_iform_to_iclass_string(iform, 1); +} + +char const* xed_iform_to_iclass_string_intel(xed_iform_enum_t iform) { + return xed_iform_to_iclass_string(iform, 0); +} diff --git a/src/xed-ild-support.c b/src/xed-ild-support.c new file mode 100644 index 0000000..fd0ad43 --- /dev/null +++ b/src/xed-ild-support.c @@ -0,0 +1,140 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// 2014-11-20: This file has code duplication with other parts of the XED +// code base. It is intended to be the bare minimum required to allow +// clients to use the ILD standalone (libxed-ild) library. Ultimately, I +// should remove the code duplication by splitting a few more of the files. + +#include "xed-types.h" +#include "xed-util.h" +#include "xed-portability.h" +#include "xed-portability-private.h" +#include "xed-common-defs.h" +#include "xed-common-hdrs.h" +#include "xed-state.h" +#include "xed-decoded-inst.h" +#include "xed-operand-accessors.h" + +#include //fprint, stderr +#include //memset + +#if defined(__linux__) && defined(__STDC_HOSTED__) && __STDC_HOSTED__ == 0 + extern void abort (void) __attribute__ ((__noreturn__)); +#else +# include +#endif + +int xed_verbose=2; +#if defined(XED_MESSAGES) +FILE* xed_log_file; +#endif + +void xed_derror(const char* s) { + XED2DIE((xed_log_file,"%s\n", s)); + (void)s; //pacify compiler when msgs are disabled +} + +static xed_user_abort_function_t xed_user_abort_function = 0; + + +static void* xed_user_abort_other = 0; + +void xed_register_abort_function(xed_user_abort_function_t fn, + void* other) { + xed_user_abort_function = fn; + xed_user_abort_other = other; +} + +void xed_internal_assert( const char* msg, const char* file, int line) { + if (xed_user_abort_function) { + (*xed_user_abort_function)(msg, file, line, xed_user_abort_other); + } + else { + fprintf(stderr,"ASSERTION FAILURE %s at %s:%d\n", msg, file, line); + } + abort(); +} + + + + +void xed_operand_values_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate) { + + /* set MODE, SMODE and REALMODE */ + xed3_operand_set_realmode(p,0); + switch(xed_state_get_machine_mode(dstate)) + { + case XED_MACHINE_MODE_LONG_64: + xed3_operand_set_mode(p,2); + xed3_operand_set_smode(p,2); + return; + + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LONG_COMPAT_32: + xed3_operand_set_mode(p,1); + break; + + case XED_MACHINE_MODE_REAL_16: + xed3_operand_set_realmode(p,1); + xed3_operand_set_mode(p,0); + break; + + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_LONG_COMPAT_16: + xed3_operand_set_mode(p,0); + break; + default: + xed_derror("Bad machine mode in xed_operand_values_set_mode() call"); + } + + // 64b mode returns above. this is for 16/32b modes only + switch(xed_state_get_stack_address_width(dstate)) { + case XED_ADDRESS_WIDTH_16b: + xed3_operand_set_smode(p,0); + break; + case XED_ADDRESS_WIDTH_32b: + xed3_operand_set_smode(p,1); + break; + default: + break; + } +} + +XED_DLL_EXPORT void +xed_decoded_inst_zero_set_mode(xed_decoded_inst_t* p, + const xed_state_t* dstate) +{ + memset(p, 0, sizeof(xed_decoded_inst_t)); + xed_operand_values_set_mode(p,dstate); +} + +void xed_set_verbosity(int v) { + xed_verbose = v; +} + +void xed_set_log_file(void* o) { +#if defined(XED_MESSAGES) + xed_log_file = (FILE*)o; +#else + (void)o; +#endif + +} + diff --git a/src/xed-ild.c b/src/xed-ild.c new file mode 100644 index 0000000..9d1c66a --- /dev/null +++ b/src/xed-ild.c @@ -0,0 +1,1637 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-ild.c +/// instruction length decoder + +/* + FIXME: + + need these opcode/mode/prefix based tables: + has_modrm (boolean) + disp_bytes = 1,2,4,8 bytes + imm_bytes = 1,2,4,8 bytes + + >90% instructions have MODRM. + + Key on the MOD pattern prebinding + + >90% of the displacements come from the MODRM.MOD byte processing. + + Some come from the pattern: + Nonterminals: BRDISP8, BRDISP32, MEMDISPv, BRDISPz + + >90% of the are 1B and come from using map3. + + xed grammar has UIMM32, UIMM16, UIMM8,UIMM8_1, SIMM8, SIMMz. The + signed/unsigned should move to an attribute or the xed_inst_t. The + UIMM32 is used on AMD XOP instructions. + + uimm16: opcodes 9A, C2, C8, CA, EA + + */ + + /* FIXME:we might have invalid map (TNI maps) - in this case + * we should check for it before looking up in tables for + * modrm/imm/disp/static decoding + * Also invalid map value cannot be 0xFF - we allocate 3 bits + * for MAP operand in key for static lookup. + */ + +#include "xed-internal-header.h" +#include "xed-ild.h" +#include "xed-util-private.h" +#include // strcmp + +#include "xed-ild-modrm.h" +#include "xed-ild-disp-bytes.h" +#include "xed-ild-imm-bytes.h" +#include "xed-operand-accessors.h" + + + +static XED_INLINE int xed3_mode_64b(xed_decoded_inst_t* d) { + return (xed3_operand_get_mode(d) == XED_GRAMMAR_MODE_64); +} + +/* + * The scanners cannot return arbitrarily. They MUST return by calling the + * next scanner. + */ + + +static void init_has_disp_regular_table(void); +static void init_eamode_table(void); +static void init_has_sib_table(void); +static void set_has_modrm(xed_decoded_inst_t* d); + + + +static void set_hint(xed_uint8_t b, xed_decoded_inst_t* d){ + switch(b){ + case 0x2e: + xed3_operand_set_hint(d, 1); + return; + case 0x3e: + xed3_operand_set_hint(d, 2); + return; + default: + xed_assert(0); + } +} + +// conservative filter table for fast prefix checking +// 2014-07-30: +// Timing perftest: 2-6% gain +// Without the filter: +// Average: 384.08s Minimum: 352.74s +// With the filter: +// Average: 362.97s Minimum: 346.26s +// Could use 2x the space and the 64b mode thing to pick the right table. +// That would speed up 32b prefix decodes. + +#define XED_PREFIX_TABLE_SIZE 8 +static xed_uint32_t prefix_table[XED_PREFIX_TABLE_SIZE]; // 32B=256b 32*8=2^5*2^3 + +static void set_prefix_table_bit(xed_uint8_t a) +{ + xed_uint32_t x = a >> 5; + xed_uint32_t y = a & 0x1F; + prefix_table[x] |= (1<> 5; + xed_uint32_t y = a & 0x1F; + return (prefix_table[x] >> y ) & 1; +} + +static void init_prefix_table(void); +static void init_prefix_table(void) +{ + int i; + static xed_uint8_t legacy_prefixes[] = { + 0xF0, // lock + 0x66, // osz + 0x67, // asz + + 0xF2, 0xF3, // rep/repne + + 0x2E, 0x3E, // 6 segment prefixes + 0x26, 0x36, + 0x64, 0x65, + + 0 // sentinel + }; + + for (i=0;i= XED_MAX_INSTRUCTION_BYTES) + xed3_operand_set_error(d,XED_ERROR_INSTR_TOO_LONG); + else + xed3_operand_set_error(d,XED_ERROR_BUFFER_TOO_SHORT); +} + +static void XED_NOINLINE bad_map(xed_decoded_inst_t* d) +{ + xed3_operand_set_map(d,XED_ILD_MAP_INVALID); + xed3_operand_set_error(d,XED_ERROR_BAD_MAP); +} + +#if defined(XED_SUPPORTS_AVX512) +static void XED_NOINLINE bad_v4(xed_decoded_inst_t* d) +{ + xed3_operand_set_error(d,XED_ERROR_BAD_EVEX_V_PRIME); +} +#endif + +static void prefix_scanner(xed_decoded_inst_t* d) +{ + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t nprefixes = 0; + xed_uint8_t nseg_prefixes = 0; + xed_uint8_t nrexes = 0; + unsigned char rex = 0; + + while(length < max_bytes) + { + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + + // fast check to see if something might be a prefix + // includes REX prefixes in 32b mode + if (get_prefix_table_bit(b)==0) + goto out; + + switch(b) { + case 0x66: + xed3_operand_set_osz(d, 1); + xed3_operand_set_prefix66(d, 1); + /*ignore possible REX prefix encoutered earlier */ + rex = 0; + break; + + case 0x67: + xed3_operand_set_asz(d, 1); + rex = 0; + break; + + /* segment prefixes */ + case 0x2E: + case 0x3E: + set_hint(b,d); + //INTENTIONAL FALLTHROUGH + case 0x26: + case 0x36: + if (xed3_mode_64b(d)==0) + xed3_operand_set_ild_seg(d, b); + nseg_prefixes++; + /*ignore possible REX prefix encountered earlier */ + rex = 0; + + break; + case 0x64: + case 0x65: + //for 64b mode we are ignoring non valid segment prefixes + //only FS=0x64 and GS=0x64 are valid for 64b mode + xed3_operand_set_ild_seg(d, b); + + nseg_prefixes++; + /*ignore possible REX prefix encountered earlier */ + rex = 0; + break; + + case 0xF0: + xed3_operand_set_lock(d, 1); + rex = 0; + break; + + case 0xF3: + xed3_operand_set_ild_f3(d, 1); + xed3_operand_set_last_f2f3(d, 3); + if(xed3_operand_get_first_f2f3(d) == 0) + xed3_operand_set_first_f2f3(d, 3); + + rex = 0; + break; + + case 0xF2: + xed3_operand_set_ild_f2(d, 1); + xed3_operand_set_last_f2f3(d, 2); + if(xed3_operand_get_first_f2f3(d) == 0) + xed3_operand_set_first_f2f3(d, 2); + + rex = 0; + break; + + default: + /*Take care of REX prefix */ + if (xed3_mode_64b(d) && + (b & 0xf0) == 0x40) { + nrexes++; + rex = b; + } + else + goto out; + } + length++; + nprefixes++; + } +out: + //set counts + xed_decoded_inst_set_length(d, length); + xed3_operand_set_nprefixes(d, nprefixes); + xed3_operand_set_nseg_prefixes(d, nseg_prefixes); + xed3_operand_set_nrexes(d, nrexes); + + //set REX, REXW, etc. + if (rex) { + xed3_operand_set_rexw(d, (rex>>3) & 1); + xed3_operand_set_rexr(d, (rex>>2) & 1); + xed3_operand_set_rexx(d, (rex>>1) & 1); + xed3_operand_set_rexb(d, (rex) & 1); + xed3_operand_set_rex(d, 1); + } + + //set REP and REFINING + if (xed3_operand_get_mode_first_prefix(d)) + xed3_operand_set_rep(d, xed3_operand_get_first_f2f3(d)); + else + xed3_operand_set_rep(d, xed3_operand_get_last_f2f3(d)); + + //set SEG_OVD + /*FIXME: lookup table for seg_ovd ? */ + /*FIXME: make the grammar use the raw byte value instead of the 1..6 + * recoding */ + switch(xed3_operand_get_ild_seg(d)) { + case 0x2e: + xed3_operand_set_seg_ovd(d, 1); + break; + case 0x3e: + xed3_operand_set_seg_ovd(d, 2); + break; + case 0x26: + xed3_operand_set_seg_ovd(d, 3); + break; + case 0x64: + xed3_operand_set_seg_ovd(d, 4); + break; + case 0x65: + xed3_operand_set_seg_ovd(d, 5); + break; + case 0x36: + xed3_operand_set_seg_ovd(d, 6); + break; + default: + break; + } + + //check max bytes + if (length >= max_bytes) { + /* all available length was taken by prefixes, but we for sure need + * at least one additional byte for an opcode, hence we are out of + * bytes. */ + too_short(d); + return; + } +} + +#if defined(XED_AVX) || defined(XED_SUPPORTS_KNC) +//VEX_PREFIX use 2 as F2 and 3 as F3 so table is required. +static unsigned int vex_prefix_recoding[/*pp*/] = { 0,1,3,2 }; +#endif + +#if defined(XED_AVX) + +typedef union { // C4 payload 1 + struct { + xed_uint32_t map:5; + xed_uint32_t b_inv:1; + xed_uint32_t x_inv:1; + xed_uint32_t r_inv:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx_c4_payload1_t; + +typedef union { // C4 payload 2 + struct { + xed_uint32_t pp:2; + xed_uint32_t l:1; + xed_uint32_t vvv210:3; + xed_uint32_t v3:1; + xed_uint32_t w:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx_c4_payload2_t; + +typedef union { // C5 payload 1 + struct { + xed_uint32_t pp:2; + xed_uint32_t l:1; + xed_uint32_t vvv210:3; + xed_uint32_t v3:1; + xed_uint32_t r_inv:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx_c5_payload_t; + +static void evex_vex_opcode_scanner(xed_decoded_inst_t* d); //prototype + +static void vex_c4_scanner(xed_decoded_inst_t* d) +{ + /* assumption: length < max_bytes + * This is checked in prefix_scanner. + * If any other scanner is added before vex_scanner, this condition + * should be preserved. + * FIXME: check length < max_bytes here anyway? This will be less + * error-prone, but that's an additional non-necessary branch. + */ + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + if (xed3_mode_64b(d)) { + length++; /* eat the c4/c5 */ + } + /* we don't need to check (d->length < d->max_bytes) because + * it was already checked in previous scanner (prefix_scanner). + */ + else if (length + 1 < max_bytes) { + xed_uint8_t n = xed_decoded_inst_get_byte(d,length +1); + /* in 16/32b modes, the MODRM.MOD field MUST be 0b11 */ + if ((n&0xC0) == 0xC0) { + length++; /* eat the c4/c5 */ + } + else { + /* A little optimization: + * this is not a vex prefix, we can proceed to + * next scanner */ + return; + } + } + else { /* don't have enough bytes to check if it's vex prefix, + * we are out of bytes */ + too_short(d); + return ; + } + + /* we want to make sure, that we have additional 3 bytes + * available for reading - for 2 vex payload bytes and opcode */ + if ((length + 3) <= max_bytes) { + xed_avx_c4_payload1_t c4byte1; + xed_avx_c4_payload2_t c4byte2; + + c4byte1.u32 = xed_decoded_inst_get_byte(d, length); + c4byte2.u32 = xed_decoded_inst_get_byte(d, length + 1); + + // these 2 are guaranteed to be 1 in 16/32b mode by above check + xed3_operand_set_rexr(d, ~c4byte1.s.r_inv&1); + xed3_operand_set_rexx(d, ~c4byte1.s.x_inv&1); + + xed3_operand_set_rexb(d, (xed3_mode_64b(d) & ~c4byte1.s.b_inv)&1); + + xed3_operand_set_rexw(d, c4byte2.s.w); + + xed3_operand_set_vexdest3(d, c4byte2.s.v3); + xed3_operand_set_vexdest210(d, c4byte2.s.vvv210); + + xed3_operand_set_vl(d, c4byte2.s.l); + + xed3_operand_set_vex_prefix(d, vex_prefix_recoding[c4byte2.s.pp]); + + xed3_operand_set_map(d,c4byte1.s.map); + + if (c4byte1.s.map == XED_ILD_MAP3) + xed3_operand_set_imm_width(d, bytes2bits(1)); + + // this is a success indicator for downstreaam decoding + xed3_operand_set_vexvalid(d, 1); // AVX1/2 + + length += 2; /* eat the c4 vex 2B payload */ + xed_decoded_inst_set_length(d, length); + /* FIXME: too hardcoded? maybe define graph data structure?*/ + evex_vex_opcode_scanner(d); + return; + } + else { + /* We don't have 3 bytes available for reading, but we for sure + * need to read them - for 2 vex payload bytes and opcode byte, + * hence we are out of bytes. + */ + xed_decoded_inst_set_length(d, length); + too_short(d); + return; + } +} + +static void vex_c5_scanner(xed_decoded_inst_t* d) +{ + /* assumption: length < max_bytes + * This is checked in prefix_scanner. + * If any other scanner is added before vex_scanner, this condition + * should be preserved. + * FIXME: check length < max_bytes here anyway? This will be less + * error-prone, but that's an additional non-necessary branch. + */ + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + if (xed3_mode_64b(d)) + { + length++; /* eat the c4/c5 */ + } + /* we don't need to check (d->length < d->max_bytes) because + * it was already checked in previous scanner (prefix_scanner). + */ + else if (length + 1 < max_bytes) + { + xed_uint8_t n = xed_decoded_inst_get_byte(d, length+1); + /* in 16/32b modes, the MODRM.MOD field MUST be 0b11 */ + if ((n&0xC0) == 0xC0) + { + length++; /* eat the c4/c5 */ + } + else + { + /* A little optimization: + * this is not a vex prefix, we can proceed to + * next scanner */ + return; + } + } + else + { /* don't have enough bytes to check if it's vex prefix, + * we are out of bytes */ + too_short(d); + return ; + } + + + /* we want to make sure, that we have additional 2 bytes + * available for reading - for vex payload byte and opcode */ + if ((length + 2) <= max_bytes) { + xed_avx_c5_payload_t c5byte1; + c5byte1.u32 = xed_decoded_inst_get_byte(d, length); + + xed3_operand_set_rexr(d, ~c5byte1.s.r_inv&1); + xed3_operand_set_vexdest3(d, c5byte1.s.v3); + xed3_operand_set_vexdest210(d, c5byte1.s.vvv210); + + xed3_operand_set_vl(d, c5byte1.s.l); + xed3_operand_set_vex_prefix(d, vex_prefix_recoding[c5byte1.s.pp]); + + /* MAP is a special case - although it is a derived operand in + * newvex_prexix(), we need to set it here, because we use map + * later in ILD - for modrm, imm and disp + */ + xed3_operand_set_map(d, XED_ILD_MAP1); + + // this is a success indicator for downstreaam decoding + xed3_operand_set_vexvalid(d, 1); // AVX1/2 + + length++; /* eat the vex opcode payload */ + xed_decoded_inst_set_length(d, length); + + + /* FIXME: too hardcoded? maybe define graph data structure?*/ + evex_vex_opcode_scanner(d); + return; + } + else { + /* We don't have 2 bytes available for reading, but we for sure + * need to read them - for vex payload byte and opcode bytes, + * hence we are out of bytes. + */ + xed_decoded_inst_set_length(d, length); + too_short(d); + return ; + } +} + + +#if defined(XED_AMD_ENABLED) + +static XED_INLINE xed_uint_t get_modrm_reg_field(xed_uint8_t b) { + return (b & 0x38) >> 3; +} + +static void xop_scanner(xed_decoded_inst_t* d) +{ + /* assumption: length < max_bytes + * This is checked in prefix_scanner. + * If any other scanner is added before vex_scanner, this condition + * should be preserved. + * FIXME: check length < max_bytes here anyway? This will be less + * error-prone, but that's an additional non-necessary branch. + */ + + /* we don't need to check (d->length < d->max_bytes) because + * it was already checked in previous scanner (prefix_scanner). + */ + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + + if (length + 1 < max_bytes) { + xed_uint8_t n = xed_decoded_inst_get_byte(d, length+1); + /* in all modes, the MODRM.REG field MUST NOT be 0b000. + mm-rrr-nnn -> mmrr_rnnn + */ + + if ( get_modrm_reg_field(n) != 0 ) { + length++; /* eat the 0x8f */ + } + else { + /* A little optimization: this is not an xop prefix, we can + * proceed to next scanner */ + return; + } + } + else { + /* don't have enough bytes to check if it's an xop prefix, we + * are out of bytes */ + too_short(d); + return ; + } + + /* we want to make sure, that we have additional 3 bytes + * available for reading - for 2 xop payload bytes and opcode */ + if ((length + 3) <= max_bytes) + { + xed_avx_c4_payload1_t xop_byte1; + xed_avx_c4_payload2_t xop_byte2; + xed_uint8_t map; + xop_byte1.u32 = xed_decoded_inst_get_byte(d, length); + xop_byte2.u32 = xed_decoded_inst_get_byte(d, length + 1); + + map = xop_byte1.s.map; + if (map == 0x9) { + xed3_operand_set_map(d,XED_ILD_MAP_XOP9); + xed3_operand_set_imm_width(d, 0); //bits + } + else if (map == 0x8){ + xed3_operand_set_map(d,XED_ILD_MAP_XOP8); + xed3_operand_set_imm_width(d, bytes2bits(1)); + } + else if (map == 0xA){ + xed3_operand_set_map(d,XED_ILD_MAP_XOPA); + xed3_operand_set_imm_width(d, bytes2bits(4)); + } + else + bad_map(d); + + + xed3_operand_set_rexr(d, ~xop_byte1.s.r_inv&1); + xed3_operand_set_rexx(d, ~xop_byte1.s.x_inv&1); + xed3_operand_set_rexb(d, (xed3_mode_64b(d) & ~xop_byte1.s.b_inv)&1); + + xed3_operand_set_rexw(d, xop_byte2.s.w); + + xed3_operand_set_vexdest3(d, xop_byte2.s.v3); + xed3_operand_set_vexdest210(d, xop_byte2.s.vvv210); + + xed3_operand_set_vl(d, xop_byte2.s.l); + xed3_operand_set_vex_prefix(d, vex_prefix_recoding[xop_byte2.s.pp]); + + xed3_operand_set_vexvalid(d, 3); + + length += 2; /* eat the 8f xop 2B payload */ + /* FIXME: too hardcoded? maybe define graph data structure?*/ + /* using the VEX opcode scanner for xop opcodes too. */ + xed_decoded_inst_set_length(d, length); + evex_vex_opcode_scanner(d); + return; + } + else { + /* We don't have 3 bytes available for reading, but we for sure + * need to read them - for 2 vex payload bytes and opcode byte, + * hence we are out of bytes. + */ + xed_decoded_inst_set_length(d, length); + too_short(d); + return; + } +} +#endif +#endif + +#if defined(XED_AVX) + +# if defined(XED_AMD_ENABLED) +static XED_INLINE xed_uint_t chip_is_intel_specific(xed_decoded_inst_t* d) +{ + xed_chip_enum_t chip = xed_decoded_inst_get_input_chip(d); + if (chip == XED_CHIP_INVALID || + chip == XED_CHIP_ALL || + chip == XED_CHIP_AMD) + return 0; + return 1; +} +# endif + + +static void vex_scanner(xed_decoded_inst_t* d) +{ + /* this handles the AVX C4/C5 VEX prefixes and also the AMD XOP 0x8F + * prefix */ + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + if (b == 0xC5) { + if (!xed3_operand_get_out_of_bytes(d)) + vex_c5_scanner(d); + return; + } + else if (b == 0xC4) { + if (!xed3_operand_get_out_of_bytes(d)) + vex_c4_scanner(d); + return; + } +#if defined(XED_AMD_ENABLED) + else if (b == 0x8f && chip_is_intel_specific(d)==0 ) { + if (!xed3_operand_get_out_of_bytes(d)) + xop_scanner(d); + return; + } +#endif +} +#endif + +static void get_next_as_opcode(xed_decoded_inst_t* d) { + if (xed_decoded_inst_get_length(d) < xed3_operand_get_max_bytes(d)) { + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + xed3_operand_set_nominal_opcode(d, b); + xed_decoded_inst_inc_length(d); + //st SRM (partial opcode instructions need it) + xed3_operand_set_srm(d, xed_modrm_rm(b)); + } + else { + too_short(d); + } +} + + +// has_disp_regular[eamode][modrm.mod][modrm.rm] +static xed_uint8_t has_disp_regular[3][4][8]; + +static void init_has_disp_regular_table(void) { + xed_uint8_t eamode; + xed_uint8_t rm; + xed_uint8_t mod; + + for (eamode = 0; eamode <3; eamode++) + for (mod=0; mod < 4; mod++) + for (rm=0; rm<8; rm++) + has_disp_regular[eamode][mod][rm] = 0; + + //fill the eamode16 + has_disp_regular[0][0][6] = 2; + for (rm = 0; rm < 8; rm++) { + for (mod = 1; mod <= 2; mod++) + has_disp_regular[0][mod][rm] = mod; + } + + //fill eamode32/64 + for(eamode = 1; eamode <= 2; eamode++) { + for (rm = 0; rm < 8; rm++) { + has_disp_regular[eamode][1][rm] = 1; + has_disp_regular[eamode][2][rm] = 4; + }; + has_disp_regular[eamode][0][5] = 4; + + } +} + +// eamode_table[asz][mmode] +static xed_uint8_t eamode_table[2][XED_GRAMMAR_MODE_64+1]; + +static void init_eamode_table(void) { + xed_uint8_t mode; + xed_uint8_t asz; + + for (asz=0; asz<2; asz++) + for (mode=0; mode= max_bytes, and we are out of bytes*/ + too_short(d); + return; + } + + } + /*no modrm, set RM from nominal_opcode*/ + //rm = xed_modrm_rm(xed3_operand_get_nominal_opcode(d)); + //xed3_operand_set_rm(d, rm); + + /* a little optimization: we don't have modrm and hence don't have sib. + * Hence we don't need to call sib scanner and can go straight to disp*/ + /*FIXME: Better to call next scanner anyway for better modularity?*/ +} + +static void sib_scanner(xed_decoded_inst_t* d) +{ + + if (xed3_operand_get_has_sib(d)) { + unsigned char length = xed_decoded_inst_get_length(d); + if (length < xed3_operand_get_max_bytes(d)) { + xed_uint8_t b; + b = xed_decoded_inst_get_byte(d, length); + + xed3_operand_set_pos_sib(d, length); + xed3_operand_set_sibscale(d, xed_sib_scale(b)); + xed3_operand_set_sibindex(d, xed_sib_index(b)); + xed3_operand_set_sibbase(d, xed_sib_base(b)); + + xed_decoded_inst_inc_length(d); /* eat sib */ + + if (xed_sib_base(b) == 5) { + /* other mod values are set by modrm processing */ + if (xed3_operand_get_mod(d) == 0) + xed3_operand_set_disp_width(d, bytes2bits(4)); + } + } + else { /*has_sib but not enough length -> out of bytes */ + too_short(d); + return; + } + } +} + + + +/*probably this table should be generated. Leaving it here for now. + Maybe in one of the following commits it will be moved to auto generated + code.*/ +const xed_ild_l1_func_t* disp_bits_2d[XED_ILD_MAP2] = { + disp_width_map_0x0, + disp_width_map_0x0F +}; + +static void disp_scanner(xed_decoded_inst_t* d) +{ + /* 0 1 2 3 4 5 6 7 8 */ + static const xed_uint8_t ilog2[] = { 99 , 0, 1, 99, 2, 99, 99, 99, 3 }; + + xed_ild_map_enum_t map = (xed_ild_map_enum_t)xed3_operand_get_map(d); + xed_uint8_t opcode = xed3_operand_get_nominal_opcode(d); + xed_uint8_t disp_bytes; + xed_uint8_t length = xed_decoded_inst_get_length(d); + /*Checked dumped tables of maps 2 ,3 and 3dnow: + they all have standard displacement resolution, we are not going + to use their lookup tables*/ + if (map < XED_ILD_MAP2) { + /*get the L1 function pointer and use it */ + xed_ild_l1_func_t fptr = disp_bits_2d[map][opcode]; + /*most map-opcodes have disp_bytes set in modrm/sib scanners + for those we have L1 functions that do nothing*/ + if (fptr == 0){ + xed3_operand_set_error(d,XED_ERROR_GENERAL_ERROR); + return; + } + (*fptr)(d); + } + /*All other maps should have been set earlier*/ + disp_bytes = bits2bytes(xed3_operand_get_disp_width(d)); + if (disp_bytes) { + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + if ((length + disp_bytes) <= max_bytes) { + + //set disp value + const xed_uint8_t* itext = d->_byte_array._dec; + xed_uint8_t* disp_ptr = (xed_uint8_t*)(itext + length); + + // sign extend the displacement to 64b while passing to accessor + + switch(ilog2[disp_bytes]) { + case 0: { // 1B=8b. ilog2(1) = 0 + xed_int8_t byte = *(xed_int8_t*)disp_ptr; + xed3_operand_set_disp(d, byte); + break; + } + case 1: { // 2B=16b ilog2(2) = 1 + xed_int16_t word = *(xed_int16_t*)disp_ptr; + xed3_operand_set_disp(d, word); + break; + } + case 2: { // 4B=32b ilog2(4) = 2 + xed_int32_t dword = *(xed_int32_t*)disp_ptr; + xed3_operand_set_disp(d, dword); + break; + } + case 3: {// 8B=64b ilog2(8) = 3 + xed_int64_t qword = *(xed_int64_t*)disp_ptr; + xed3_operand_set_disp(d, qword); + break; + } + default: + xed_assert(0); + } + + xed3_operand_set_pos_disp(d, length); + xed_decoded_inst_set_length(d, length + disp_bytes); + } + else { + too_short(d); + return; + } + } +} + + + + +#if defined(XED_EXTENDED) +# include "xed-ild-extension.h" +#endif + +/*probably this table should be generated. Leaving it here for now. + Maybe in one of the following commits it will be moved to auto generated + code.*/ +const xed_uint8_t* has_modrm_2d[XED_ILD_MAP2] = { + has_modrm_map_0x0, + has_modrm_map_0x0F +}; + +static void set_has_modrm(xed_decoded_inst_t* d) { + /* This assumes that the lookup arrays do not have undefined opcodes. + It means we must fill has_modrm property for illegal opcodes at + build time in (ild.py) */ + /*some 3dnow instructions conflict on has_modrm property with other + instructions. However all 3dnow instructions have modrm, hence we + just set has_modrm to 1 in case of 3dnow (map==XED_ILD_MAPAMD) */ + xed_ild_map_enum_t map = (xed_ild_map_enum_t)xed3_operand_get_map(d); + xed_uint8_t opcode = xed3_operand_get_nominal_opcode(d); + /* we set HAS_MODRM and not MODRM operand, because MODRM operand is 1 + * bit only and we need to for MODRM_IGNORE value for CR and DR + * instructions + */ + xed3_operand_set_has_modrm(d,1); + if (map < XED_ILD_MAP2) + xed3_operand_set_has_modrm(d,has_modrm_2d[map][opcode]); +} + + + +/*probably this table should be generated. Leaving it here for now. + Maybe in one of the following commits it will be moved to auto generated + code.*/ +const xed_ild_l1_func_t* imm_bits_2d[XED_ILD_MAP2] = { + imm_width_map_0x0, + imm_width_map_0x0F +}; + +static void set_imm_bytes(xed_decoded_inst_t* d) { + xed_ild_map_enum_t map = (xed_ild_map_enum_t)xed3_operand_get_map(d); + xed_uint8_t opcode = xed3_operand_get_nominal_opcode(d); + xed_uint8_t imm_bits = xed3_operand_get_imm_width(d); + /* FIXME: not taking care of illegal map-opcodes yet. + Probably should fill them in ild_storage.py + Now illegal map-opcodes have 0 as function pointer in lookup tables*/ + if (!imm_bits) { + if (map < XED_ILD_MAP2) { + /*get the L1 function pointer and use it */ + xed_ild_l1_func_t fptr = imm_bits_2d[map][opcode]; + if (fptr == 0){ + xed3_operand_set_error(d,XED_ERROR_GENERAL_ERROR); + return; + } + (*fptr)(d); + return; + } + /*All other maps should have been set earlier*/ + } +} + +//////////////////////////////////////////////////////////////////////////////// + +#if !defined(XED_SUPPORTS_AVX512) && !defined(XED_SUPPORTS_KNC) +static void imm_scanner(xed_decoded_inst_t* d) +{ + xed_uint8_t imm_bytes; + xed_uint8_t imm1_bytes; + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + unsigned int pos_imm = 0; + const xed_uint8_t* itext = d->_byte_array._dec; + const xed_uint8_t* imm_ptr = 0; + + set_imm_bytes(d); + + if (xed3_operand_get_amd3dnow(d)) { + if (length < max_bytes) { + /*opcode is in immediate*/ + xed3_operand_set_nominal_opcode(d, + xed_decoded_inst_get_byte(d, length)); + /*count the pseudo immediate byte, which is opcode*/ + xed_decoded_inst_inc_length(d); + /*imm_bytes == imm_bytes1 == 0 for amd3dnow */ + return; + } + else { + too_short(d); + return; + } + } + + imm_bytes = bits2bytes(xed3_operand_get_imm_width(d)); + imm1_bytes = xed3_operand_get_imm1_bytes(d); + + if (imm_bytes) { + if (length + imm_bytes <= max_bytes) { + xed3_operand_set_pos_imm(d, length); + /* eat imm */ + length += imm_bytes; + xed_decoded_inst_set_length(d, length); + + if (imm1_bytes) { + if (length + imm1_bytes <= max_bytes) { + xed3_operand_set_pos_imm1(d, length); + imm_ptr = itext + length; + length += imm1_bytes; /* eat imm1 */ + xed_decoded_inst_set_length(d, length); + //set uimm1 value + xed3_operand_set_uimm1(d, *imm_ptr); + } + else {/* Ugly code */ + too_short(d); + return; + } + } + } + else { + too_short(d); + return; + } + } + + /* FIXME: setting UIMM chunks. This can be done better, + * for example special capturing function in ILD, like for imm_bytes*/ + pos_imm = xed3_operand_get_pos_imm(d); + imm_ptr = itext + pos_imm; + switch(imm_bytes){ + case 0: + break; + case 1: { + xed_uint8_t uimm0 = *(xed_uint8_t*)(imm_ptr); + xed3_operand_set_uimm0(d, uimm0); + + //for SE_IMM8() we need to set here the esrc as well + xed3_operand_set_esrc(d,uimm0 >> 4); + break; + } + case 2:{ + xed_uint16_t uimm0 = *(xed_uint16_t*)(imm_ptr); + xed3_operand_set_uimm0(d, uimm0); + break; + } + case 4:{ + xed_uint32_t uimm0 = *(xed_uint32_t*)(imm_ptr); + xed3_operand_set_uimm0(d, uimm0); + break; + } + case 8:{ + xed_uint64_t uimm0 = *(xed_uint64_t*)(imm_ptr); + xed3_operand_set_uimm0(d, uimm0); + break; + } + default: + /*Unexpected immediate width, this should never happen*/ + xed_assert(0); + } + + /* uimm1 is set earlier */ +} +#endif // !defined(XED_SUPPORTS_AVX512) && !defined(XED_SUPPORTS_KNC) +//////////////////////////////////////////////////////////////////////////////// + +#if defined(XED_AVX) +static void catch_invalid_rex_or_legacy_prefixes(xed_decoded_inst_t* d) +{ + // REX, F2, F3, 66 are not allowed before VEX or EVEX prefixes + if ( xed3_mode_64b(d) && xed3_operand_get_rex(d) ) + xed3_operand_set_error(d,XED_ERROR_BAD_REX_PREFIX); + else if ( xed3_operand_get_osz(d) || + xed3_operand_get_ild_f3(d) || + xed3_operand_get_ild_f2(d) ) + xed3_operand_set_error(d,XED_ERROR_BAD_LEGACY_PREFIX); +} +static void catch_invalid_mode(xed_decoded_inst_t* d) +{ + // we know we have VEX or EVEX instr. + if(xed3_operand_get_realmode(d)) { + xed3_operand_set_error(d,XED_ERROR_INVALID_MODE); + } +} + +static void evex_vex_opcode_scanner(xed_decoded_inst_t* d) +{ + /* no need to check max_bytes here, it was checked in previous + scanner */ + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + xed3_operand_set_nominal_opcode(d, b); + xed3_operand_set_pos_nominal_opcode(d, length); + xed_decoded_inst_inc_length(d); + catch_invalid_rex_or_legacy_prefixes(d); + catch_invalid_mode(d); +} +#endif + +static void opcode_scanner(xed_decoded_inst_t* d) +{ + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + xed_uint8_t opcode = 0; + + /*no need to check max_bytes - it was checked in previous scanners*/ + + /* no need to check for VEX here anymore, because if VEX + prefix was encountered, we would get to evex_vex_opcode_scanner */ + if (b != 0x0F) { + xed3_operand_set_map(d, XED_ILD_MAP0); + xed3_operand_set_nominal_opcode(d, b); + xed3_operand_set_pos_nominal_opcode(d, length); + xed_decoded_inst_inc_length(d); + goto out; + } + + length++; /* eat the 0x0F */ + xed3_operand_set_pos_nominal_opcode(d, length); + + /* 0x0F opcodes MAPS 1,2,3 */ + //FIXME: finish here + if (length < xed3_operand_get_max_bytes(d)) { + xed_uint8_t m = xed_decoded_inst_get_byte(d, length); + if (m == 0x38) { + length++; /* eat the 0x38 */ + xed3_operand_set_map(d, XED_ILD_MAP2); + xed_decoded_inst_set_length(d, length); + get_next_as_opcode( d); + return; + } + else if (m == 0x3A) { + length++; /* eat the 0x3A */ + xed3_operand_set_map(d, XED_ILD_MAP3); + xed_decoded_inst_set_length(d, length); + xed3_operand_set_imm_width(d, bytes2bits(1)); + get_next_as_opcode( d); + return; + } + else if (m == 0x3B) { + length++; /* eat the 0x3B */ + bad_map(d); + xed_decoded_inst_set_length(d, length); + get_next_as_opcode( d); + return; + //FIXME: TNI maps have no modrm, imm, disp ?? + /* BTW we use MAP as index to static decoding lookup tables.. + * with INVALID_MAP we will have segv there, need to check + * for it after ILD phase. + * Maybe set some common ILD_INVALID member to indicate that + * there is no need to do static decoding? + */ + } + else if (m > 0x38 && m <= 0x3F) { + length++; /* eat the 0x39...0x3F (minus 3A and 3B) */ + bad_map(d); + + xed_decoded_inst_set_length(d, length); + get_next_as_opcode( d); + return; //FIXME: TNI maps have no modrm, imm, disp ?? + /* BTW we use MAP as index static decoding lookup tables.. + * with INVALID_MAP we will have segv there, need to check + * for it after ILD phase */ + } + else if (m == 0x0F) { /* FIXME: CAREFUL */ + xed3_operand_set_amd3dnow(d, 1); + /* opcode is in immediate later on */ + length++; /*eat the second 0F */ + xed3_operand_set_nominal_opcode(d, 0x0F); + /*special map for amd3dnow */ + xed3_operand_set_map(d, XED_ILD_MAPAMD); + xed_decoded_inst_set_length(d, length); + } + else { + length++; /* eat the 2nd opcode byte */ + xed3_operand_set_nominal_opcode(d, m); + xed3_operand_set_map(d, XED_ILD_MAP1); + xed_decoded_inst_set_length(d, length); + } + } + else{ + too_short(d); + return; + } + +out: + //set SRM (partial opcode instructions need it) + opcode = xed3_operand_get_nominal_opcode(d); + xed3_operand_set_srm(d, xed_modrm_rm(opcode)); +} + +////////////////////////////////////////////////////////////////////////// +// KNC/AVX512 EVEX and EVEX-IMM8 scanners + + + +#if defined(XED_SUPPORTS_AVX512) || defined(XED_SUPPORTS_KNC) + +typedef union { // Common KNC & AVX512 + struct { + xed_uint32_t map:4; + xed_uint32_t rr_inv:1; + xed_uint32_t b_inv:1; + xed_uint32_t x_inv:1; + xed_uint32_t r_inv:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx512_payload1_t; + +typedef union { // Common KNC & AVX512 + struct { + xed_uint32_t pp:2; + xed_uint32_t ubit:1; + xed_uint32_t vexdest210:3; + xed_uint32_t vexdest3:1; + xed_uint32_t rexw:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx512_payload2_t; + +typedef union{ // KNC only + struct { + xed_uint32_t mask:3; + xed_uint32_t vexdest4p:1; + xed_uint32_t swiz:3; + xed_uint32_t nr:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_knc_payload3_t; + + +typedef union{ // AVX512 only + struct { + xed_uint32_t mask:3; + xed_uint32_t vexdest4p:1; + xed_uint32_t bcrc:1; + xed_uint32_t llrc:2; + xed_uint32_t z:1; + xed_uint32_t pad:24; + } s; + xed_uint32_t u32; +} xed_avx512_payload3_t; + + +static void evex_scanner(xed_decoded_inst_t* d) +{ + /* assumption: length < max_bytes + * This is checked in prefix_scanner. + * If any other scanner is added before evex_scanner, this condition + * should be preserved. + * FIXME: check length < max_bytes here anyway? This will be less + * error-prone, but that's an additional non-necessary branch. + */ + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + xed_uint8_t b = xed_decoded_inst_get_byte(d, length); + + if (b == 0x62) + { + /*first check that it is not a BOUND instruction */ + if(!xed3_mode_64b(d)) { + /*make sure we can read one additional byte */ + if (length + 1 < max_bytes) { + xed_uint8_t n = xed_decoded_inst_get_byte(d, length+1); + if ((n&0xC0) != 0xC0) { + /*this is a BOUND instruction */ + /* FIXME: could have set opcode here and call + * modrm_scanner but that would be a code + * duplication */ + return; + } + } + else { + too_short(d); + return; + } + } + /*we want to ensure that we have enough bytes available to + read: 4 bytes for evex prefix and 1 byte for an opcode */ + if (length + 5 <= max_bytes) { + xed_avx512_payload1_t evex1; + xed_avx512_payload2_t evex2; + + evex1.u32 = xed_decoded_inst_get_byte(d, length+1); + evex2.u32 = xed_decoded_inst_get_byte(d, length+2); + + // above check guarantees that r and x are 1 in 16/32b mode. + xed3_operand_set_rexr(d, ~evex1.s.r_inv&1); + xed3_operand_set_rexx(d, ~evex1.s.x_inv&1); + + // force rexb to zero in 16/32b mode because it can be used for gprs + xed3_operand_set_rexb(d, (xed3_mode_64b(d) & ~evex1.s.b_inv)&1); + // rexrr not used for gprs. Only for evex x/y/zmm regs + xed3_operand_set_rexrr(d, ~evex1.s.rr_inv&1); + + xed3_operand_set_map(d, evex1.s.map); + + xed3_operand_set_rexw(d, evex2.s.rexw); + xed3_operand_set_vexdest3(d, evex2.s.vexdest3); + xed3_operand_set_vexdest210(d, evex2.s.vexdest210); + xed3_operand_set_ubit(d, evex2.s.ubit); + if (evex2.s.ubit) + xed3_operand_set_vexvalid(d, 2); // AVX512 EVEX U=1 req'd + else + { +#if defined(XED_SUPPORTS_KNC) + xed3_operand_set_vexvalid(d, 4); // KNC EVEX U=0 req'd +#else + xed3_operand_set_error(d,XED_ERROR_BAD_EVEX_UBIT); +#endif + } + + xed3_operand_set_vex_prefix(d,vex_prefix_recoding[evex2.s.pp]); + + if (evex1.s.map == XED_ILD_MAP3) + xed3_operand_set_imm_width(d, bytes2bits(1)); + + if (evex2.s.ubit) // AVX512 only (Not KNC) + { +#if defined(XED_SUPPORTS_AVX512) + xed_avx512_payload3_t evex3; + evex3.u32 = xed_decoded_inst_get_byte(d, length+3); + + xed3_operand_set_zeroing(d, evex3.s.z); + + // llrc is still required for rounding fixup much later + // during decode. + xed3_operand_set_llrc(d, evex3.s.llrc); + + xed3_operand_set_vl(d, evex3.s.llrc); + xed3_operand_set_bcrc(d, evex3.s.bcrc); + xed3_operand_set_vexdest4(d, ~evex3.s.vexdest4p&1); + if (!xed3_mode_64b(d) && evex3.s.vexdest4p==0) + bad_v4(d); + + xed3_operand_set_mask(d, evex3.s.mask); +#endif + } +#if defined(XED_SUPPORTS_KNC) + else // KNC + { + const xed_uint_t vl_512=2; + xed_knc_payload3_t evex3; + evex3.u32 = xed_decoded_inst_get_byte(d, length+3); + xed3_operand_set_vl(d, vl_512); //Indicates vector length 512b + + xed3_operand_set_nr(d, evex3.s.nr); + xed3_operand_set_swiz(d, evex3.s.swiz); + xed3_operand_set_vexdest4(d, ~evex3.s.vexdest4p&1); + xed3_operand_set_mask(d, evex3.s.mask); + } +#endif + + length += 4; + xed_decoded_inst_set_length(d, length); + /* vex opcode scanner fits for evex instructions too: it just reads + * one byte as nominal opcode, this is exactly what we want for + * evex*/ + evex_vex_opcode_scanner(d); + } + else { + /*there is no enough bytes, hence we are out of bytes */ + too_short(d); + } + } +} + +static void evex_imm_scanner(xed_decoded_inst_t* d) +{ + xed_uint8_t imm_bytes; + xed_uint8_t imm1_bytes; + xed_uint8_t max_bytes = xed3_operand_get_max_bytes(d); + unsigned char length = xed_decoded_inst_get_length(d); + unsigned int pos_imm = 0; + const xed_uint8_t* itext = d->_byte_array._dec; + const xed_uint8_t* imm_ptr = 0; + + set_imm_bytes(d); + + if (xed3_operand_get_amd3dnow(d)) { + if (length < max_bytes) { + /*opcode is in immediate*/ + xed3_operand_set_nominal_opcode(d, + xed_decoded_inst_get_byte(d, length)); + /*count the pseudo immediate byte, which is opcode*/ + xed_decoded_inst_inc_length(d); + /*imm_bytes == imm_bytes1 == 0 for amd3dnow */ + return; + } + else { + too_short(d); + return; + } + } + + imm_bytes = bits2bytes(xed3_operand_get_imm_width(d)); + imm1_bytes = xed3_operand_get_imm1_bytes(d); + + if (imm_bytes) { + if (length + imm_bytes <= max_bytes) { + xed3_operand_set_pos_imm(d, length); + /* eat imm */ + length += imm_bytes; + xed_decoded_inst_set_length(d, length); + + if (imm1_bytes) { + if (length + imm1_bytes <= max_bytes) { + xed3_operand_set_pos_imm1(d, length); + imm_ptr = itext + length; + length += imm1_bytes; /* eat imm1 */ + xed_decoded_inst_set_length(d, length); + //set uimm1 value + xed3_operand_set_uimm1(d, *imm_ptr); + } + else {/* Ugly code */ + too_short(d); + return; + } + } + } + else { + too_short(d); + return; + } + } + + /* FIXME: setting UIMM chunks. This can be done better, + * for example special capturing function in ILD, like for imm_bytes*/ + pos_imm = xed3_operand_get_pos_imm(d); + imm_ptr = itext + pos_imm; + switch(imm_bytes) + { + case 0: + break; + case 1: + { + xed_uint8_t uimm0 = *imm_ptr; + xed_uint8_t esrc = uimm0 >> 4; + + xed3_operand_set_uimm0(d, uimm0); + xed3_operand_set_esrc(d, esrc); + break; + } + case 2: + xed3_operand_set_uimm0(d, *(xed_uint16_t*)imm_ptr); + break; + case 4: + xed3_operand_set_uimm0(d, *(xed_uint32_t*)imm_ptr); + break; + case 8: + xed3_operand_set_uimm0(d, *(xed_uint64_t*)imm_ptr); + break; + default: + /*Unexpected immediate width, this should never happen*/ + xed_assert(0); + } + + /* uimm1 is set earlier */ +} + +#endif // defined(XED_SUPPORTS_AVX512) + +//////////////////////////////////////////////////////////////////////////////// + +void xed_ild_lookup_init(void) { + xed_ild_eosz_init(); + xed_ild_easz_init(); + + xed_ild_imm_l3_init(); + xed_ild_disp_l3_init(); + + init_has_disp_regular_table(); + init_eamode_table(); + init_has_sib_table(); + +} + +void xed_ild_init(void) { + init_prefix_table(); + xed_ild_lookup_init(); +} + + + + +void +xed_instruction_length_decode(xed_decoded_inst_t* ild) +{ + prefix_scanner(ild); +#if defined(XED_AVX) + if (xed3_operand_get_out_of_bytes(ild)) + return; + vex_scanner(ild); +#endif +#if defined(XED_SUPPORTS_AVX512) || defined(XED_SUPPORTS_KNC) + // if we got a vex prefix (which also sucks down the opcode), + // then we do not need to scan for evex prefixes. + if (!xed3_operand_get_vexvalid(ild)) { + if (xed3_operand_get_out_of_bytes(ild)) + return; + evex_scanner(ild); + } +#endif + + if (xed3_operand_get_out_of_bytes(ild)) + return; +#if defined(XED_AVX) + // vex/xop prefixes also eat the vex/xop opcode + if (!xed3_operand_get_vexvalid(ild)) + opcode_scanner(ild); +#else + opcode_scanner(ild); +#endif + modrm_scanner(ild); + sib_scanner(ild); + disp_scanner(ild); +#if defined(XED_SUPPORTS_AVX512) || defined(XED_SUPPORTS_KNC) + evex_imm_scanner(ild); +#else + imm_scanner(ild); +#endif +} + +#include "xed-chip-modes.h" + +/// This is the second main entry point for the decoder +/// used for new xed3 decoding. +XED_DLL_EXPORT xed_error_enum_t +xed_ild_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes) +{ + xed_uint_t tbytes; + xed_chip_enum_t chip = xed_decoded_inst_get_input_chip(xedd); + + set_chip_modes(xedd,chip,0); //FIXME: add support for cpuid features + + xedd->_byte_array._dec = itext; + + tbytes = bytes; + if (bytes > XED_MAX_INSTRUCTION_BYTES) + tbytes = XED_MAX_INSTRUCTION_BYTES; + xed3_operand_set_max_bytes(xedd, tbytes); + xed_instruction_length_decode(xedd); + + if (xed3_operand_get_out_of_bytes(xedd)) + return XED_ERROR_BUFFER_TOO_SHORT; + if (xed3_operand_get_map(xedd) == XED_ILD_MAP_INVALID) + return XED_ERROR_GENERAL_ERROR; + + return XED_ERROR_NONE; +} + + +// xed-ild-private.h +xed_bits_t +xed_ild_cvt_mode(xed_machine_mode_enum_t mmode) { + + xed_bits_t result = 0; + switch(mmode) + { + case XED_MACHINE_MODE_LONG_64: + result = XED_GRAMMAR_MODE_64; + + break; + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LONG_COMPAT_32: + result = XED_GRAMMAR_MODE_32; + break; + + case XED_MACHINE_MODE_REAL_16: + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_LONG_COMPAT_16: + result = XED_GRAMMAR_MODE_16; + break; + default: + xed_derror("Bad machine mode in xed_ild_cvt_mode() call"); + } + return result; +} + diff --git a/src/xed-immdis.c b/src/xed-immdis.c new file mode 100644 index 0000000..a238262 --- /dev/null +++ b/src/xed-immdis.c @@ -0,0 +1,409 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immdis.c +/// + + + +#include "xed-immdis.h" +#include "xed-util-private.h" +#include "xed-portability.h" + +static int xed_immdis__print_ptr(const xed_immdis_t* p, char* buf, int buflen) { + xed_uint_t i; + char tbuf[100]; + char* x = tbuf; + int blen = buflen; + const xed_bool_t lowercase=1; + blen = xed_strncpy(buf,"PTR:",blen); + // Note: no 0x needed because this is private and called in the context + // where a leading 0x is provided. + for( i=0; i< p->currently_used_space; i++ ) { + *x++ = xed_to_ascii_hex_nibble(p->value.x[i]>>4, lowercase); + *x++ = xed_to_ascii_hex_nibble(p->value.x[i]&0xF, lowercase); + } + *x = 0; + blen = xed_strncat(buf, tbuf, blen); + return blen; +} + +static void xed_immdis__check(xed_immdis_t* q, int p) { + xed_assert(q->currently_used_space == 0); + q->present = 1; + q->currently_used_space = p; + xed_assert(q->currently_used_space <= q->max_allocated_space); +} + + +void xed_immdis_init(xed_immdis_t* p, int max_bytes) { + xed_assert(max_bytes == 4 || max_bytes == 8); + p->currently_used_space=0; + p->max_allocated_space=max_bytes; + p->present=0; + p->immediate_is_unsigned=0; + p->value.q = 0; +} + +/// return the number of bytes added +unsigned int xed_immdis_get_bytes(const xed_immdis_t* p) { + return p->currently_used_space; +} + + + +xed_bool_t +xed_immdis_is_zero(const xed_immdis_t* p) +{ + //FIXME: could just check value.q if willing to rely on initialization + xed_uint_t i; + for(i=0; i < p->currently_used_space; i++) + { + if (p->value.x[i] != 0) + { + return 0; // not zero + } + } + return 1;// is zero +} + +xed_bool_t +xed_immdis_is_one(const xed_immdis_t* p) +{ + if (p->value.x[0] == 1) + { + xed_uint_t i; + for( i=1; i < p->currently_used_space; i++) + { + if (p->value.x[i] != 0) + { + return 0; // not one + } + } + return 1; // a 1 and the rest, if any, are zeros + } + return 0; // not one +} + +/// Access the i'th byte of the immediate +xed_uint8_t xed_immdis_get_byte(const xed_immdis_t* p, unsigned int i) { + xed_assert(i < p->currently_used_space); + return p->value.x[i]; +} + +/// @name Presence / absence of an immediate or displacement + +void xed_immdis_set_present(xed_immdis_t* p) +{ + p->present = 1; +} +/// 1 if the object has had a value or individual bytes added to it. +xed_bool_t xed_immdis_is_present(const xed_immdis_t* p) { + return p->present; +} + + +/// @name Initialization and setup + +void xed_immdis_set_max_len(xed_immdis_t* p, unsigned int mx) +{ + xed_assert(mx <= XED_MAX_IMMDIS_BYTES); + p->max_allocated_space = mx; +} +void +xed_immdis_zero(xed_immdis_t* p) +{ + p->present = 0; + p->immediate_is_unsigned = 0; + p->currently_used_space = 0; +#if defined(XED_SQUEAKY_CLEAN) + p->value.q = 0; +#endif +} + +unsigned int xed_immdis_get_max_length(const xed_immdis_t* p) { + return p->max_allocated_space; +} + + +/// Return 1 if signed. +xed_bool_t +xed_immdis_is_unsigned(const xed_immdis_t* p) { + return p->immediate_is_unsigned; +} +/// Return 1 if signed. +xed_bool_t +xed_immdis_is_signed(const xed_immdis_t* p) { + return !p->immediate_is_unsigned; +} + +/// Set the immediate to be signed; For decoder use only. +void +xed_immdis_set_signed(xed_immdis_t* p) { + p->immediate_is_unsigned = 0; +} +/// Set the immediate to be unsigned; For decoder use only. +void +xed_immdis_set_unsigned( xed_immdis_t* p) { + p->immediate_is_unsigned = 1; +} + + +/// add an 8 bit value to the byte array +void +xed_immdis_add8(xed_immdis_t* p, xed_int8_t d) +{ + xed_immdis__check(p,1); + p->value.x[0] = d; +} + +/// add a 16 bit value to the byte array +void +xed_immdis_add16(xed_immdis_t* p, xed_int16_t d) +{ + xed_immdis__check(p,2); + p->value.x[0] = XED_BYTE_CAST(d); + p->value.x[1] = XED_BYTE_CAST(d>>8); +} + +/// add a 32 bit value to the byte array +void +xed_immdis_add32(xed_immdis_t* p, xed_int32_t d) +{ + xed_immdis__check(p,4); + p->value.x[0] = XED_BYTE_CAST(d); + p->value.x[1] = XED_BYTE_CAST(d>>8); + p->value.x[2] = XED_BYTE_CAST(d>>16); + p->value.x[3] = XED_BYTE_CAST(d>>24); +} + +/// add a 64 bit value to the byte array. +void +xed_immdis_add64(xed_immdis_t* p, xed_int64_t d) +{ + int i; + xed_immdis__check(p,8); + for(i = 0; i < 8 ;i++) { + p->value.x[i] = XED_BYTE_CAST( d>>(8*i) ); + } +} + + + +xed_uint64_t +xed_immdis_get_unsigned64(const xed_immdis_t* p) +{ + // Variable-width little endian storage. + // If it were fixed width, I could just cast. + xed_uint64_t v = 0; + xed_uint64_t mul = 1; + xed_uint_t i; + for ( i=0 ; i< p->currently_used_space ; i++ ) + { + v = v + xed_immdis_get_byte(p,i) * mul; + mul = mul * 256; + } + return v; +} + +xed_int64_t +xed_immdis_get_signed64(const xed_immdis_t* p) +{ + // Variable-width little endian storage. + // If it were fixed width, I could just cast. + xed_uint64_t v = 0; + xed_uint64_t mul = 1; + xed_uint_t i; + for ( i=0 ; i< p->currently_used_space ; i++ ) { + v = v + xed_immdis_get_byte(p,i) * mul; + mul = mul * 256; + } + + if ( p->currently_used_space>0) { + // sign extend + if ((xed_immdis_get_byte(p,p->currently_used_space-1) & 0x80) == 0x80) { + const xed_uint64_t sext = 0xff; + xed_uint_t j; + for ( j = p->currently_used_space ; j < p->max_allocated_space ; j++ ) { + v = v + sext * mul; + mul = mul * 256; + } + } + } + + //xed_int64_t r = xed_int64_t(v); + return XED_STATIC_CAST(xed_int64_t,v); +} + +void +xed_immdis_add_shortest_width_unsigned(xed_immdis_t* q, xed_uint64_t x, xed_uint8_t legal_widths) +{ + xed_uint64_t p = x; + int i; + XED2VMSG((xed_log_file, + "adding bytes from " XED_FMT_LX " using legal_widths %d\n", + x, (int)legal_widths)); + for(i=0;i 0) + if ( i == 1 || i == 2 || i == 4 ) + if ((i & legal_widths) == i) + break; + + b = XED_BYTE_CAST(p); + xed_immdis_add_byte(q,b); + p = p >> 8; + } + XED2VMSG((xed_log_file, "Stopped on byte %d\n",i)); +} + +void +xed_immdis_add_shortest_width_signed(xed_immdis_t* q, xed_int64_t x, xed_uint8_t legal_widths) +{ + xed_int64_t p = x; + int i; + int last_bit_high = 0; + + + XED2VMSG((xed_log_file, "adding bytes from " XED_FMT_LX " using legal_widths %d\n", + x, (int)legal_widths)); + // Intestesting test cases: + // ff7777 Needs to know if the last iterations upper bit was 1. + // 008888 Needs to know if the last iterations upper bit was 0. + for(i=0;i 0) + { + if ( i == 1 || i == 2 || i == 4 ) { + if ((i & legal_widths) == i) + break; + } + } + + b = XED_BYTE_CAST(p); + XED2VMSG((xed_log_file, "adding byte %x\n",(int)b)); + + xed_immdis_add_byte(q,b); + last_bit_high = (b >> 7) & 0x1; + p = p >> 8; + } + XED2VMSG((xed_log_file, "Stopped on byte %d\n",i)); +} + + +int xed_immdis_print(const xed_immdis_t* p, char* buf, int buflen) { + xed_uint_t i; + int blen = buflen; + char tbuf[100]; + char* x=tbuf; + char uppercase=0; + blen = xed_strncpy(buf,"0x",blen); + for( i=0; i< p->currently_used_space; i++ ) { + *x++ = xed_to_ascii_hex_nibble(p->value.x[i]>>4, uppercase); + *x++ = xed_to_ascii_hex_nibble(p->value.x[i], uppercase); + } + *x = 0; + blen = xed_strncat(buf,tbuf,blen); + return blen; +} + +int xed_immdis_print_signed_or_unsigned(const xed_immdis_t* p, char* buf, int buflen) { + if (p->immediate_is_unsigned) + return xed_immdis_print_value_unsigned(p,buf,buflen); + else + return xed_immdis_print_value_signed(p,buf,buflen); +} + +static int xed_immdis_print_helper(xed_uint64_t d64, xed_uint_t len, char* buf, int buflen) { + char tbuf[100]; + char ubuf[100]; + char* x=ubuf; + xed_uint_t tlen; + int i,plen; + xed_bool_t leading_zeros = 1; + int blen = buflen; + blen = xed_strncpy(buf,"0x",blen); + (void)xed_itoa_hex_zeros(tbuf, d64, len*8 , leading_zeros,100); + tlen = xed_strlen(tbuf); + plen = len - tlen; // how much to pad + if (plen>0) { + for(i=0;ipresent = 1; + if (p->currently_used_space >= p->max_allocated_space) { + XED2DIE((xed_log_file, + "adding too many bytes to immdis. max_allocated_space=%d currently_used_space=%d\n",p->max_allocated_space , p->currently_used_space)); + } + p->value.x[ p->currently_used_space++ ] = b; +} + +void xed_immdis_add_byte_array(xed_immdis_t* p, int nb, xed_uint8_t* ba) { + int i; + XED2VMSG((xed_log_file,"nb= %d\n", nb)); + for(i=0; i < nb; i++ ) { + xed_immdis_add_byte(p,ba[i]); + } + XED2VMSG((xed_log_file, "Set %d bytes\n", (int)p->currently_used_space)); +} + + + diff --git a/src/xed-immed.c b/src/xed-immed.c new file mode 100644 index 0000000..6c93141 --- /dev/null +++ b/src/xed-immed.c @@ -0,0 +1,64 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immed.c +/// + +#include "xed-immed.h" +#include "xed-portability.h" + +xed_int64_t xed_immed_from_bytes(xed_int8_t* bytes, xed_uint_t n) { + /* + See the header file. + */ + + xed_int64_t r; + xed_union64_t m1, m2; + int i; + xed_uint8_t* ub = (xed_uint8_t*) bytes; + m1.s.hi32 = 0xFFFFFFFF; + m1.s.lo32 = 0; + m2.s.hi32 = 0xFFFFFFFF; + m2.s.lo32 = 0xFFFF0000; + if (n == 0) + return 0; + else if (n == 4) { + r = (ub[3]<<24) | (ub[2]<<16) | (ub[1] << 8) | ub[0]; + if (bytes[3] < 0) { + r = r | m1.i64; + } + return r; + } + else if (n == 1) + return bytes[0]; + else if (n == 8) { + r = 0; + for(i=n-1;i>=0;i--) + r = (r << 8) | ub[i]; + return r; + } + else if (n == 2) { + r = (ub[1] << 8) | ub[0]; + /*printf("(%x)", r); */ + if (bytes[1] < 0) { + r = r | m2.i64; + } + return r; + } + xed_assert(n==0||n==1||n==2||n==4||n==8); + return 0; +} diff --git a/src/xed-init-ild.c b/src/xed-init-ild.c new file mode 100644 index 0000000..ae57b89 --- /dev/null +++ b/src/xed-init-ild.c @@ -0,0 +1,36 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#if defined(XED_MESSAGES) +# include +#endif + +extern void xed_ild_init(void); + +XED_DLL_EXPORT void +xed_tables_init(void) +{ + static int first_time = 1; + if (first_time == 0) + return; + first_time = 0; +#if defined(XED_MESSAGES) + xed_log_file = stdout; +#endif + xed_ild_init(); +} diff --git a/src/xed-init.c b/src/xed-init.c new file mode 100644 index 0000000..834aacb --- /dev/null +++ b/src/xed-init.c @@ -0,0 +1,114 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-init.c + + + +// This declares the major tables used by XED +#include "xed-tables-decl.h" + +#include "xed-internal-header.h" + +#include "xed-init.h" + +extern void xed_init_inst_table(void); +extern void xed_init_pointer_names(void); +extern void xed_init_operand_ctypes(void); +extern void xed_init_width_mappings(void); +extern void xed_init_reg_mappings(void); +extern void xed_init_chip_model_info(void); +extern void xed_init_convert_tables(void); +extern void xed_ild_init(void); +#if defined(XED_MESSAGES) +# include +#endif +#include "xed-ild.h" + +static void +xed_common_init(void) +{ + static int first_time = 1; + if (first_time == 0) + return; + first_time = 0; +#if defined(XED_MESSAGES) + xed_log_file=stdout; +#endif +} + +static void +xed_decode_init(void) +{ + static int first_time = 1; + if (first_time == 0) + return; + first_time = 0; + xed_common_init(); + xed_init_width_mappings(); + xed_init_reg_mappings(); + + xed_init_pointer_names(); // generated function + xed_init_operand_ctypes(); // generated function + xed_init_inst_table(); // generated function + xed_init_chip_model_info(); + xed_init_convert_tables(); +} + +#if defined(XED_ENCODER) +extern void xed_init_encode_table(void); +extern void xed_init_encoder_order(void); + +static void +xed_encode_init(void) { + static int first_time = 1; + if (first_time == 0) + return; + first_time = 0; + xed_common_init(); + // must have the decoder to use the encoder because of the + // init-from-decode stuff + xed_decode_init(); + xed_init_encode_table(); // generated function + xed_init_encoder_order(); // generated function +} + +#endif + +extern void xed_table_sizes(void); + +XED_DLL_EXPORT void +xed_tables_init(void) +{ + static int first_time = 1; + if (first_time == 0) + return; + first_time = 0; + + xed_table_sizes(); + + xed_common_init(); + xed_decode_init(); +#if defined(XED_ENCODER) + xed_encode_init(); +#endif +#if defined(XED_DECODER) + xed_ild_init(); +#endif +} + + diff --git a/src/xed-inst.c b/src/xed-inst.c new file mode 100644 index 0000000..2d1e483 --- /dev/null +++ b/src/xed-inst.c @@ -0,0 +1,161 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-inst.c + + +//////////////////////////////////////////////////////////////////////////// +#include "xed-internal-header.h" +#include "xed-inst.h" +#include "xed-inst-private.h" +#include "xed-portability.h" +#include "xed-tables-extern.h" +#include "xed-operand-action.h" + + +const xed_inst_t* xed_inst_table_base(void) { + return xed_inst_table; +} + + +xed_uint_t xed_operand_read(const xed_operand_t* p) { + return xed_operand_action_read(p->_rw); +} +xed_uint_t xed_operand_read_only(const xed_operand_t* p) { + return xed_operand_action_read_only(p->_rw); +} +xed_uint_t xed_operand_written(const xed_operand_t* p) { + return xed_operand_action_written(p->_rw); +} +xed_uint_t xed_operand_written_only(const xed_operand_t* p) { + return xed_operand_action_written_only(p->_rw); +} +xed_uint_t xed_operand_read_and_written(const xed_operand_t* p) { + return xed_operand_action_read_and_written(p->_rw); +} +xed_uint_t xed_operand_conditional_read(const xed_operand_t* p) { + return xed_operand_action_conditional_read(p->_rw); +} +xed_uint_t xed_operand_conditional_write(const xed_operand_t* p) { + return xed_operand_action_conditional_write(p->_rw); +} + +xed_uint32_t xed_operand_width_bits(const xed_operand_t* p, + const xed_uint32_t eosz) { + const xed_operand_width_enum_t width = xed_operand_width(p); + + xed_assert(width < XED_OPERAND_WIDTH_LAST); + xed_assert(eosz <= 3); + return xed_width_bits[width][eosz]; +} + +xed_nonterminal_enum_t xed_operand_nt_lookup_fn_enum(const xed_operand_t* p) { + return p->_u._nt; +} + + + + +void xed_inst_init(xed_inst_t* p) { + //p->_confirmer = 0; + p->_noperands = 0; + p->_operand_base = 0; + p->_flag_info_index = 0; + p->_flag_complex = 0; + p->_cpl=0; +} + +unsigned int xed_inst_cpl(const xed_inst_t* p) { + return p->_cpl; +} + + + + + + + +xed_uint32_t xed_inst_flag_info_index(const xed_inst_t* p) { + return p->_flag_info_index; +} + + +void xed_operand_print(const xed_operand_t* p, char* buf, int buflen) { + int blen = buflen; + blen = xed_strncpy(buf,xed_operand_enum_t2str(p->_name),blen); + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf,xed_operand_action_enum_t2str(p->_rw),blen); + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf, xed_operand_width_enum_t2str(p->_oc2),blen); + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf, xed_operand_visibility_enum_t2str(p->_operand_visibility),blen); + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf, xed_operand_type_enum_t2str(p->_type),blen); + if (p->_type == XED_OPERAND_TYPE_REG) { + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf, xed_reg_enum_t2str(xed_operand_reg(p)),blen); + } + else if (p->_type == XED_OPERAND_TYPE_IMM_CONST) { + xed_bool_t leading_zeros = 0; + char tbuf[50]; + blen = xed_strncat(buf,"/",blen); + (void)xed_itoa_hex_zeros(tbuf,xed_operand_imm(p),64,leading_zeros,50); + blen = xed_strncat(buf,tbuf,blen); + } + else if (p->_nt) { + blen = xed_strncat(buf,"/",blen); + blen = xed_strncat(buf, + xed_nonterminal_enum_t2str(xed_operand_nt_lookup_fn_enum(p)), + blen); + } +} + +unsigned int xed_attribute_max(void) { + return XED_MAX_ATTRIBUTE_COUNT; +} + +xed_attribute_enum_t xed_attribute(unsigned int i) { + xed_assert(i < XED_MAX_ATTRIBUTE_COUNT); + return xed_attributes_table[i]; +} + +extern const xed_attributes_t xed_attributes[XED_MAX_REQUIRED_ATTRIBUTES]; + +xed_uint32_t +xed_inst_get_attribute(const xed_inst_t* p, + xed_attribute_enum_t attr) { + + const xed_attributes_t* a = xed_attributes + p->_attributes; + const xed_uint64_t one = 1; + if (XED_CAST(xed_uint_t,attr) < 64) + return (a->a1 & (one<a2 & (one<<(attr-64))) != 0; +} + + +xed_attributes_t +xed_inst_get_attributes(const xed_inst_t* p) { + return xed_attributes[p->_attributes]; +} + + +const xed_operand_t* +xed_inst_operand(const xed_inst_t* p, unsigned int i) { + xed_assert(i < p->_noperands); + return &(xed_operand[xed_operand_sequences[p->_operand_base + i]]); +} + diff --git a/src/xed-isa-set.c b/src/xed-isa-set.c new file mode 100644 index 0000000..d2efdab --- /dev/null +++ b/src/xed-isa-set.c @@ -0,0 +1,37 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-isa-set.c + +#include "xed-isa-set.h" +#include "xed-util.h" +#include "xed-chip-features-table.h" +xed_bool_t +xed_isa_set_is_valid_for_chip(xed_isa_set_enum_t isa_set, + xed_chip_enum_t chip) { + const xed_uint64_t one=1; + const unsigned int n = XED_CAST(unsigned int,isa_set) / 64; + const unsigned int r = XED_CAST(unsigned int,isa_set) - (64*n); + xed_uint64_t features = 0; + + xed_assert(chip < XED_CHIP_LAST); + xed_assert(isa_set > XED_ISA_SET_INVALID && isa_set < XED_ISA_SET_LAST); + features = xed_chip_features[chip][n]; + if (features & (one< //memset + +#include "xed-ild.h" + + +xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits_raw( + const xed_operand_values_t* p) +{ + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + return xed_operand_values_get_memory_displacement_length_bits(p); +} + +xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits( + const xed_operand_values_t* p) +{ + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + return xed3_operand_get_disp_width(p); +} + + +xed_int64_t xed_operand_values_get_memory_displacement_int64( + const xed_operand_values_t* p) { + if (xed_operand_values_has_memory_displacement(p) == 0) + return 0; + + return xed3_operand_get_disp(p); +} + +// unscaled. the raw vs scaled distinction is only relevant for AVX512 +xed_int64_t +xed_operand_values_get_memory_displacement_int64_raw( + const xed_operand_values_t* p) +{ + return xed_operand_values_get_memory_displacement_int64(p); +} + + diff --git a/src/xed-operand-values-interface.c b/src/xed-operand-values-interface.c new file mode 100644 index 0000000..56d5a59 --- /dev/null +++ b/src/xed-operand-values-interface.c @@ -0,0 +1,1050 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-values-interface.c +/// + + +#include "xed-internal-header.h" +#include "xed-operand-values-interface.h" +#include "xed-util.h" +#include "xed-util-private.h" +#include "xed-init-pointer-names.h" +#include "xed-operand-ctype-enum.h" +#include "xed-operand-ctype-map.h" +#include "xed-reg-class.h" +#include "xed-operand-accessors.h" +#include //memset + +void xed_operand_values_init(xed_operand_values_t* p) { + memset(&(p->_operands),0,sizeof(xed_operand_storage_t)); +} + +void xed_operand_values_init_keep_mode( xed_operand_values_t* dst, + const xed_operand_values_t* src) { + const xed_bits_t real_mode = xed3_operand_get_realmode(src); + const xed_bits_t mode = xed3_operand_get_mode(src); + const xed_bits_t smode = xed3_operand_get_smode(src); + xed_operand_values_init(dst); + xed3_operand_set_realmode(dst,real_mode); + xed3_operand_set_mode(dst,mode); + xed3_operand_set_smode(dst,smode); +} + + +void xed_operand_values_init_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate) { + xed_operand_values_init(p); + xed_operand_values_set_mode(p,dstate); +} + +void xed_operand_values_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate) { + + /* set MODE, SMODE and REALMODE */ + xed3_operand_set_realmode(p,0); + switch(xed_state_get_machine_mode(dstate)) + { + case XED_MACHINE_MODE_LONG_64: + xed3_operand_set_mode(p,2); + xed3_operand_set_smode(p,2); + return; + + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LONG_COMPAT_32: + xed3_operand_set_mode(p,1); + break; + + case XED_MACHINE_MODE_REAL_16: + xed3_operand_set_realmode(p,1); + xed3_operand_set_mode(p,0); + break; + + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_LONG_COMPAT_16: + xed3_operand_set_mode(p,0); + break; + default: + xed_derror("Bad machine mode in xed_operand_values_set_mode() call"); + } + + // 64b mode returns above. this is for 16/32b modes only + switch(xed_state_get_stack_address_width(dstate)) { + case XED_ADDRESS_WIDTH_16b: + xed3_operand_set_smode(p,0); + break; + case XED_ADDRESS_WIDTH_32b: + xed3_operand_set_smode(p,1); + break; + default: + break; + } +} + +xed_bool_t xed_operand_values_get_long_mode(const xed_operand_values_t* p) { + return (xed3_operand_get_mode(p)==2); +} +xed_bool_t xed_operand_values_get_real_mode(const xed_operand_values_t* p) { + return (xed3_operand_get_realmode(p)!=0); +} + + +xed_uint32_t +xed_operand_values_get_stack_address_width(const xed_operand_values_t* p) { + xed_uint32_t smode = xed3_operand_get_smode(p); + switch(smode) { + case 0: return 16; + case 1: return 32; + case 2: return 64; + default: xed_assert(0); return 0; + } +} +xed_uint32_t +xed_operand_values_get_effective_address_width(const xed_operand_values_t* p) { + xed_uint32_t easz = xed3_operand_get_easz(p); + switch(easz) { + case 0: xed_assert(0); return 0; + case 1: return 16; + case 2: return 32; + case 3: return 64; + default: xed_assert(0); return 0; + } +} + +xed_uint32_t +xed_operand_values_get_effective_operand_width(const xed_operand_values_t* p) +{ + xed_uint32_t eosz = xed3_operand_get_eosz(p); + switch(eosz) { + case 0: return 8; + case 1: return 16; + case 2: return 32; + case 3: return 64; + default: xed_assert(0); return 0; + } +} + +#if defined(XED_DECODER) +xed_bool_t +xed_operand_values_has_real_rep(const xed_operand_values_t* p) { + xed_uint32_t rep = xed_decoded_inst_get_attribute(p,XED_ATTRIBUTE_REP); + if ( rep ) { + xed_bits_t r = xed3_operand_get_rep(p); + return (r == 3 || r == 2); + } + return 0; +} +#endif + +xed_bool_t +xed_operand_values_has_rep_prefix(const xed_operand_values_t* p) { + return xed3_operand_get_rep(p) == 3; +} + +xed_bool_t +xed_operand_values_has_repne_prefix(const xed_operand_values_t* p) { + return xed3_operand_get_rep(p) == 2; +} + +//FIXME: 2015-05-27: DEPRECATED -- remove when pin is fixed to not call +//this function. +void xed_operand_values_clear_rep(xed_operand_values_t* p) { + xed3_operand_set_rep(p,0); +} + + +xed_bool_t +xed_operand_values_has_segment_prefix(const xed_operand_values_t* p) +{ + return xed3_operand_get_seg_ovd(p) != 0; +} + +xed_reg_enum_t +xed_operand_values_segment_prefix(const xed_operand_values_t* p) +{ + switch(xed3_operand_get_seg_ovd(p)) { + case 0: return XED_REG_INVALID; + case 1: return XED_REG_CS; + case 2: return XED_REG_DS; + case 3: return XED_REG_ES; + case 4: return XED_REG_FS; + case 5: return XED_REG_GS; + case 6: return XED_REG_SS; + } + return XED_REG_INVALID; +} + +xed_bool_t +xed_operand_values_has_lock_prefix(const xed_operand_values_t* p) { + return xed3_operand_get_lock(p) != 0; +} + +#if defined(XED_DECODER) +xed_bool_t +xed_operand_values_get_atomic(const xed_operand_values_t* p) { + return xed_decoded_inst_get_attribute(p,XED_ATTRIBUTE_LOCKED); +} + + +xed_bool_t +xed_operand_values_lockable(const xed_operand_values_t* p) { + if (xed_decoded_inst_get_attribute(p,XED_ATTRIBUTE_LOCKABLE)) + return 1; + //XCHG accessing memory is always atomic, lockable + if (xed3_operand_get_iclass(p) == XED_ICLASS_XCHG) + if (xed3_operand_get_mem0(p)) + return 1; + return 0; +} +#endif + +xed_bool_t +xed_operand_values_using_default_segment(const xed_operand_values_t* p, + unsigned int i) { + + switch(i){ + case(0): return xed3_operand_get_using_default_segment0(p); + case(1): return xed3_operand_get_using_default_segment1(p); + default: xed_assert(0); + } + return 0; //will not ever happen, pacify the compiler + +} + +xed_bool_t +xed_operand_values_memop_without_modrm(const xed_operand_values_t* p) { + return (xed3_operand_get_mem0(p) && + xed3_operand_get_disp_width(p) && + xed3_operand_get_modrm(p)==0); +} + +xed_bool_t +xed_operand_values_has_modrm_byte(const xed_operand_values_t* p) { + return xed3_operand_get_modrm(p); +} +xed_bool_t +xed_operand_values_has_sib_byte(const xed_operand_values_t* p) { + return xed3_operand_get_sib(p); +} + +xed_bool_t +xed_operand_values_has_immediate(const xed_operand_values_t* p) { + if (xed3_operand_get_imm_width(p)) + return 1; + return 0; +} + + +xed_bool_t +xed_operand_values_has_displacement(const xed_operand_values_t* p) +{ + if (xed3_operand_get_disp_width(p)) + return 1; + if (xed3_operand_get_brdisp_width(p)) + return 1; + return 0; +} + +xed_bool_t +xed_operand_values_has_memory_displacement(const xed_operand_values_t* p) +{ + if (xed3_operand_get_brdisp_width(p)) + return 0; + if (xed3_operand_get_disp_width(p)) + return 1; + return 0; +} +xed_bool_t +xed_operand_values_has_branch_displacement(const xed_operand_values_t* p) +{ + if (xed3_operand_get_brdisp_width(p)) + return 1; + return 0; +} + +xed_bool_t +xed_operand_values_get_displacement_for_memop(const xed_operand_values_t* p) +{ + return xed_operand_values_has_memory_displacement(p); +} + + +xed_uint32_t +xed_operand_values_get_branch_displacement_length( + const xed_operand_values_t* p) +{ + return xed3_operand_get_brdisp_width(p)/8; +} +xed_uint32_t +xed_operand_values_get_branch_displacement_length_bits( + const xed_operand_values_t* p) +{ + return xed3_operand_get_brdisp_width(p); +} + +xed_uint32_t +xed_operand_values_get_memory_displacement_length( + const xed_operand_values_t* p) +{ + return xed_operand_values_get_memory_displacement_length_bits(p)/8; +} + +xed_bool_t +xed_operand_values_has_address_size_prefix(const xed_operand_values_t* p) +{ + if (xed3_operand_get_asz(p)) + return 1; + return 0; +} + +xed_bool_t +xed_operand_values_has_operand_size_prefix(const xed_operand_values_t* p) +{ + // If REFINING66() executed, then we zero the OSZ variable. The other + // osz's live on to be returned as 1 here. The REFINING indicator is + // not removed for OSZ-nonrefining operations. + if ( xed3_operand_get_osz(p)) + return 1; + return 0; +} +xed_bool_t +xed_operand_values_has_66_prefix(const xed_operand_values_t* p) +{ + if ( xed3_operand_get_prefix66(p)) + return 1; + return 0; +} + +xed_bool_t +xed_operand_values_has_rexw_prefix(const xed_operand_values_t* p) +{ + if ( xed3_operand_get_rexw(p)) + return 1; + return 0; +} + +xed_bool_t +xed_operand_values_accesses_memory(const xed_operand_values_t* p) +{ + if (xed3_operand_get_mem0(p) || + xed3_operand_get_mem1(p) ) + return 1; + return 0; +} + +unsigned int +xed_operand_values_number_of_memory_operands(const xed_operand_values_t* p) { + unsigned int memops = xed3_operand_get_mem0(p) + + xed3_operand_get_mem1(p); + return memops; +} + + +xed_reg_enum_t +xed_operand_values_get_base_reg(const xed_operand_values_t* p, + unsigned int memop_idx) { + if (memop_idx == 0) + return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_base0(p)); + if (memop_idx == 1) + return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_base1(p)); + xed_assert(0); + return XED_REG_INVALID; +} + +xed_reg_enum_t +xed_operand_values_get_seg_reg(const xed_operand_values_t* p, + unsigned int memop_idx) +{ + if (memop_idx == 0) + return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_seg0(p)); + if (memop_idx == 1) + return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_seg1(p)); + xed_assert(0); + return XED_REG_INVALID; +} + +xed_reg_enum_t +xed_operand_values_get_index_reg(const xed_operand_values_t* p, + unsigned int memop_idx) +{ + if (memop_idx == 0) + return XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_index(p)); + xed_assert(0); + return XED_REG_INVALID; +} + +unsigned int +xed_operand_values_get_scale(const xed_operand_values_t* p) +{ + if (xed3_operand_get_mem0(p) || xed3_operand_get_agen(p)) + return (xed3_operand_get_scale(p))?xed3_operand_get_scale(p):1; + return 0; +} + +xed_bool_t +xed_operand_values_branch_not_taken_hint(const xed_operand_values_t* p) +{ + if (xed3_operand_get_hint(p)==3) + return 1; + return 0; +} +xed_bool_t +xed_operand_values_branch_taken_hint(const xed_operand_values_t* p) +{ + if (xed3_operand_get_hint(p)==4) + return 1; + return 0; +} + + + +xed_bool_t +xed_operand_values_is_nop(const xed_operand_values_t* p) +{ + const xed_iclass_enum_t iclass = xed_operand_values_get_iclass(p); + + if (iclass == XED_ICLASS_NOP) + return 1; + if (iclass >= XED_ICLASS_NOP2 && iclass <= XED_ICLASS_NOP9) + return 1; + + if (iclass == XED_ICLASS_XCHG) { + xed_reg_enum_t r0 = XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_reg0(p)); + xed_reg_enum_t r1 = XED_STATIC_CAST(xed_reg_enum_t,xed3_operand_get_reg1(p)); + + // EAX is special on the 32b 1-byte NOP in 64b mode. It is a + // NOP. That is critically caught by the above test!!!! + + //Any other register in this situation is NOT a nop! Even EAX with + //a non-one-byte XCHG is not a NOP! It zero's the upper part of + //RAX. (or whatever dest reg). So we exclude the 32b regs below in + //64b mode. + + // we can also call xchg reg64,reg64 a nop xchg reg8,reg8 xchg + // reg16,reg16 NOPs if the regs are the same in any mode. Those + // are not official NOPs but act like them. + + if (r0 == r1) { + if (xed_operand_values_get_long_mode(p)) + if (xed_gpr_reg_class(r0) == XED_REG_CLASS_GPR32) + return 0; + return 1; + } + } + + return 0; +} + + + + + +xed_int32_t +xed_operand_values_get_branch_displacement_int32( + const xed_operand_values_t* p) +{ + const xed_decoded_inst_t* xedd = (const xed_decoded_inst_t*)p; // same type + unsigned int len = xed3_operand_get_brdisp_width(xedd); + switch(len) { + case 8: + case 16: + case 32: + return xed3_operand_get_disp(xedd); + default: + return 0; + } +} + +xed_int64_t +xed_operand_values_get_immediate_int64(const xed_operand_values_t* p) +{ + xed_uint8_t len = xed3_operand_get_imm_width(p); + xed_uint64_t raw_imm = xed3_operand_get_uimm0(p); + switch(len){ + case 8: return xed_sign_extend8_64(raw_imm); + case 16: return xed_sign_extend16_64(raw_imm); + case 32: return xed_sign_extend32_64(raw_imm); + case 64: return raw_imm; + default: + return 0; + } + return 0; + +} + +xed_uint64_t +xed_operand_values_get_immediate_uint64(const xed_operand_values_t* p) { + return xed3_operand_get_uimm0(p); +} + +xed_uint_t +xed_operand_values_get_immediate_is_signed(const xed_operand_values_t* p) { + return xed3_operand_get_imm0signed(p); +} + +xed_uint8_t +xed_operand_values_get_immediate_byte(const xed_operand_values_t* p, + unsigned int i) { + unsigned int len = xed3_operand_get_imm_width(p); + if (xed3_operand_get_imm0(p)) { + xed_uint64_t y = xed_operand_values_get_immediate_uint64(p); //FIXME: BENDIAN + return xed_get_byte(y, i, len); + } + return 0; +} + +xed_uint8_t +xed_operand_values_get_second_immediate(const xed_operand_values_t* p) { + if (xed3_operand_get_imm1(p)) + return xed3_operand_get_uimm1(p); + return 0; +} + +xed_uint8_t +xed_operand_values_get_memory_displacement_byte(const xed_operand_values_t* p, + unsigned int i) { + unsigned int len = xed3_operand_get_disp_width(p); + xed_uint64_t y = xed_operand_values_get_memory_displacement_int64(p); //FIXME: BENDIAN + return xed_get_byte(y, i, len); +} + +xed_uint8_t +xed_operand_values_get_branch_displacement_byte(const xed_operand_values_t* p, + unsigned int i) { + unsigned int len = xed3_operand_get_brdisp_width(p); + xed_int32_t v = xed_operand_values_get_branch_displacement_int32(p); //FIXME: BENDIAN + return xed_get_byte(v, i, len); +} + +xed_iclass_enum_t +xed_operand_values_get_iclass(const xed_operand_values_t* p) { + return XED_STATIC_CAST(xed_iclass_enum_t,xed3_operand_get_iclass(p)); +} + +//////////////////////////////////////////////////////////////////// +// ENCODE +//////////////////////////////////////////////////////////////////// +void xed_operand_values_zero_immediate(xed_operand_values_t* p) { + xed3_operand_set_imm_width(p,0); + xed3_operand_set_uimm0(p,0); +} + +void xed_operand_values_zero_branch_displacement(xed_operand_values_t* p) { + xed3_operand_set_brdisp_width(p,0); + xed3_operand_set_disp(p,0); +} + +void xed_operand_values_zero_memory_displacement(xed_operand_values_t* p) { + xed3_operand_set_disp_width(p,0); + xed3_operand_set_disp(p,0); +} + +void xed_operand_values_set_lock(xed_operand_values_t* p) { + xed3_operand_set_lock(p,1); +} +void xed_operand_values_zero_segment_override(xed_operand_values_t* p) { + xed3_operand_set_seg_ovd(p,0); + /* Also remove the segment specifiers in SEG0/SEG1. If they are + * default, they don't matter for encoding. This is assumed to be part + * of a re-encode sequence. 2008-10-01 */ + xed3_operand_set_seg0(p,XED_REG_INVALID); + xed3_operand_set_seg1(p,XED_REG_INVALID); +} + +void +xed_operand_values_set_iclass(xed_operand_values_t* p, + xed_iclass_enum_t iclass) { + xed3_operand_set_iclass(p,iclass); +} + +void +xed_operand_values_set_relbr(xed_operand_values_t* p) { + xed3_operand_set_relbr(p,1); +} + +void +xed_operand_values_set_effective_operand_width(xed_operand_values_t* p, + unsigned int width) { + unsigned int eosz=0; + switch(width) { + case 8: eosz=0; break; + case 16: eosz=1; break; + case 32: eosz=2; break; + case 64: eosz=3; break; // default is 2 + default: xed_assert(0); + } + xed3_operand_set_eosz(p,eosz); +} + +void +xed_operand_values_set_effective_address_width(xed_operand_values_t* p, + unsigned int width) { + unsigned int easz=0; + switch(width) { + case 16: easz=1; break; + case 32: easz=2; break; + case 64: easz=3; break; + default: xed_assert(0); + } + xed3_operand_set_easz(p,easz); +} + +void +xed_operand_values_set_memory_operand_length(xed_operand_values_t* p, + unsigned int memop_length) { + xed3_operand_set_mem_width(p,XED_STATIC_CAST(xed_uint32_t,memop_length)); +} + +unsigned int +xed_operand_values_get_memory_operand_length(const xed_operand_values_t* p, + unsigned int memop_idx) { + return xed3_operand_get_mem_width(p); + (void)memop_idx; +} + +void +xed_operand_values_set_memory_displacement(xed_operand_values_t* p, + xed_int64_t x, + unsigned int len) { + xed_operand_values_set_memory_displacement_bits(p,x,len*8); +} + +void +xed_operand_values_set_memory_displacement_bits(xed_operand_values_t* p, + xed_int64_t x, + unsigned int len) { + /* Set the real displacement value x in big-endian form for emitting. + * Make sure that the LSB of x is the MSB of the xed3_operand_get_(p)* field + * because we emit them starting from the MSB based on the width */ + + xed_assert(len==0 || len==8 || len==16 || len==32 || len==64); + if (len==0){ + xed3_operand_set_disp(p,0); + } + else{ + xed3_operand_set_disp(p,x); + } + xed3_operand_set_disp_width(p,len); +} + +void +xed_operand_values_set_branch_displacement(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len) { + xed_operand_values_set_branch_displacement_bits(p,x,len*8); +} +void +xed_operand_values_set_branch_displacement_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len) { + /* Set the real displacement value x in big-endian form for emitting. + * Make sure that the LSB of x is the MSB of the xed3_operand_get_(p)* field + * because we emit them starting from the MSB based on the width */ + xed_assert(len==0 || len==8 || len==16 || len==32); + if (len ==0){ + xed3_operand_set_disp(p,0); + } + else{ + xed3_operand_set_disp(p,x); + } + xed3_operand_set_brdisp_width(p,XED_STATIC_CAST(xed_uint16_t,len)); + +} + +void xed_operand_values_set_immediate_signed(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len) { + xed_operand_values_set_immediate_signed_bits(p,x,len*8); +} + +void xed_operand_values_set_immediate_signed_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len) { + + xed_int64_t x_64 = x; //for sign extension + xed_operand_values_set_immediate_unsigned_bits(p,x_64,len); + xed3_operand_set_imm0signed(p,1); +} + +void xed_operand_values_set_immediate_unsigned(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bytes) { + xed_operand_values_set_immediate_unsigned_bits(p,x,bytes*8); +} +void xed_operand_values_set_immediate_unsigned_bits(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bits) { + + /* Set the real displacement value x in big-endian form for emitting. + * Make sure that the LSB of x is the MSB of the xed3_operand_get_(p)* field + * because we emit them starting from the MSB based on the width */ + + xed_assert(bits==0 || bits==8 || bits==16 || bits==32 || bits==64); + if (bits == 0){ + xed3_operand_set_uimm0(p,0); + } + else{ + xed3_operand_set_uimm0(p,x); + } + + xed3_operand_set_imm_width(p,bits); + xed3_operand_set_imm0signed(p,0); +} + + +/*-----------------------------------------------------------------------------*/ + +void xed_operand_values_set_base_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_base) { + if (memop_idx == 0) + xed3_operand_set_base0(p,new_base); + else if (memop_idx == 1) + xed3_operand_set_base1(p,new_base); + else + xed_assert(0); +} + +void xed_operand_values_set_seg_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_seg) { + if (memop_idx == 0) + xed3_operand_set_seg0(p,new_seg); + else if (memop_idx == 1) + xed3_operand_set_seg1(p,new_seg); + else + xed_assert(0); +} + + +void xed_operand_values_set_index_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_index) { + if (memop_idx == 0) + xed3_operand_set_index(p,new_index); + else + xed_assert(0); +} + +void xed_operand_values_set_scale(xed_operand_values_t* p, + xed_uint_t memop_idx, + xed_uint_t new_scale) { + if (memop_idx == 0) + xed3_operand_set_scale(p,new_scale); + else + xed_assert(0); +} + +void +xed_operand_values_set_operand_reg(xed_operand_values_t* p, + xed_operand_enum_t operand_name, + xed_reg_enum_t reg_name) { + switch(operand_name){ + case XED_OPERAND_REG0: xed3_operand_set_reg0(p,reg_name); break; + case XED_OPERAND_REG1: xed3_operand_set_reg1(p,reg_name); break; + case XED_OPERAND_REG2: xed3_operand_set_reg2(p,reg_name); break; + case XED_OPERAND_REG3: xed3_operand_set_reg3(p,reg_name); break; + case XED_OPERAND_REG4: xed3_operand_set_reg4(p,reg_name); break; + case XED_OPERAND_REG5: xed3_operand_set_reg5(p,reg_name); break; + case XED_OPERAND_REG6: xed3_operand_set_reg6(p,reg_name); break; + case XED_OPERAND_REG7: xed3_operand_set_reg7(p,reg_name); break; + case XED_OPERAND_REG8: xed3_operand_set_reg8(p,reg_name); break; + case XED_OPERAND_BASE0: xed3_operand_set_base0(p,reg_name); break; + case XED_OPERAND_BASE1: xed3_operand_set_base1(p,reg_name); break; + case XED_OPERAND_INDEX: xed3_operand_set_index(p,reg_name); break; + case XED_OPERAND_SEG0: xed3_operand_set_seg0(p,reg_name); break; + case XED_OPERAND_SEG1: xed3_operand_set_seg1(p,reg_name); break; + default: xed_assert(0); + } +} + +//////////////////////////////////////////////////////////////////// +// PRINTING +//////////////////////////////////////////////////////////////////// +static const char* xed_ptr_size(xed_uint_t bytes) { + extern const char* xed_pointer_name[XED_MAX_POINTER_NAMES]; + if (bytes < XED_MAX_POINTER_NAMES) + if (xed_pointer_name[bytes]) + return xed_pointer_name[bytes]; + return ""; +} + +void xed_operand_values_print_short(const xed_operand_values_t* ov, char* buf, int buflen) { + xed_operand_values_dump(ov,buf, buflen); +} + +static xed_bool_t add_comma(xed_bool_t emitted, char* buf, int* blen) { + if (emitted) + *blen = xed_strncat(buf,", ", *blen); + return 1; +} + +static int emit_agen_and_mem(const xed_operand_values_t* ov, + char * buf, + int i, + int buflen) +{ + xed_reg_enum_t base = xed3_operand_get_base0(ov); + xed_reg_enum_t seg = xed3_operand_get_seg0(ov); + xed_reg_enum_t index = xed3_operand_get_index(ov); + xed_int64_t be_disp = xed_operand_values_get_memory_displacement_int64(ov); + xed_bits_t scale = xed3_operand_get_scale(ov); + xed_bool_t started = 0; + xed_bool_t leading_zeros = 0; + xed_uint_t bytes = xed_operand_values_get_memory_operand_length(ov,0); + int blen = buflen; + blen = xed_strncat(buf, xed_operand_enum_t2str(XED_STATIC_CAST(xed_operand_enum_t,i)),blen); + blen = xed_strncat(buf, ":", blen); + blen = xed_strncat(buf, xed_ptr_size(bytes),blen); + blen = xed_strncat(buf,"ptr ",blen); + if (seg != XED_REG_INVALID) + if (i != XED_OPERAND_AGEN) + blen = xed_strncat(buf, xed_reg_enum_t2str(seg),blen); + blen = xed_strncat(buf,"[",blen); + if (base != XED_REG_INVALID) { + blen = xed_strncat(buf, xed_reg_enum_t2str(base),blen); + started = 1; + } + if (index != XED_REG_INVALID) { + if (started) + blen = xed_strncat(buf,"+",blen); + started = 1; + blen = xed_strncat(buf, xed_reg_enum_t2str(index),blen); + blen = xed_strncat(buf,"*",blen); + blen = xed_itoa(buf+xed_strlen(buf), XED_STATIC_CAST(xed_uint_t,scale),blen); + } + + if (be_disp != 0) { + unsigned int disp_bits = xed_operand_values_get_memory_displacement_length_bits(ov); + xed_uint_t negative = (be_disp < 0) ? 1 : 0; + if (started) { + if (negative) { + blen = xed_strncat(buf,"-",blen); + be_disp = - be_disp; + } + else + blen = xed_strncat(buf,"+",blen); + } + blen = xed_strncat(buf,"0x",blen); + blen = xed_itoa_hex_zeros(buf+xed_strlen(buf), be_disp, disp_bits, leading_zeros,blen); + } + blen = xed_strncat(buf,"]",blen); + return blen; +} + +void +xed_operand_values_dump( const xed_operand_values_t* ov, + char* buf, + int buflen) +{ + xed_uint_t i = XED_OPERAND_INVALID+1; + xed_bool_t leading_zeros = 0; + xed_bool_t emitted = 0; + int blen = buflen; + *buf = 0; /* allow use of xed_strncat */ + for( ; i 1){ + blen = xed_strncat(buf, ":", blen); + blen = xed_strncat(buf+xed_strlen(tmp_buf), tmp_buf,blen); + } + } + } /* default block*/ + } /* switch */ + } /* for */ + } + + + diff --git a/src/xed-portability.c b/src/xed-portability.c new file mode 100644 index 0000000..daa91cd --- /dev/null +++ b/src/xed-portability.c @@ -0,0 +1,115 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-portability.cpp +/// + + + +//////////////////////////////////////////////////////////////////////////// +#include "xed-portability.h" +#include "xed-util.h" +#include // scrcat, strncat, strlen +//////////////////////////////////////////////////////////////////////////// +// DEFINES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// TYPES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// PROTOTYPES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// GLOBALS +//////////////////////////////////////////////////////////////////////////// + + + +#if 0 /* not used */ +void xed_strcat(char* dst, const char* src) { +#if defined(_WIN32) && !defined(__GNUC__) +# if defined(XED_MSVC6) || defined(XED_MSVC7) || defined(XED_IPF) || defined(PIN_CRT) + strcat(dst, src); +# else + // total hack to avoid warnings. Assuming people don't overflow their + // input buffers. FIXME + strcat_s(dst,xed_strlen(dst)+xed_strlen(src)+1, src); +# endif +#else + strcat(dst,src); +#endif +} +#endif + +int xed_strncat(char* dst, const char* src, int len) { + int dst_len = xed_strlen(dst); + int orig_max = dst_len + len; + int new_length = dst_len + xed_strlen(src) + 1; /* with null */ + if (len <= 0) + return 0; + /* if our source string with our dest string overflows the buffer, then + * stop adding stuff to the buffer. The null is included in the + * estimate of the new string length. */ + if (new_length > orig_max) + return 0; + // len is the maximum number of bytes to copy. +#if defined(_WIN32) && !defined(__GNUC__) +# if defined(XED_MSVC6) || defined(XED_MSVC7) || defined(XED_IPF) || defined(PIN_CRT) + strncat(dst, src, len); +# else + // MS wants the total length of the dst buffer and not the number of + // bytes to copy. + strcat_s(dst, xed_strlen(dst)+len, src); +# endif +#else + strncat(dst,src,len); +#endif + return orig_max - xed_strlen(dst); +} + +xed_uint_t xed_strlen(const char* s) { + return XED_STATIC_CAST(xed_uint_t,strlen(s)); +} + +void xed_strcpy(char* dst, const char* src) { + const char* psrc = src; + char* pdst = dst; + while(*psrc) + *pdst++ = *psrc++; + *pdst = 0; +} +int xed_strncpy(char* dst, const char* src, int len) { + int orig_max = len; + const char* psrc = src; + char* pdst = dst; + int i=0; + if (len <= 0) + return 0; + for(;*psrc && immode),blen); + blen = xed_strncat(buf," AddrWidth: ",blen); + blen = xed_strncat(buf, + xed_address_width_enum_t2str(xed_state_get_address_width(p)),blen); + blen = xed_strncat(buf," StackAddrWidth: ",blen); + blen = xed_strncat(buf, + xed_address_width_enum_t2str(p->stack_addr_width),blen); + return blen; +} + + diff --git a/src/xed-table-sizes.c b/src/xed-table-sizes.c new file mode 100644 index 0000000..db7f281 --- /dev/null +++ b/src/xed-table-sizes.c @@ -0,0 +1,74 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include +#include "xed-interface.h" +#include "xed-tables-extern.h" + +#define XED_PRINT_TSZ(x) \ + do { \ + bytes += sizeof(x) ; \ + printf("%8ld : " #x "\n", sizeof(x)); \ + } while(0) + +void xed_table_sizes(void) { +#if defined(XED_INTROSPECTIVE) + xed_uint32_t bytes = 0; + printf("Tables:\n"); + XED_PRINT_TSZ( xed_inst_table ); + XED_PRINT_TSZ( xed_operand ); + XED_PRINT_TSZ( xed_operand_sequences ); + XED_PRINT_TSZ( xed_iform_db ); + XED_PRINT_TSZ( xed_decode_graph ); + XED_PRINT_TSZ( xed_attributes_table ); + XED_PRINT_TSZ( xed_iform_first_per_iclass_table ); + XED_PRINT_TSZ( xed_iform_max_per_iclass_table ); + XED_PRINT_TSZ( xed_enc_func ); + XED_PRINT_TSZ( xed_encode_order ); + XED_PRINT_TSZ( xed_encode_order_limit ); + XED_PRINT_TSZ( xed_reg_class_array ); + XED_PRINT_TSZ( xed_gpr_reg_class_array ); + XED_PRINT_TSZ( xed_reg_width_bits ); + XED_PRINT_TSZ( xed_largest_enclosing_register_array ); + XED_PRINT_TSZ( xed_width_bits ); + XED_PRINT_TSZ( xed_operand_type_table ); + XED_PRINT_TSZ( xed_operand_xtype_info ); + XED_PRINT_TSZ( xed_operand_element_width ); + XED_PRINT_TSZ( xed_width_is_bytes ); + XED_PRINT_TSZ( xed_flags_simple_table ); + XED_PRINT_TSZ( xed_flags_complex_table ); + XED_PRINT_TSZ( xed_flag_action_table ); + + printf("%8d : Total\n", bytes); + + printf("\nUnderlying Data structures:\n"); + XED_PRINT_TSZ( xed_simple_flag_t ); + XED_PRINT_TSZ( xed_decoded_inst_t ); + XED_PRINT_TSZ( xed_graph_node_t ); + XED_PRINT_TSZ( xed_inst_t ); + XED_PRINT_TSZ( xed_operand_t ); + XED_PRINT_TSZ( xed_decode_cache_entry_t ); + XED_PRINT_TSZ( xed_decode_cache_t ); + + printf("\nFlags Data structures:\n"); + + XED_PRINT_TSZ( xed_flag_action_t ); + XED_PRINT_TSZ( xed_flag_set_t ); +#endif +} diff --git a/src/xed-util.c b/src/xed-util.c new file mode 100644 index 0000000..cd42355 --- /dev/null +++ b/src/xed-util.c @@ -0,0 +1,615 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-util.c +/// + + +//////////////////////////////////////////////////////////////////////////// + +#include "xed-types.h" +#include "xed-util.h" +#include "xed-util-private.h" +#include "xed-portability.h" +#include "xed-portability-private.h" +#include "xed-common-defs.h" +#include "xed-common-hdrs.h" + +#if defined(__linux__) && defined(__STDC_HOSTED__) && __STDC_HOSTED__ == 0 + extern void abort (void) __attribute__ ((__noreturn__)); +#else +# include +#endif + +#include + + +//////////////////////////////////////////////////////////////////////////// +int xed_verbose = 2; + +#include //required for fprintf,stderr in xed_abort() +#if defined(XED_MESSAGES) +FILE* xed_log_file; +#endif + +//////////////////////////////////////////////////////////////////////////// +void xed_set_verbosity(int v) { + xed_verbose = v; +} + +void xed_set_log_file(void* o) { +#if defined(XED_MESSAGES) + xed_log_file = (FILE*)o; +#else + (void)o; +#endif + +} + + + + + +#if !defined(XED_64B) +static XED_INLINE xed_uint64_t get_bit63(xed_uint64_t x) { + const xed_uint64_t s = 63; + return (x >> s) & 1; +} + +static XED_INLINE xed_uint64_t xed_divide_by_10_64by32(xed_uint64_t numerator) { + /* ONLY WORKS FOR DIVIDE BY 10 because 2*9+1=19 and that is < 20, so I can use subtract */ + int i=0; + const xed_uint32_t denominator = 10; + xed_uint64_t tn=numerator; + xed_uint64_t tqlo=0; + xed_uint32_t ir=0,b=0; + xed_uint32_t num=0; + xed_uint32_t qbit=0; + + /* binary long division */ + for(i=0;i<64;i++) { + b = get_bit63(tn); // next bit of the numerator + num = (ir << 1) | b; // intermediate remainder from last step + new numerator bit + if (num >= denominator) { + ir = num - denominator; + qbit = 1; + } + else { + ir = num; + qbit = 0; + } + tqlo = (tqlo <<1) | qbit; + tn = tn << 1; + } + + // ignore quotient overflow; + return tqlo; +} +#endif + +int xed_itoa(char* buf, xed_uint64_t f, int buflen) { + char tbuf[100]; + char* p = tbuf; + char* fp; + xed_uint64_t t = f; + xed_uint64_t x,v; + + if (f == 0) { + *p++ = '0'; + *p = 0; + return xed_strncpy(buf,tbuf,buflen); + } + + while(t) { +#if defined(XED_64B) + x = t / 10; +#else + x = xed_divide_by_10_64by32(t); +#endif + v = t - (x*10); + *p++ = '0' + v; + t = x; + } + /* reverse string */ + *p=0; + p--; + fp = tbuf; + while(fp < p) { + char ec = *p; + char fc = *fp; + *fp = ec; + *p = fc; + fp++; + p--; + } + + return xed_strncpy(buf,tbuf,buflen); +} + +static int add_leading_zeros(char* buf, + char* tbuf, + int buflen, + xed_uint_t bits_to_print) +{ + char* p = buf; + xed_uint_t ilen = xed_strlen(tbuf); + if (ilen < bits_to_print) { + xed_uint_t i; + xed_uint_t zeros = bits_to_print - ilen; + for(i=0 ; i < zeros && buflen>0 ; i++) { + buflen--; + *p++ = '0'; + } + } + return xed_strncpy(p,tbuf,buflen); +} + + +int xed_itoa_hex_ul(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen, + xed_bool_t lowercase) +{ + const xed_uint64_t one = 1; + xed_uint_t nibbles_to_print = (bits_to_print+3)/4; + xed_uint64_t mul,rdiv; + xed_uint64_t n; + char tbuf[100]; + char* p = tbuf; + // mask the value to the bits we care about. makes everything else easier. + xed_uint64_t ff,t; + xed_uint_t div = 0; + char base_letter; + + if (bits_to_print == 64) // no masking required + ff = f; + else + ff = f & ((one<> 4; + div++; + } + + n = ff; + + if (lowercase) + base_letter = 'a'; + else + base_letter = 'A'; + + while(div > 0) { + + div--; + rdiv = one<<(4*div); + //mul = xed_divide(n,rdiv); + mul = (n >> (4*div)) & 0xF; + if (div <= nibbles_to_print) { + if (mul<10) + *p++ = XED_STATIC_CAST(char,mul + '0'); + else + *p++ = XED_STATIC_CAST(char,mul - 10 + base_letter); + } + n = n - (mul*rdiv); + } + + // tack on a null + *p = 0; + if (leading_zeros) + return add_leading_zeros(buf,tbuf,buflen,bits_to_print); + return xed_strncpy(buf,tbuf,buflen); +} + +int xed_itoa_hex_zeros(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen) { + const xed_bool_t lowercase=1; + return xed_itoa_hex_ul(buf,f,bits_to_print, leading_zeros, buflen, lowercase); + (void) leading_zeros; +} + +int xed_itoa_hex(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + int buflen) +{ + const xed_bool_t lowercase = 1; + const xed_bool_t leading_zeros = 0; + return xed_itoa_hex_ul(buf, f, bits_to_print, leading_zeros, buflen, lowercase); +} + +int xed_itoa_signed(char* buf, xed_int64_t f, int buflen) { + xed_uint64_t x; + int blen = buflen; + if (f<0) { + blen = xed_strncpy(buf,"-",blen); + x = -f; + } + else + x = f; + return xed_itoa(buf+xed_strlen(buf), x, blen); +} + +int xed_sprintf_uint8_hex(char* buf, xed_uint8_t x, int buflen) { + return xed_itoa_hex(buf,x,8,buflen); +} +int xed_sprintf_uint16_hex(char* buf, xed_uint16_t x, int buflen) { + return xed_itoa_hex(buf,x,16,buflen); +} +int xed_sprintf_uint32_hex(char* buf, xed_uint32_t x, int buflen) { + return xed_itoa_hex(buf,x,32,buflen); +} +int xed_sprintf_uint64_hex(char* buf, xed_uint64_t x, int buflen) { + return xed_itoa_hex(buf,x,64,buflen); +} +int xed_sprintf_uint8(char* buf, xed_uint8_t x, int buflen) { + return xed_itoa(buf, x, buflen); +} +int xed_sprintf_uint16(char* buf, xed_uint16_t x, int buflen) { + return xed_itoa(buf, x, buflen); +} +int xed_sprintf_uint32(char* buf, xed_uint32_t x, int buflen) { + return xed_itoa(buf, x, buflen); +} +int xed_sprintf_uint64(char* buf, xed_uint64_t x, int buflen) { + return xed_itoa(buf, x, buflen); +} +int xed_sprintf_int8(char* buf, xed_int8_t x, int buflen) { + return xed_itoa_signed(buf,x,buflen); +} +int xed_sprintf_int16(char* buf, xed_int16_t x, int buflen) { + return xed_itoa_signed(buf,x,buflen); +} +int xed_sprintf_int32(char* buf, xed_int32_t x, int buflen) { + return xed_itoa_signed(buf,x,buflen); +} +int xed_sprintf_int64(char* buf, xed_int64_t x, int buflen) { + return xed_itoa_signed(buf,x,buflen); +} + +char xed_to_ascii_hex_nibble(xed_uint_t x, xed_bool_t lowercase) { + if (x<=9) + return XED_STATIC_CAST(char,x+'0'); + if (x<=15) { + if (lowercase) + return XED_STATIC_CAST(char,x-10+'a'); + else + return XED_STATIC_CAST(char,x-10+'A'); + } + return '?'; +} +static char xed_tolower(char c) { + if (c >= 'A' && c <= 'Z') + return c-'A'+'a'; + return c; +} + + +int xed_strncat_lower(char* dst, const char* src, int len) { + unsigned int dst_len = xed_strlen(dst) ; + unsigned int orig_max = dst_len + len; + unsigned int i; + unsigned int src_len = xed_strlen(src); + unsigned int copy_max = src_len; + unsigned int ulen = (unsigned int)len-1; + if (len <= 0) + return 0; + + /* do not copy more bytes than fit in the buffer including the null */ + + if (src_len > ulen) + copy_max = ulen; + + for(i=0;i %x\n", x,y); + z= xed_sign_extend32_64(y); + //printf("SEXT -> %lx\n", z); + return z; + } + case 64: { + xed_uint64_t z = xed_make_uint64(xed_bswap32(hi_le),xed_bswap32(lo_le)); + return XED_STATIC_CAST(xed_int64_t,z); + } + default: + xed_assert(0); + return 0; + } +} +xed_uint64_t xed_little_endian_hilo_to_uint64(xed_uint32_t hi_le, xed_uint32_t lo_le, unsigned int len) { + switch(len) { + case 4: + return XED_STATIC_CAST(xed_uint8_t,lo_le&0xF); + case 8: + return XED_STATIC_CAST(xed_uint8_t,lo_le); + case 16: + return xed_bswap16(XED_STATIC_CAST(xed_uint16_t,lo_le)); + case 32: + return xed_bswap32(XED_STATIC_CAST(xed_uint32_t,lo_le)); + case 64: + return xed_make_uint64(xed_bswap32(hi_le),xed_bswap32(lo_le)); + default: + xed_assert(0); + return 0; + } +} + +xed_uint64_t xed_little_endian_to_uint64(xed_uint64_t x, unsigned int len) { + switch(len) { + case 4: + return XED_STATIC_CAST(xed_uint8_t,x&0xF); + case 8: + return XED_STATIC_CAST(xed_uint8_t,x); + case 16: + return xed_bswap16(XED_STATIC_CAST(xed_uint16_t,x)); + case 32: + return xed_bswap32(XED_STATIC_CAST(xed_uint32_t,x)); + case 64: + return xed_bswap64(x); + default: + xed_assert(0); + return 0; + } +} + +xed_int64_t xed_little_endian_to_int64(xed_uint64_t x, unsigned int len){ + switch(len) { + case 4: + return xed_sign_extend4_64(XED_STATIC_CAST(xed_int8_t,x&0xF)); + case 8: + return xed_sign_extend8_64(XED_STATIC_CAST(xed_int8_t,x)); + case 16: + return xed_sign_extend16_64(xed_bswap16(XED_STATIC_CAST(xed_uint16_t,x))); + case 32: { + xed_int32_t y = xed_bswap32(XED_STATIC_CAST(xed_uint32_t,x)); + xed_int64_t z; + //printf("BSWAPING %lx -> %x\n", x,y); + z= xed_sign_extend32_64(y); + //printf("SEXT -> %lx\n", z); + return z; + } + case 64: + return XED_STATIC_CAST(xed_int64_t,xed_bswap64(x)); + default: + xed_assert(0); + return 0; + } +} + +xed_int32_t xed_little_endian_to_int32(xed_uint64_t x, unsigned int len){ + // heavily reliant on the type system + switch(len) { + case 4: + return xed_sign_extend4_32(XED_STATIC_CAST(xed_int8_t,x&0xF)); + case 8: + return xed_sign_extend8_32(XED_STATIC_CAST(xed_int8_t,x)); + case 16: + return xed_sign_extend16_32(xed_bswap16(XED_STATIC_CAST(xed_uint16_t,x))); + case 32: { + xed_int32_t y = xed_bswap32(XED_STATIC_CAST(xed_uint32_t,x)); + return y; + } + default: + xed_assert(0); + return 0; + } +} +#endif + +xed_uint8_t xed_get_byte(xed_uint64_t x, unsigned int i, unsigned int len) { + // THIS IS THE "IN REGISTER" VIEW! + // 1B .. .. .. .. .. .. .. 00 + // 2B .. .. .. .. .. .. 11 00 + // 4B .. .. .. .. 33 22 11 00 + // 8B 77 66 55 44 33 22 11 00 + // (The least significant byte is 00) + + xed_assert (i < len); + return XED_BYTE_CAST(x >> (i*8)); + (void)len; //pacify compiler +} + + + +xed_uint_t +xed_shortest_width_signed(xed_int64_t x, xed_uint8_t legal_widths) { + static const xed_int64_t max1[] = { 0x7f, 0x7fff, 0x7fffffff }; + static const xed_int64_t min1[] = { -128, + 0xffffffffffff8000LL, + 0xffffffff80000000LL }; + /*historical note: I experimented with different ways of computing the + * constants without making memory references, by shifting, etc. The + * thing is that any way I coded it, Gcc's optimizer unrolled the loop, + * removed the shifts or memops and did the right thing! I was + * astounded. This version of the code was the simplest to maintain + * and understand so I'm sticking with it. + */ + unsigned int i,j; + for(i=0;i<3;i++) + { + j = 1 << i; + if ((j & legal_widths)==j) + if (x <= max1[i] && x >= min1[i]) + break; + } + /* returns 1,2,4 or 8 */ + return 1<_inst - xed_inst_table); + + xed3_chain_function_t capture_fptr; + + + capture_fptr = xed3_chain_fptr_lu[inum]; + + return (*capture_fptr)(d); +} + +/* sets information about register operands with ntluf */ +XED_DLL_EXPORT +xed_error_enum_t xed3_decode_operands(xed_decoded_inst_t* d) +{ + xed_uint32_t inum = + (xed_uint32_t)(d->_inst - xed_inst_table); + + xed3_chain_function_t capture_fptr; + + + capture_fptr = xed3_op_chain_fptr_lu[inum]; + + return (*capture_fptr)(d); +} + diff --git a/src/xed3-static-decode.c b/src/xed3-static-decode.c new file mode 100644 index 0000000..579e2ae --- /dev/null +++ b/src/xed3-static-decode.c @@ -0,0 +1,52 @@ +/*BEGIN_LEGAL + +Copyright (c) 2016 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed3-static-decode.c +/// static info decoder (xed_inst_t) + + + +#include "xed-ild.h" +#include "xed3-phash.h" + +/* returns the index for xed_inst_table */ +XED_DLL_EXPORT +void xed3_static_decode(xed_decoded_inst_t* d) +{ + xed_uint_t vv = xed3_operand_get_vexvalid(d); + xed_ild_map_enum_t map = xed3_operand_get_map(d); + xed_uint32_t xed3_idx=0; + const xed_inst_t* inst; + + if (map < XED_PHASH_MAP_LIMIT) + { + // KW gets a false positive on the next line for indices. + xed3_find_func_t const* find_f_arr = xed3_phash_lu[vv][map]; + if (find_f_arr) // very predictable branch, mostly taken + { + xed_uint8_t opcode; + opcode = (xed_uint8_t)xed3_operand_get_nominal_opcode(d); + // we have 0 for undefined map-opcodes as function pointer + xed3_find_func_t find_f = find_f_arr[opcode]; + if (find_f) + xed3_idx = (*find_f)(d); + } + } + inst = xed_inst_table + xed3_idx; + xed_decoded_inst_set_inst(d, inst); +} + diff --git a/tests/REBASE.TESTS b/tests/REBASE.TESTS new file mode 100755 index 0000000..2875102 --- /dev/null +++ b/tests/REBASE.TESTS @@ -0,0 +1,2 @@ +./run-cmd.py --build-dir ../obj/examples --rebase-tests --tests tests-base --tests tests-avx512 --tests tests-xop --tests test-avx512pf +./run-cmd.py --build-dir ../obj-knc/examples --rebase-tests --tests tests-knc diff --git a/tests/RECREATE.TESTS b/tests/RECREATE.TESTS new file mode 100755 index 0000000..8dc3639 --- /dev/null +++ b/tests/RECREATE.TESTS @@ -0,0 +1,9 @@ +./run-cmd.py --build-dir ../obj/examples -b bulk-tests/bulk-tests.txt -b bulk-tests/avx-bulk-tests.txt -b bulk-tests/hsw-bulk-tests.txt -b bulk-tests/new-tests.txt --otests tests-base + +./run-cmd.py --build-dir ../obj/examples --otests tests-avx512 -b bulk-tests/avx512x-bulk-tests.txt +./run-cmd.py --build-dir ../obj/examples --otests tests-avx512pf -b bulk-tests/avx512pf-bulk-tests.txt + +./run-cmd.py --build-dir ../obj/examples-knc --otests tests-knc -b bulk-tests/knc-bulk-tests.txt + +./run-cmd.py --build-dir ../obj/examples --otests tests-xop -b bulk-tests/amd-xop-bulk-tests.txt + diff --git a/tests/RUN.TESTS b/tests/RUN.TESTS new file mode 100755 index 0000000..70460eb --- /dev/null +++ b/tests/RUN.TESTS @@ -0,0 +1,2 @@ +./run-cmd.py --build-dir ../obj/examples --tests tests-base --tests tests-avx512 --tests tests-avx512pf +./run-cmd.py --build-dir ../obj-knc/examples --tests tests-base --tests tests-knc diff --git a/tests/bulk-tests/amd-xop-bulk-tests.txt b/tests/bulk-tests/amd-xop-bulk-tests.txt new file mode 100644 index 0000000..2151d30 --- /dev/null +++ b/tests/bulk-tests/amd-xop-bulk-tests.txt @@ -0,0 +1,4 @@ +ENC AVX XOP ; BUILDDIR/xed -e vpshaw xmm7 MEM16:ecx xmm6 +ENC AVX XOP DEC ; BUILDDIR/xed -de 8f e9 48 99 39 +ENC AVX XOP ; BUILDDIR/xed -e vpmadcswd xmm7 xmm1 xmm0 xmm3 +ENC AVX XOP DEC ; BUILDDIR/xed -de 8FE870B6F830 diff --git a/tests/bulk-tests/avx-bulk-tests.txt b/tests/bulk-tests/avx-bulk-tests.txt new file mode 100644 index 0000000..2efe1b9 --- /dev/null +++ b/tests/bulk-tests/avx-bulk-tests.txt @@ -0,0 +1,19 @@ +DEC AVX ; BUILDDIR/xed -d C5EC58CB +DEC AVX ; BUILDDIR/xed -d 66C5EC58CB +ENC AVX ; BUILDDIR/xed-ex3 vaddps ymm1 ymm2 ymm3 +ENC AVX ; BUILDDIR/xed-ex3 -64 vpinsrb xmm1 xmm2 eax IMM:ff +ENC AVX ; BUILDDIR/xed-ex3 -64 vpinsrb/64 xmm1 xmm2 eax IMM:ff +DEC AVX ; BUILDDIR/xed -64 -d C4E36920C8FF +DEC AVX ; BUILDDIR/xed -64 -d C4 E3 E9 20C8FF +DEC AVX ; BUILDDIR/xed -d C4 E3 E9 20C8FF +DEC AVX ; BUILDDIR/xed -d C4 E3 69 20C8FF +ENC AVX ; BUILDDIR/xed-ex3 -64 vpinsrw xmm1 xmm2 eax IMM:ff +DEC AVX ; BUILDDIR/xed -64 -d C5E9C4C8FF +DEC AVX ; BUILDDIR/xed -64 -d C4 E1 69 C4 C8 FF +DEC AVX ; BUILDDIR/xed -64 -d C4 E1 E9 C4 C8 FF +ENC AVX ; BUILDDIR/xed-ex3 -64 vbroadcastss/32 xmm1 MEM4:rax +ENC AVX ; BUILDDIR/xed-ex3 -64 vbroadcastss/64 xmm1 MEM4:rax +DEC AVX ; BUILDDIR/xed -64 -d 67C4226D934CC500 +DEC AVX ; BUILDDIR/xed -64 -d 67C4E23593AC3ED8B2080A +DEC AVX ; BUILDDIR/xed -64 -d C4A23D91043D00000000 +DEC AVX ; BUILDDIR/xed -64 -d C462159124058076ED5E diff --git a/tests/bulk-tests/avx512pf-bulk-tests.txt b/tests/bulk-tests/avx512pf-bulk-tests.txt new file mode 100644 index 0000000..6128af6 --- /dev/null +++ b/tests/bulk-tests/avx512pf-bulk-tests.txt @@ -0,0 +1,5 @@ +DEC AVX512PF ; BUILDDIR/xed -64 -d 62 F2 7D 48 C66C00FF +DEC AVX512PF ; BUILDDIR/xed -64 -d 62 F2 7D 49 C66C00FF +ENC AVX512PF ; BUILDDIR/xed -64 -e VSCATTERPF0DPS MEM1:RAX,ZMM0,1,ff k0 +ENC AVX512PF ; BUILDDIR/xed -64 -e VSCATTERPF0DPS MEM1:RAX,ZMM0,1,ff k1 + diff --git a/tests/bulk-tests/avx512x-bulk-tests.txt b/tests/bulk-tests/avx512x-bulk-tests.txt new file mode 100644 index 0000000..e65c43f --- /dev/null +++ b/tests/bulk-tests/avx512x-bulk-tests.txt @@ -0,0 +1,6 @@ +ENC AVX512X ; BUILDDIR/xed-ex3 -64 vaddps ymm3 k1 ymm1 ymm2 +DEC AVX512X ; BUILDDIR/xed -64 -d 62F1742958DA +ENC AVX512X ; BUILDDIR/xed-ex3 -64 vaddps xmm3 k1 xmm1 xmm2 +DEC AVX512X ; BUILDDIR/xed -64 -d 62F1740958DA +DEC ENC AVX512X ; BUILDDIR/xed -64 -de 62 e1 ad 0f 58 64 d9 08 +DEC ENC AVX512X ; BUILDDIR/xed -64 -de 62 f1 7e 78 2d f0 diff --git a/tests/bulk-tests/bulk-tests.txt b/tests/bulk-tests/bulk-tests.txt new file mode 100644 index 0000000..4a3ea97 --- /dev/null +++ b/tests/bulk-tests/bulk-tests.txt @@ -0,0 +1,451 @@ +ENC ; BUILDDIR/xed-ex3 MOVLPD XMM1 MEM8:EBX,EAX,4,00 +ENC ; BUILDDIR/xed-ex3 ADD EAX EAX +ENC ; BUILDDIR/xed-ex3 ADD EAX EBX +ENC ; BUILDDIR/xed-ex3 ADD EAX MEM4:EBX,EAX,4,00 +ENC ; BUILDDIR/xed-ex3 -64 POP/64 RSI +ENC ; BUILDDIR/xed-ex3 -64 MOV/64 R9 RDX +ENC ; BUILDDIR/xed-ex3 -64 AND/64 RSP SIMM:f0 +ENC ; BUILDDIR/xed-ex3 JMP_FAR PTR:11223344 IMM:5566 +DEC ; BUILDDIR/xed -d EA112233445566 +ENC ; BUILDDIR/xed-ex3 JLE BRDISP:11223344 +DEC ENC ; BUILDDIR/xed -v 4 -64 -de 488B05411D1100 +DEC ; BUILDDIR/xed -d 90 +DEC ENC ; BUILDDIR/xed -de f390 +DEC ENC ; BUILDDIR/xed -de f391 +DEC ENC ; BUILDDIR/xed -de f290 +ENC ; BUILDDIR/xed-ex3 REPE_CMPSB +DEC ENC ; BUILDDIR/xed -de F3A6 +DEC ENC ; BUILDDIR/xed -de 8d00 +ENC ; BUILDDIR/xed-ex3 LEA EAX AGEN:ECX +ENC ; BUILDDIR/xed-ex3 LEA EAX AGEN:EAX,-,-,00 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RAX,-,-,00 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RCX +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:ECX +ENC ; BUILDDIR/xed-ex3 -64 LEA/32 EAX AGEN:RAX,-,-,00 +ENC ; BUILDDIR/xed-ex3 -64 LEA/32 EAX AGEN:EAX,-,-,00 +DEC ENC ; BUILDDIR/xed -de A230 +DEC ENC ; BUILDDIR/xed -de A211223344 +DEC ENC ; BUILDDIR/xed -de 36A011 +DEC ENC ; BUILDDIR/xed -de 36A011223344 +ENC ; BUILDDIR/xed-ex3 PUSH IMM:11223344 +DEC ENC ; BUILDDIR/xed -de 7402 +DEC ENC AVX ; BUILDDIR/xed -de 40ff4c5000 +DEC ENC AVX ; BUILDDIR/xed -de 41ff4c5000 +DEC ENC ; BUILDDIR/xed -de 90 +DEC ENC ; BUILDDIR/xed -de 6690 +DEC ENC ; BUILDDIR/xed -de 87c0 +DEC ENC ; BUILDDIR/xed -I -64 -de 4b8d446d00 +DEC ENC ; BUILDDIR/xed -I -64 -de 4b8d447500 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,R13,2,00 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,R14,2,00 +DEC ; BUILDDIR/xed -d 97 +ENC ; BUILDDIR/xed-ex3 LEA EAX AGEN:EBP,ESI,2 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,RSI,2 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RBP,RDI,2 +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RBP +ENC ; BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13 +DEC ; BUILDDIR/xed -d 0f ad c3 +DEC ENC ; BUILDDIR/xed -de f30f7edf +DEC ENC ; BUILDDIR/xed -de 660fd6fb +DEC ENC ; BUILDDIR/xed -64 -de 66450f7e07 +DEC ENC ; BUILDDIR/xed -64 -de 664d0f7e07 +ENC ; BUILDDIR/xed-ex3 -64 ADD/64 RAX MEM8:RIP,-,-,11223344 +DEC ENC ; BUILDDIR/xed -64 -de 48030544332211 +DEC ENC ; BUILDDIR/xed -64 -de 6748030544332211 +DEC ; BUILDDIR/xed -64 -d 4f0f38f000 +DEC ; BUILDDIR/xed -64 -d 664f0f38f000 +DEC ; BUILDDIR/xed -64 -d 660f38f000 +DEC ; BUILDDIR/xed -64 -d 0f38f000 +DEC ; BUILDDIR/xed -d 0f38f000 +DEC ; BUILDDIR/xed -d 660f38f000 +DEC ENC ; BUILDDIR/xed -de 678b46ff +DEC ENC ; BUILDDIR/xed -de 67648b46ff +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bp,di,1,ff +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bp,di,1 +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bp,di,-,ffff +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bp +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:di +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bx,-,-,ffff +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bx,-,-,ff +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:bx +ENC ; BUILDDIR/xed-ex3 mov eax MEM4:fs:bx +ENC ; BUILDDIR/xed-ex3 mov/16 ax MEM2:fs:bx +DEC ; BUILDDIR/xed -d 663e0fc70e +DEC ; BUILDDIR/xed -d 663e0fc70e +DEC ; BUILDDIR/xed -64 -d 3e0fc70e +DEC ; BUILDDIR/xed -64 -d 483e0fc70e +DEC ; BUILDDIR/xed -64 -d 480fc70e +DEC ; BUILDDIR/xed -64 -d 3e480fc70e +DEC ; BUILDDIR/xed -64 -d 66e480fc70e +DEC ; BUILDDIR/xed -64 -d 0fc70e +DEC ; BUILDDIR/xed -64 -d 660fc70e +DEC ; BUILDDIR/xed -16 -d 660fc70e +DEC ; BUILDDIR/xed -16 -d 0fc70e00 +DEC ; BUILDDIR/xed -16 -d 0fc70e0000 +DEC ; BUILDDIR/xed -16 -d 0fc70e1111 +ENC ; BUILDDIR/xed-ex3 cmpxchg8b mem8:esi +DEC ENC ; BUILDDIR/xed -de 0fc70e +DEC ENC ; BUILDDIR/xed -64 -de 0fc70e +DEC ENC ; BUILDDIR/xed -64 -de 480fc70e +DEC ENC ; BUILDDIR/xed -16 -de 660fc70e111111 +DEC ENC ; BUILDDIR/xed -16 -de 0fc70e111111 +DEC ENC ; BUILDDIR/xed -de f3c3 +DEC ENC ; BUILDDIR/xed -64 -de 66 E8 11 22 33 44 +DEC ENC ; BUILDDIR/xed -64 -de E8 11 22 33 44 +DEC ENC ; BUILDDIR/xed -64 -de 67 E8 11 22 33 44 +DEC ENC ; BUILDDIR/xed -de E8 11 22 33 44 +DEC ENC ; BUILDDIR/xed -de 66 E8 11 22 +DEC ENC ; BUILDDIR/xed -16 -de 66 E8 11 22 33 44 +DEC ENC ; BUILDDIR/xed -16 -de E8 11 22 +DEC ENC ; BUILDDIR/xed -64 -de 0f8411223344 +DEC ENC ; BUILDDIR/xed -64 -de 660f8411223344 +DEC ENC ; BUILDDIR/xed -de 9a11223344aabb +DEC ENC ; BUILDDIR/xed -16 -de 669a11223344aabb +DEC ENC ; BUILDDIR/xed -de 669a1122aabb +DEC ENC ; BUILDDIR/xed -de 679a11223344aabb +DEC ENC ; BUILDDIR/xed -v 5 -de 0fa0 +DEC ENC ; BUILDDIR/xed -64 -v 5 -de 0fa0 +DEC ; BUILDDIR/xed-ex1 9c +DEC ; BUILDDIR/xed-ex1 9d +DEC ; BUILDDIR/xed-ex1 0c e0 00 +DEC ; BUILDDIR/xed-ex1 0c e0 f0 +DEC ; BUILDDIR/xed-ex1 0c e0 40 +DEC ; BUILDDIR/xed -d 3e 66 d7 +DEC ; BUILDDIR/xed -d 3ed7 +DEC ; BUILDDIR/xed -d 658a0511223344 +DEC ; BUILDDIR/xed -d 65A011223344 +DEC ; BUILDDIR/xed -d 65A4 +DEC ; BUILDDIR/xed -d 65a6 +DEC ; BUILDDIR/xed -d 65d7 +DEC ; BUILDDIR/xed -d 65ff30 +DEC ; BUILDDIR/xed -d A4 +DEC ; BUILDDIR/xed -d a6 +DEC ; BUILDDIR/xed -d d7 +DEC ; BUILDDIR/xed -d ff30 +DEC ENC ; BUILDDIR/xed -de 65 a6 +DEC ENC ; BUILDDIR/xed -de 65 d7 +DEC ENC ; BUILDDIR/xed -de 65A011223344 +DEC ENC ; BUILDDIR/xed -de 65A4 +DEC ENC ; BUILDDIR/xed -de 65a6 +DEC ENC ; BUILDDIR/xed -de 67d6 +DEC ENC ; BUILDDIR/xed -de 67d7 +ENC ; BUILDDIR/xed-ex3 MOV AL MEM1:-,-,-,11223344 +ENC ; BUILDDIR/xed-ex3 MOV AL MEM1:GS:-,-,-,11223344 +ENC ; BUILDDIR/xed-ex3 SALC SEG:GS +ENC ; BUILDDIR/xed-ex3 XLAT SEG:GS +ENC ; BUILDDIR/xed-ex3 XLAT SEG0:GS +ENC ; BUILDDIR/xed-ex3 movsb +ENC ; BUILDDIR/xed-ex3 movsb SEG1:DS +DEC ; BUILDDIR/xed-ex1 65 a6 +DEC ; BUILDDIR/xed -d f000c0 +DEC ; BUILDDIR/xed -d f00000 +DEC ; BUILDDIR/xed -d 0fc708 +DEC ; BUILDDIR/xed -d f00fc708 +DEC ENC ; BUILDDIR/xed -de 0000 +DEC ; BUILDDIR/xed-ex1 00 00 +ENC ; BUILDDIR/xed-ex3 -64 lea r8d AGEN:r8d +ENC ; BUILDDIR/xed-ex3 -64 lea r8d AGEN:r8d,ebx,8 +ENC ; BUILDDIR/xed-ex3 lea eax AGEN:r8d,ebx,8 +ENC ; BUILDDIR/xed-ex3 lea eax AGEN:eax,ebx,8 +DEC ; BUILDDIR/xed-ex1 f2 0f 12 c0 +DEC ; BUILDDIR/xed-ex1 0f 12 c0 +DEC ; BUILDDIR/xed-ex1 c9 +DEC ; BUILDDIR/xed-ex1 -64 c9 +DEC ENC ; BUILDDIR/xed -de c9 +DEC ENC ; BUILDDIR/xed -64 -de c9 +DEC ; BUILDDIR/xed -64 -d 65c9 +DEC ; BUILDDIR/xed -d 65c9 +DEC ENC ; BUILDDIR/xed -64 -de 6741C745FF44332211 +ENC ; BUILDDIR/xed-ex3 -64 MOV MEM4:R13D,-,-,FF IMM:11223344 +DEC ; BUILDDIR/xed -64 -d f3f267662e6465363e26c000ff +DEC ; BUILDDIR/xed -64 -d 70ff +DEC ; BUILDDIR/xed -64 -d 3e70ff +DEC ; BUILDDIR/xed -64 -d 2e70ff +DEC ENC ; BUILDDIR/xed -64 -de 70ff +DEC ENC ; BUILDDIR/xed -64 -de 3e70ff +DEC ENC ; BUILDDIR/xed -64 -de 2e70ff +DEC ; BUILDDIR/xed-ex1 66 0f 3a 15 c8 00 +DEC ENC ; BUILDDIR/xed -16 -de 0f 20 c0 +DEC ENC ; BUILDDIR/xed -32 -de 0f 20 c0 +DEC ENC ; BUILDDIR/xed -64 -de 0f 20 c0 +DEC ENC ; BUILDDIR/xed -16 -de 66 0f 20 c0 +DEC ENC ; BUILDDIR/xed -32 -de 66 0f 20 c0 +DEC ENC ; BUILDDIR/xed -64 -de 66 0f 20 c0 +DEC ; BUILDDIR/xed-ex1 -16 0f 20 c0 +DEC ; BUILDDIR/xed-ex1 0f 20 c0 +DEC ; BUILDDIR/xed-ex1 -64 0f 20 c0 +ENC ; BUILDDIR/xed-ex3 -16 mov_cr eax cr0 +ENC ; BUILDDIR/xed-ex3 -32 mov_cr eax cr0 +ENC ; BUILDDIR/xed-ex3 -64 mov_cr rax cr0 +DEC ; BUILDDIR/xed-ex1 -64 f2 f3 64 67 3e 66 2e 36 65 26 f3 0f 2c 0f +DEC ; BUILDDIR/xed-ex1 -64 f3 f2 67 66 2e 64 65 36 3e 26 d0 00 +DEC ; BUILDDIR/xed-ex1 -chip I286 da c0 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO da c0 +DEC ; BUILDDIR/xed-ex1 -chip SALTWELL da c0 +DEC ; BUILDDIR/xed-ex4 -xml f0 00 00 +DEC ; BUILDDIR/xed-ex4 8B 44 18 00 +DEC ; BUILDDIR/xed-ex4 -no-unit-scale 8B 44 18 00 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 a7 +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 e0 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 e1 aa +DEC ; BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 e1 aa +ENC ; BUILDDIR/xed-ex3 -64 lea r13d agen:r13d,-,-,00000000 +ENC ; BUILDDIR/xed-ex3 -64 lea r13d agen:r13d +DEC AVX ; BUILDDIR/xed -d c5 1d 0000 0000 +DEC AVX ; BUILDDIR/xed -d 66 c5 1d 0000 0000 +DEC AVX ; BUILDDIR/xed -d c4 1d 0000 0000 +DEC AVX ; BUILDDIR/xed -d 66 c4 1d 0000 0000 +DEC ; BUILDDIR/xed -b 0xfffffff0 -16 -d e9 0d00 +ENC ; BUILDDIR/xed-ex3 -64 xor ah bh +ENC ; BUILDDIR/xed-ex3 -64 xor ah al +ENC ; BUILDDIR/xed-ex3 -64 xor al bl +ENC ; BUILDDIR/xed-ex3 -64 xor sil al +ENC ; BUILDDIR/xed-ex3 -64 xor al sil +ENC ; BUILDDIR/xed-ex3 -64 xor sil bpl +ENC ; BUILDDIR/xed-ex3 -64 xor sil ah +ENC ; BUILDDIR/xed-ex3 -64 xor ah sil +ENC ; BUILDDIR/xed-ex3 -64 pop rdx +ENC ; BUILDDIR/xed-ex3 -64 pop/64 rdx +ENC ; BUILDDIR/xed-ex3 -64 pop edx +ENC ; BUILDDIR/xed-ex3 -64 pop/16 dx +ENC ; BUILDDIR/xed-ex3 -64 pop dx +ENC ; BUILDDIR/xed-ex3 -16 pop dx +ENC ; BUILDDIR/xed-ex3 -16 pop/32 edx +ENC ; BUILDDIR/xed-ex3 -32 pop/16 dx +ENC ; BUILDDIR/xed-ex3 -32 pop edx +ENC ; BUILDDIR/xed-ex3 -32 pop rdx +DEC ; BUILDDIR/xed -32 -d 0f05 +DEC ; BUILDDIR/xed -64 -d 0f05 +ENC ; BUILDDIR/xed-ex3 -64 sysret +ENC ; BUILDDIR/xed-ex3 -64 sysret/64 +ENC ; BUILDDIR/xed-ex3 -32 sysret +ENC ; BUILDDIR/xed-ex3 -32 sysret_amd +DEC ; BUILDDIR/xed -64 -d 66 36 64 2e f0 67 f2 26 3e f3 65 0f 16 8d 4b +DEC ; BUILDDIR/xed -64 -d 66 36 64 2e f0 67 f2 26 3e f3 65 0f 16 8d +DEC ; BUILDDIR/xed-ex1 -64 0fb20000 +DEC ; BUILDDIR/xed-ex1 -64 ff18 +DEC ; BUILDDIR/xed-ex1 -64 48ff18 +DEC ; BUILDDIR/xed-ex1 0f01c8 +DEC ; BUILDDIR/xed-ex1 0f01c9 +DEC ; BUILDDIR/xed-ex1 66 0f 38 10 ff +DEC ; BUILDDIR/xed-ex1 66 0f 38 14 ff +DEC ENC ; BUILDDIR/xed -64 -de ff 10 +DEC ENC ; BUILDDIR/xed -de ff 10 +DEC ENC ; BUILDDIR/xed -de ff e0 +DEC ENC ; BUILDDIR/xed -de 66 ff e0 +DEC ENC ; BUILDDIR/xed -64 -de ff e0 +DEC ENC ; BUILDDIR/xed -64 -de 66 ff e0 +DEC ENC ; BUILDDIR/xed-ex6 -64 64 67 f0 48 81 24 e5 1c 68 48 43 5f a6 b7 cd +DEC ; BUILDDIR/xed-ex1 -chip SALTWELL 0f 0d 08 +DEC ; BUILDDIR/xed-ex1 -chip PENRYN_E 0f 01 d0 +DEC ; BUILDDIR/xed-ex1 -chip NEHALEM 0f 01 d0 +DEC ; BUILDDIR/xed -A -d a1 00 70 70 c1 +DEC ; BUILDDIR/xed -A -d 00 80 00 70 70 c1 +DEC AVX ; BUILDDIR/xed -d c4 e2 f1 92 64 40 11 +DEC ENC AVX ; BUILDDIR/xed -de c4 e2 f1 92 64 40 11 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERDPS xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERDPS ymm0 MEM32:rax,ymm1,1 ymm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERDD xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERDD ymm0 MEM32:rax,xmm1,1 ymm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERDQ xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERDQ ymm0 MEM32:rax,xmm1,1 ymm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERDPD xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERDPD ymm0 MEM32:rax,xmm1,1 ymm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERQPS xmm0 MEM8:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERQPS xmm0 MEM16:rax,ymm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERQPD xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VGATHERQPD ymm0 MEM32:rax,ymm1,1 ymm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERQD xmm0 MEM8:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERQD xmm0 MEM16:rax,ymm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERQQ xmm0 MEM16:rax,xmm1,1 xmm2 +ENC AVX ; BUILDDIR/xed-ex3 -64 VPGATHERQQ ymm0 MEM32:rax,ymm1,1 ymm2 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E269920408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E26D920408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E269900408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E26D900408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2E9900408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2ED900408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2E9920408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2ED920408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E269930408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E26D930408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2E9930408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2ED930408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E26D910408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E269910408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2E9910408 +DEC ENC AVX ; BUILDDIR/xed -64 -de C4E2ED910408 +DEC XOP ; BUILDDIR/xed-ex-ild2 -64 8f e9 78 81 ca +DEC XOP ; BUILDDIR/xed-ex-ild2 -64 -chip WESTMERE 8f e9 78 81 ca +DEC ENC ; BUILDDIR/xed -64 -de 0f1aff +DEC ENC ; BUILDDIR/xed -64 -de 0f1bff +DEC ENC ; BUILDDIR/xed -64 -de f30f1bff +DEC AVX ; BUILDDIR/xed -32 -d c4 c3 bd 79 f2 45 +DEC AVX ; BUILDDIR/xed -64 -d c4 c3 bd 79 f2 45 +DEC AVX ; BUILDDIR/xed -32 -d c4 c3 b9 79 f2 45 +DEC ENC AVX ; BUILDDIR/xed -64 -de c4 c3 39 79 f2 45 +DEC AVX ; BUILDDIR/xed -d c5 fd 57 c0 +DEC ENC AVX ; BUILDDIR/xed -64 -de c5 fd 57 c0 +ENC AVX ; BUILDDIR/xed-ex3 -64 vxorpd ymm0 ymm0 ymm0 +ENC AVX ; BUILDDIR/xed-ex3 vxorpd ymm0 ymm0 ymm0 +DEC AVX ; BUILDDIR/xed -32 -d c4 e3 fd 79 42 45 93 +DEC AVX ; BUILDDIR/xed -64 -d c4 e3 fd 79 42 45 93 +DEC ; BUILDDIR/xed -64 -d 8F 43 24 +DEC AVX XOP ; BUILDDIR/xed -64 -d c4 03 f1 49 fe 0f +DEC AVX XOP ; BUILDDIR/xed -64 -d c4 03 71 49 fe 0f +DEC AVX XOP ; BUILDDIR/xed -64 -d c4 83 f1 48 fe 0f +DEC AVX XOP ; BUILDDIR/xed -64 -d c4 03 f1 49 7e 0f 00 +DEC AVX XOP ; BUILDDIR/xed -64 -d c4 03 71 49 7e 7f ff +DEC AVX ; BUILDDIR/xed -64 -d c4 dc 9b c3 72 d7 68 3e +DEC AVX ; BUILDDIR/xed -64 -d 4d c4 12 bd 79 f2 45 +DEC ; BUILDDIR/xed -64 -d a0 11 22 33 44 55 66 77 88 +DEC ; BUILDDIR/xed -64 -d 65 66 41 0F +DEC AVX ; BUILDDIR/xed -d c4 e2 f1 92 44 40 11 +DEC AVX ; BUILDDIR/xed -d c4 e2 f9 92 64 40 11 +DEC AVX ; BUILDDIR/xed -d c4 e2 d9 92 64 40 11 +ENC ; BUILDDIR/xed -e INSB +ENC ; BUILDDIR/xed -e INSW/16 +ENC ; BUILDDIR/xed -e INSD +ENC ; BUILDDIR/xed -e INSD +ENC ; BUILDDIR/xed -e OUTSB +ENC ; BUILDDIR/xed -e OUTSW/16 +ENC ; BUILDDIR/xed -e OUTSD +ENC ; BUILDDIR/xed -e OUTSD +ENC ; BUILDDIR/xed -e PUSHF/16 +ENC ; BUILDDIR/xed -e PUSHFD +ENC ; BUILDDIR/xed -64 -e PUSHFQ/64 +ENC ; BUILDDIR/xed -e POPF/16 +ENC ; BUILDDIR/xed -e POPFD +ENC ; BUILDDIR/xed -64 -e POPFQ/64 +ENC ; BUILDDIR/xed -e MOVSB +ENC ; BUILDDIR/xed -e MOVSW/16 +ENC ; BUILDDIR/xed -e MOVSD +ENC ; BUILDDIR/xed -64 -e MOVSQ/64 +ENC ; BUILDDIR/xed -e CMPSB +ENC ; BUILDDIR/xed -e CMPSW/16 +ENC ; BUILDDIR/xed -e CMPSD +ENC ; BUILDDIR/xed -64 -e CMPSQ/64 +ENC ; BUILDDIR/xed -e STOSB +ENC ; BUILDDIR/xed -e STOSW/16 +ENC ; BUILDDIR/xed -e STOSD +ENC ; BUILDDIR/xed -64 -e STOSQ/64 +ENC ; BUILDDIR/xed -e LODSB +ENC ; BUILDDIR/xed -e LODSW/16 +ENC ; BUILDDIR/xed -e LODSD +ENC ; BUILDDIR/xed -64 -e LODSQ/64 +ENC ; BUILDDIR/xed -e SCASB +ENC ; BUILDDIR/xed -e SCASW/16 +ENC ; BUILDDIR/xed -e SCASD +ENC ; BUILDDIR/xed -64 -e SCASQ/64 +ENC ; BUILDDIR/xed -e IRET/16 +ENC ; BUILDDIR/xed -e IRETD +ENC ; BUILDDIR/xed -64 -e IRETQ/64 +ENC ; BUILDDIR/xed -e CLD +ENC ; BUILDDIR/xed -e STD +ENC ; BUILDDIR/xed -64 -e SYSCALL/64 +ENC ; BUILDDIR/xed -64 -e SYSRET/64 +ENC ; BUILDDIR/xed -e RSM +DEC ; BUILDDIR/xed-ex1 6C +DEC ; BUILDDIR/xed-ex1 666D +DEC ; BUILDDIR/xed-ex1 6D +DEC ; BUILDDIR/xed-ex1 6D +DEC ; BUILDDIR/xed-ex1 6E +DEC ; BUILDDIR/xed-ex1 666F +DEC ; BUILDDIR/xed-ex1 6F +DEC ; BUILDDIR/xed-ex1 6F +DEC ; BUILDDIR/xed-ex1 669C +DEC ; BUILDDIR/xed-ex1 9C +DEC ; BUILDDIR/xed-ex1 -64 9C +DEC ; BUILDDIR/xed-ex1 669D +DEC ; BUILDDIR/xed-ex1 9D +DEC ; BUILDDIR/xed-ex1 -64 9D +DEC ; BUILDDIR/xed-ex1 A4 +DEC ; BUILDDIR/xed-ex1 66A5 +DEC ; BUILDDIR/xed-ex1 A5 +DEC ; BUILDDIR/xed-ex1 -64 48A5 +DEC ; BUILDDIR/xed-ex1 A6 +DEC ; BUILDDIR/xed-ex1 66A7 +DEC ; BUILDDIR/xed-ex1 A7 +DEC ; BUILDDIR/xed-ex1 -64 48A7 +DEC ; BUILDDIR/xed-ex1 AA +DEC ; BUILDDIR/xed-ex1 66AB +DEC ; BUILDDIR/xed-ex1 AB +DEC ; BUILDDIR/xed-ex1 -64 48AB +DEC ; BUILDDIR/xed-ex1 AC +DEC ; BUILDDIR/xed-ex1 66AD +DEC ; BUILDDIR/xed-ex1 AD +DEC ; BUILDDIR/xed-ex1 -64 48AD +DEC ; BUILDDIR/xed-ex1 AE +DEC ; BUILDDIR/xed-ex1 66AF +DEC ; BUILDDIR/xed-ex1 AF +DEC ; BUILDDIR/xed-ex1 -64 48AF +DEC ; BUILDDIR/xed-ex1 66CF +DEC ; BUILDDIR/xed-ex1 CF +DEC ; BUILDDIR/xed-ex1 -64 48CF +DEC ; BUILDDIR/xed-ex1 FC +DEC ; BUILDDIR/xed-ex1 FD +DEC ; BUILDDIR/xed-ex1 -64 0F05 +DEC ; BUILDDIR/xed-ex1 -64 480F07 +DEC ; BUILDDIR/xed-ex1 0FAA +DEC ; BUILDDIR/xed-ex1 f3 6C +DEC ; BUILDDIR/xed-ex1 f3 666D +DEC ; BUILDDIR/xed-ex1 f3 6D +DEC ; BUILDDIR/xed-ex1 f3 6D +DEC ; BUILDDIR/xed-ex1 f3 6E +DEC ; BUILDDIR/xed-ex1 f3 666F +DEC ; BUILDDIR/xed-ex1 f3 6F +DEC ; BUILDDIR/xed-ex1 f3 6F +DEC ; BUILDDIR/xed-ex1 f3 A4 +DEC ; BUILDDIR/xed-ex1 f3 66A5 +DEC ; BUILDDIR/xed-ex1 f3 A5 +DEC ; BUILDDIR/xed-ex1 -64 f3 48A5 +DEC ; BUILDDIR/xed-ex1 f2 A6 +DEC ; BUILDDIR/xed-ex1 f2 66A7 +DEC ; BUILDDIR/xed-ex1 f2 A7 +DEC ; BUILDDIR/xed-ex1 -64 f2 48A7 +DEC ; BUILDDIR/xed-ex1 f3 A6 +DEC ; BUILDDIR/xed-ex1 f3 66A7 +DEC ; BUILDDIR/xed-ex1 f3 A7 +DEC ; BUILDDIR/xed-ex1 -64 f3 48A7 +DEC ; BUILDDIR/xed-ex1 f3 AA +DEC ; BUILDDIR/xed-ex1 f3 66AB +DEC ; BUILDDIR/xed-ex1 f3 AB +DEC ; BUILDDIR/xed-ex1 -64 f3 48AB +DEC ; BUILDDIR/xed-ex1 f3 AC +DEC ; BUILDDIR/xed-ex1 f3 66AD +DEC ; BUILDDIR/xed-ex1 f3 AD +DEC ; BUILDDIR/xed-ex1 -64 f3 48AD +DEC ; BUILDDIR/xed-ex1 f3 AE +DEC ; BUILDDIR/xed-ex1 f3 66AF +DEC ; BUILDDIR/xed-ex1 f3 AF +DEC ; BUILDDIR/xed-ex1 -64 f3 48AF +DEC ; BUILDDIR/xed-ex1 f2 AE +DEC ; BUILDDIR/xed-ex1 f2 66AF +DEC ; BUILDDIR/xed-ex1 f2 AF +DEC ; BUILDDIR/xed-ex1 -64 f2 48AF diff --git a/tests/bulk-tests/hsw-bulk-tests.txt b/tests/bulk-tests/hsw-bulk-tests.txt new file mode 100644 index 0000000..45c3dc3 --- /dev/null +++ b/tests/bulk-tests/hsw-bulk-tests.txt @@ -0,0 +1,2 @@ +ENC AVX ; BUILDDIR/xed-ex3 -64 vgatherdps ymm1 MEM32:RAX,YMM2,2 YMM3 +ENC AVX ; BUILDDIR/xed-ex3 -64 vgatherdps ymm1 MEM32:RBP,YMM2,2 YMM3 diff --git a/tests/bulk-tests/knc-bulk-tests.txt b/tests/bulk-tests/knc-bulk-tests.txt new file mode 100644 index 0000000..fd7243c --- /dev/null +++ b/tests/bulk-tests/knc-bulk-tests.txt @@ -0,0 +1,10 @@ +DEC ENC KNC ; BUILDDIR/xed -64 -de 62F279081815C0C23200 +DEC ENC KNC ; BUILDDIR/xed -64 -de 626279585A2588223D00 +DEC ENC KNC ; BUILDDIR/xed -64 -de 62F1782B28C1 +DEC ENC KNC ; BUILDDIR/xed -64 -de 62F17808295C2404 +DEC ENC KNC ; BUILDDIR/xed -64 -de 62F2F90AD14598 +DEC KNC ; BUILDDIR/xed -64 -d C4E0687410 +DEC ENC KNC ; BUILDDIR/xed -64 -de 62E178082805F6412900 +DEC ENC KNC ; BUILDDIR/xed -64 -de C5F8182D79022900 +DEC KNC ; BUILDDIR/xed -64 -d 62B2F98D901CE580136900 +DEC ENC KNC ; BUILDDIR/xed -64 -de 62D2790AA29C950023AE00 diff --git a/tests/bulk-tests/new-tests.txt b/tests/bulk-tests/new-tests.txt new file mode 100644 index 0000000..151eaf5 --- /dev/null +++ b/tests/bulk-tests/new-tests.txt @@ -0,0 +1,34 @@ +DEC ; BUILDDIR/xed -d 0fbc00 +DEC HSW ; BUILDDIR/xed -d f30fbc00 +DEC HSW ; BUILDDIR/xed -chip-check HASWELL -d f30fbc00 +DEC HSW ; BUILDDIR/xed -chip-check IVYBRIDGE -d f30fbc00 +DEC HSW ; BUILDDIR/xed -chip-check HASWELL -d 0fbc00 +DEC ; BUILDDIR/xed -chip-check QUARK -d F2E100 +DEC ; BUILDDIR/xed -chip-check QUARK -d E100 +DEC ; BUILDDIR/xed -chip-check QUARK -d F3E100 +DEC ; BUILDDIR/xed -chip-check PENTIUM -d F2E100 +DEC ; BUILDDIR/xed -chip-check PENTIUM -d E100 +DEC ; BUILDDIR/xed -chip-check PENTIUM -d F3E100 +DEC ENC ; BUILDDIR/xed -64 -de f266440f38f1fa +DEC ENC ; BUILDDIR/xed -64 -de f2480f38f1fa +DEC ENC ; BUILDDIR/xed -64 -de f2440f38f1fa +DEC ENC ; BUILDDIR/xed -32 -de f20f38f1fa +DEC ENC ; BUILDDIR/xed -32 -de f2660f38f1fa +DEC ENC ; BUILDDIR/xed -16 -de f20f38f1fa +DEC ENC ; BUILDDIR/xed -16 -de f2660f38f1fa +DEC AVX ; BUILDDIR/xed -64 -chip-check SANDYBRIDGE -d 0fae30 +DEC ENC ; BUILDDIR/xed -de f2 f0 01 03 +ENC ; BUILDDIR/xed -e movsd_xmm xmm0 MEM4:eax +DEC END ; BUILDDIR/xed -de f30f5100 +ENC ; BUILDDIR/xed -e sqrtss xmm0 mem4:eax +DEC AVX ; BUILDDIR/xed -16 -d 36 C4 E2 68 F3 0C +DEC AVX ; BUILDDIR/xed -32 -d 65 C4 E3 7B F0 BC 35 79 4A B6 0D 67 +DEC AVX ; BUILDDIR/xed -32 -d 65 C4 E3 FB F0 BC 35 79 4A B6 0D 67 +DEC AVX ; BUILDDIR/xed -64 -d 65 C4 E3 7B F0 BC 35 79 4A B6 0D 67 +DEC AVX ; BUILDDIR/xed -64 -d 65 C4 E3 FB F0 BC 35 79 4A B6 0D 67 +DEC AVX ; BUILDDIR/xed-ex-cpuid f3 0f bc 00 +DEC AVX ; BUILDDIR/xed-ex-cpuid -nobmi f3 0f bc 00 +DEC AVX ; BUILDDIR/xed -d c4 e2 b1 92 12 +ENC ; BUILDDIR/xed -64 -e JRCXZ 'BRDISP:1E' +DEC ENC ; BUILDDIR/xed -64 -de e31e +DEC ; BUILDDIR/xed -64 -d e31e diff --git a/tests/bulk-tests/old-amd-sse5-bulk-tests.txt b/tests/bulk-tests/old-amd-sse5-bulk-tests.txt new file mode 100644 index 0000000..7772671 --- /dev/null +++ b/tests/bulk-tests/old-amd-sse5-bulk-tests.txt @@ -0,0 +1,8 @@ +DEC ENC ; BUILDDIR/xed -16 -de 0F252E3630000005 +DEC ENC ; BUILDDIR/xed -16 -de 0F2401D310 +ENC ; BUILDDIR/xed-ex3 fmaddpd xmm1, xmm1, xmm2, xmm3 +DEC ENC ; BUILDDIR/xed -16 -de 0F7A12CA +DEC ENC ; BUILDDIR/xed -de 0F2401D310 +DEC ; BUILDDIR/xed -d 0f240bda45 +DEC ; BUILDDIR/xed -64 -d 0f240bda45 +DEC ; BUILDDIR/xed -d 0f240bda40 diff --git a/tests/resync/rsync.asm b/tests/resync/rsync.asm new file mode 100644 index 0000000..27bb938 --- /dev/null +++ b/tests/resync/rsync.asm @@ -0,0 +1,15 @@ + ;; this is a test to see if the xed resync mechanism works + ;; when it encounters function symbols. + + [bits 64] + + SECTION .text + global foo:function +foo: + ret + db 0x00 + global bar:function +bar: + db 0x00, 0x00 + ret + diff --git a/tests/resync/sectwo.asm b/tests/resync/sectwo.asm new file mode 100644 index 0000000..9e3fcf0 --- /dev/null +++ b/tests/resync/sectwo.asm @@ -0,0 +1,24 @@ + ;; this is a test to see if the xed resync mechanism works + ;; when it encounters function symbols. + + [bits 64] + + SECTION .text + global foo:function +foo: + ret + db 0x00 + global bar:function +bar: + db 0x00, 0x00 + ret + + SECTION .text1 + global foo1:function +foo1: + ret + global bar1:function +bar1: + db 0x00, 0x00 + ret + diff --git a/tests/run-cmd.py b/tests/run-cmd.py new file mode 100755 index 0000000..936098a --- /dev/null +++ b/tests/run-cmd.py @@ -0,0 +1,277 @@ +#!/usr/bin/env python +#-*- python -*- + +# The tests XED by running a bunch of cmd files from a bunch of directories. +# It tests for correctness by looking at the return code, the stdout and stderr. +# +# FIXME: The version number changes need to be ignored. +# +# This can also create a bunch of test directories from a bulk command +# line file. It substitutes BUILDDIR for the path to the xed examples, +# typically ../obj and that value comes from the env['build_dir'] + + +import sys +import os +import re +import time +import difflib + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +sys.path = [find_dir('mbuild')] + sys.path + +import mbuild + +def write_file(fn,lines): + print "[EMIT] %s" % (fn) + f = open(fn,"w") + if lines: + for line in lines: + f.write(line) + f.close() + + +def create_reference(env, test_dir, codes_and_cmd, make_new=True): + mbuild.cmkdir(test_dir) + + if make_new: + codes, cmd = codes_and_cmd.split(';') + cmd_fn = os.path.join(test_dir,"cmd") + write_file(cmd_fn,cmd + '\n') + codes_fn = os.path.join(test_dir,"codes") + write_file(codes_fn,codes + '\n') + else: + cmd = codes_and_cmd + + # abspath required for windoze + build_dir = mbuild.posix_slashes(os.path.abspath(env['build_dir'])) + cmd2 = re.sub('BUILDDIR',build_dir,cmd) + print cmd2 + + (retcode, stdout,stderr) = mbuild.run_command(cmd2,separate_stderr=True) + print "Retcode %s" % (str(retcode)) + if stdout: + for line in stdout: + print "[STDOUT] %s" % (line) + if stderr: + for line in stderr: + print "[STDERR] %s" % (line) + + write_file(os.path.join(test_dir,"retcode.reference"), [ str(retcode) + "\n" ]) + write_file(os.path.join(test_dir,"stdout.reference"), stdout) + write_file(os.path.join(test_dir,"stderr.reference"), stderr) + +def make_bulk_tests(env): + i = 0 + for bulk_test_file in env['bulk_tests']: + print "[READING BULK TESTS] %s" % (bulk_test_file) + tests = file(bulk_test_file).readlines() + tests = map(lambda x: x.strip(), tests) + for test in tests: + if test: + si = mbuild.join(env['otests'],"test-%05d" % (i)) + create_reference(env, si, test, make_new=True) + i = i + 1 + +def compare_file(reference, this_test): + ref_lines = file(reference).readlines() + ref_lines = map(lambda x: x.rstrip(), ref_lines) + this_test = map(lambda x: x.rstrip(), this_test) + for line in difflib.unified_diff(ref_lines, this_test, + fromfile=reference, tofile="current"): + sys.stdout.write(line.rstrip()+'\n') + if len(ref_lines) != len(this_test): + mbuild.msgb("DIFFERENT NUMBER OF LINES", "ref %d test %d" % (len(ref_lines),len(this_test))) + for ref in ref_lines: + mbuild.msgb("EXPECTED",'%s' % (ref.strip())) + return False + for (ref,test) in zip(ref_lines,this_test): + if ref.strip() != test.strip(): + if ref.find("XED version") != -1: # skip the version lines + continue + mbuild.msgb("DIFFERENT", "\n\tref [%s]\n\ttest [%s]" % (ref, test)) + return False + return True + +def all_codes_present(specified_codes, test_codes): + """The test codes must be a subset of the specified codes. + If no codes are specified, we do everything. + """ + if specified_codes: + print "comparing restriction: {} and test: {}".format(str(specified_codes), str(test_codes)) + s = set(specified_codes) + t = set(test_codes) + u = s.union(t) + if u-s: + # there are codes in t that are not in s, so we reject this test + return False + return True + +def one_test(env,test_dir): + + cmd_fn = os.path.join(test_dir,"cmd") + cmd = file(cmd_fn).readlines()[0] + + # abspath required for windoze + build_dir = mbuild.posix_slashes(os.path.abspath(env['build_dir'])) + cmd2 = re.sub('BUILDDIR',build_dir,cmd) + cmd2 = cmd2.strip() + print cmd2 + + (retcode, stdout,stderr) = mbuild.run_command(cmd2,separate_stderr=True) + print "Retcode %s" % (str(retcode)) + if stdout: + if len(stdout) == 1: + stdout= stdout[0].split("\n") + if len(stdout) == 1 and stdout[0] == '': + stdout = [] + if len(stdout) > 0 and len(stdout[-1]) == 0: + stdout.pop() + for line in stdout: + print "[STDOUT] %d %s" % (len(line),line) + if stderr: + if len(stderr) == 1: + stderr= stderr[0].split("\n") + if len(stderr) == 1 and stderr[0] == '': + stderr = [] + for line in stderr: + print "[STDERR] %s" % (line) + + + + ret_match = compare_file(os.path.join(test_dir,"retcode.reference"), [ str(retcode) ]) + stdout_match = compare_file(os.path.join(test_dir,"stdout.reference"), stdout) + stderr_match = compare_file(os.path.join(test_dir,"stderr.reference"), stderr) + + okay = True + if not ret_match: + mbuild.msgb("RETCODE MISMATCH") + okay = False + if not stdout_match: + mbuild.msgb("STDOUT MISMATCH") + okay = False + if not stderr_match: + mbuild.msgb("STDERR MISMATCH") + okay = False + print "-"*40 + "\n\n\n" + return okay + +def find_tests(env): + test_dirs = [] + for d in env['tests']: + test_dirs.extend(mbuild.glob(mbuild.join(d,"test-[0-9][0-9]*"))) + return test_dirs + +def rebase_tests(env): + test_dirs = find_tests(env) + for test_dir in test_dirs: + cmd_fn = os.path.join(test_dir,"cmd") + test_cmd = file(cmd_fn).readlines()[0] + create_reference(env, test_dir, test_cmd, make_new=False) + +def run_tests(env): + failing_tests = [] + test_dirs = find_tests(env) + errors = 0 + skipped = 0 + for tdir in test_dirs: + #if env.on_windows(): + # time.sleep(1) # try to avoid a bug on windows running commands to quickly + print '-'*40 + mbuild.msgb("TESTING" , tdir) + + codes_fn = os.path.join(tdir,"codes") + codes = file(codes_fn).readlines()[0].strip().split() + + if all_codes_present(env['codes'],codes): + okay = one_test(env,tdir) + if not okay: + failing_tests.append(tdir) + errors += 1 + else: + mbuild.msgb("SKIPPING DUE TO TEST SUBSET RESTRICTION") + print '-'*40 + "\n\n\n" + skipped += 1 + + ntests = len(test_dirs) + tested = ntests-skipped + mbuild.msgb("TESTS", str(ntests)) + mbuild.msgb("SKIPPED", str(skipped)) + mbuild.msgb("TESTED", str(tested)) + mbuild.msgb("ERRORS", str(errors)) + if tested: + mbuild.msgb("PASS_PCT", "%2.4f%%" % (100.0 * (tested-errors)/tested)) + else: + mbuild.msgb("PASS_PCT", '0%') + failing_tests.sort() + for t in failing_tests: + mbuild.msgb("FAIL", t) + return errors + +#############################################3 + +def work(): + env = mbuild.env_t() + env.parser.add_option( + "--bulk-make-tests", "-b", + dest="bulk_tests", action="append", + default=[], + help="List of bulk tests from which to create test references. Repeatable") + env.parser.add_option("--rebase-tests", + dest="rebase_tests", + action="store_true", + default=False, + help="Update the reference output files. Do not compare.") + env.parser.add_option("--tests", + dest="tests", + action="append", + default=[], + help="Directory where tests live.") + env.parser.add_option("--otests", + dest="otests", + action="store", + default='tests-base', + help="Directory where tests live.") + env.parser.add_option("-c", "--code", + dest="codes", + action="append", + default=[], + help="Codes for test subsetting (DEC, ENC, AVX, " + + "AVX512X, AVX512PF, XOP, KNC)." + + " Only used for running tests, not creating them.") + env.parse_args() + + if not env['tests']: + env['tests'] = ['tests-base'] + + xed = mbuild.join(env['build_dir'],'xed') + #xedexe = xed + ".exe" + #if not os.path.exists(xed) and not os.path.exists(xedexe): + # mbuild.die("Need the xed command line tool: %s or %s\n\n" % (xed,xedexe)) + + if len(env['bulk_tests']) != 0: + mbuild.msgb("MAKE BULK TESTS") + make_bulk_tests(env) + sys.exit(0) + + if env['rebase_tests']: + rebase_tests(env) + sys.exit(0) + + + errors=run_tests(env) + sys.exit(errors) + + +if __name__ == "__main__": + work() diff --git a/tests/split-tests.py b/tests/split-tests.py new file mode 100755 index 0000000..87ae4b4 --- /dev/null +++ b/tests/split-tests.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python +# -*- python -*- + +import os,sys,re,glob + +def work(): + files = glob.glob("*.txt") + for fn in files: + lines = file(fn).readlines() + lines = map(lambda x: x.strip(), lines) + ofn = fn + ".new" + of = open(ofn,'w') + for line in lines: + if line: + incodes, cmd = line.split(';') # incodes are tossed + cmd = cmd.strip() + codes = [] + if ' -de ' in cmd: + codes.append('DEC') + codes.append('ENC') + elif ' -e ' in cmd: + codes.append('ENC') + elif ' -d ' in cmd: + codes.append('DEC') + elif 'ild' in cmd: + codes.append('DEC') + elif 'ex1' in cmd: + codes.append('DEC') + elif 'ex3' in cmd: + codes.append('ENC') + elif 'ex4' in cmd: + codes.append('DEC') + elif 'ex6' in cmd: + codes.append('DEC') + codes.append('ENC') + else: + codes.append('OTHER') + + if 'C4' in cmd or 'C5' in cmd or 'c4' in cmd or 'c5' in cmd: + codes.append('AVX') + if ' 8f' in cmd: # total hack: FIXME, miss some xop stuff in c4 space + codes.append('XOP') + if ' v' in cmd or ' V' in cmd: + codes.append('AVX') + + cs = " ".join(codes) + of.write("{0:20s} ; {1}\n".format(cs, cmd)) + + of.close() + + +if __name__ == "__main__": + work() diff --git a/tests/test1.py b/tests/test1.py new file mode 100755 index 0000000..8609fda --- /dev/null +++ b/tests/test1.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python +# -*- python -*- +import sys, optparse, stat, os, re, shutil, copy, time, glob + +def find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None +sys.path = [find_dir('mbuild')] + sys.path + +def dirname_n(s,n): + t = s + for i in range(0,n): + t = os.path.dirname(t) + return t + +import mbuild +start_time=mbuild.get_time() + +env = mbuild.env_t() +env.parse_args() +work_queue = mbuild.work_queue_t(env['jobs']) + + +cmds= ['obj/xed -64 -i /bin/ls > ls.out', + 'obj/xed -n 10m -v 0 -64 -i /usr/X11R6/bin/Xvnc ' ] +for cmd in cmds: + c = mbuild.command_t(cmd) + work_queue.add(c) + +phase = "XED2-TESTS" +okay = work_queue.build() +if not okay: + mbuild.die("[%s] failed" % (phase)) +mbuild.msgb(phase, "succeeded") + +end_time=mbuild.get_time() +mbuild.msgb("ELAPSED TIME", mbuild.get_elapsed_time(start_time,end_time)) diff --git a/tests/tests-avx512/test-00000/cmd b/tests/tests-avx512/test-00000/cmd new file mode 100644 index 0000000..4902db8 --- /dev/null +++ b/tests/tests-avx512/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vaddps ymm3 k1 ymm1 ymm2 diff --git a/tests/tests-avx512/test-00000/codes b/tests/tests-avx512/test-00000/codes new file mode 100644 index 0000000..c47906b --- /dev/null +++ b/tests/tests-avx512/test-00000/codes @@ -0,0 +1 @@ +ENC AVX512X diff --git a/tests/tests-avx512/test-00000/retcode.reference b/tests/tests-avx512/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00000/stderr.reference b/tests/tests-avx512/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00000/stdout.reference b/tests/tests-avx512/test-00000/stdout.reference new file mode 100644 index 0000000..a0f97e0 --- /dev/null +++ b/tests/tests-avx512/test-00000/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VADDPS MODE:2, REG0:YMM3, REG1:K1, REG2:YMM1, REG3:YMM2, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 REG3 + +Encodable! 62F1742958DA diff --git a/tests/tests-avx512/test-00001/cmd b/tests/tests-avx512/test-00001/cmd new file mode 100644 index 0000000..a29790f --- /dev/null +++ b/tests/tests-avx512/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 62F1742958DA diff --git a/tests/tests-avx512/test-00001/codes b/tests/tests-avx512/test-00001/codes new file mode 100644 index 0000000..7c17433 --- /dev/null +++ b/tests/tests-avx512/test-00001/codes @@ -0,0 +1 @@ +DEC AVX512X diff --git a/tests/tests-avx512/test-00001/retcode.reference b/tests/tests-avx512/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00001/stderr.reference b/tests/tests-avx512/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00001/stdout.reference b/tests/tests-avx512/test-00001/stdout.reference new file mode 100644 index 0000000..a56038b --- /dev/null +++ b/tests/tests-avx512/test-00001/stdout.reference @@ -0,0 +1,3 @@ +62F1742958DA +ICLASS: VADDPS CATEGORY: AVX512 EXTENSION: AVX512EVEX IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 ISA_SET: AVX512F_256 +SHORT: vaddps ymm3{k1}, ymm1, ymm2 diff --git a/tests/tests-avx512/test-00002/cmd b/tests/tests-avx512/test-00002/cmd new file mode 100644 index 0000000..eaa867c --- /dev/null +++ b/tests/tests-avx512/test-00002/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vaddps xmm3 k1 xmm1 xmm2 diff --git a/tests/tests-avx512/test-00002/codes b/tests/tests-avx512/test-00002/codes new file mode 100644 index 0000000..c47906b --- /dev/null +++ b/tests/tests-avx512/test-00002/codes @@ -0,0 +1 @@ +ENC AVX512X diff --git a/tests/tests-avx512/test-00002/retcode.reference b/tests/tests-avx512/test-00002/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00002/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00002/stderr.reference b/tests/tests-avx512/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00002/stdout.reference b/tests/tests-avx512/test-00002/stdout.reference new file mode 100644 index 0000000..79027f0 --- /dev/null +++ b/tests/tests-avx512/test-00002/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VADDPS MODE:2, REG0:XMM3, REG1:K1, REG2:XMM1, REG3:XMM2, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 REG3 + +Encodable! 62F1740958DA diff --git a/tests/tests-avx512/test-00003/cmd b/tests/tests-avx512/test-00003/cmd new file mode 100644 index 0000000..81cfa35 --- /dev/null +++ b/tests/tests-avx512/test-00003/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 62F1740958DA diff --git a/tests/tests-avx512/test-00003/codes b/tests/tests-avx512/test-00003/codes new file mode 100644 index 0000000..7c17433 --- /dev/null +++ b/tests/tests-avx512/test-00003/codes @@ -0,0 +1 @@ +DEC AVX512X diff --git a/tests/tests-avx512/test-00003/retcode.reference b/tests/tests-avx512/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00003/stderr.reference b/tests/tests-avx512/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00003/stdout.reference b/tests/tests-avx512/test-00003/stdout.reference new file mode 100644 index 0000000..81bdd4b --- /dev/null +++ b/tests/tests-avx512/test-00003/stdout.reference @@ -0,0 +1,3 @@ +62F1740958DA +ICLASS: VADDPS CATEGORY: AVX512 EXTENSION: AVX512EVEX IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 ISA_SET: AVX512F_128 +SHORT: vaddps xmm3{k1}, xmm1, xmm2 diff --git a/tests/tests-avx512/test-00004/cmd b/tests/tests-avx512/test-00004/cmd new file mode 100644 index 0000000..08ce943 --- /dev/null +++ b/tests/tests-avx512/test-00004/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62 e1 ad 0f 58 64 d9 08 diff --git a/tests/tests-avx512/test-00004/codes b/tests/tests-avx512/test-00004/codes new file mode 100644 index 0000000..d68a82a --- /dev/null +++ b/tests/tests-avx512/test-00004/codes @@ -0,0 +1 @@ +DEC ENC AVX512X diff --git a/tests/tests-avx512/test-00004/retcode.reference b/tests/tests-avx512/test-00004/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00004/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00004/stderr.reference b/tests/tests-avx512/test-00004/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00004/stdout.reference b/tests/tests-avx512/test-00004/stdout.reference new file mode 100644 index 0000000..43fb924 --- /dev/null +++ b/tests/tests-avx512/test-00004/stdout.reference @@ -0,0 +1,5 @@ +62E1AD0F5864D908 +ICLASS: VADDPD CATEGORY: AVX512 EXTENSION: AVX512EVEX IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 ISA_SET: AVX512F_128 +SHORT: vaddpd xmm20{k7}, xmm10, xmmword ptr [rcx+rbx*8+0x80] +Encodable! 62E1AD0F5864D908 +Identical re-encoding diff --git a/tests/tests-avx512/test-00005/cmd b/tests/tests-avx512/test-00005/cmd new file mode 100644 index 0000000..ab5dc82 --- /dev/null +++ b/tests/tests-avx512/test-00005/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62 f1 7e 78 2d f0 diff --git a/tests/tests-avx512/test-00005/codes b/tests/tests-avx512/test-00005/codes new file mode 100644 index 0000000..d68a82a --- /dev/null +++ b/tests/tests-avx512/test-00005/codes @@ -0,0 +1 @@ +DEC ENC AVX512X diff --git a/tests/tests-avx512/test-00005/retcode.reference b/tests/tests-avx512/test-00005/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512/test-00005/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512/test-00005/stderr.reference b/tests/tests-avx512/test-00005/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512/test-00005/stdout.reference b/tests/tests-avx512/test-00005/stdout.reference new file mode 100644 index 0000000..23e5fc3 --- /dev/null +++ b/tests/tests-avx512/test-00005/stdout.reference @@ -0,0 +1,5 @@ +62F17E782DF0 +ICLASS: VCVTSS2SI CATEGORY: CONVERT EXTENSION: AVX512EVEX IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 ISA_SET: AVX512F_SCALAR +SHORT: vcvtss2si esi{rz-sae}, xmm0 +Encodable! 62F17E782DF0 +Identical re-encoding diff --git a/tests/tests-avx512pf/test-00000/cmd b/tests/tests-avx512pf/test-00000/cmd new file mode 100644 index 0000000..6f46f2a --- /dev/null +++ b/tests/tests-avx512pf/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 62 F2 7D 48 C66C00FF diff --git a/tests/tests-avx512pf/test-00000/codes b/tests/tests-avx512pf/test-00000/codes new file mode 100644 index 0000000..1be1ff5 --- /dev/null +++ b/tests/tests-avx512pf/test-00000/codes @@ -0,0 +1 @@ +DEC AVX512PF diff --git a/tests/tests-avx512pf/test-00000/retcode.reference b/tests/tests-avx512pf/test-00000/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-avx512pf/test-00000/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-avx512pf/test-00000/stderr.reference b/tests/tests-avx512pf/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512pf/test-00000/stdout.reference b/tests/tests-avx512pf/test-00000/stdout.reference new file mode 100644 index 0000000..ee33639 --- /dev/null +++ b/tests/tests-avx512pf/test-00000/stdout.reference @@ -0,0 +1,2 @@ +62F27D48C66C00FF +ERROR: BAD_REGISTER Could not decode at offset: 0x0 PC: 0x0: [62F27D48C66C00FF00000000000000] diff --git a/tests/tests-avx512pf/test-00001/cmd b/tests/tests-avx512pf/test-00001/cmd new file mode 100644 index 0000000..cc507b0 --- /dev/null +++ b/tests/tests-avx512pf/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 62 F2 7D 49 C66C00FF diff --git a/tests/tests-avx512pf/test-00001/codes b/tests/tests-avx512pf/test-00001/codes new file mode 100644 index 0000000..1be1ff5 --- /dev/null +++ b/tests/tests-avx512pf/test-00001/codes @@ -0,0 +1 @@ +DEC AVX512PF diff --git a/tests/tests-avx512pf/test-00001/retcode.reference b/tests/tests-avx512pf/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512pf/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512pf/test-00001/stderr.reference b/tests/tests-avx512pf/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512pf/test-00001/stdout.reference b/tests/tests-avx512pf/test-00001/stdout.reference new file mode 100644 index 0000000..7d930e3 --- /dev/null +++ b/tests/tests-avx512pf/test-00001/stdout.reference @@ -0,0 +1,3 @@ +62F27D49C66C00FF +ICLASS: VSCATTERPF0DPS CATEGORY: SCATTER EXTENSION: AVX512EVEX IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 ISA_SET: AVX512PF_512 +SHORT: vscatterpf0dps byte ptr [rax+zmm0*1-0x4], k1 diff --git a/tests/tests-avx512pf/test-00002/cmd b/tests/tests-avx512pf/test-00002/cmd new file mode 100644 index 0000000..323a26b --- /dev/null +++ b/tests/tests-avx512pf/test-00002/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e VSCATTERPF0DPS MEM1:RAX,ZMM0,1,ff k0 diff --git a/tests/tests-avx512pf/test-00002/codes b/tests/tests-avx512pf/test-00002/codes new file mode 100644 index 0000000..ab15d29 --- /dev/null +++ b/tests/tests-avx512pf/test-00002/codes @@ -0,0 +1 @@ +ENC AVX512PF diff --git a/tests/tests-avx512pf/test-00002/retcode.reference b/tests/tests-avx512pf/test-00002/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-avx512pf/test-00002/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-avx512pf/test-00002/stderr.reference b/tests/tests-avx512pf/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512pf/test-00002/stdout.reference b/tests/tests-avx512pf/test-00002/stdout.reference new file mode 100644 index 0000000..0a3ee72 --- /dev/null +++ b/tests/tests-avx512pf/test-00002/stdout.reference @@ -0,0 +1,5 @@ +Request: VSCATTERPF0DPS DISP_WIDTH:8, MEM_WIDTH:1, MEM0:byte ptr [RAX+ZMM0*1-0x1], MODE:2, REG0:K0, SMODE:2 +OPERAND ORDER: MEM0 REG0 +Could not encode: VSCATTERPF0DPS MEM1:RAX,ZMM0,1,ff k0 +Error code was: GENERAL_ERROR +[XED CLIENT ERROR] Dying diff --git a/tests/tests-avx512pf/test-00003/cmd b/tests/tests-avx512pf/test-00003/cmd new file mode 100644 index 0000000..3b89bd2 --- /dev/null +++ b/tests/tests-avx512pf/test-00003/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e VSCATTERPF0DPS MEM1:RAX,ZMM0,1,ff k1 diff --git a/tests/tests-avx512pf/test-00003/codes b/tests/tests-avx512pf/test-00003/codes new file mode 100644 index 0000000..ab15d29 --- /dev/null +++ b/tests/tests-avx512pf/test-00003/codes @@ -0,0 +1 @@ +ENC AVX512PF diff --git a/tests/tests-avx512pf/test-00003/retcode.reference b/tests/tests-avx512pf/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-avx512pf/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-avx512pf/test-00003/stderr.reference b/tests/tests-avx512pf/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-avx512pf/test-00003/stdout.reference b/tests/tests-avx512pf/test-00003/stdout.reference new file mode 100644 index 0000000..dbbf605 --- /dev/null +++ b/tests/tests-avx512pf/test-00003/stdout.reference @@ -0,0 +1,4 @@ +Request: VSCATTERPF0DPS DISP_WIDTH:8, MEM_WIDTH:1, MEM0:byte ptr [RAX+ZMM0*1-0x1], MODE:2, REG0:K1, SMODE:2 +OPERAND ORDER: MEM0 REG0 +Encodable! 62F27D49C66C00FF +.byte 0x62,0xf2,0x7d,0x49,0xc6,0x6c,0x00,0xff diff --git a/tests/tests-base/test-00000/cmd b/tests/tests-base/test-00000/cmd new file mode 100644 index 0000000..448e961 --- /dev/null +++ b/tests/tests-base/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 MOVLPD XMM1 MEM8:EBX,EAX,4,00 diff --git a/tests/tests-base/test-00000/codes b/tests/tests-base/test-00000/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00000/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00000/retcode.reference b/tests/tests-base/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00000/stderr.reference b/tests/tests-base/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00000/stdout.reference b/tests/tests-base/test-00000/stdout.reference new file mode 100644 index 0000000..823d684 --- /dev/null +++ b/tests/tests-base/test-00000/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOVLPD DISP_WIDTH:8, EASZ:2, MEM_WIDTH:8, MEM0:qword ptr [EBX+EAX*4], MODE:1, REG0:XMM1, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 660F124C8300 diff --git a/tests/tests-base/test-00001/cmd b/tests/tests-base/test-00001/cmd new file mode 100644 index 0000000..0b7dd44 --- /dev/null +++ b/tests/tests-base/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 ADD EAX EAX diff --git a/tests/tests-base/test-00001/codes b/tests/tests-base/test-00001/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00001/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00001/retcode.reference b/tests/tests-base/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00001/stderr.reference b/tests/tests-base/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00001/stdout.reference b/tests/tests-base/test-00001/stdout.reference new file mode 100644 index 0000000..08d7b4f --- /dev/null +++ b/tests/tests-base/test-00001/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +ADD MODE:1, REG0:EAX, REG1:EAX, SMODE:1 +OPERAND ORDER: REG0 REG1 + +Encodable! 01C0 diff --git a/tests/tests-base/test-00002/cmd b/tests/tests-base/test-00002/cmd new file mode 100644 index 0000000..3575d65 --- /dev/null +++ b/tests/tests-base/test-00002/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 ADD EAX EBX diff --git a/tests/tests-base/test-00002/codes b/tests/tests-base/test-00002/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00002/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00002/retcode.reference b/tests/tests-base/test-00002/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00002/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00002/stderr.reference b/tests/tests-base/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00002/stdout.reference b/tests/tests-base/test-00002/stdout.reference new file mode 100644 index 0000000..c158039 --- /dev/null +++ b/tests/tests-base/test-00002/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +ADD MODE:1, REG0:EAX, REG1:EBX, SMODE:1 +OPERAND ORDER: REG0 REG1 + +Encodable! 01D8 diff --git a/tests/tests-base/test-00003/cmd b/tests/tests-base/test-00003/cmd new file mode 100644 index 0000000..fc91222 --- /dev/null +++ b/tests/tests-base/test-00003/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 ADD EAX MEM4:EBX,EAX,4,00 diff --git a/tests/tests-base/test-00003/codes b/tests/tests-base/test-00003/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00003/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00003/retcode.reference b/tests/tests-base/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00003/stderr.reference b/tests/tests-base/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00003/stdout.reference b/tests/tests-base/test-00003/stdout.reference new file mode 100644 index 0000000..9b23600 --- /dev/null +++ b/tests/tests-base/test-00003/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +ADD DISP_WIDTH:8, EASZ:2, MEM_WIDTH:4, MEM0:dword ptr [EBX+EAX*4], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 03448300 diff --git a/tests/tests-base/test-00004/cmd b/tests/tests-base/test-00004/cmd new file mode 100644 index 0000000..242d3a5 --- /dev/null +++ b/tests/tests-base/test-00004/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 POP/64 RSI diff --git a/tests/tests-base/test-00004/codes b/tests/tests-base/test-00004/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00004/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00004/retcode.reference b/tests/tests-base/test-00004/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00004/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00004/stderr.reference b/tests/tests-base/test-00004/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00004/stdout.reference b/tests/tests-base/test-00004/stdout.reference new file mode 100644 index 0000000..d4b4f01 --- /dev/null +++ b/tests/tests-base/test-00004/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +POP EOSZ:3, MODE:2, REG0:RSI, SMODE:2 +OPERAND ORDER: REG0 + +Encodable! 5E diff --git a/tests/tests-base/test-00005/cmd b/tests/tests-base/test-00005/cmd new file mode 100644 index 0000000..427fb95 --- /dev/null +++ b/tests/tests-base/test-00005/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 MOV/64 R9 RDX diff --git a/tests/tests-base/test-00005/codes b/tests/tests-base/test-00005/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00005/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00005/retcode.reference b/tests/tests-base/test-00005/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00005/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00005/stderr.reference b/tests/tests-base/test-00005/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00005/stdout.reference b/tests/tests-base/test-00005/stdout.reference new file mode 100644 index 0000000..2b5be66 --- /dev/null +++ b/tests/tests-base/test-00005/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EOSZ:3, MODE:2, REG0:R9, REG1:RDX, SMODE:2 +OPERAND ORDER: REG0 REG1 + +Encodable! 4989D1 diff --git a/tests/tests-base/test-00006/cmd b/tests/tests-base/test-00006/cmd new file mode 100644 index 0000000..ff2c171 --- /dev/null +++ b/tests/tests-base/test-00006/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 AND/64 RSP SIMM:f0 diff --git a/tests/tests-base/test-00006/codes b/tests/tests-base/test-00006/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00006/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00006/retcode.reference b/tests/tests-base/test-00006/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00006/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00006/stderr.reference b/tests/tests-base/test-00006/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00006/stdout.reference b/tests/tests-base/test-00006/stdout.reference new file mode 100644 index 0000000..c43cae4 --- /dev/null +++ b/tests/tests-base/test-00006/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +AND EOSZ:3, IMM_WIDTH:8, IMM0SIGNED, IMM0:0xf0, MODE:2, REG0:RSP, SMODE:2 +OPERAND ORDER: REG0 IMM0 + +Encodable! 4883E4F0 diff --git a/tests/tests-base/test-00007/cmd b/tests/tests-base/test-00007/cmd new file mode 100644 index 0000000..a838de6 --- /dev/null +++ b/tests/tests-base/test-00007/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 JMP_FAR PTR:11223344 IMM:5566 diff --git a/tests/tests-base/test-00007/codes b/tests/tests-base/test-00007/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00007/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00007/retcode.reference b/tests/tests-base/test-00007/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00007/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00007/stderr.reference b/tests/tests-base/test-00007/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00007/stdout.reference b/tests/tests-base/test-00007/stdout.reference new file mode 100644 index 0000000..0bf85b2 --- /dev/null +++ b/tests/tests-base/test-00007/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +JMP_FAR BRDISP_WIDTH:32, IMM_WIDTH:16, IMM0:0x5566, MODE:1, PTR:0x11223344, SMODE:1 +OPERAND ORDER: PTR IMM0 + +Encodable! EA443322116655 diff --git a/tests/tests-base/test-00008/cmd b/tests/tests-base/test-00008/cmd new file mode 100644 index 0000000..aedf522 --- /dev/null +++ b/tests/tests-base/test-00008/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d EA112233445566 diff --git a/tests/tests-base/test-00008/codes b/tests/tests-base/test-00008/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00008/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00008/retcode.reference b/tests/tests-base/test-00008/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00008/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00008/stderr.reference b/tests/tests-base/test-00008/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00008/stdout.reference b/tests/tests-base/test-00008/stdout.reference new file mode 100644 index 0000000..44b7083 --- /dev/null +++ b/tests/tests-base/test-00008/stdout.reference @@ -0,0 +1,3 @@ +EA112233445566 +ICLASS: JMP_FAR CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_FAR_PTRp_IMMw ISA_SET: I86 +SHORT: jmp far 0x44332211, 0x6655 diff --git a/tests/tests-base/test-00009/cmd b/tests/tests-base/test-00009/cmd new file mode 100644 index 0000000..af3c846 --- /dev/null +++ b/tests/tests-base/test-00009/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 JLE BRDISP:11223344 diff --git a/tests/tests-base/test-00009/codes b/tests/tests-base/test-00009/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00009/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00009/retcode.reference b/tests/tests-base/test-00009/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00009/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00009/stderr.reference b/tests/tests-base/test-00009/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00009/stdout.reference b/tests/tests-base/test-00009/stdout.reference new file mode 100644 index 0000000..2b3bd1b --- /dev/null +++ b/tests/tests-base/test-00009/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +JLE BRDISP_WIDTH:32, MODE:1, RELBR:0x11223344, SMODE:1 +OPERAND ORDER: RELBR + +Encodable! 0F8E44332211 diff --git a/tests/tests-base/test-00010/cmd b/tests/tests-base/test-00010/cmd new file mode 100644 index 0000000..317fe12 --- /dev/null +++ b/tests/tests-base/test-00010/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -v 4 -64 -de 488B05411D1100 diff --git a/tests/tests-base/test-00010/codes b/tests/tests-base/test-00010/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00010/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00010/retcode.reference b/tests/tests-base/test-00010/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00010/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00010/stderr.reference b/tests/tests-base/test-00010/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00010/stdout.reference b/tests/tests-base/test-00010/stdout.reference new file mode 100644 index 0000000..c05ebd5 --- /dev/null +++ b/tests/tests-base/test-00010/stdout.reference @@ -0,0 +1,10 @@ +#XED version: [7.53.0-14-g3904991 2016-12-12] +488B05411D1100 +MOV MOV_GPRv_MEMv DISP_WIDTH:32, EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAX_BYTES:7, MEM0:ptr [RIP+0x111d41], MODE:2, MODRM, MODRM_BYTE:5, NEED_MEMDISP:32, NOMINAL_OPCODE:139, NPREFIXES:1, NREXES:1, OUTREG:RAX, P4, POS_DISP:3, POS_NOMINAL_OPCODE:1, POS_MODRM:2, REG0:RAX, REX, REXW, RM:5, SMODE:2, SRM:3, TZCNT, USING_DEFAULT_SEGMENT0 +0 REG0/W/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +1 MEM0/R/V/EXPLICIT/IMM_CONST/1 +YDIS: mov rax, qword ptr [rip+0x111d41] +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_GPRv_MEMv ISA_SET: I86 +SHORT: mov rax, qword ptr [rip+0x111d41] +Encodable! 488B05411D1100 +Identical re-encoding diff --git a/tests/tests-base/test-00011/cmd b/tests/tests-base/test-00011/cmd new file mode 100644 index 0000000..2d02e73 --- /dev/null +++ b/tests/tests-base/test-00011/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 90 diff --git a/tests/tests-base/test-00011/codes b/tests/tests-base/test-00011/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00011/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00011/retcode.reference b/tests/tests-base/test-00011/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00011/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00011/stderr.reference b/tests/tests-base/test-00011/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00011/stdout.reference b/tests/tests-base/test-00011/stdout.reference new file mode 100644 index 0000000..05ea540 --- /dev/null +++ b/tests/tests-base/test-00011/stdout.reference @@ -0,0 +1,3 @@ +90 +ICLASS: NOP CATEGORY: NOP EXTENSION: BASE IFORM: NOP_90 ISA_SET: I86 +SHORT: nop diff --git a/tests/tests-base/test-00012/cmd b/tests/tests-base/test-00012/cmd new file mode 100644 index 0000000..15dc617 --- /dev/null +++ b/tests/tests-base/test-00012/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f390 diff --git a/tests/tests-base/test-00012/codes b/tests/tests-base/test-00012/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00012/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00012/retcode.reference b/tests/tests-base/test-00012/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00012/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00012/stderr.reference b/tests/tests-base/test-00012/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00012/stdout.reference b/tests/tests-base/test-00012/stdout.reference new file mode 100644 index 0000000..58fceef --- /dev/null +++ b/tests/tests-base/test-00012/stdout.reference @@ -0,0 +1,5 @@ +F390 +ICLASS: PAUSE CATEGORY: MISC EXTENSION: PAUSE IFORM: PAUSE ISA_SET: PAUSE +SHORT: pause +Encodable! F390 +Identical re-encoding diff --git a/tests/tests-base/test-00013/cmd b/tests/tests-base/test-00013/cmd new file mode 100644 index 0000000..7326615 --- /dev/null +++ b/tests/tests-base/test-00013/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f391 diff --git a/tests/tests-base/test-00013/codes b/tests/tests-base/test-00013/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00013/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00013/retcode.reference b/tests/tests-base/test-00013/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00013/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00013/stderr.reference b/tests/tests-base/test-00013/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00013/stdout.reference b/tests/tests-base/test-00013/stdout.reference new file mode 100644 index 0000000..544677a --- /dev/null +++ b/tests/tests-base/test-00013/stdout.reference @@ -0,0 +1,5 @@ +F391 +ICLASS: XCHG CATEGORY: DATAXFER EXTENSION: BASE IFORM: XCHG_GPRv_OrAX ISA_SET: I86 +SHORT: xchg ecx, eax +Encodable! F391 +Identical re-encoding diff --git a/tests/tests-base/test-00014/cmd b/tests/tests-base/test-00014/cmd new file mode 100644 index 0000000..e3345d0 --- /dev/null +++ b/tests/tests-base/test-00014/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f290 diff --git a/tests/tests-base/test-00014/codes b/tests/tests-base/test-00014/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00014/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00014/retcode.reference b/tests/tests-base/test-00014/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00014/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00014/stderr.reference b/tests/tests-base/test-00014/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00014/stdout.reference b/tests/tests-base/test-00014/stdout.reference new file mode 100644 index 0000000..bd5784d --- /dev/null +++ b/tests/tests-base/test-00014/stdout.reference @@ -0,0 +1,5 @@ +F290 +ICLASS: NOP CATEGORY: NOP EXTENSION: BASE IFORM: NOP_90 ISA_SET: I86 +SHORT: nop +Encodable! F290 +Identical re-encoding diff --git a/tests/tests-base/test-00015/cmd b/tests/tests-base/test-00015/cmd new file mode 100644 index 0000000..75be4e8 --- /dev/null +++ b/tests/tests-base/test-00015/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 REPE_CMPSB diff --git a/tests/tests-base/test-00015/codes b/tests/tests-base/test-00015/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00015/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00015/retcode.reference b/tests/tests-base/test-00015/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00015/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00015/stderr.reference b/tests/tests-base/test-00015/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00015/stdout.reference b/tests/tests-base/test-00015/stdout.reference new file mode 100644 index 0000000..5e3f2b7 --- /dev/null +++ b/tests/tests-base/test-00015/stdout.reference @@ -0,0 +1,4 @@ +Encode request: +REPE_CMPSB MODE:1, SMODE:1 + +Encodable! F3A6 diff --git a/tests/tests-base/test-00016/cmd b/tests/tests-base/test-00016/cmd new file mode 100644 index 0000000..80bfdbd --- /dev/null +++ b/tests/tests-base/test-00016/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de F3A6 diff --git a/tests/tests-base/test-00016/codes b/tests/tests-base/test-00016/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00016/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00016/retcode.reference b/tests/tests-base/test-00016/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00016/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00016/stderr.reference b/tests/tests-base/test-00016/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00016/stdout.reference b/tests/tests-base/test-00016/stdout.reference new file mode 100644 index 0000000..7feb509 --- /dev/null +++ b/tests/tests-base/test-00016/stdout.reference @@ -0,0 +1,5 @@ +F3A6 +ICLASS: REPE_CMPSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: REPE_CMPSB ISA_SET: I86 +SHORT: rep cmpsb byte ptr [esi], byte ptr [edi] +Encodable! F3A6 +Identical re-encoding diff --git a/tests/tests-base/test-00017/cmd b/tests/tests-base/test-00017/cmd new file mode 100644 index 0000000..199bb1d --- /dev/null +++ b/tests/tests-base/test-00017/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 8d00 diff --git a/tests/tests-base/test-00017/codes b/tests/tests-base/test-00017/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00017/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00017/retcode.reference b/tests/tests-base/test-00017/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00017/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00017/stderr.reference b/tests/tests-base/test-00017/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00017/stdout.reference b/tests/tests-base/test-00017/stdout.reference new file mode 100644 index 0000000..947a3f1 --- /dev/null +++ b/tests/tests-base/test-00017/stdout.reference @@ -0,0 +1,5 @@ +8D00 +ICLASS: LEA CATEGORY: MISC EXTENSION: BASE IFORM: LEA_GPRv_AGEN ISA_SET: I86 +SHORT: lea eax, ptr [eax] +Encodable! 8D00 +Identical re-encoding diff --git a/tests/tests-base/test-00018/cmd b/tests/tests-base/test-00018/cmd new file mode 100644 index 0000000..1dd82f8 --- /dev/null +++ b/tests/tests-base/test-00018/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 LEA EAX AGEN:ECX diff --git a/tests/tests-base/test-00018/codes b/tests/tests-base/test-00018/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00018/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00018/retcode.reference b/tests/tests-base/test-00018/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00018/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00018/stderr.reference b/tests/tests-base/test-00018/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00018/stdout.reference b/tests/tests-base/test-00018/stdout.reference new file mode 100644 index 0000000..587291d --- /dev/null +++ b/tests/tests-base/test-00018/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [ECX], EASZ:2, MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 AGEN + +Encodable! 8D01 diff --git a/tests/tests-base/test-00019/cmd b/tests/tests-base/test-00019/cmd new file mode 100644 index 0000000..69b47a7 --- /dev/null +++ b/tests/tests-base/test-00019/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 LEA EAX AGEN:EAX,-,-,00 diff --git a/tests/tests-base/test-00019/codes b/tests/tests-base/test-00019/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00019/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00019/retcode.reference b/tests/tests-base/test-00019/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00019/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00019/stderr.reference b/tests/tests-base/test-00019/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00019/stdout.reference b/tests/tests-base/test-00019/stdout.reference new file mode 100644 index 0000000..aac2f90 --- /dev/null +++ b/tests/tests-base/test-00019/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [EAX], DISP_WIDTH:8, EASZ:2, MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 AGEN + +Encodable! 8D4000 diff --git a/tests/tests-base/test-00020/cmd b/tests/tests-base/test-00020/cmd new file mode 100644 index 0000000..18c545d --- /dev/null +++ b/tests/tests-base/test-00020/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RAX,-,-,00 diff --git a/tests/tests-base/test-00020/codes b/tests/tests-base/test-00020/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00020/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00020/retcode.reference b/tests/tests-base/test-00020/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00020/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00020/stderr.reference b/tests/tests-base/test-00020/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00020/stdout.reference b/tests/tests-base/test-00020/stdout.reference new file mode 100644 index 0000000..e8bd100 --- /dev/null +++ b/tests/tests-base/test-00020/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [RAX], DISP_WIDTH:8, EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 488D4000 diff --git a/tests/tests-base/test-00021/cmd b/tests/tests-base/test-00021/cmd new file mode 100644 index 0000000..e3f96a6 --- /dev/null +++ b/tests/tests-base/test-00021/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RCX diff --git a/tests/tests-base/test-00021/codes b/tests/tests-base/test-00021/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00021/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00021/retcode.reference b/tests/tests-base/test-00021/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00021/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00021/stderr.reference b/tests/tests-base/test-00021/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00021/stdout.reference b/tests/tests-base/test-00021/stdout.reference new file mode 100644 index 0000000..4ce2314 --- /dev/null +++ b/tests/tests-base/test-00021/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [RCX], EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 488D01 diff --git a/tests/tests-base/test-00022/cmd b/tests/tests-base/test-00022/cmd new file mode 100644 index 0000000..8890ae1 --- /dev/null +++ b/tests/tests-base/test-00022/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:ECX diff --git a/tests/tests-base/test-00022/codes b/tests/tests-base/test-00022/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00022/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00022/retcode.reference b/tests/tests-base/test-00022/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00022/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00022/stderr.reference b/tests/tests-base/test-00022/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00022/stdout.reference b/tests/tests-base/test-00022/stdout.reference new file mode 100644 index 0000000..a36dc99 --- /dev/null +++ b/tests/tests-base/test-00022/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [ECX], EASZ:2, EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 67488D01 diff --git a/tests/tests-base/test-00023/cmd b/tests/tests-base/test-00023/cmd new file mode 100644 index 0000000..0697cfd --- /dev/null +++ b/tests/tests-base/test-00023/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/32 EAX AGEN:RAX,-,-,00 diff --git a/tests/tests-base/test-00023/codes b/tests/tests-base/test-00023/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00023/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00023/retcode.reference b/tests/tests-base/test-00023/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00023/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00023/stderr.reference b/tests/tests-base/test-00023/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00023/stdout.reference b/tests/tests-base/test-00023/stdout.reference new file mode 100644 index 0000000..f738029 --- /dev/null +++ b/tests/tests-base/test-00023/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [RAX], DISP_WIDTH:8, EOSZ:2, MODE:2, REG0:EAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 8D4000 diff --git a/tests/tests-base/test-00024/cmd b/tests/tests-base/test-00024/cmd new file mode 100644 index 0000000..335bebd --- /dev/null +++ b/tests/tests-base/test-00024/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/32 EAX AGEN:EAX,-,-,00 diff --git a/tests/tests-base/test-00024/codes b/tests/tests-base/test-00024/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00024/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00024/retcode.reference b/tests/tests-base/test-00024/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00024/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00024/stderr.reference b/tests/tests-base/test-00024/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00024/stdout.reference b/tests/tests-base/test-00024/stdout.reference new file mode 100644 index 0000000..efe2baf --- /dev/null +++ b/tests/tests-base/test-00024/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [EAX], DISP_WIDTH:8, EASZ:2, EOSZ:2, MODE:2, REG0:EAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 678D4000 diff --git a/tests/tests-base/test-00025/cmd b/tests/tests-base/test-00025/cmd new file mode 100644 index 0000000..b95ef82 --- /dev/null +++ b/tests/tests-base/test-00025/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de A230 diff --git a/tests/tests-base/test-00025/codes b/tests/tests-base/test-00025/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00025/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00025/retcode.reference b/tests/tests-base/test-00025/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00025/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00025/stderr.reference b/tests/tests-base/test-00025/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00025/stdout.reference b/tests/tests-base/test-00025/stdout.reference new file mode 100644 index 0000000..151c0e1 --- /dev/null +++ b/tests/tests-base/test-00025/stdout.reference @@ -0,0 +1,2 @@ +A230 +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [A23000000000000000000000000000] diff --git a/tests/tests-base/test-00026/cmd b/tests/tests-base/test-00026/cmd new file mode 100644 index 0000000..f43c5db --- /dev/null +++ b/tests/tests-base/test-00026/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de A211223344 diff --git a/tests/tests-base/test-00026/codes b/tests/tests-base/test-00026/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00026/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00026/retcode.reference b/tests/tests-base/test-00026/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00026/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00026/stderr.reference b/tests/tests-base/test-00026/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00026/stdout.reference b/tests/tests-base/test-00026/stdout.reference new file mode 100644 index 0000000..d507503 --- /dev/null +++ b/tests/tests-base/test-00026/stdout.reference @@ -0,0 +1,5 @@ +A211223344 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_MEMb_AL ISA_SET: I86 +SHORT: mov byte ptr [0x44332211], al +Encodable! A211223344 +Identical re-encoding diff --git a/tests/tests-base/test-00027/cmd b/tests/tests-base/test-00027/cmd new file mode 100644 index 0000000..5a5652a --- /dev/null +++ b/tests/tests-base/test-00027/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 36A011 diff --git a/tests/tests-base/test-00027/codes b/tests/tests-base/test-00027/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00027/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00027/retcode.reference b/tests/tests-base/test-00027/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00027/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00027/stderr.reference b/tests/tests-base/test-00027/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00027/stdout.reference b/tests/tests-base/test-00027/stdout.reference new file mode 100644 index 0000000..c2b810f --- /dev/null +++ b/tests/tests-base/test-00027/stdout.reference @@ -0,0 +1,2 @@ +36A011 +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [36A011000000000000000000000000] diff --git a/tests/tests-base/test-00028/cmd b/tests/tests-base/test-00028/cmd new file mode 100644 index 0000000..cfb6564 --- /dev/null +++ b/tests/tests-base/test-00028/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 36A011223344 diff --git a/tests/tests-base/test-00028/codes b/tests/tests-base/test-00028/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00028/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00028/retcode.reference b/tests/tests-base/test-00028/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00028/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00028/stderr.reference b/tests/tests-base/test-00028/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00028/stdout.reference b/tests/tests-base/test-00028/stdout.reference new file mode 100644 index 0000000..c893c9d --- /dev/null +++ b/tests/tests-base/test-00028/stdout.reference @@ -0,0 +1,5 @@ +36A011223344 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_AL_MEMb ISA_SET: I86 +SHORT: mov al, byte ptr ss:[0x44332211] +Encodable! 36A011223344 +Identical re-encoding diff --git a/tests/tests-base/test-00029/cmd b/tests/tests-base/test-00029/cmd new file mode 100644 index 0000000..95d2123 --- /dev/null +++ b/tests/tests-base/test-00029/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 PUSH IMM:11223344 diff --git a/tests/tests-base/test-00029/codes b/tests/tests-base/test-00029/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00029/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00029/retcode.reference b/tests/tests-base/test-00029/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00029/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00029/stderr.reference b/tests/tests-base/test-00029/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00029/stdout.reference b/tests/tests-base/test-00029/stdout.reference new file mode 100644 index 0000000..d3fee27 --- /dev/null +++ b/tests/tests-base/test-00029/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +PUSH IMM_WIDTH:32, IMM0:0x11223344, MODE:1, SMODE:1 +OPERAND ORDER: IMM0 + +Encodable! 6844332211 diff --git a/tests/tests-base/test-00030/cmd b/tests/tests-base/test-00030/cmd new file mode 100644 index 0000000..2d358e3 --- /dev/null +++ b/tests/tests-base/test-00030/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 7402 diff --git a/tests/tests-base/test-00030/codes b/tests/tests-base/test-00030/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00030/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00030/retcode.reference b/tests/tests-base/test-00030/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00030/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00030/stderr.reference b/tests/tests-base/test-00030/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00030/stdout.reference b/tests/tests-base/test-00030/stdout.reference new file mode 100644 index 0000000..04f93e9 --- /dev/null +++ b/tests/tests-base/test-00030/stdout.reference @@ -0,0 +1,5 @@ +7402 +ICLASS: JZ CATEGORY: COND_BR EXTENSION: BASE IFORM: JZ_RELBRb ISA_SET: I86 +SHORT: jz 0x4 +Encodable! 7402 +Identical re-encoding diff --git a/tests/tests-base/test-00031/cmd b/tests/tests-base/test-00031/cmd new file mode 100644 index 0000000..4fa6584 --- /dev/null +++ b/tests/tests-base/test-00031/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 40ff4c5000 diff --git a/tests/tests-base/test-00031/codes b/tests/tests-base/test-00031/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00031/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00031/retcode.reference b/tests/tests-base/test-00031/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00031/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00031/stderr.reference b/tests/tests-base/test-00031/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00031/stdout.reference b/tests/tests-base/test-00031/stdout.reference new file mode 100644 index 0000000..1ad20bf --- /dev/null +++ b/tests/tests-base/test-00031/stdout.reference @@ -0,0 +1,5 @@ +40FF4C5000 +ICLASS: INC CATEGORY: BINARY EXTENSION: BASE IFORM: INC_GPRv_40 ISA_SET: I86 +SHORT: inc eax +Encodable! 40 +Identical re-encoding diff --git a/tests/tests-base/test-00032/cmd b/tests/tests-base/test-00032/cmd new file mode 100644 index 0000000..a4e40ba --- /dev/null +++ b/tests/tests-base/test-00032/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 41ff4c5000 diff --git a/tests/tests-base/test-00032/codes b/tests/tests-base/test-00032/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00032/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00032/retcode.reference b/tests/tests-base/test-00032/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00032/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00032/stderr.reference b/tests/tests-base/test-00032/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00032/stdout.reference b/tests/tests-base/test-00032/stdout.reference new file mode 100644 index 0000000..8fc7d76 --- /dev/null +++ b/tests/tests-base/test-00032/stdout.reference @@ -0,0 +1,5 @@ +41FF4C5000 +ICLASS: INC CATEGORY: BINARY EXTENSION: BASE IFORM: INC_GPRv_40 ISA_SET: I86 +SHORT: inc ecx +Encodable! 41 +Identical re-encoding diff --git a/tests/tests-base/test-00033/cmd b/tests/tests-base/test-00033/cmd new file mode 100644 index 0000000..ed4360a --- /dev/null +++ b/tests/tests-base/test-00033/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 90 diff --git a/tests/tests-base/test-00033/codes b/tests/tests-base/test-00033/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00033/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00033/retcode.reference b/tests/tests-base/test-00033/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00033/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00033/stderr.reference b/tests/tests-base/test-00033/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00033/stdout.reference b/tests/tests-base/test-00033/stdout.reference new file mode 100644 index 0000000..05e6840 --- /dev/null +++ b/tests/tests-base/test-00033/stdout.reference @@ -0,0 +1,5 @@ +90 +ICLASS: NOP CATEGORY: NOP EXTENSION: BASE IFORM: NOP_90 ISA_SET: I86 +SHORT: nop +Encodable! 90 +Identical re-encoding diff --git a/tests/tests-base/test-00034/cmd b/tests/tests-base/test-00034/cmd new file mode 100644 index 0000000..bccabbe --- /dev/null +++ b/tests/tests-base/test-00034/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 6690 diff --git a/tests/tests-base/test-00034/codes b/tests/tests-base/test-00034/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00034/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00034/retcode.reference b/tests/tests-base/test-00034/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00034/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00034/stderr.reference b/tests/tests-base/test-00034/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00034/stdout.reference b/tests/tests-base/test-00034/stdout.reference new file mode 100644 index 0000000..39d2bca --- /dev/null +++ b/tests/tests-base/test-00034/stdout.reference @@ -0,0 +1,5 @@ +6690 +ICLASS: NOP CATEGORY: NOP EXTENSION: BASE IFORM: NOP_90 ISA_SET: I86 +SHORT: data16 nop +Encodable! 6690 +Identical re-encoding diff --git a/tests/tests-base/test-00035/cmd b/tests/tests-base/test-00035/cmd new file mode 100644 index 0000000..9d9532e --- /dev/null +++ b/tests/tests-base/test-00035/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 87c0 diff --git a/tests/tests-base/test-00035/codes b/tests/tests-base/test-00035/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00035/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00035/retcode.reference b/tests/tests-base/test-00035/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00035/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00035/stderr.reference b/tests/tests-base/test-00035/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00035/stdout.reference b/tests/tests-base/test-00035/stdout.reference new file mode 100644 index 0000000..1804a81 --- /dev/null +++ b/tests/tests-base/test-00035/stdout.reference @@ -0,0 +1,11 @@ +87C0 +ICLASS: XCHG CATEGORY: DATAXFER EXTENSION: BASE IFORM: XCHG_GPRv_GPRv ISA_SET: I86 +SHORT: xchg eax, eax +Encodable! 90 +Discrepenacy after re-encoding. dec_len= 2 [87C0] enc_olen= 1 [90] for instruction: XCHG XCHG_GPRv_GPRv EASZ:2, EOSZ:2, HAS_MODRM:1, LZCNT, MAX_BYTES:2, MOD:3, MODE:1, MODRM_BYTE:192, NOMINAL_OPCODE:135, OUTREG:EAX, P4, POS_MODRM:1, REG0:EAX, REG1:EAX, SMODE:1, TZCNT +0 REG0/RW/V/EXPLICIT/NT_LOOKUP_FN/GPRV_B +1 REG1/RW/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +YDIS: xchg eax, eax +vs Encode request: XCHG EASZ:2, EOSZ:2, HAS_MODRM:1, LZCNT, MAX_BYTES:2, MOD:3, MODE:1, MODRM_BYTE:192, NOMINAL_OPCODE:135, OUTREG:EAX, P4, POS_MODRM:1, REG0:EAX, REG1:EAX, SMODE:1, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00036/cmd b/tests/tests-base/test-00036/cmd new file mode 100644 index 0000000..a1e4df4 --- /dev/null +++ b/tests/tests-base/test-00036/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -I -64 -de 4b8d446d00 diff --git a/tests/tests-base/test-00036/codes b/tests/tests-base/test-00036/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00036/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00036/retcode.reference b/tests/tests-base/test-00036/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00036/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00036/stderr.reference b/tests/tests-base/test-00036/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00036/stdout.reference b/tests/tests-base/test-00036/stdout.reference new file mode 100644 index 0000000..aebf70c --- /dev/null +++ b/tests/tests-base/test-00036/stdout.reference @@ -0,0 +1,5 @@ +4B8D446D00 +ICLASS: LEA CATEGORY: MISC EXTENSION: BASE IFORM: LEA_GPRv_AGEN ISA_SET: I86 +SHORT: lea rax, ptr [r13+r13*2] +Encodable! 4B8D446D00 +Identical re-encoding diff --git a/tests/tests-base/test-00037/cmd b/tests/tests-base/test-00037/cmd new file mode 100644 index 0000000..85ffa19 --- /dev/null +++ b/tests/tests-base/test-00037/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -I -64 -de 4b8d447500 diff --git a/tests/tests-base/test-00037/codes b/tests/tests-base/test-00037/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00037/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00037/retcode.reference b/tests/tests-base/test-00037/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00037/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00037/stderr.reference b/tests/tests-base/test-00037/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00037/stdout.reference b/tests/tests-base/test-00037/stdout.reference new file mode 100644 index 0000000..d9bc040 --- /dev/null +++ b/tests/tests-base/test-00037/stdout.reference @@ -0,0 +1,5 @@ +4B8D447500 +ICLASS: LEA CATEGORY: MISC EXTENSION: BASE IFORM: LEA_GPRv_AGEN ISA_SET: I86 +SHORT: lea rax, ptr [r13+r14*2] +Encodable! 4B8D447500 +Identical re-encoding diff --git a/tests/tests-base/test-00038/cmd b/tests/tests-base/test-00038/cmd new file mode 100644 index 0000000..05522a1 --- /dev/null +++ b/tests/tests-base/test-00038/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,R13,2,00 diff --git a/tests/tests-base/test-00038/codes b/tests/tests-base/test-00038/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00038/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00038/retcode.reference b/tests/tests-base/test-00038/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00038/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00038/stderr.reference b/tests/tests-base/test-00038/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00038/stdout.reference b/tests/tests-base/test-00038/stdout.reference new file mode 100644 index 0000000..686eb33 --- /dev/null +++ b/tests/tests-base/test-00038/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13+R13*2], DISP_WIDTH:8, EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 4B8D446D00 diff --git a/tests/tests-base/test-00039/cmd b/tests/tests-base/test-00039/cmd new file mode 100644 index 0000000..0308792 --- /dev/null +++ b/tests/tests-base/test-00039/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,R14,2,00 diff --git a/tests/tests-base/test-00039/codes b/tests/tests-base/test-00039/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00039/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00039/retcode.reference b/tests/tests-base/test-00039/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00039/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00039/stderr.reference b/tests/tests-base/test-00039/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00039/stdout.reference b/tests/tests-base/test-00039/stdout.reference new file mode 100644 index 0000000..5cc6662 --- /dev/null +++ b/tests/tests-base/test-00039/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13+R14*2], DISP_WIDTH:8, EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 4B8D447500 diff --git a/tests/tests-base/test-00040/cmd b/tests/tests-base/test-00040/cmd new file mode 100644 index 0000000..009e4bd --- /dev/null +++ b/tests/tests-base/test-00040/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 97 diff --git a/tests/tests-base/test-00040/codes b/tests/tests-base/test-00040/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00040/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00040/retcode.reference b/tests/tests-base/test-00040/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00040/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00040/stderr.reference b/tests/tests-base/test-00040/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00040/stdout.reference b/tests/tests-base/test-00040/stdout.reference new file mode 100644 index 0000000..be08ea5 --- /dev/null +++ b/tests/tests-base/test-00040/stdout.reference @@ -0,0 +1,3 @@ +97 +ICLASS: XCHG CATEGORY: DATAXFER EXTENSION: BASE IFORM: XCHG_GPRv_OrAX ISA_SET: I86 +SHORT: xchg edi, eax diff --git a/tests/tests-base/test-00041/cmd b/tests/tests-base/test-00041/cmd new file mode 100644 index 0000000..9c2adac --- /dev/null +++ b/tests/tests-base/test-00041/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 LEA EAX AGEN:EBP,ESI,2 diff --git a/tests/tests-base/test-00041/codes b/tests/tests-base/test-00041/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00041/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00041/retcode.reference b/tests/tests-base/test-00041/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00041/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00041/stderr.reference b/tests/tests-base/test-00041/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00041/stdout.reference b/tests/tests-base/test-00041/stdout.reference new file mode 100644 index 0000000..eff2bb3 --- /dev/null +++ b/tests/tests-base/test-00041/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [EBP+ESI*2], EASZ:2, MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 AGEN + +Encodable! 8D447500 diff --git a/tests/tests-base/test-00042/cmd b/tests/tests-base/test-00042/cmd new file mode 100644 index 0000000..c89f6d4 --- /dev/null +++ b/tests/tests-base/test-00042/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13,RSI,2 diff --git a/tests/tests-base/test-00042/codes b/tests/tests-base/test-00042/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00042/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00042/retcode.reference b/tests/tests-base/test-00042/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00042/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00042/stderr.reference b/tests/tests-base/test-00042/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00042/stdout.reference b/tests/tests-base/test-00042/stdout.reference new file mode 100644 index 0000000..9f978a6 --- /dev/null +++ b/tests/tests-base/test-00042/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13+RSI*2], EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 498D447500 diff --git a/tests/tests-base/test-00043/cmd b/tests/tests-base/test-00043/cmd new file mode 100644 index 0000000..fdb77d9 --- /dev/null +++ b/tests/tests-base/test-00043/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RBP,RDI,2 diff --git a/tests/tests-base/test-00043/codes b/tests/tests-base/test-00043/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00043/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00043/retcode.reference b/tests/tests-base/test-00043/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00043/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00043/stderr.reference b/tests/tests-base/test-00043/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00043/stdout.reference b/tests/tests-base/test-00043/stdout.reference new file mode 100644 index 0000000..ec5c96e --- /dev/null +++ b/tests/tests-base/test-00043/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [RBP+RDI*2], EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 488D447D00 diff --git a/tests/tests-base/test-00044/cmd b/tests/tests-base/test-00044/cmd new file mode 100644 index 0000000..e172dfe --- /dev/null +++ b/tests/tests-base/test-00044/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:RBP diff --git a/tests/tests-base/test-00044/codes b/tests/tests-base/test-00044/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00044/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00044/retcode.reference b/tests/tests-base/test-00044/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00044/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00044/stderr.reference b/tests/tests-base/test-00044/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00044/stdout.reference b/tests/tests-base/test-00044/stdout.reference new file mode 100644 index 0000000..25ba9fd --- /dev/null +++ b/tests/tests-base/test-00044/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [RBP], EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 488D4500 diff --git a/tests/tests-base/test-00045/cmd b/tests/tests-base/test-00045/cmd new file mode 100644 index 0000000..707caa2 --- /dev/null +++ b/tests/tests-base/test-00045/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 LEA/64 RAX AGEN:R13 diff --git a/tests/tests-base/test-00045/codes b/tests/tests-base/test-00045/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00045/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00045/retcode.reference b/tests/tests-base/test-00045/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00045/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00045/stderr.reference b/tests/tests-base/test-00045/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00045/stdout.reference b/tests/tests-base/test-00045/stdout.reference new file mode 100644 index 0000000..671b790 --- /dev/null +++ b/tests/tests-base/test-00045/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13], EOSZ:3, MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 498D4500 diff --git a/tests/tests-base/test-00046/cmd b/tests/tests-base/test-00046/cmd new file mode 100644 index 0000000..418df5f --- /dev/null +++ b/tests/tests-base/test-00046/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 0f ad c3 diff --git a/tests/tests-base/test-00046/codes b/tests/tests-base/test-00046/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00046/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00046/retcode.reference b/tests/tests-base/test-00046/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00046/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00046/stderr.reference b/tests/tests-base/test-00046/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00046/stdout.reference b/tests/tests-base/test-00046/stdout.reference new file mode 100644 index 0000000..c3e7e7c --- /dev/null +++ b/tests/tests-base/test-00046/stdout.reference @@ -0,0 +1,3 @@ +0FADC3 +ICLASS: SHRD CATEGORY: SHIFT EXTENSION: BASE IFORM: SHRD_GPRv_GPRv_CL ISA_SET: I386 +SHORT: shrd ebx, eax, cl diff --git a/tests/tests-base/test-00047/cmd b/tests/tests-base/test-00047/cmd new file mode 100644 index 0000000..0774999 --- /dev/null +++ b/tests/tests-base/test-00047/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f30f7edf diff --git a/tests/tests-base/test-00047/codes b/tests/tests-base/test-00047/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00047/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00047/retcode.reference b/tests/tests-base/test-00047/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00047/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00047/stderr.reference b/tests/tests-base/test-00047/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00047/stdout.reference b/tests/tests-base/test-00047/stdout.reference new file mode 100644 index 0000000..fa0bda8 --- /dev/null +++ b/tests/tests-base/test-00047/stdout.reference @@ -0,0 +1,11 @@ +F30F7EDF +ICLASS: MOVQ CATEGORY: DATAXFER EXTENSION: SSE2 IFORM: MOVQ_XMMdq_XMMq_0F7E ISA_SET: SSE2 +SHORT: movq xmm3, xmm7 +Encodable! 660FD6FB +Discrepenacy after re-encoding. dec_len= 4 [F30F7EDF] enc_olen= 4 [660FD6FB] for instruction: MOVQ MOVQ_XMMdq_XMMq_0F7E EASZ:2, EOSZ:2, FIRST_F2F3:3, HAS_MODRM:1, ILD_F3, LAST_F2F3:3, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:1, MODRM_BYTE:223, NOMINAL_OPCODE:126, NPREFIXES:1, OSZ, OUTREG:XMM7, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, REG:7, REG0:XMM3, REG1:XMM7, RM:3, SMODE:1, SRM:6, TZCNT +0 REG0/W/DQ/EXPLICIT/NT_LOOKUP_FN/XMM_R +1 REG1/R/Q/EXPLICIT/NT_LOOKUP_FN/XMM_B +YDIS: movq xmm3, xmm7 +vs Encode request: MOVQ EASZ:2, EOSZ:2, FIRST_F2F3:3, HAS_MODRM:1, ILD_F3, LAST_F2F3:3, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:1, MODRM_BYTE:223, NOMINAL_OPCODE:126, NPREFIXES:1, OSZ, OUTREG:XMM7, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, REG:7, REG0:XMM3, REG1:XMM7, RM:3, SMODE:1, SRM:6, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00048/cmd b/tests/tests-base/test-00048/cmd new file mode 100644 index 0000000..db558f5 --- /dev/null +++ b/tests/tests-base/test-00048/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 660fd6fb diff --git a/tests/tests-base/test-00048/codes b/tests/tests-base/test-00048/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00048/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00048/retcode.reference b/tests/tests-base/test-00048/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00048/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00048/stderr.reference b/tests/tests-base/test-00048/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00048/stdout.reference b/tests/tests-base/test-00048/stdout.reference new file mode 100644 index 0000000..b40696f --- /dev/null +++ b/tests/tests-base/test-00048/stdout.reference @@ -0,0 +1,5 @@ +660FD6FB +ICLASS: MOVQ CATEGORY: DATAXFER EXTENSION: SSE2 IFORM: MOVQ_XMMdq_XMMq_0FD6 ISA_SET: SSE2 +SHORT: movq xmm3, xmm7 +Encodable! 660FD6FB +Identical re-encoding diff --git a/tests/tests-base/test-00049/cmd b/tests/tests-base/test-00049/cmd new file mode 100644 index 0000000..5366c4c --- /dev/null +++ b/tests/tests-base/test-00049/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 66450f7e07 diff --git a/tests/tests-base/test-00049/codes b/tests/tests-base/test-00049/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00049/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00049/retcode.reference b/tests/tests-base/test-00049/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00049/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00049/stderr.reference b/tests/tests-base/test-00049/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00049/stdout.reference b/tests/tests-base/test-00049/stdout.reference new file mode 100644 index 0000000..b5aabc0 --- /dev/null +++ b/tests/tests-base/test-00049/stdout.reference @@ -0,0 +1,5 @@ +66450F7E07 +ICLASS: MOVD CATEGORY: DATAXFER EXTENSION: SSE2 IFORM: MOVD_MEMd_XMMd ISA_SET: SSE2 +SHORT: movd dword ptr [r15], xmm8 +Encodable! 66450F7E07 +Identical re-encoding diff --git a/tests/tests-base/test-00050/cmd b/tests/tests-base/test-00050/cmd new file mode 100644 index 0000000..7290a94 --- /dev/null +++ b/tests/tests-base/test-00050/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 664d0f7e07 diff --git a/tests/tests-base/test-00050/codes b/tests/tests-base/test-00050/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00050/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00050/retcode.reference b/tests/tests-base/test-00050/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00050/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00050/stderr.reference b/tests/tests-base/test-00050/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00050/stdout.reference b/tests/tests-base/test-00050/stdout.reference new file mode 100644 index 0000000..151dbf8 --- /dev/null +++ b/tests/tests-base/test-00050/stdout.reference @@ -0,0 +1,11 @@ +664D0F7E07 +ICLASS: MOVQ CATEGORY: DATAXFER EXTENSION: SSE2 IFORM: MOVQ_MEMq_XMMq_0F7E ISA_SET: SSE2 +SHORT: movq qword ptr [r15], xmm8 +Encodable! 664D0FD607 +Discrepenacy after re-encoding. dec_len= 5 [664D0F7E07] enc_olen= 5 [664D0FD607] for instruction: MOVQ MOVQ_MEMq_XMMq_0F7E EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:5, MEM_WIDTH:8, MEM0:qword ptr [R15], MODE:2, MODRM, MODRM_BYTE:7, NOMINAL_OPCODE:126, NPREFIXES:2, NREXES:1, OSZ, OUTREG:XMM8, P4, POS_NOMINAL_OPCODE:3, POS_MODRM:4, PREFIX66, REG0:XMM8, REXB, REXR, REXW, RM:7, SMODE:2, SRM:6, TZCNT, USING_DEFAULT_SEGMENT0 +0 MEM0/W/Q/EXPLICIT/IMM_CONST/1 +1 REG0/R/Q/EXPLICIT/NT_LOOKUP_FN/XMM_R +YDIS: movq qword ptr [r15], xmm8 +vs Encode request: MOVQ EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:5, MEM_WIDTH:8, MEM0:qword ptr [R15], MODE:2, MODRM, MODRM_BYTE:7, NOMINAL_OPCODE:126, NPREFIXES:2, NREXES:1, OSZ, OUTREG:XMM8, P4, POS_NOMINAL_OPCODE:3, POS_MODRM:4, PREFIX66, REG0:XMM8, REXB, REXR, REXW, RM:7, SMODE:2, SRM:6, TZCNT, USING_DEFAULT_SEGMENT0 +OPERAND ORDER: MEM0 REG0 + diff --git a/tests/tests-base/test-00051/cmd b/tests/tests-base/test-00051/cmd new file mode 100644 index 0000000..7b0bfd6 --- /dev/null +++ b/tests/tests-base/test-00051/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 ADD/64 RAX MEM8:RIP,-,-,11223344 diff --git a/tests/tests-base/test-00051/codes b/tests/tests-base/test-00051/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00051/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00051/retcode.reference b/tests/tests-base/test-00051/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00051/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00051/stderr.reference b/tests/tests-base/test-00051/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00051/stdout.reference b/tests/tests-base/test-00051/stdout.reference new file mode 100644 index 0000000..4cd956b --- /dev/null +++ b/tests/tests-base/test-00051/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +ADD DISP_WIDTH:32, EOSZ:3, MEM_WIDTH:8, MEM0:qword ptr [RIP+0x11223344], MODE:2, REG0:RAX, SMODE:2 +OPERAND ORDER: REG0 MEM0 + +Encodable! 48030544332211 diff --git a/tests/tests-base/test-00052/cmd b/tests/tests-base/test-00052/cmd new file mode 100644 index 0000000..35a5d4f --- /dev/null +++ b/tests/tests-base/test-00052/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 48030544332211 diff --git a/tests/tests-base/test-00052/codes b/tests/tests-base/test-00052/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00052/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00052/retcode.reference b/tests/tests-base/test-00052/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00052/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00052/stderr.reference b/tests/tests-base/test-00052/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00052/stdout.reference b/tests/tests-base/test-00052/stdout.reference new file mode 100644 index 0000000..6e70e72 --- /dev/null +++ b/tests/tests-base/test-00052/stdout.reference @@ -0,0 +1,5 @@ +48030544332211 +ICLASS: ADD CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_GPRv_MEMv ISA_SET: I86 +SHORT: add rax, qword ptr [rip+0x11223344] +Encodable! 48030544332211 +Identical re-encoding diff --git a/tests/tests-base/test-00053/cmd b/tests/tests-base/test-00053/cmd new file mode 100644 index 0000000..24bd3cc --- /dev/null +++ b/tests/tests-base/test-00053/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 6748030544332211 diff --git a/tests/tests-base/test-00053/codes b/tests/tests-base/test-00053/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00053/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00053/retcode.reference b/tests/tests-base/test-00053/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00053/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00053/stderr.reference b/tests/tests-base/test-00053/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00053/stdout.reference b/tests/tests-base/test-00053/stdout.reference new file mode 100644 index 0000000..8767edc --- /dev/null +++ b/tests/tests-base/test-00053/stdout.reference @@ -0,0 +1,5 @@ +6748030544332211 +ICLASS: ADD CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_GPRv_MEMv ISA_SET: I86 +SHORT: add rax, qword ptr [rip+0x11223344] +Encodable! 6748030544332211 +Identical re-encoding diff --git a/tests/tests-base/test-00054/cmd b/tests/tests-base/test-00054/cmd new file mode 100644 index 0000000..a58d6e4 --- /dev/null +++ b/tests/tests-base/test-00054/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 4f0f38f000 diff --git a/tests/tests-base/test-00054/codes b/tests/tests-base/test-00054/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00054/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00054/retcode.reference b/tests/tests-base/test-00054/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00054/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00054/stderr.reference b/tests/tests-base/test-00054/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00054/stdout.reference b/tests/tests-base/test-00054/stdout.reference new file mode 100644 index 0000000..025c33d --- /dev/null +++ b/tests/tests-base/test-00054/stdout.reference @@ -0,0 +1,3 @@ +4F0F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe r8, qword ptr [r8] diff --git a/tests/tests-base/test-00055/cmd b/tests/tests-base/test-00055/cmd new file mode 100644 index 0000000..44c1e4f --- /dev/null +++ b/tests/tests-base/test-00055/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 664f0f38f000 diff --git a/tests/tests-base/test-00055/codes b/tests/tests-base/test-00055/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00055/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00055/retcode.reference b/tests/tests-base/test-00055/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00055/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00055/stderr.reference b/tests/tests-base/test-00055/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00055/stdout.reference b/tests/tests-base/test-00055/stdout.reference new file mode 100644 index 0000000..d9e714d --- /dev/null +++ b/tests/tests-base/test-00055/stdout.reference @@ -0,0 +1,3 @@ +664F0F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe r8, qword ptr [r8] diff --git a/tests/tests-base/test-00056/cmd b/tests/tests-base/test-00056/cmd new file mode 100644 index 0000000..562f703 --- /dev/null +++ b/tests/tests-base/test-00056/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 660f38f000 diff --git a/tests/tests-base/test-00056/codes b/tests/tests-base/test-00056/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00056/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00056/retcode.reference b/tests/tests-base/test-00056/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00056/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00056/stderr.reference b/tests/tests-base/test-00056/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00056/stdout.reference b/tests/tests-base/test-00056/stdout.reference new file mode 100644 index 0000000..fb09c51 --- /dev/null +++ b/tests/tests-base/test-00056/stdout.reference @@ -0,0 +1,3 @@ +660F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe ax, word ptr [rax] diff --git a/tests/tests-base/test-00057/cmd b/tests/tests-base/test-00057/cmd new file mode 100644 index 0000000..dbef7fd --- /dev/null +++ b/tests/tests-base/test-00057/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 0f38f000 diff --git a/tests/tests-base/test-00057/codes b/tests/tests-base/test-00057/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00057/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00057/retcode.reference b/tests/tests-base/test-00057/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00057/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00057/stderr.reference b/tests/tests-base/test-00057/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00057/stdout.reference b/tests/tests-base/test-00057/stdout.reference new file mode 100644 index 0000000..9a084b1 --- /dev/null +++ b/tests/tests-base/test-00057/stdout.reference @@ -0,0 +1,3 @@ +0F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe eax, dword ptr [rax] diff --git a/tests/tests-base/test-00058/cmd b/tests/tests-base/test-00058/cmd new file mode 100644 index 0000000..a8b6771 --- /dev/null +++ b/tests/tests-base/test-00058/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 0f38f000 diff --git a/tests/tests-base/test-00058/codes b/tests/tests-base/test-00058/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00058/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00058/retcode.reference b/tests/tests-base/test-00058/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00058/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00058/stderr.reference b/tests/tests-base/test-00058/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00058/stdout.reference b/tests/tests-base/test-00058/stdout.reference new file mode 100644 index 0000000..e249e6e --- /dev/null +++ b/tests/tests-base/test-00058/stdout.reference @@ -0,0 +1,3 @@ +0F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe eax, dword ptr [eax] diff --git a/tests/tests-base/test-00059/cmd b/tests/tests-base/test-00059/cmd new file mode 100644 index 0000000..e52fceb --- /dev/null +++ b/tests/tests-base/test-00059/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 660f38f000 diff --git a/tests/tests-base/test-00059/codes b/tests/tests-base/test-00059/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00059/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00059/retcode.reference b/tests/tests-base/test-00059/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00059/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00059/stderr.reference b/tests/tests-base/test-00059/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00059/stdout.reference b/tests/tests-base/test-00059/stdout.reference new file mode 100644 index 0000000..4a34b24 --- /dev/null +++ b/tests/tests-base/test-00059/stdout.reference @@ -0,0 +1,3 @@ +660F38F000 +ICLASS: MOVBE CATEGORY: DATAXFER EXTENSION: MOVBE IFORM: MOVBE_GPRv_MEMv ISA_SET: MOVBE +SHORT: movbe ax, word ptr [eax] diff --git a/tests/tests-base/test-00060/cmd b/tests/tests-base/test-00060/cmd new file mode 100644 index 0000000..403c6b7 --- /dev/null +++ b/tests/tests-base/test-00060/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 678b46ff diff --git a/tests/tests-base/test-00060/codes b/tests/tests-base/test-00060/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00060/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00060/retcode.reference b/tests/tests-base/test-00060/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00060/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00060/stderr.reference b/tests/tests-base/test-00060/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00060/stdout.reference b/tests/tests-base/test-00060/stdout.reference new file mode 100644 index 0000000..79a16a8 --- /dev/null +++ b/tests/tests-base/test-00060/stdout.reference @@ -0,0 +1,5 @@ +678B46FF +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_GPRv_MEMv ISA_SET: I86 +SHORT: mov eax, dword ptr [bp-0x1] +Encodable! 678B46FF +Identical re-encoding diff --git a/tests/tests-base/test-00061/cmd b/tests/tests-base/test-00061/cmd new file mode 100644 index 0000000..3a4b5f6 --- /dev/null +++ b/tests/tests-base/test-00061/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 67648b46ff diff --git a/tests/tests-base/test-00061/codes b/tests/tests-base/test-00061/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00061/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00061/retcode.reference b/tests/tests-base/test-00061/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00061/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00061/stderr.reference b/tests/tests-base/test-00061/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00061/stdout.reference b/tests/tests-base/test-00061/stdout.reference new file mode 100644 index 0000000..ff06fba --- /dev/null +++ b/tests/tests-base/test-00061/stdout.reference @@ -0,0 +1,5 @@ +67648B46FF +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_GPRv_MEMv ISA_SET: I86 +SHORT: mov eax, dword ptr fs:[bp-0x1] +Encodable! 67648B46FF +Identical re-encoding diff --git a/tests/tests-base/test-00062/cmd b/tests/tests-base/test-00062/cmd new file mode 100644 index 0000000..f66c3d0 --- /dev/null +++ b/tests/tests-base/test-00062/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bp,di,1,ff diff --git a/tests/tests-base/test-00062/codes b/tests/tests-base/test-00062/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00062/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00062/retcode.reference b/tests/tests-base/test-00062/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00062/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00062/stderr.reference b/tests/tests-base/test-00062/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00062/stdout.reference b/tests/tests-base/test-00062/stdout.reference new file mode 100644 index 0000000..32d4a6f --- /dev/null +++ b/tests/tests-base/test-00062/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:8, EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BP+DI*1-0x1], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B43FF diff --git a/tests/tests-base/test-00063/cmd b/tests/tests-base/test-00063/cmd new file mode 100644 index 0000000..b6af243 --- /dev/null +++ b/tests/tests-base/test-00063/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bp,di,1 diff --git a/tests/tests-base/test-00063/codes b/tests/tests-base/test-00063/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00063/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00063/retcode.reference b/tests/tests-base/test-00063/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00063/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00063/stderr.reference b/tests/tests-base/test-00063/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00063/stdout.reference b/tests/tests-base/test-00063/stdout.reference new file mode 100644 index 0000000..b14269b --- /dev/null +++ b/tests/tests-base/test-00063/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BP+DI*1], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B03 diff --git a/tests/tests-base/test-00064/cmd b/tests/tests-base/test-00064/cmd new file mode 100644 index 0000000..639c127 --- /dev/null +++ b/tests/tests-base/test-00064/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bp,di,-,ffff diff --git a/tests/tests-base/test-00064/codes b/tests/tests-base/test-00064/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00064/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00064/retcode.reference b/tests/tests-base/test-00064/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00064/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00064/stderr.reference b/tests/tests-base/test-00064/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00064/stdout.reference b/tests/tests-base/test-00064/stdout.reference new file mode 100644 index 0000000..37dd58d --- /dev/null +++ b/tests/tests-base/test-00064/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:16, EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BP+DI*1-0x1], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B83FFFF diff --git a/tests/tests-base/test-00065/cmd b/tests/tests-base/test-00065/cmd new file mode 100644 index 0000000..90de0d0 --- /dev/null +++ b/tests/tests-base/test-00065/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bp diff --git a/tests/tests-base/test-00065/codes b/tests/tests-base/test-00065/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00065/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00065/retcode.reference b/tests/tests-base/test-00065/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00065/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00065/stderr.reference b/tests/tests-base/test-00065/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00065/stdout.reference b/tests/tests-base/test-00065/stdout.reference new file mode 100644 index 0000000..b8c3b83 --- /dev/null +++ b/tests/tests-base/test-00065/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BP], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B4600 diff --git a/tests/tests-base/test-00066/cmd b/tests/tests-base/test-00066/cmd new file mode 100644 index 0000000..98b7e40 --- /dev/null +++ b/tests/tests-base/test-00066/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:di diff --git a/tests/tests-base/test-00066/codes b/tests/tests-base/test-00066/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00066/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00066/retcode.reference b/tests/tests-base/test-00066/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00066/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00066/stderr.reference b/tests/tests-base/test-00066/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00066/stdout.reference b/tests/tests-base/test-00066/stdout.reference new file mode 100644 index 0000000..ffe7bc5 --- /dev/null +++ b/tests/tests-base/test-00066/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [DI], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B05 diff --git a/tests/tests-base/test-00067/cmd b/tests/tests-base/test-00067/cmd new file mode 100644 index 0000000..8eab321 --- /dev/null +++ b/tests/tests-base/test-00067/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bx,-,-,ffff diff --git a/tests/tests-base/test-00067/codes b/tests/tests-base/test-00067/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00067/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00067/retcode.reference b/tests/tests-base/test-00067/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00067/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00067/stderr.reference b/tests/tests-base/test-00067/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00067/stdout.reference b/tests/tests-base/test-00067/stdout.reference new file mode 100644 index 0000000..4de0864 --- /dev/null +++ b/tests/tests-base/test-00067/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:16, EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BX-0x1], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B87FFFF diff --git a/tests/tests-base/test-00068/cmd b/tests/tests-base/test-00068/cmd new file mode 100644 index 0000000..64af0a7 --- /dev/null +++ b/tests/tests-base/test-00068/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bx,-,-,ff diff --git a/tests/tests-base/test-00068/codes b/tests/tests-base/test-00068/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00068/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00068/retcode.reference b/tests/tests-base/test-00068/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00068/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00068/stderr.reference b/tests/tests-base/test-00068/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00068/stdout.reference b/tests/tests-base/test-00068/stdout.reference new file mode 100644 index 0000000..8183935 --- /dev/null +++ b/tests/tests-base/test-00068/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:8, EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BX-0x1], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B47FF diff --git a/tests/tests-base/test-00069/cmd b/tests/tests-base/test-00069/cmd new file mode 100644 index 0000000..4c84f59 --- /dev/null +++ b/tests/tests-base/test-00069/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:bx diff --git a/tests/tests-base/test-00069/codes b/tests/tests-base/test-00069/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00069/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00069/retcode.reference b/tests/tests-base/test-00069/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00069/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00069/stderr.reference b/tests/tests-base/test-00069/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00069/stdout.reference b/tests/tests-base/test-00069/stdout.reference new file mode 100644 index 0000000..e39739c --- /dev/null +++ b/tests/tests-base/test-00069/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, MEM_WIDTH:4, MEM0:dword ptr [BX], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 678B07 diff --git a/tests/tests-base/test-00070/cmd b/tests/tests-base/test-00070/cmd new file mode 100644 index 0000000..570ba03 --- /dev/null +++ b/tests/tests-base/test-00070/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov eax MEM4:fs:bx diff --git a/tests/tests-base/test-00070/codes b/tests/tests-base/test-00070/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00070/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00070/retcode.reference b/tests/tests-base/test-00070/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00070/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00070/stderr.reference b/tests/tests-base/test-00070/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00070/stdout.reference b/tests/tests-base/test-00070/stdout.reference new file mode 100644 index 0000000..5245630 --- /dev/null +++ b/tests/tests-base/test-00070/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, MEM_WIDTH:4, MEM0:dword ptr FS[BX], MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 67648B07 diff --git a/tests/tests-base/test-00071/cmd b/tests/tests-base/test-00071/cmd new file mode 100644 index 0000000..5b7e269 --- /dev/null +++ b/tests/tests-base/test-00071/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 mov/16 ax MEM2:fs:bx diff --git a/tests/tests-base/test-00071/codes b/tests/tests-base/test-00071/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00071/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00071/retcode.reference b/tests/tests-base/test-00071/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00071/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00071/stderr.reference b/tests/tests-base/test-00071/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00071/stdout.reference b/tests/tests-base/test-00071/stdout.reference new file mode 100644 index 0000000..180ee25 --- /dev/null +++ b/tests/tests-base/test-00071/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV EASZ:1, EOSZ:1, MEM_WIDTH:2, MEM0:word ptr FS[BX], MODE:1, REG0:AX, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 6667648B07 diff --git a/tests/tests-base/test-00072/cmd b/tests/tests-base/test-00072/cmd new file mode 100644 index 0000000..d4b6f2b --- /dev/null +++ b/tests/tests-base/test-00072/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 663e0fc70e diff --git a/tests/tests-base/test-00072/codes b/tests/tests-base/test-00072/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00072/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00072/retcode.reference b/tests/tests-base/test-00072/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00072/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00072/stderr.reference b/tests/tests-base/test-00072/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00072/stdout.reference b/tests/tests-base/test-00072/stdout.reference new file mode 100644 index 0000000..800ca6b --- /dev/null +++ b/tests/tests-base/test-00072/stdout.reference @@ -0,0 +1,3 @@ +663E0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [esi] diff --git a/tests/tests-base/test-00073/cmd b/tests/tests-base/test-00073/cmd new file mode 100644 index 0000000..d4b6f2b --- /dev/null +++ b/tests/tests-base/test-00073/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 663e0fc70e diff --git a/tests/tests-base/test-00073/codes b/tests/tests-base/test-00073/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00073/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00073/retcode.reference b/tests/tests-base/test-00073/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00073/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00073/stderr.reference b/tests/tests-base/test-00073/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00073/stdout.reference b/tests/tests-base/test-00073/stdout.reference new file mode 100644 index 0000000..800ca6b --- /dev/null +++ b/tests/tests-base/test-00073/stdout.reference @@ -0,0 +1,3 @@ +663E0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [esi] diff --git a/tests/tests-base/test-00074/cmd b/tests/tests-base/test-00074/cmd new file mode 100644 index 0000000..c540b9a --- /dev/null +++ b/tests/tests-base/test-00074/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 3e0fc70e diff --git a/tests/tests-base/test-00074/codes b/tests/tests-base/test-00074/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00074/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00074/retcode.reference b/tests/tests-base/test-00074/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00074/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00074/stderr.reference b/tests/tests-base/test-00074/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00074/stdout.reference b/tests/tests-base/test-00074/stdout.reference new file mode 100644 index 0000000..e795ef9 --- /dev/null +++ b/tests/tests-base/test-00074/stdout.reference @@ -0,0 +1,3 @@ +3E0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [rsi] diff --git a/tests/tests-base/test-00075/cmd b/tests/tests-base/test-00075/cmd new file mode 100644 index 0000000..647c5b6 --- /dev/null +++ b/tests/tests-base/test-00075/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 483e0fc70e diff --git a/tests/tests-base/test-00075/codes b/tests/tests-base/test-00075/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00075/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00075/retcode.reference b/tests/tests-base/test-00075/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00075/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00075/stderr.reference b/tests/tests-base/test-00075/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00075/stdout.reference b/tests/tests-base/test-00075/stdout.reference new file mode 100644 index 0000000..8060770 --- /dev/null +++ b/tests/tests-base/test-00075/stdout.reference @@ -0,0 +1,3 @@ +483E0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [rsi] diff --git a/tests/tests-base/test-00076/cmd b/tests/tests-base/test-00076/cmd new file mode 100644 index 0000000..63faa1f --- /dev/null +++ b/tests/tests-base/test-00076/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 480fc70e diff --git a/tests/tests-base/test-00076/codes b/tests/tests-base/test-00076/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00076/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00076/retcode.reference b/tests/tests-base/test-00076/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00076/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00076/stderr.reference b/tests/tests-base/test-00076/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00076/stdout.reference b/tests/tests-base/test-00076/stdout.reference new file mode 100644 index 0000000..faf61ba --- /dev/null +++ b/tests/tests-base/test-00076/stdout.reference @@ -0,0 +1,3 @@ +480FC70E +ICLASS: CMPXCHG16B CATEGORY: SEMAPHORE EXTENSION: LONGMODE IFORM: CMPXCHG16B_MEMdq ISA_SET: CMPXCHG16B +SHORT: cmpxchg16b xmmword ptr [rsi] diff --git a/tests/tests-base/test-00077/cmd b/tests/tests-base/test-00077/cmd new file mode 100644 index 0000000..de3d3a0 --- /dev/null +++ b/tests/tests-base/test-00077/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 3e480fc70e diff --git a/tests/tests-base/test-00077/codes b/tests/tests-base/test-00077/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00077/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00077/retcode.reference b/tests/tests-base/test-00077/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00077/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00077/stderr.reference b/tests/tests-base/test-00077/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00077/stdout.reference b/tests/tests-base/test-00077/stdout.reference new file mode 100644 index 0000000..5c5a321 --- /dev/null +++ b/tests/tests-base/test-00077/stdout.reference @@ -0,0 +1,3 @@ +3E480FC70E +ICLASS: CMPXCHG16B CATEGORY: SEMAPHORE EXTENSION: LONGMODE IFORM: CMPXCHG16B_MEMdq ISA_SET: CMPXCHG16B +SHORT: cmpxchg16b xmmword ptr [rsi] diff --git a/tests/tests-base/test-00078/cmd b/tests/tests-base/test-00078/cmd new file mode 100644 index 0000000..e2a5911 --- /dev/null +++ b/tests/tests-base/test-00078/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 66e480fc70e diff --git a/tests/tests-base/test-00078/codes b/tests/tests-base/test-00078/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00078/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00078/retcode.reference b/tests/tests-base/test-00078/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00078/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00078/stderr.reference b/tests/tests-base/test-00078/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00078/stdout.reference b/tests/tests-base/test-00078/stdout.reference new file mode 100644 index 0000000..b950149 --- /dev/null +++ b/tests/tests-base/test-00078/stdout.reference @@ -0,0 +1 @@ +[XED CLIENT ERROR] test string was not an even number of nibbles diff --git a/tests/tests-base/test-00079/cmd b/tests/tests-base/test-00079/cmd new file mode 100644 index 0000000..d5c0d94 --- /dev/null +++ b/tests/tests-base/test-00079/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 0fc70e diff --git a/tests/tests-base/test-00079/codes b/tests/tests-base/test-00079/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00079/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00079/retcode.reference b/tests/tests-base/test-00079/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00079/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00079/stderr.reference b/tests/tests-base/test-00079/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00079/stdout.reference b/tests/tests-base/test-00079/stdout.reference new file mode 100644 index 0000000..3ef82ac --- /dev/null +++ b/tests/tests-base/test-00079/stdout.reference @@ -0,0 +1,3 @@ +0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [rsi] diff --git a/tests/tests-base/test-00080/cmd b/tests/tests-base/test-00080/cmd new file mode 100644 index 0000000..8d183f8 --- /dev/null +++ b/tests/tests-base/test-00080/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 660fc70e diff --git a/tests/tests-base/test-00080/codes b/tests/tests-base/test-00080/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00080/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00080/retcode.reference b/tests/tests-base/test-00080/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00080/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00080/stderr.reference b/tests/tests-base/test-00080/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00080/stdout.reference b/tests/tests-base/test-00080/stdout.reference new file mode 100644 index 0000000..b9d3b24 --- /dev/null +++ b/tests/tests-base/test-00080/stdout.reference @@ -0,0 +1,3 @@ +660FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [rsi] diff --git a/tests/tests-base/test-00081/cmd b/tests/tests-base/test-00081/cmd new file mode 100644 index 0000000..cb1e358 --- /dev/null +++ b/tests/tests-base/test-00081/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -d 660fc70e diff --git a/tests/tests-base/test-00081/codes b/tests/tests-base/test-00081/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00081/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00081/retcode.reference b/tests/tests-base/test-00081/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00081/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00081/stderr.reference b/tests/tests-base/test-00081/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00081/stdout.reference b/tests/tests-base/test-00081/stdout.reference new file mode 100644 index 0000000..5c6db86 --- /dev/null +++ b/tests/tests-base/test-00081/stdout.reference @@ -0,0 +1,2 @@ +660FC70E +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [660FC70E0000000000000000000000] diff --git a/tests/tests-base/test-00082/cmd b/tests/tests-base/test-00082/cmd new file mode 100644 index 0000000..9fc025d --- /dev/null +++ b/tests/tests-base/test-00082/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -d 0fc70e00 diff --git a/tests/tests-base/test-00082/codes b/tests/tests-base/test-00082/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00082/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00082/retcode.reference b/tests/tests-base/test-00082/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00082/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00082/stderr.reference b/tests/tests-base/test-00082/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00082/stdout.reference b/tests/tests-base/test-00082/stdout.reference new file mode 100644 index 0000000..9494273 --- /dev/null +++ b/tests/tests-base/test-00082/stdout.reference @@ -0,0 +1,2 @@ +0FC70E00 +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [0FC70E000000000000000000000000] diff --git a/tests/tests-base/test-00083/cmd b/tests/tests-base/test-00083/cmd new file mode 100644 index 0000000..35a1bde --- /dev/null +++ b/tests/tests-base/test-00083/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -d 0fc70e0000 diff --git a/tests/tests-base/test-00083/codes b/tests/tests-base/test-00083/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00083/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00083/retcode.reference b/tests/tests-base/test-00083/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00083/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00083/stderr.reference b/tests/tests-base/test-00083/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00083/stdout.reference b/tests/tests-base/test-00083/stdout.reference new file mode 100644 index 0000000..0350582 --- /dev/null +++ b/tests/tests-base/test-00083/stdout.reference @@ -0,0 +1,3 @@ +0FC70E0000 +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [0x0] diff --git a/tests/tests-base/test-00084/cmd b/tests/tests-base/test-00084/cmd new file mode 100644 index 0000000..08b3e8c --- /dev/null +++ b/tests/tests-base/test-00084/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -d 0fc70e1111 diff --git a/tests/tests-base/test-00084/codes b/tests/tests-base/test-00084/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00084/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00084/retcode.reference b/tests/tests-base/test-00084/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00084/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00084/stderr.reference b/tests/tests-base/test-00084/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00084/stdout.reference b/tests/tests-base/test-00084/stdout.reference new file mode 100644 index 0000000..6800b0e --- /dev/null +++ b/tests/tests-base/test-00084/stdout.reference @@ -0,0 +1,3 @@ +0FC70E1111 +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [0x1111] diff --git a/tests/tests-base/test-00085/cmd b/tests/tests-base/test-00085/cmd new file mode 100644 index 0000000..63ffc48 --- /dev/null +++ b/tests/tests-base/test-00085/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 cmpxchg8b mem8:esi diff --git a/tests/tests-base/test-00085/codes b/tests/tests-base/test-00085/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00085/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00085/retcode.reference b/tests/tests-base/test-00085/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00085/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00085/stderr.reference b/tests/tests-base/test-00085/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00085/stdout.reference b/tests/tests-base/test-00085/stdout.reference new file mode 100644 index 0000000..e516f1b --- /dev/null +++ b/tests/tests-base/test-00085/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +CMPXCHG8B EASZ:2, MEM_WIDTH:8, MEM0:qword ptr [ESI], MODE:1, SMODE:1 +OPERAND ORDER: MEM0 + +Encodable! 0FC70E diff --git a/tests/tests-base/test-00086/cmd b/tests/tests-base/test-00086/cmd new file mode 100644 index 0000000..51ec4e4 --- /dev/null +++ b/tests/tests-base/test-00086/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 0fc70e diff --git a/tests/tests-base/test-00086/codes b/tests/tests-base/test-00086/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00086/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00086/retcode.reference b/tests/tests-base/test-00086/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00086/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00086/stderr.reference b/tests/tests-base/test-00086/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00086/stdout.reference b/tests/tests-base/test-00086/stdout.reference new file mode 100644 index 0000000..82f4a8b --- /dev/null +++ b/tests/tests-base/test-00086/stdout.reference @@ -0,0 +1,5 @@ +0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [esi] +Encodable! 0FC70E +Identical re-encoding diff --git a/tests/tests-base/test-00087/cmd b/tests/tests-base/test-00087/cmd new file mode 100644 index 0000000..2b53f3e --- /dev/null +++ b/tests/tests-base/test-00087/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0fc70e diff --git a/tests/tests-base/test-00087/codes b/tests/tests-base/test-00087/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00087/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00087/retcode.reference b/tests/tests-base/test-00087/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00087/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00087/stderr.reference b/tests/tests-base/test-00087/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00087/stdout.reference b/tests/tests-base/test-00087/stdout.reference new file mode 100644 index 0000000..a541aaf --- /dev/null +++ b/tests/tests-base/test-00087/stdout.reference @@ -0,0 +1,5 @@ +0FC70E +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [rsi] +Encodable! 0FC70E +Identical re-encoding diff --git a/tests/tests-base/test-00088/cmd b/tests/tests-base/test-00088/cmd new file mode 100644 index 0000000..359e20f --- /dev/null +++ b/tests/tests-base/test-00088/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 480fc70e diff --git a/tests/tests-base/test-00088/codes b/tests/tests-base/test-00088/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00088/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00088/retcode.reference b/tests/tests-base/test-00088/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00088/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00088/stderr.reference b/tests/tests-base/test-00088/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00088/stdout.reference b/tests/tests-base/test-00088/stdout.reference new file mode 100644 index 0000000..add5d01 --- /dev/null +++ b/tests/tests-base/test-00088/stdout.reference @@ -0,0 +1,5 @@ +480FC70E +ICLASS: CMPXCHG16B CATEGORY: SEMAPHORE EXTENSION: LONGMODE IFORM: CMPXCHG16B_MEMdq ISA_SET: CMPXCHG16B +SHORT: cmpxchg16b xmmword ptr [rsi] +Encodable! 480FC70E +Identical re-encoding diff --git a/tests/tests-base/test-00089/cmd b/tests/tests-base/test-00089/cmd new file mode 100644 index 0000000..af5870d --- /dev/null +++ b/tests/tests-base/test-00089/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 660fc70e111111 diff --git a/tests/tests-base/test-00089/codes b/tests/tests-base/test-00089/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00089/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00089/retcode.reference b/tests/tests-base/test-00089/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00089/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00089/stderr.reference b/tests/tests-base/test-00089/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00089/stdout.reference b/tests/tests-base/test-00089/stdout.reference new file mode 100644 index 0000000..2fc95a1 --- /dev/null +++ b/tests/tests-base/test-00089/stdout.reference @@ -0,0 +1,15 @@ +660FC70E111111 +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [0x1111] +Encodable! 0FC70E1111 +Discrepenacy after re-encoding. dec_len= 6 [660FC70E1111] enc_olen= 5 [0FC70E1111] for instruction: CMPXCHG8B CMPXCHG8B_MEMq DF32, DISP_WIDTH:16, EASZ:1, EOSZ:2, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:7, MEM_WIDTH:8, MEM0:qword ptr DS[0x1111], MODRM, MODRM_BYTE:14, NEED_MEMDISP:16, NOMINAL_OPCODE:199, NPREFIXES:1, OUTREG:FLAGS, P4, POS_DISP:4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG:1, REG0:EDX, REG1:EAX, REG2:ECX, REG3:EBX, REG4:FLAGS, RM:6, SMODE:1, SRM:7, TZCNT, USING_DEFAULT_SEGMENT0 +0 MEM0/RCW/Q/EXPLICIT/IMM_CONST/1 +1 REG0/RCW/D/SUPPRESSED/REG/EDX +2 REG1/RCW/D/SUPPRESSED/REG/EAX +3 REG2/R/D/SUPPRESSED/REG/ECX +4 REG3/R/D/SUPPRESSED/REG/EBX +5 REG4/W/Y/SUPPRESSED/NT_LOOKUP_FN/RFLAGS +YDIS: cmpxchg8b qword ptr [0x1111] +vs Encode request: CMPXCHG8B DF32, DISP_WIDTH:16, EASZ:1, EOSZ:2, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:7, MEM_WIDTH:8, MEM0:qword ptr DS[0x1111], MODRM, MODRM_BYTE:14, NEED_MEMDISP:16, NOMINAL_OPCODE:199, NPREFIXES:1, OUTREG:FLAGS, P4, POS_DISP:4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG:1, REG0:EDX, REG1:EAX, REG2:ECX, REG3:EBX, REG4:FLAGS, RM:6, SMODE:1, SRM:7, TZCNT, USING_DEFAULT_SEGMENT0 +OPERAND ORDER: MEM0 + diff --git a/tests/tests-base/test-00090/cmd b/tests/tests-base/test-00090/cmd new file mode 100644 index 0000000..f24cac7 --- /dev/null +++ b/tests/tests-base/test-00090/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 0fc70e111111 diff --git a/tests/tests-base/test-00090/codes b/tests/tests-base/test-00090/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00090/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00090/retcode.reference b/tests/tests-base/test-00090/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00090/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00090/stderr.reference b/tests/tests-base/test-00090/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00090/stdout.reference b/tests/tests-base/test-00090/stdout.reference new file mode 100644 index 0000000..e24de40 --- /dev/null +++ b/tests/tests-base/test-00090/stdout.reference @@ -0,0 +1,5 @@ +0FC70E111111 +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [0x1111] +Encodable! 0FC70E1111 +Identical re-encoding diff --git a/tests/tests-base/test-00091/cmd b/tests/tests-base/test-00091/cmd new file mode 100644 index 0000000..f3b8f43 --- /dev/null +++ b/tests/tests-base/test-00091/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f3c3 diff --git a/tests/tests-base/test-00091/codes b/tests/tests-base/test-00091/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00091/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00091/retcode.reference b/tests/tests-base/test-00091/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00091/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00091/stderr.reference b/tests/tests-base/test-00091/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00091/stdout.reference b/tests/tests-base/test-00091/stdout.reference new file mode 100644 index 0000000..2f6d902 --- /dev/null +++ b/tests/tests-base/test-00091/stdout.reference @@ -0,0 +1,5 @@ +F3C3 +ICLASS: RET_NEAR CATEGORY: RET EXTENSION: BASE IFORM: RET_NEAR ISA_SET: I86 +SHORT: ret +Encodable! F3C3 +Identical re-encoding diff --git a/tests/tests-base/test-00092/cmd b/tests/tests-base/test-00092/cmd new file mode 100644 index 0000000..5445261 --- /dev/null +++ b/tests/tests-base/test-00092/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 66 E8 11 22 33 44 diff --git a/tests/tests-base/test-00092/codes b/tests/tests-base/test-00092/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00092/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00092/retcode.reference b/tests/tests-base/test-00092/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00092/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00092/stderr.reference b/tests/tests-base/test-00092/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00092/stdout.reference b/tests/tests-base/test-00092/stdout.reference new file mode 100644 index 0000000..9d322aa --- /dev/null +++ b/tests/tests-base/test-00092/stdout.reference @@ -0,0 +1,14 @@ +66E811223344 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRd ISA_SET: I86 +SHORT: call 0x44332217 +Encodable! E811223344 +Discrepenacy after re-encoding. dec_len= 6 [66E811223344] enc_olen= 5 [E811223344] for instruction: CALL_NEAR CALL_NEAR_RELBRd BRDISP_WIDTH:32, DF64, DISP_WIDTH:32, EASZ:3, EOSZ:3, LZCNT, MAX_BYTES:6, MEM_WIDTH:8, MEM0:qword ptr [RSP], MODE:2, NOMINAL_OPCODE:232, NPREFIXES:1, P4, POS_DISP:2, POS_NOMINAL_OPCODE:1, PREFIX66, REG0:STACKPUSH, REG1:RIP, RELBR:0x44332211, SMODE:2, TZCNT, USING_DEFAULT_SEGMENT0 +0 RELBR/R/D/EXPLICIT/IMM_CONST/1 +1 REG0/W/SPW/SUPPRESSED/REG/STACKPUSH +2 REG1/RW/V/SUPPRESSED/NT_LOOKUP_FN/RIP +3 MEM0/W/SPW/SUPPRESSED/IMM_CONST/1 +4 BASE0/RW/SSZ/SUPPRESSED/NT_LOOKUP_FN/SRSP +YDIS: call 0x44332217 +vs Encode request: CALL_NEAR BRDISP_WIDTH:32, DF64, DISP_WIDTH:32, EASZ:3, EOSZ:3, LZCNT, MAX_BYTES:6, MEM_WIDTH:8, MEM0:qword ptr [RSP], MODE:2, NOMINAL_OPCODE:232, NPREFIXES:1, P4, POS_DISP:2, POS_NOMINAL_OPCODE:1, PREFIX66, REG0:STACKPUSH, REG1:RIP, RELBR:0x44332211, SMODE:2, TZCNT, USING_DEFAULT_SEGMENT0 +OPERAND ORDER: RELBR + diff --git a/tests/tests-base/test-00093/cmd b/tests/tests-base/test-00093/cmd new file mode 100644 index 0000000..1352199 --- /dev/null +++ b/tests/tests-base/test-00093/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de E8 11 22 33 44 diff --git a/tests/tests-base/test-00093/codes b/tests/tests-base/test-00093/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00093/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00093/retcode.reference b/tests/tests-base/test-00093/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00093/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00093/stderr.reference b/tests/tests-base/test-00093/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00093/stdout.reference b/tests/tests-base/test-00093/stdout.reference new file mode 100644 index 0000000..bcf0791 --- /dev/null +++ b/tests/tests-base/test-00093/stdout.reference @@ -0,0 +1,5 @@ +E811223344 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRd ISA_SET: I86 +SHORT: call 0x44332216 +Encodable! E811223344 +Identical re-encoding diff --git a/tests/tests-base/test-00094/cmd b/tests/tests-base/test-00094/cmd new file mode 100644 index 0000000..ae10b87 --- /dev/null +++ b/tests/tests-base/test-00094/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 67 E8 11 22 33 44 diff --git a/tests/tests-base/test-00094/codes b/tests/tests-base/test-00094/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00094/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00094/retcode.reference b/tests/tests-base/test-00094/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00094/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00094/stderr.reference b/tests/tests-base/test-00094/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00094/stdout.reference b/tests/tests-base/test-00094/stdout.reference new file mode 100644 index 0000000..3243b35 --- /dev/null +++ b/tests/tests-base/test-00094/stdout.reference @@ -0,0 +1,5 @@ +67E811223344 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRd ISA_SET: I86 +SHORT: addr32 call 0x44332217 +Encodable! 67E811223344 +Identical re-encoding diff --git a/tests/tests-base/test-00095/cmd b/tests/tests-base/test-00095/cmd new file mode 100644 index 0000000..19fbbe4 --- /dev/null +++ b/tests/tests-base/test-00095/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de E8 11 22 33 44 diff --git a/tests/tests-base/test-00095/codes b/tests/tests-base/test-00095/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00095/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00095/retcode.reference b/tests/tests-base/test-00095/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00095/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00095/stderr.reference b/tests/tests-base/test-00095/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00095/stdout.reference b/tests/tests-base/test-00095/stdout.reference new file mode 100644 index 0000000..565b3d3 --- /dev/null +++ b/tests/tests-base/test-00095/stdout.reference @@ -0,0 +1,5 @@ +E811223344 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRz ISA_SET: I86 +SHORT: call 0x44332216 +Encodable! E811223344 +Identical re-encoding diff --git a/tests/tests-base/test-00096/cmd b/tests/tests-base/test-00096/cmd new file mode 100644 index 0000000..f7e1290 --- /dev/null +++ b/tests/tests-base/test-00096/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 66 E8 11 22 diff --git a/tests/tests-base/test-00096/codes b/tests/tests-base/test-00096/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00096/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00096/retcode.reference b/tests/tests-base/test-00096/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00096/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00096/stderr.reference b/tests/tests-base/test-00096/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00096/stdout.reference b/tests/tests-base/test-00096/stdout.reference new file mode 100644 index 0000000..45fcff6 --- /dev/null +++ b/tests/tests-base/test-00096/stdout.reference @@ -0,0 +1,5 @@ +66E81122 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRz ISA_SET: I86 +SHORT: call 0x2215 +Encodable! 66E81122 +Identical re-encoding diff --git a/tests/tests-base/test-00097/cmd b/tests/tests-base/test-00097/cmd new file mode 100644 index 0000000..4179d4f --- /dev/null +++ b/tests/tests-base/test-00097/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 66 E8 11 22 33 44 diff --git a/tests/tests-base/test-00097/codes b/tests/tests-base/test-00097/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00097/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00097/retcode.reference b/tests/tests-base/test-00097/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00097/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00097/stderr.reference b/tests/tests-base/test-00097/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00097/stdout.reference b/tests/tests-base/test-00097/stdout.reference new file mode 100644 index 0000000..6f62a88 --- /dev/null +++ b/tests/tests-base/test-00097/stdout.reference @@ -0,0 +1,5 @@ +66E811223344 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRz ISA_SET: I86 +SHORT: call 0x44332217 +Encodable! 66E811223344 +Identical re-encoding diff --git a/tests/tests-base/test-00098/cmd b/tests/tests-base/test-00098/cmd new file mode 100644 index 0000000..66ee4cf --- /dev/null +++ b/tests/tests-base/test-00098/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de E8 11 22 diff --git a/tests/tests-base/test-00098/codes b/tests/tests-base/test-00098/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00098/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00098/retcode.reference b/tests/tests-base/test-00098/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00098/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00098/stderr.reference b/tests/tests-base/test-00098/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00098/stdout.reference b/tests/tests-base/test-00098/stdout.reference new file mode 100644 index 0000000..0f01b10 --- /dev/null +++ b/tests/tests-base/test-00098/stdout.reference @@ -0,0 +1,5 @@ +E81122 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_RELBRz ISA_SET: I86 +SHORT: call 0x2214 +Encodable! E81122 +Identical re-encoding diff --git a/tests/tests-base/test-00099/cmd b/tests/tests-base/test-00099/cmd new file mode 100644 index 0000000..55a04a3 --- /dev/null +++ b/tests/tests-base/test-00099/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f8411223344 diff --git a/tests/tests-base/test-00099/codes b/tests/tests-base/test-00099/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00099/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00099/retcode.reference b/tests/tests-base/test-00099/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00099/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00099/stderr.reference b/tests/tests-base/test-00099/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00099/stdout.reference b/tests/tests-base/test-00099/stdout.reference new file mode 100644 index 0000000..f0e98e6 --- /dev/null +++ b/tests/tests-base/test-00099/stdout.reference @@ -0,0 +1,5 @@ +0F8411223344 +ICLASS: JZ CATEGORY: COND_BR EXTENSION: BASE IFORM: JZ_RELBRd ISA_SET: I86 +SHORT: jz 0x44332217 +Encodable! 0F8411223344 +Identical re-encoding diff --git a/tests/tests-base/test-00100/cmd b/tests/tests-base/test-00100/cmd new file mode 100644 index 0000000..9b95e5f --- /dev/null +++ b/tests/tests-base/test-00100/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 660f8411223344 diff --git a/tests/tests-base/test-00100/codes b/tests/tests-base/test-00100/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00100/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00100/retcode.reference b/tests/tests-base/test-00100/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00100/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00100/stderr.reference b/tests/tests-base/test-00100/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00100/stdout.reference b/tests/tests-base/test-00100/stdout.reference new file mode 100644 index 0000000..4c2e1f0 --- /dev/null +++ b/tests/tests-base/test-00100/stdout.reference @@ -0,0 +1,12 @@ +660F8411223344 +ICLASS: JZ CATEGORY: COND_BR EXTENSION: BASE IFORM: JZ_RELBRd ISA_SET: I86 +SHORT: jz 0x44332218 +Encodable! 0F8411223344 +Discrepenacy after re-encoding. dec_len= 7 [660F8411223344] enc_olen= 6 [0F8411223344] for instruction: JZ JZ_RELBRd BRDISP_WIDTH:32, DF64, DISP_WIDTH:32, EASZ:3, EOSZ:3, LZCNT, MAP:1, MAX_BYTES:7, MODE:2, NOMINAL_OPCODE:132, NPREFIXES:1, OUTREG:RFLAGS, P4, POS_DISP:3, POS_NOMINAL_OPCODE:2, PREFIX66, REG0:RIP, REG1:RFLAGS, RELBR:0x44332211, SMODE:2, SRM:4, TZCNT +0 RELBR/R/D/EXPLICIT/IMM_CONST/1 +1 REG0/RW/V/SUPPRESSED/NT_LOOKUP_FN/RIP +2 REG1/R/Y/SUPPRESSED/NT_LOOKUP_FN/RFLAGS +YDIS: jz 0x44332218 +vs Encode request: JZ BRDISP_WIDTH:32, DF64, DISP_WIDTH:32, EASZ:3, EOSZ:3, LZCNT, MAP:1, MAX_BYTES:7, MODE:2, NOMINAL_OPCODE:132, NPREFIXES:1, OUTREG:RFLAGS, P4, POS_DISP:3, POS_NOMINAL_OPCODE:2, PREFIX66, REG0:RIP, REG1:RFLAGS, RELBR:0x44332211, SMODE:2, SRM:4, TZCNT +OPERAND ORDER: RELBR + diff --git a/tests/tests-base/test-00101/cmd b/tests/tests-base/test-00101/cmd new file mode 100644 index 0000000..f9e2c7f --- /dev/null +++ b/tests/tests-base/test-00101/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 9a11223344aabb diff --git a/tests/tests-base/test-00101/codes b/tests/tests-base/test-00101/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00101/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00101/retcode.reference b/tests/tests-base/test-00101/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00101/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00101/stderr.reference b/tests/tests-base/test-00101/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00101/stdout.reference b/tests/tests-base/test-00101/stdout.reference new file mode 100644 index 0000000..95ae151 --- /dev/null +++ b/tests/tests-base/test-00101/stdout.reference @@ -0,0 +1,5 @@ +9A11223344AABB +ICLASS: CALL_FAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_FAR_PTRp_IMMw ISA_SET: I86 +SHORT: call far 0x44332211, 0xbbaa +Encodable! 9A11223344AABB +Identical re-encoding diff --git a/tests/tests-base/test-00102/cmd b/tests/tests-base/test-00102/cmd new file mode 100644 index 0000000..afac203 --- /dev/null +++ b/tests/tests-base/test-00102/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 669a11223344aabb diff --git a/tests/tests-base/test-00102/codes b/tests/tests-base/test-00102/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00102/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00102/retcode.reference b/tests/tests-base/test-00102/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00102/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00102/stderr.reference b/tests/tests-base/test-00102/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00102/stdout.reference b/tests/tests-base/test-00102/stdout.reference new file mode 100644 index 0000000..a892e24 --- /dev/null +++ b/tests/tests-base/test-00102/stdout.reference @@ -0,0 +1,5 @@ +669A11223344AABB +ICLASS: CALL_FAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_FAR_PTRp_IMMw ISA_SET: I86 +SHORT: call far 0x44332211, 0xbbaa +Encodable! 669A11223344AABB +Identical re-encoding diff --git a/tests/tests-base/test-00103/cmd b/tests/tests-base/test-00103/cmd new file mode 100644 index 0000000..9749d2c --- /dev/null +++ b/tests/tests-base/test-00103/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 669a1122aabb diff --git a/tests/tests-base/test-00103/codes b/tests/tests-base/test-00103/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00103/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00103/retcode.reference b/tests/tests-base/test-00103/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00103/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00103/stderr.reference b/tests/tests-base/test-00103/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00103/stdout.reference b/tests/tests-base/test-00103/stdout.reference new file mode 100644 index 0000000..5a06ee5 --- /dev/null +++ b/tests/tests-base/test-00103/stdout.reference @@ -0,0 +1,5 @@ +669A1122AABB +ICLASS: CALL_FAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_FAR_PTRp_IMMw ISA_SET: I86 +SHORT: call far 0x2211, 0xbbaa +Encodable! 669A1122AABB +Identical re-encoding diff --git a/tests/tests-base/test-00104/cmd b/tests/tests-base/test-00104/cmd new file mode 100644 index 0000000..330cf4c --- /dev/null +++ b/tests/tests-base/test-00104/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 679a11223344aabb diff --git a/tests/tests-base/test-00104/codes b/tests/tests-base/test-00104/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00104/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00104/retcode.reference b/tests/tests-base/test-00104/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00104/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00104/stderr.reference b/tests/tests-base/test-00104/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00104/stdout.reference b/tests/tests-base/test-00104/stdout.reference new file mode 100644 index 0000000..0f92acc --- /dev/null +++ b/tests/tests-base/test-00104/stdout.reference @@ -0,0 +1,5 @@ +679A11223344AABB +ICLASS: CALL_FAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_FAR_PTRp_IMMw ISA_SET: I86 +SHORT: addr16 call far 0x44332211, 0xbbaa +Encodable! 679A11223344AABB +Identical re-encoding diff --git a/tests/tests-base/test-00105/cmd b/tests/tests-base/test-00105/cmd new file mode 100644 index 0000000..245e15f --- /dev/null +++ b/tests/tests-base/test-00105/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -v 5 -de 0fa0 diff --git a/tests/tests-base/test-00105/codes b/tests/tests-base/test-00105/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00105/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00105/retcode.reference b/tests/tests-base/test-00105/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00105/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00105/stderr.reference b/tests/tests-base/test-00105/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00105/stdout.reference b/tests/tests-base/test-00105/stdout.reference new file mode 100644 index 0000000..8b73f17 --- /dev/null +++ b/tests/tests-base/test-00105/stdout.reference @@ -0,0 +1,14 @@ +Initializing XED tables... +Done initialing XED tables. +#XED version: [7.53.0-14-g3904991 2016-12-12] +0FA0 +PUSH PUSH_FS EASZ:2, EOSZ:2, LZCNT, MAP:1, MAX_BYTES:2, MEM0:ptr SS[ESP], MODE:1, NOMINAL_OPCODE:160, OUTREG:SS, P4, POS_NOMINAL_OPCODE:1, REG0:FS, REG1:STACKPUSH, SMODE:1, TZCNT, USING_DEFAULT_SEGMENT0 +0 REG0/R/W/IMPLICIT/REG/FS +1 REG1/W/SPW/SUPPRESSED/REG/STACKPUSH +2 MEM0/W/SPW/SUPPRESSED/IMM_CONST/1 +3 BASE0/RW/SSZ/SUPPRESSED/NT_LOOKUP_FN/SRSP +YDIS: push fs +ICLASS: PUSH CATEGORY: PUSH EXTENSION: BASE IFORM: PUSH_FS ISA_SET: I86 +SHORT: push fs +Encodable! 0FA0 +Identical re-encoding diff --git a/tests/tests-base/test-00106/cmd b/tests/tests-base/test-00106/cmd new file mode 100644 index 0000000..0aac578 --- /dev/null +++ b/tests/tests-base/test-00106/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -v 5 -de 0fa0 diff --git a/tests/tests-base/test-00106/codes b/tests/tests-base/test-00106/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00106/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00106/retcode.reference b/tests/tests-base/test-00106/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00106/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00106/stderr.reference b/tests/tests-base/test-00106/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00106/stdout.reference b/tests/tests-base/test-00106/stdout.reference new file mode 100644 index 0000000..ae2c134 --- /dev/null +++ b/tests/tests-base/test-00106/stdout.reference @@ -0,0 +1,14 @@ +Initializing XED tables... +Done initialing XED tables. +#XED version: [7.53.0-14-g3904991 2016-12-12] +0FA0 +PUSH PUSH_FS DF64, EASZ:3, EOSZ:3, LZCNT, MAP:1, MAX_BYTES:2, MEM0:ptr [RSP], MODE:2, NOMINAL_OPCODE:160, P4, POS_NOMINAL_OPCODE:1, REG0:FS, REG1:STACKPUSH, SMODE:2, TZCNT, USING_DEFAULT_SEGMENT0 +0 REG0/R/W/IMPLICIT/REG/FS +1 REG1/W/SPW/SUPPRESSED/REG/STACKPUSH +2 MEM0/W/SPW/SUPPRESSED/IMM_CONST/1 +3 BASE0/RW/SSZ/SUPPRESSED/NT_LOOKUP_FN/SRSP +YDIS: push fs +ICLASS: PUSH CATEGORY: PUSH EXTENSION: BASE IFORM: PUSH_FS ISA_SET: I86 +SHORT: push fs +Encodable! 0FA0 +Identical re-encoding diff --git a/tests/tests-base/test-00107/cmd b/tests/tests-base/test-00107/cmd new file mode 100644 index 0000000..28b5df5 --- /dev/null +++ b/tests/tests-base/test-00107/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 9c diff --git a/tests/tests-base/test-00107/codes b/tests/tests-base/test-00107/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00107/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00107/retcode.reference b/tests/tests-base/test-00107/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00107/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00107/stderr.reference b/tests/tests-base/test-00107/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00107/stdout.reference b/tests/tests-base/test-00107/stdout.reference new file mode 100644 index 0000000..6245c16 --- /dev/null +++ b/tests/tests-base/test-00107/stdout.reference @@ -0,0 +1,28 @@ +Attempting to decode: 9c +iclass PUSHFD category PUSH ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PUSHFD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPUSH SUPPRESSED W D 32 4 1 32 INT PSEUDO +1 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst + read: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 STACKPUSH0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00108/cmd b/tests/tests-base/test-00108/cmd new file mode 100644 index 0000000..432470d --- /dev/null +++ b/tests/tests-base/test-00108/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 9d diff --git a/tests/tests-base/test-00108/codes b/tests/tests-base/test-00108/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00108/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00108/retcode.reference b/tests/tests-base/test-00108/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00108/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00108/stderr.reference b/tests/tests-base/test-00108/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00108/stdout.reference b/tests/tests-base/test-00108/stdout.reference new file mode 100644 index 0000000..f4a1012 --- /dev/null +++ b/tests/tests-base/test-00108/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 9d +iclass POPFD category POP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name POPFD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R D 32 4 1 32 INT PSEUDO +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm vip mask=0x123000 + written: of sf zf af pf cf df vif iopl if ac rf nt tf id mask=0x2d7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX STACKPOP0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00109/cmd b/tests/tests-base/test-00109/cmd new file mode 100644 index 0000000..db37361 --- /dev/null +++ b/tests/tests-base/test-00109/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0c e0 00 diff --git a/tests/tests-base/test-00109/codes b/tests/tests-base/test-00109/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00109/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00109/retcode.reference b/tests/tests-base/test-00109/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00109/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00109/stderr.reference b/tests/tests-base/test-00109/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00109/stdout.reference b/tests/tests-base/test-00109/stdout.reference new file mode 100644 index 0000000..f37d28e --- /dev/null +++ b/tests/tests-base/test-00109/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 0c e0 00 +iclass OR category LOGICAL ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OR_AL_IMMb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 18 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL IMPLICIT RW B 8 1 1 8 INT GPR +1 IMM0 0xe0(8b) EXPLICIT R B 8 1 1 8 UINT INVALID +2 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags of-0 sf-mod zf-mod af-u pf-mod cf-0 + read: mask=0x0 + written: of sf zf af pf cf mask=0x8d5 + undefined: af mask=0x10 +ATTRIBUTES: BYTEOP +ISA SET: [I86] diff --git a/tests/tests-base/test-00110/cmd b/tests/tests-base/test-00110/cmd new file mode 100644 index 0000000..9df024f --- /dev/null +++ b/tests/tests-base/test-00110/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0c e0 f0 diff --git a/tests/tests-base/test-00110/codes b/tests/tests-base/test-00110/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00110/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00110/retcode.reference b/tests/tests-base/test-00110/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00110/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00110/stderr.reference b/tests/tests-base/test-00110/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00110/stdout.reference b/tests/tests-base/test-00110/stdout.reference new file mode 100644 index 0000000..bff7077 --- /dev/null +++ b/tests/tests-base/test-00110/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 0c e0 f0 +iclass OR category LOGICAL ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OR_AL_IMMb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 18 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL IMPLICIT RW B 8 1 1 8 INT GPR +1 IMM0 0xe0(8b) EXPLICIT R B 8 1 1 8 UINT INVALID +2 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags of-0 sf-mod zf-mod af-u pf-mod cf-0 + read: mask=0x0 + written: of sf zf af pf cf mask=0x8d5 + undefined: af mask=0x10 +ATTRIBUTES: BYTEOP +ISA SET: [I86] diff --git a/tests/tests-base/test-00111/cmd b/tests/tests-base/test-00111/cmd new file mode 100644 index 0000000..c78d99b --- /dev/null +++ b/tests/tests-base/test-00111/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0c e0 40 diff --git a/tests/tests-base/test-00111/codes b/tests/tests-base/test-00111/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00111/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00111/retcode.reference b/tests/tests-base/test-00111/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00111/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00111/stderr.reference b/tests/tests-base/test-00111/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00111/stdout.reference b/tests/tests-base/test-00111/stdout.reference new file mode 100644 index 0000000..fe54337 --- /dev/null +++ b/tests/tests-base/test-00111/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 0c e0 40 +iclass OR category LOGICAL ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OR_AL_IMMb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 18 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL IMPLICIT RW B 8 1 1 8 INT GPR +1 IMM0 0xe0(8b) EXPLICIT R B 8 1 1 8 UINT INVALID +2 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags of-0 sf-mod zf-mod af-u pf-mod cf-0 + read: mask=0x0 + written: of sf zf af pf cf mask=0x8d5 + undefined: af mask=0x10 +ATTRIBUTES: BYTEOP +ISA SET: [I86] diff --git a/tests/tests-base/test-00112/cmd b/tests/tests-base/test-00112/cmd new file mode 100644 index 0000000..f4da5c6 --- /dev/null +++ b/tests/tests-base/test-00112/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 3e 66 d7 diff --git a/tests/tests-base/test-00112/codes b/tests/tests-base/test-00112/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00112/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00112/retcode.reference b/tests/tests-base/test-00112/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00112/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00112/stderr.reference b/tests/tests-base/test-00112/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00112/stdout.reference b/tests/tests-base/test-00112/stdout.reference new file mode 100644 index 0000000..ecf6c85 --- /dev/null +++ b/tests/tests-base/test-00112/stdout.reference @@ -0,0 +1,3 @@ +3E66D7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: data16 xlat diff --git a/tests/tests-base/test-00113/cmd b/tests/tests-base/test-00113/cmd new file mode 100644 index 0000000..e536890 --- /dev/null +++ b/tests/tests-base/test-00113/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 3ed7 diff --git a/tests/tests-base/test-00113/codes b/tests/tests-base/test-00113/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00113/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00113/retcode.reference b/tests/tests-base/test-00113/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00113/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00113/stderr.reference b/tests/tests-base/test-00113/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00113/stdout.reference b/tests/tests-base/test-00113/stdout.reference new file mode 100644 index 0000000..48877ee --- /dev/null +++ b/tests/tests-base/test-00113/stdout.reference @@ -0,0 +1,3 @@ +3ED7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: xlat diff --git a/tests/tests-base/test-00114/cmd b/tests/tests-base/test-00114/cmd new file mode 100644 index 0000000..5ef869f --- /dev/null +++ b/tests/tests-base/test-00114/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 658a0511223344 diff --git a/tests/tests-base/test-00114/codes b/tests/tests-base/test-00114/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00114/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00114/retcode.reference b/tests/tests-base/test-00114/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00114/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00114/stderr.reference b/tests/tests-base/test-00114/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00114/stdout.reference b/tests/tests-base/test-00114/stdout.reference new file mode 100644 index 0000000..a819374 --- /dev/null +++ b/tests/tests-base/test-00114/stdout.reference @@ -0,0 +1,3 @@ +658A0511223344 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_GPR8_MEMb ISA_SET: I86 +SHORT: mov al, byte ptr gs:[0x44332211] diff --git a/tests/tests-base/test-00115/cmd b/tests/tests-base/test-00115/cmd new file mode 100644 index 0000000..e8ff98d --- /dev/null +++ b/tests/tests-base/test-00115/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65A011223344 diff --git a/tests/tests-base/test-00115/codes b/tests/tests-base/test-00115/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00115/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00115/retcode.reference b/tests/tests-base/test-00115/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00115/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00115/stderr.reference b/tests/tests-base/test-00115/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00115/stdout.reference b/tests/tests-base/test-00115/stdout.reference new file mode 100644 index 0000000..84631df --- /dev/null +++ b/tests/tests-base/test-00115/stdout.reference @@ -0,0 +1,3 @@ +65A011223344 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_AL_MEMb ISA_SET: I86 +SHORT: mov al, byte ptr gs:[0x44332211] diff --git a/tests/tests-base/test-00116/cmd b/tests/tests-base/test-00116/cmd new file mode 100644 index 0000000..a99bded --- /dev/null +++ b/tests/tests-base/test-00116/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65A4 diff --git a/tests/tests-base/test-00116/codes b/tests/tests-base/test-00116/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00116/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00116/retcode.reference b/tests/tests-base/test-00116/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00116/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00116/stderr.reference b/tests/tests-base/test-00116/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00116/stdout.reference b/tests/tests-base/test-00116/stdout.reference new file mode 100644 index 0000000..b6d8214 --- /dev/null +++ b/tests/tests-base/test-00116/stdout.reference @@ -0,0 +1,3 @@ +65A4 +ICLASS: MOVSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: MOVSB ISA_SET: I86 +SHORT: movsb byte ptr [edi], byte ptr gs:[esi] diff --git a/tests/tests-base/test-00117/cmd b/tests/tests-base/test-00117/cmd new file mode 100644 index 0000000..1d303dd --- /dev/null +++ b/tests/tests-base/test-00117/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65a6 diff --git a/tests/tests-base/test-00117/codes b/tests/tests-base/test-00117/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00117/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00117/retcode.reference b/tests/tests-base/test-00117/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00117/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00117/stderr.reference b/tests/tests-base/test-00117/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00117/stdout.reference b/tests/tests-base/test-00117/stdout.reference new file mode 100644 index 0000000..167a387 --- /dev/null +++ b/tests/tests-base/test-00117/stdout.reference @@ -0,0 +1,3 @@ +65A6 +ICLASS: CMPSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: CMPSB ISA_SET: I86 +SHORT: cmpsb byte ptr gs:[esi], byte ptr [edi] diff --git a/tests/tests-base/test-00118/cmd b/tests/tests-base/test-00118/cmd new file mode 100644 index 0000000..8f5d5f1 --- /dev/null +++ b/tests/tests-base/test-00118/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65d7 diff --git a/tests/tests-base/test-00118/codes b/tests/tests-base/test-00118/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00118/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00118/retcode.reference b/tests/tests-base/test-00118/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00118/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00118/stderr.reference b/tests/tests-base/test-00118/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00118/stdout.reference b/tests/tests-base/test-00118/stdout.reference new file mode 100644 index 0000000..f03e8b1 --- /dev/null +++ b/tests/tests-base/test-00118/stdout.reference @@ -0,0 +1,3 @@ +65D7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: xlat gs diff --git a/tests/tests-base/test-00119/cmd b/tests/tests-base/test-00119/cmd new file mode 100644 index 0000000..9278abe --- /dev/null +++ b/tests/tests-base/test-00119/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65ff30 diff --git a/tests/tests-base/test-00119/codes b/tests/tests-base/test-00119/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00119/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00119/retcode.reference b/tests/tests-base/test-00119/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00119/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00119/stderr.reference b/tests/tests-base/test-00119/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00119/stdout.reference b/tests/tests-base/test-00119/stdout.reference new file mode 100644 index 0000000..8e79e90 --- /dev/null +++ b/tests/tests-base/test-00119/stdout.reference @@ -0,0 +1,3 @@ +65FF30 +ICLASS: PUSH CATEGORY: PUSH EXTENSION: BASE IFORM: PUSH_MEMv ISA_SET: I86 +SHORT: push dword ptr gs:[eax] diff --git a/tests/tests-base/test-00120/cmd b/tests/tests-base/test-00120/cmd new file mode 100644 index 0000000..a3701f8 --- /dev/null +++ b/tests/tests-base/test-00120/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d A4 diff --git a/tests/tests-base/test-00120/codes b/tests/tests-base/test-00120/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00120/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00120/retcode.reference b/tests/tests-base/test-00120/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00120/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00120/stderr.reference b/tests/tests-base/test-00120/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00120/stdout.reference b/tests/tests-base/test-00120/stdout.reference new file mode 100644 index 0000000..c3070ca --- /dev/null +++ b/tests/tests-base/test-00120/stdout.reference @@ -0,0 +1,3 @@ +A4 +ICLASS: MOVSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: MOVSB ISA_SET: I86 +SHORT: movsb byte ptr [edi], byte ptr [esi] diff --git a/tests/tests-base/test-00121/cmd b/tests/tests-base/test-00121/cmd new file mode 100644 index 0000000..9a01471 --- /dev/null +++ b/tests/tests-base/test-00121/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d a6 diff --git a/tests/tests-base/test-00121/codes b/tests/tests-base/test-00121/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00121/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00121/retcode.reference b/tests/tests-base/test-00121/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00121/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00121/stderr.reference b/tests/tests-base/test-00121/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00121/stdout.reference b/tests/tests-base/test-00121/stdout.reference new file mode 100644 index 0000000..6732068 --- /dev/null +++ b/tests/tests-base/test-00121/stdout.reference @@ -0,0 +1,3 @@ +A6 +ICLASS: CMPSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: CMPSB ISA_SET: I86 +SHORT: cmpsb byte ptr [esi], byte ptr [edi] diff --git a/tests/tests-base/test-00122/cmd b/tests/tests-base/test-00122/cmd new file mode 100644 index 0000000..3681ed2 --- /dev/null +++ b/tests/tests-base/test-00122/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d d7 diff --git a/tests/tests-base/test-00122/codes b/tests/tests-base/test-00122/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00122/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00122/retcode.reference b/tests/tests-base/test-00122/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00122/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00122/stderr.reference b/tests/tests-base/test-00122/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00122/stdout.reference b/tests/tests-base/test-00122/stdout.reference new file mode 100644 index 0000000..7f57aaa --- /dev/null +++ b/tests/tests-base/test-00122/stdout.reference @@ -0,0 +1,3 @@ +D7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: xlat diff --git a/tests/tests-base/test-00123/cmd b/tests/tests-base/test-00123/cmd new file mode 100644 index 0000000..40b12dc --- /dev/null +++ b/tests/tests-base/test-00123/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d ff30 diff --git a/tests/tests-base/test-00123/codes b/tests/tests-base/test-00123/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00123/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00123/retcode.reference b/tests/tests-base/test-00123/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00123/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00123/stderr.reference b/tests/tests-base/test-00123/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00123/stdout.reference b/tests/tests-base/test-00123/stdout.reference new file mode 100644 index 0000000..98b1caa --- /dev/null +++ b/tests/tests-base/test-00123/stdout.reference @@ -0,0 +1,3 @@ +FF30 +ICLASS: PUSH CATEGORY: PUSH EXTENSION: BASE IFORM: PUSH_MEMv ISA_SET: I86 +SHORT: push dword ptr [eax] diff --git a/tests/tests-base/test-00124/cmd b/tests/tests-base/test-00124/cmd new file mode 100644 index 0000000..e6722e9 --- /dev/null +++ b/tests/tests-base/test-00124/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 65 a6 diff --git a/tests/tests-base/test-00124/codes b/tests/tests-base/test-00124/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00124/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00124/retcode.reference b/tests/tests-base/test-00124/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00124/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00124/stderr.reference b/tests/tests-base/test-00124/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00124/stdout.reference b/tests/tests-base/test-00124/stdout.reference new file mode 100644 index 0000000..839eeef --- /dev/null +++ b/tests/tests-base/test-00124/stdout.reference @@ -0,0 +1,5 @@ +65A6 +ICLASS: CMPSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: CMPSB ISA_SET: I86 +SHORT: cmpsb byte ptr gs:[esi], byte ptr [edi] +Encodable! 65A6 +Identical re-encoding diff --git a/tests/tests-base/test-00125/cmd b/tests/tests-base/test-00125/cmd new file mode 100644 index 0000000..d9ecc02 --- /dev/null +++ b/tests/tests-base/test-00125/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 65 d7 diff --git a/tests/tests-base/test-00125/codes b/tests/tests-base/test-00125/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00125/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00125/retcode.reference b/tests/tests-base/test-00125/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00125/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00125/stderr.reference b/tests/tests-base/test-00125/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00125/stdout.reference b/tests/tests-base/test-00125/stdout.reference new file mode 100644 index 0000000..a4dab07 --- /dev/null +++ b/tests/tests-base/test-00125/stdout.reference @@ -0,0 +1,5 @@ +65D7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: xlat gs +Encodable! 65D7 +Identical re-encoding diff --git a/tests/tests-base/test-00126/cmd b/tests/tests-base/test-00126/cmd new file mode 100644 index 0000000..159d4ae --- /dev/null +++ b/tests/tests-base/test-00126/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 65A011223344 diff --git a/tests/tests-base/test-00126/codes b/tests/tests-base/test-00126/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00126/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00126/retcode.reference b/tests/tests-base/test-00126/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00126/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00126/stderr.reference b/tests/tests-base/test-00126/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00126/stdout.reference b/tests/tests-base/test-00126/stdout.reference new file mode 100644 index 0000000..7771310 --- /dev/null +++ b/tests/tests-base/test-00126/stdout.reference @@ -0,0 +1,5 @@ +65A011223344 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_AL_MEMb ISA_SET: I86 +SHORT: mov al, byte ptr gs:[0x44332211] +Encodable! 65A011223344 +Identical re-encoding diff --git a/tests/tests-base/test-00127/cmd b/tests/tests-base/test-00127/cmd new file mode 100644 index 0000000..8043166 --- /dev/null +++ b/tests/tests-base/test-00127/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 65A4 diff --git a/tests/tests-base/test-00127/codes b/tests/tests-base/test-00127/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00127/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00127/retcode.reference b/tests/tests-base/test-00127/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00127/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00127/stderr.reference b/tests/tests-base/test-00127/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00127/stdout.reference b/tests/tests-base/test-00127/stdout.reference new file mode 100644 index 0000000..06b576a --- /dev/null +++ b/tests/tests-base/test-00127/stdout.reference @@ -0,0 +1,5 @@ +65A4 +ICLASS: MOVSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: MOVSB ISA_SET: I86 +SHORT: movsb byte ptr [edi], byte ptr gs:[esi] +Encodable! 65A4 +Identical re-encoding diff --git a/tests/tests-base/test-00128/cmd b/tests/tests-base/test-00128/cmd new file mode 100644 index 0000000..71d73a8 --- /dev/null +++ b/tests/tests-base/test-00128/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 65a6 diff --git a/tests/tests-base/test-00128/codes b/tests/tests-base/test-00128/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00128/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00128/retcode.reference b/tests/tests-base/test-00128/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00128/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00128/stderr.reference b/tests/tests-base/test-00128/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00128/stdout.reference b/tests/tests-base/test-00128/stdout.reference new file mode 100644 index 0000000..839eeef --- /dev/null +++ b/tests/tests-base/test-00128/stdout.reference @@ -0,0 +1,5 @@ +65A6 +ICLASS: CMPSB CATEGORY: STRINGOP EXTENSION: BASE IFORM: CMPSB ISA_SET: I86 +SHORT: cmpsb byte ptr gs:[esi], byte ptr [edi] +Encodable! 65A6 +Identical re-encoding diff --git a/tests/tests-base/test-00129/cmd b/tests/tests-base/test-00129/cmd new file mode 100644 index 0000000..fb3aae6 --- /dev/null +++ b/tests/tests-base/test-00129/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 67d6 diff --git a/tests/tests-base/test-00129/codes b/tests/tests-base/test-00129/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00129/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00129/retcode.reference b/tests/tests-base/test-00129/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00129/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00129/stderr.reference b/tests/tests-base/test-00129/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00129/stdout.reference b/tests/tests-base/test-00129/stdout.reference new file mode 100644 index 0000000..09a04cf --- /dev/null +++ b/tests/tests-base/test-00129/stdout.reference @@ -0,0 +1,5 @@ +67D6 +ICLASS: SALC CATEGORY: FLAGOP EXTENSION: BASE IFORM: SALC ISA_SET: I86 +SHORT: addr16 salc +Encodable! 67D6 +Identical re-encoding diff --git a/tests/tests-base/test-00130/cmd b/tests/tests-base/test-00130/cmd new file mode 100644 index 0000000..752e486 --- /dev/null +++ b/tests/tests-base/test-00130/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 67d7 diff --git a/tests/tests-base/test-00130/codes b/tests/tests-base/test-00130/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00130/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00130/retcode.reference b/tests/tests-base/test-00130/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00130/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00130/stderr.reference b/tests/tests-base/test-00130/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00130/stdout.reference b/tests/tests-base/test-00130/stdout.reference new file mode 100644 index 0000000..913a6f2 --- /dev/null +++ b/tests/tests-base/test-00130/stdout.reference @@ -0,0 +1,5 @@ +67D7 +ICLASS: XLAT CATEGORY: MISC EXTENSION: BASE IFORM: XLAT ISA_SET: I86 +SHORT: addr16 xlat +Encodable! 67D7 +Identical re-encoding diff --git a/tests/tests-base/test-00131/cmd b/tests/tests-base/test-00131/cmd new file mode 100644 index 0000000..c559f59 --- /dev/null +++ b/tests/tests-base/test-00131/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 MOV AL MEM1:-,-,-,11223344 diff --git a/tests/tests-base/test-00131/codes b/tests/tests-base/test-00131/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00131/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00131/retcode.reference b/tests/tests-base/test-00131/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00131/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00131/stderr.reference b/tests/tests-base/test-00131/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00131/stdout.reference b/tests/tests-base/test-00131/stdout.reference new file mode 100644 index 0000000..e9fe5d2 --- /dev/null +++ b/tests/tests-base/test-00131/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:32, MEM_WIDTH:1, MEM0:byte ptr [0x11223344], MODE:1, REG0:AL, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! A044332211 diff --git a/tests/tests-base/test-00132/cmd b/tests/tests-base/test-00132/cmd new file mode 100644 index 0000000..aa82d98 --- /dev/null +++ b/tests/tests-base/test-00132/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 MOV AL MEM1:GS:-,-,-,11223344 diff --git a/tests/tests-base/test-00132/codes b/tests/tests-base/test-00132/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00132/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00132/retcode.reference b/tests/tests-base/test-00132/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00132/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00132/stderr.reference b/tests/tests-base/test-00132/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00132/stdout.reference b/tests/tests-base/test-00132/stdout.reference new file mode 100644 index 0000000..27f4688 --- /dev/null +++ b/tests/tests-base/test-00132/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:32, MEM_WIDTH:1, MEM0:byte ptr GS[0x11223344], MODE:1, REG0:AL, SMODE:1 +OPERAND ORDER: REG0 MEM0 + +Encodable! 65A044332211 diff --git a/tests/tests-base/test-00133/cmd b/tests/tests-base/test-00133/cmd new file mode 100644 index 0000000..5e47f33 --- /dev/null +++ b/tests/tests-base/test-00133/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 SALC SEG:GS diff --git a/tests/tests-base/test-00133/codes b/tests/tests-base/test-00133/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00133/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00133/retcode.reference b/tests/tests-base/test-00133/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00133/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00133/stderr.reference b/tests/tests-base/test-00133/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00133/stdout.reference b/tests/tests-base/test-00133/stdout.reference new file mode 100644 index 0000000..61daaea --- /dev/null +++ b/tests/tests-base/test-00133/stdout.reference @@ -0,0 +1,4 @@ +Encode request: +SALC MODE:1, SMODE:1 + +Encodable! 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A4 diff --git a/tests/tests-base/test-00138/cmd b/tests/tests-base/test-00138/cmd new file mode 100644 index 0000000..40cc68f --- /dev/null +++ b/tests/tests-base/test-00138/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 65 a6 diff --git a/tests/tests-base/test-00138/codes b/tests/tests-base/test-00138/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00138/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00138/retcode.reference b/tests/tests-base/test-00138/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00138/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00138/stderr.reference b/tests/tests-base/test-00138/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00138/stdout.reference b/tests/tests-base/test-00138/stdout.reference new file mode 100644 index 0000000..254ae80 --- /dev/null +++ b/tests/tests-base/test-00138/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 65 a6 +iclass CMPSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= GS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00139/cmd b/tests/tests-base/test-00139/cmd new file mode 100644 index 0000000..dacd0ec --- /dev/null +++ b/tests/tests-base/test-00139/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d f000c0 diff --git a/tests/tests-base/test-00139/codes b/tests/tests-base/test-00139/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00139/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00139/retcode.reference b/tests/tests-base/test-00139/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00139/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00139/stderr.reference b/tests/tests-base/test-00139/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git 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a/tests/tests-base/test-00140/stderr.reference b/tests/tests-base/test-00140/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00140/stdout.reference b/tests/tests-base/test-00140/stdout.reference new file mode 100644 index 0000000..6f10f6e --- /dev/null +++ b/tests/tests-base/test-00140/stdout.reference @@ -0,0 +1,3 @@ +F00000 +ICLASS: ADD_LOCK CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_LOCK_MEMb_GPR8 ISA_SET: I86 +SHORT: lock add byte ptr [eax], al diff --git a/tests/tests-base/test-00141/cmd b/tests/tests-base/test-00141/cmd new file mode 100644 index 0000000..57e853a --- /dev/null +++ b/tests/tests-base/test-00141/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 0fc708 diff --git a/tests/tests-base/test-00141/codes b/tests/tests-base/test-00141/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00141/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00141/retcode.reference b/tests/tests-base/test-00141/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00141/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00141/stderr.reference b/tests/tests-base/test-00141/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00141/stdout.reference b/tests/tests-base/test-00141/stdout.reference new file mode 100644 index 0000000..ec45358 --- /dev/null +++ b/tests/tests-base/test-00141/stdout.reference @@ -0,0 +1,3 @@ +0FC708 +ICLASS: CMPXCHG8B CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_MEMq ISA_SET: PENTIUMREAL +SHORT: cmpxchg8b qword ptr [eax] diff --git a/tests/tests-base/test-00142/cmd b/tests/tests-base/test-00142/cmd new file mode 100644 index 0000000..57e2e57 --- /dev/null +++ b/tests/tests-base/test-00142/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d f00fc708 diff --git a/tests/tests-base/test-00142/codes b/tests/tests-base/test-00142/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00142/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00142/retcode.reference b/tests/tests-base/test-00142/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00142/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00142/stderr.reference b/tests/tests-base/test-00142/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00142/stdout.reference b/tests/tests-base/test-00142/stdout.reference new file mode 100644 index 0000000..9cbc3bd --- /dev/null +++ b/tests/tests-base/test-00142/stdout.reference @@ -0,0 +1,3 @@ +F00FC708 +ICLASS: CMPXCHG8B_LOCK CATEGORY: SEMAPHORE EXTENSION: BASE IFORM: CMPXCHG8B_LOCK_MEMq ISA_SET: PENTIUMREAL +SHORT: lock cmpxchg8b qword ptr [eax] diff --git a/tests/tests-base/test-00143/cmd b/tests/tests-base/test-00143/cmd new file mode 100644 index 0000000..753f5cd --- /dev/null +++ b/tests/tests-base/test-00143/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 0000 diff --git a/tests/tests-base/test-00143/codes b/tests/tests-base/test-00143/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00143/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00143/retcode.reference b/tests/tests-base/test-00143/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00143/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00143/stderr.reference b/tests/tests-base/test-00143/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00143/stdout.reference b/tests/tests-base/test-00143/stdout.reference new file mode 100644 index 0000000..b536abf --- /dev/null +++ b/tests/tests-base/test-00143/stdout.reference @@ -0,0 +1,5 @@ +0000 +ICLASS: ADD CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_MEMb_GPR8 ISA_SET: I86 +SHORT: add byte ptr [eax], al +Encodable! 0000 +Identical re-encoding diff --git a/tests/tests-base/test-00144/cmd b/tests/tests-base/test-00144/cmd new file mode 100644 index 0000000..a6807fa --- /dev/null +++ b/tests/tests-base/test-00144/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 00 00 diff --git a/tests/tests-base/test-00144/codes b/tests/tests-base/test-00144/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00144/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00144/retcode.reference b/tests/tests-base/test-00144/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00144/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00144/stderr.reference b/tests/tests-base/test-00144/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00144/stdout.reference b/tests/tests-base/test-00144/stdout.reference new file mode 100644 index 0000000..f6fe14f --- /dev/null +++ b/tests/tests-base/test-00144/stdout.reference @@ -0,0 +1,26 @@ +Attempting to decode: 00 00 +iclass ADD category BINARY ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name ADD_MEMb_GPR8 +iform-enum-name-dispatch (zero based) 11 +iclass-max-iform-dispatch 18 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) EXPLICIT RW B 8 1 1 8 UINT INVALID +1 REG0 REG0=AL EXPLICIT R B 8 1 1 8 INT GPR +2 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read written SEG= DS BASE= EAX/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + must-write-rflags of-mod sf-mod zf-mod af-mod pf-mod cf-mod + read: mask=0x0 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP LOCKABLE +ISA SET: [I86] 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0000000..e69de29 diff --git a/tests/tests-base/test-00146/stdout.reference b/tests/tests-base/test-00146/stdout.reference new file mode 100644 index 0000000..59b7ead --- /dev/null +++ b/tests/tests-base/test-00146/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R8D+EBX*8], EASZ:2, MODE:2, REG0:R8D, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 67458D04D8 diff --git a/tests/tests-base/test-00147/cmd b/tests/tests-base/test-00147/cmd new file mode 100644 index 0000000..e2668a4 --- /dev/null +++ b/tests/tests-base/test-00147/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 lea eax AGEN:r8d,ebx,8 diff --git a/tests/tests-base/test-00147/codes b/tests/tests-base/test-00147/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00147/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00147/retcode.reference b/tests/tests-base/test-00147/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00147/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00147/stderr.reference b/tests/tests-base/test-00147/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00147/stdout.reference b/tests/tests-base/test-00147/stdout.reference new file mode 100644 index 0000000..7975c61 --- /dev/null +++ b/tests/tests-base/test-00147/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R8D+EBX*8], EASZ:2, MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 AGEN + +Could not encode diff --git a/tests/tests-base/test-00148/cmd b/tests/tests-base/test-00148/cmd new file mode 100644 index 0000000..9881152 --- /dev/null +++ b/tests/tests-base/test-00148/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 lea eax AGEN:eax,ebx,8 diff --git a/tests/tests-base/test-00148/codes b/tests/tests-base/test-00148/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00148/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00148/retcode.reference b/tests/tests-base/test-00148/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00148/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00148/stderr.reference b/tests/tests-base/test-00148/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00148/stdout.reference b/tests/tests-base/test-00148/stdout.reference new file mode 100644 index 0000000..d29e247 --- /dev/null +++ b/tests/tests-base/test-00148/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [EAX+EBX*8], EASZ:2, MODE:1, REG0:EAX, SMODE:1 +OPERAND ORDER: REG0 AGEN + +Encodable! 8D04D8 diff --git a/tests/tests-base/test-00149/cmd b/tests/tests-base/test-00149/cmd new file mode 100644 index 0000000..7f7e9cd --- /dev/null +++ b/tests/tests-base/test-00149/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 0f 12 c0 diff --git a/tests/tests-base/test-00149/codes b/tests/tests-base/test-00149/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00149/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00149/retcode.reference b/tests/tests-base/test-00149/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00149/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00149/stderr.reference b/tests/tests-base/test-00149/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00149/stdout.reference b/tests/tests-base/test-00149/stdout.reference new file mode 100644 index 0000000..9435bb4 --- /dev/null +++ b/tests/tests-base/test-00149/stdout.reference @@ -0,0 +1,24 @@ +Attempting to decode: f2 0f 12 c0 +iclass MOVDDUP category DATAXFER ISA-extension SSE3 ISA-set SSE3 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOVDDUP_XMMdq_XMMq +iform-enum-name-dispatch (zero based) 1 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=XMM0 EXPLICIT W DQ 128 16 4 32 INT XMM +1 REG1 REG1=XMM0 EXPLICIT R Q 64 8 1 64 INT XMM +Memory Operands + MemopBytes = 0 +ATTRIBUTES: +F2 PREFIX +EXCEPTION TYPE: SSE_TYPE_5 +Number of legacy prefixes: 1 +ISA SET: [SSE3] +0 CPUID BIT NAME: [SSE3] + Leaf 0x00000001, subleaf 0x00000000, ECX[0] diff --git a/tests/tests-base/test-00150/cmd b/tests/tests-base/test-00150/cmd new file mode 100644 index 0000000..62cfb69 --- /dev/null +++ b/tests/tests-base/test-00150/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0f 12 c0 diff --git a/tests/tests-base/test-00150/codes b/tests/tests-base/test-00150/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00150/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00150/retcode.reference b/tests/tests-base/test-00150/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00150/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00150/stderr.reference b/tests/tests-base/test-00150/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00150/stdout.reference b/tests/tests-base/test-00150/stdout.reference new file mode 100644 index 0000000..6f836e4 --- /dev/null +++ b/tests/tests-base/test-00150/stdout.reference @@ -0,0 +1,22 @@ +Attempting to decode: 0f 12 c0 +iclass MOVHLPS category DATAXFER ISA-extension SSE ISA-set SSE +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOVHLPS_XMMq_XMMq +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=XMM0 EXPLICIT W Q 64 8 2 32 SINGLE XMM +1 REG1 REG1=XMM0 EXPLICIT R Q 64 8 2 32 SINGLE XMM +Memory Operands + MemopBytes = 0 +ATTRIBUTES: +EXCEPTION TYPE: SSE_TYPE_7 +ISA SET: [SSE] +0 CPUID BIT NAME: [SSE] + Leaf 0x00000001, subleaf 0x00000000, EDX[25] diff --git a/tests/tests-base/test-00151/cmd b/tests/tests-base/test-00151/cmd new file mode 100644 index 0000000..97e5204 --- /dev/null +++ b/tests/tests-base/test-00151/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 c9 diff --git a/tests/tests-base/test-00151/codes b/tests/tests-base/test-00151/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00151/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00151/retcode.reference b/tests/tests-base/test-00151/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00151/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00151/stderr.reference b/tests/tests-base/test-00151/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00151/stdout.reference b/tests/tests-base/test-00151/stdout.reference new file mode 100644 index 0000000..21b99fa --- /dev/null +++ b/tests/tests-base/test-00151/stdout.reference @@ -0,0 +1,22 @@ +Attempting to decode: c9 +iclass LEAVE category MISC ISA-extension BASE ISA-set I186 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LEAVE +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R V 32 4 1 32 INT INVALID +1 BASE0 BASE0=EBP SUPPRESSED R ASZ 32 4 1 32 INT GPR +2 REG0 REG0=EBP SUPPRESSED RW V 32 4 1 32 INT GPR +3 REG1 REG1=ESP SUPPRESSED RW V 32 4 1 32 INT GPR +Memory Operands + 0 read SEG= SS BASE= EBP/GPR ASZ0=32 + MemopBytes = 4 +ATTRIBUTES: FIXED_BASE0 SCALABLE +ISA SET: [I186] diff --git a/tests/tests-base/test-00152/cmd b/tests/tests-base/test-00152/cmd new file mode 100644 index 0000000..7c4fcb7 --- /dev/null +++ b/tests/tests-base/test-00152/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 c9 diff --git a/tests/tests-base/test-00152/codes b/tests/tests-base/test-00152/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00152/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00152/retcode.reference b/tests/tests-base/test-00152/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00152/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00152/stderr.reference b/tests/tests-base/test-00152/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00152/stdout.reference b/tests/tests-base/test-00152/stdout.reference new file mode 100644 index 0000000..fd92949 --- /dev/null +++ b/tests/tests-base/test-00152/stdout.reference @@ -0,0 +1,22 @@ +Attempting to decode: c9 +iclass LEAVE category MISC ISA-extension BASE ISA-set I186 +instruction-length 1 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name LEAVE +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R V 64 8 1 64 INT INVALID +1 BASE0 BASE0=RBP SUPPRESSED R ASZ 64 8 1 64 INT GPR +2 REG0 REG0=RBP SUPPRESSED RW V 64 8 1 64 INT GPR +3 REG1 REG1=RSP SUPPRESSED RW V 64 8 1 64 INT GPR +Memory Operands + 0 read BASE= RBP/GPR ASZ0=64 + MemopBytes = 8 +ATTRIBUTES: FIXED_BASE0 SCALABLE +ISA SET: [I186] diff --git a/tests/tests-base/test-00153/cmd b/tests/tests-base/test-00153/cmd new file mode 100644 index 0000000..d33505b --- /dev/null +++ b/tests/tests-base/test-00153/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de c9 diff --git a/tests/tests-base/test-00153/codes b/tests/tests-base/test-00153/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00153/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00153/retcode.reference b/tests/tests-base/test-00153/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00153/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00153/stderr.reference b/tests/tests-base/test-00153/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00153/stdout.reference b/tests/tests-base/test-00153/stdout.reference new file mode 100644 index 0000000..c2319d8 --- /dev/null +++ b/tests/tests-base/test-00153/stdout.reference @@ -0,0 +1,5 @@ +C9 +ICLASS: LEAVE CATEGORY: MISC EXTENSION: BASE IFORM: LEAVE ISA_SET: I186 +SHORT: leave +Encodable! C9 +Identical re-encoding diff --git a/tests/tests-base/test-00154/cmd b/tests/tests-base/test-00154/cmd new file mode 100644 index 0000000..85508e3 --- /dev/null +++ b/tests/tests-base/test-00154/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de c9 diff --git a/tests/tests-base/test-00154/codes b/tests/tests-base/test-00154/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00154/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00154/retcode.reference b/tests/tests-base/test-00154/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00154/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00154/stderr.reference b/tests/tests-base/test-00154/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00154/stdout.reference b/tests/tests-base/test-00154/stdout.reference new file mode 100644 index 0000000..c2319d8 --- /dev/null +++ b/tests/tests-base/test-00154/stdout.reference @@ -0,0 +1,5 @@ +C9 +ICLASS: LEAVE CATEGORY: MISC EXTENSION: BASE IFORM: LEAVE ISA_SET: I186 +SHORT: leave +Encodable! C9 +Identical re-encoding diff --git a/tests/tests-base/test-00155/cmd b/tests/tests-base/test-00155/cmd new file mode 100644 index 0000000..5613a00 --- /dev/null +++ b/tests/tests-base/test-00155/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 65c9 diff --git a/tests/tests-base/test-00155/codes b/tests/tests-base/test-00155/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00155/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00155/retcode.reference b/tests/tests-base/test-00155/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00155/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00155/stderr.reference b/tests/tests-base/test-00155/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00155/stdout.reference b/tests/tests-base/test-00155/stdout.reference new file mode 100644 index 0000000..b7546b2 --- /dev/null +++ b/tests/tests-base/test-00155/stdout.reference @@ -0,0 +1,3 @@ +65C9 +ICLASS: LEAVE CATEGORY: MISC EXTENSION: BASE IFORM: LEAVE ISA_SET: I186 +SHORT: leave diff --git a/tests/tests-base/test-00156/cmd b/tests/tests-base/test-00156/cmd new file mode 100644 index 0000000..13d2b80 --- /dev/null +++ b/tests/tests-base/test-00156/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 65c9 diff --git a/tests/tests-base/test-00156/codes b/tests/tests-base/test-00156/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00156/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00156/retcode.reference b/tests/tests-base/test-00156/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00156/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00156/stderr.reference b/tests/tests-base/test-00156/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00156/stdout.reference b/tests/tests-base/test-00156/stdout.reference new file mode 100644 index 0000000..b7546b2 --- /dev/null +++ b/tests/tests-base/test-00156/stdout.reference @@ -0,0 +1,3 @@ +65C9 +ICLASS: LEAVE CATEGORY: MISC EXTENSION: BASE IFORM: LEAVE ISA_SET: I186 +SHORT: leave diff --git a/tests/tests-base/test-00157/cmd b/tests/tests-base/test-00157/cmd new file mode 100644 index 0000000..a669b85 --- /dev/null +++ b/tests/tests-base/test-00157/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 6741C745FF44332211 diff --git a/tests/tests-base/test-00157/codes b/tests/tests-base/test-00157/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00157/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00157/retcode.reference b/tests/tests-base/test-00157/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00157/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00157/stderr.reference b/tests/tests-base/test-00157/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00157/stdout.reference b/tests/tests-base/test-00157/stdout.reference new file mode 100644 index 0000000..241c8b4 --- /dev/null +++ b/tests/tests-base/test-00157/stdout.reference @@ -0,0 +1,5 @@ +6741C745FF44332211 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_MEMv_IMMz ISA_SET: I86 +SHORT: mov dword ptr [r13d-0x1], 0x11223344 +Encodable! 6741C745FF44332211 +Identical re-encoding diff --git a/tests/tests-base/test-00158/cmd b/tests/tests-base/test-00158/cmd new file mode 100644 index 0000000..12e28de --- /dev/null +++ b/tests/tests-base/test-00158/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 MOV MEM4:R13D,-,-,FF IMM:11223344 diff --git a/tests/tests-base/test-00158/codes b/tests/tests-base/test-00158/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00158/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00158/retcode.reference b/tests/tests-base/test-00158/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00158/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00158/stderr.reference b/tests/tests-base/test-00158/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00158/stdout.reference b/tests/tests-base/test-00158/stdout.reference new file mode 100644 index 0000000..7f967d3 --- /dev/null +++ b/tests/tests-base/test-00158/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV DISP_WIDTH:8, EASZ:2, IMM_WIDTH:32, IMM0:0x11223344, MEM_WIDTH:4, MEM0:dword ptr [R13D-0x1], MODE:2, SMODE:2 +OPERAND ORDER: MEM0 IMM0 + +Encodable! 6741C745FF44332211 diff --git a/tests/tests-base/test-00159/cmd b/tests/tests-base/test-00159/cmd new file mode 100644 index 0000000..8cae5e8 --- /dev/null +++ b/tests/tests-base/test-00159/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d f3f267662e6465363e26c000ff diff --git a/tests/tests-base/test-00159/codes b/tests/tests-base/test-00159/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00159/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00159/retcode.reference b/tests/tests-base/test-00159/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00159/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00159/stderr.reference b/tests/tests-base/test-00159/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00159/stdout.reference b/tests/tests-base/test-00159/stdout.reference new file mode 100644 index 0000000..dde4abb --- /dev/null +++ b/tests/tests-base/test-00159/stdout.reference @@ -0,0 +1,3 @@ +F3F267662E6465363E26C000FF +ICLASS: ROL CATEGORY: ROTATE EXTENSION: BASE IFORM: ROL_MEMb_IMMb ISA_SET: I186 +SHORT: rol byte ptr gs:[eax], 0xff diff --git a/tests/tests-base/test-00160/cmd b/tests/tests-base/test-00160/cmd new file mode 100644 index 0000000..8a0d28e --- /dev/null +++ b/tests/tests-base/test-00160/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 70ff diff --git a/tests/tests-base/test-00160/codes b/tests/tests-base/test-00160/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00160/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00160/retcode.reference b/tests/tests-base/test-00160/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00160/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00160/stderr.reference b/tests/tests-base/test-00160/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00160/stdout.reference b/tests/tests-base/test-00160/stdout.reference new file mode 100644 index 0000000..0f4b254 --- /dev/null +++ b/tests/tests-base/test-00160/stdout.reference @@ -0,0 +1,3 @@ +70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: jo 0x1 diff --git a/tests/tests-base/test-00161/cmd b/tests/tests-base/test-00161/cmd new file mode 100644 index 0000000..f702198 --- /dev/null +++ b/tests/tests-base/test-00161/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 3e70ff diff --git a/tests/tests-base/test-00161/codes b/tests/tests-base/test-00161/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00161/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00161/retcode.reference b/tests/tests-base/test-00161/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00161/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00161/stderr.reference b/tests/tests-base/test-00161/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00161/stdout.reference b/tests/tests-base/test-00161/stdout.reference new file mode 100644 index 0000000..86348ef --- /dev/null +++ b/tests/tests-base/test-00161/stdout.reference @@ -0,0 +1,3 @@ +3E70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: hint-taken jo 0x2 diff --git a/tests/tests-base/test-00162/cmd b/tests/tests-base/test-00162/cmd new file mode 100644 index 0000000..faa369a --- /dev/null +++ b/tests/tests-base/test-00162/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 2e70ff diff --git a/tests/tests-base/test-00162/codes b/tests/tests-base/test-00162/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00162/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00162/retcode.reference b/tests/tests-base/test-00162/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00162/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00162/stderr.reference b/tests/tests-base/test-00162/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00162/stdout.reference b/tests/tests-base/test-00162/stdout.reference new file mode 100644 index 0000000..263f081 --- /dev/null +++ b/tests/tests-base/test-00162/stdout.reference @@ -0,0 +1,3 @@ +2E70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: hint-not-taken jo 0x2 diff --git a/tests/tests-base/test-00163/cmd b/tests/tests-base/test-00163/cmd new file mode 100644 index 0000000..1447695 --- /dev/null +++ b/tests/tests-base/test-00163/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 70ff diff --git a/tests/tests-base/test-00163/codes b/tests/tests-base/test-00163/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00163/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00163/retcode.reference b/tests/tests-base/test-00163/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00163/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00163/stderr.reference b/tests/tests-base/test-00163/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00163/stdout.reference b/tests/tests-base/test-00163/stdout.reference new file mode 100644 index 0000000..3bf0629 --- /dev/null +++ b/tests/tests-base/test-00163/stdout.reference @@ -0,0 +1,5 @@ +70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: jo 0x1 +Encodable! 70FF +Identical re-encoding diff --git a/tests/tests-base/test-00164/cmd b/tests/tests-base/test-00164/cmd new file mode 100644 index 0000000..c8d56fd --- /dev/null +++ b/tests/tests-base/test-00164/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 3e70ff diff --git a/tests/tests-base/test-00164/codes b/tests/tests-base/test-00164/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00164/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00164/retcode.reference b/tests/tests-base/test-00164/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00164/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00164/stderr.reference b/tests/tests-base/test-00164/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00164/stdout.reference b/tests/tests-base/test-00164/stdout.reference new file mode 100644 index 0000000..e6a588e --- /dev/null +++ b/tests/tests-base/test-00164/stdout.reference @@ -0,0 +1,5 @@ +3E70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: hint-taken jo 0x2 +Encodable! 3E70FF +Identical re-encoding diff --git a/tests/tests-base/test-00165/cmd b/tests/tests-base/test-00165/cmd new file mode 100644 index 0000000..3453062 --- /dev/null +++ b/tests/tests-base/test-00165/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 2e70ff diff --git a/tests/tests-base/test-00165/codes b/tests/tests-base/test-00165/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00165/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00165/retcode.reference b/tests/tests-base/test-00165/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00165/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00165/stderr.reference b/tests/tests-base/test-00165/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00165/stdout.reference b/tests/tests-base/test-00165/stdout.reference new file mode 100644 index 0000000..97e94d0 --- /dev/null +++ b/tests/tests-base/test-00165/stdout.reference @@ -0,0 +1,5 @@ +2E70FF +ICLASS: JO CATEGORY: COND_BR EXTENSION: BASE IFORM: JO_RELBRb ISA_SET: I86 +SHORT: hint-not-taken jo 0x2 +Encodable! 2E70FF +Identical re-encoding diff --git a/tests/tests-base/test-00166/cmd b/tests/tests-base/test-00166/cmd new file mode 100644 index 0000000..f60e84e --- /dev/null +++ b/tests/tests-base/test-00166/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66 0f 3a 15 c8 00 diff --git a/tests/tests-base/test-00166/codes b/tests/tests-base/test-00166/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00166/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00166/retcode.reference b/tests/tests-base/test-00166/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00166/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00166/stderr.reference b/tests/tests-base/test-00166/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00166/stdout.reference b/tests/tests-base/test-00166/stdout.reference new file mode 100644 index 0000000..41909b5 --- /dev/null +++ b/tests/tests-base/test-00166/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 66 0f 3a 15 c8 00 +iclass PEXTRW_SSE4 category SSE ISA-extension SSE4 ISA-set SSE4 +instruction-length 6 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PEXTRW_SSE4_GPR32_XMMdq_IMMb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX EXPLICIT W D 32 4 1 32 INT GPR +1 REG1 REG1=XMM1 EXPLICIT R DQ 128 16 4 32 INT XMM +2 IMM0 0x0(8b) EXPLICIT R B 8 1 1 8 UINT INVALID +Memory Operands + MemopBytes = 0 +ATTRIBUTES: +ANY 66 PREFIX +EXCEPTION TYPE: SSE_TYPE_5 +Number of legacy prefixes: 1 +ISA SET: [SSE4] +0 CPUID BIT NAME: [SSE4] + Leaf 0x00000001, subleaf 0x00000000, ECX[19] diff --git a/tests/tests-base/test-00167/cmd b/tests/tests-base/test-00167/cmd new file mode 100644 index 0000000..e05f756 --- /dev/null +++ b/tests/tests-base/test-00167/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 0f 20 c0 diff --git a/tests/tests-base/test-00167/codes b/tests/tests-base/test-00167/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00167/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00167/retcode.reference b/tests/tests-base/test-00167/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00167/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00167/stderr.reference b/tests/tests-base/test-00167/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00167/stdout.reference b/tests/tests-base/test-00167/stdout.reference new file mode 100644 index 0000000..a77a2db --- /dev/null +++ b/tests/tests-base/test-00167/stdout.reference @@ -0,0 +1,5 @@ +0F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR32_CR ISA_SET: I86 +SHORT: mov eax, cr0 +Encodable! 0F20C0 +Identical re-encoding diff --git a/tests/tests-base/test-00168/cmd b/tests/tests-base/test-00168/cmd new file mode 100644 index 0000000..744c311 --- /dev/null +++ b/tests/tests-base/test-00168/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -de 0f 20 c0 diff --git a/tests/tests-base/test-00168/codes b/tests/tests-base/test-00168/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00168/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00168/retcode.reference b/tests/tests-base/test-00168/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00168/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00168/stderr.reference b/tests/tests-base/test-00168/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00168/stdout.reference b/tests/tests-base/test-00168/stdout.reference new file mode 100644 index 0000000..a77a2db --- /dev/null +++ b/tests/tests-base/test-00168/stdout.reference @@ -0,0 +1,5 @@ +0F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR32_CR ISA_SET: I86 +SHORT: mov eax, cr0 +Encodable! 0F20C0 +Identical re-encoding diff --git a/tests/tests-base/test-00169/cmd b/tests/tests-base/test-00169/cmd new file mode 100644 index 0000000..dba9606 --- /dev/null +++ b/tests/tests-base/test-00169/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f 20 c0 diff --git a/tests/tests-base/test-00169/codes b/tests/tests-base/test-00169/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00169/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00169/retcode.reference b/tests/tests-base/test-00169/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00169/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00169/stderr.reference b/tests/tests-base/test-00169/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00169/stdout.reference b/tests/tests-base/test-00169/stdout.reference new file mode 100644 index 0000000..2d18542 --- /dev/null +++ b/tests/tests-base/test-00169/stdout.reference @@ -0,0 +1,5 @@ +0F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR64_CR ISA_SET: I86 +SHORT: mov rax, cr0 +Encodable! 0F20C0 +Identical re-encoding diff --git a/tests/tests-base/test-00170/cmd b/tests/tests-base/test-00170/cmd new file mode 100644 index 0000000..43bb722 --- /dev/null +++ b/tests/tests-base/test-00170/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de 66 0f 20 c0 diff --git a/tests/tests-base/test-00170/codes b/tests/tests-base/test-00170/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00170/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00170/retcode.reference b/tests/tests-base/test-00170/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00170/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00170/stderr.reference b/tests/tests-base/test-00170/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00170/stdout.reference b/tests/tests-base/test-00170/stdout.reference new file mode 100644 index 0000000..9efa252 --- /dev/null +++ b/tests/tests-base/test-00170/stdout.reference @@ -0,0 +1,11 @@ +660F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR32_CR ISA_SET: I86 +SHORT: mov eax, cr0 +Encodable! 0F20C0 +Discrepenacy after re-encoding. dec_len= 4 [660F20C0] enc_olen= 3 [0F20C0] for instruction: MOV_CR MOV_CR_GPR32_CR DF32, EASZ:1, EOSZ:2, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:EAX, REG1:CR0, SMODE:1, TZCNT +0 REG0/W/D/EXPLICIT/NT_LOOKUP_FN/GPR32_B +1 REG1/R/Y/EXPLICIT/NT_LOOKUP_FN/CR_R +YDIS: mov eax, cr0 +vs Encode request: MOV_CR DF32, EASZ:1, EOSZ:2, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:EAX, REG1:CR0, SMODE:1, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00171/cmd b/tests/tests-base/test-00171/cmd new file mode 100644 index 0000000..fc59efb --- /dev/null +++ b/tests/tests-base/test-00171/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -de 66 0f 20 c0 diff --git a/tests/tests-base/test-00171/codes b/tests/tests-base/test-00171/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00171/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00171/retcode.reference b/tests/tests-base/test-00171/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00171/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00171/stderr.reference b/tests/tests-base/test-00171/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00171/stdout.reference b/tests/tests-base/test-00171/stdout.reference new file mode 100644 index 0000000..2b162d6 --- /dev/null +++ b/tests/tests-base/test-00171/stdout.reference @@ -0,0 +1,11 @@ +660F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR32_CR ISA_SET: I86 +SHORT: mov eax, cr0 +Encodable! 0F20C0 +Discrepenacy after re-encoding. dec_len= 4 [660F20C0] enc_olen= 3 [0F20C0] for instruction: MOV_CR MOV_CR_GPR32_CR DF32, EASZ:2, EOSZ:2, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:1, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:EAX, REG1:CR0, SMODE:1, TZCNT +0 REG0/W/D/EXPLICIT/NT_LOOKUP_FN/GPR32_B +1 REG1/R/Y/EXPLICIT/NT_LOOKUP_FN/CR_R +YDIS: mov eax, cr0 +vs Encode request: MOV_CR DF32, EASZ:2, EOSZ:2, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:1, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:EAX, REG1:CR0, SMODE:1, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00172/cmd b/tests/tests-base/test-00172/cmd new file mode 100644 index 0000000..f55d589 --- /dev/null +++ b/tests/tests-base/test-00172/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 66 0f 20 c0 diff --git a/tests/tests-base/test-00172/codes b/tests/tests-base/test-00172/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00172/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00172/retcode.reference b/tests/tests-base/test-00172/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00172/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00172/stderr.reference b/tests/tests-base/test-00172/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00172/stdout.reference b/tests/tests-base/test-00172/stdout.reference new file mode 100644 index 0000000..d429104 --- /dev/null +++ b/tests/tests-base/test-00172/stdout.reference @@ -0,0 +1,11 @@ +660F20C0 +ICLASS: MOV_CR CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_CR_GPR64_CR ISA_SET: I86 +SHORT: mov rax, cr0 +Encodable! 0F20C0 +Discrepenacy after re-encoding. dec_len= 4 [660F20C0] enc_olen= 3 [0F20C0] for instruction: MOV_CR MOV_CR_GPR64_CR DF64, EASZ:3, EOSZ:3, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:2, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:RAX, REG1:CR0, SMODE:2, TZCNT +0 REG0/W/Q/EXPLICIT/NT_LOOKUP_FN/GPR64_B +1 REG1/R/Y/EXPLICIT/NT_LOOKUP_FN/CR_R +YDIS: mov rax, cr0 +vs Encode request: MOV_CR DF64, EASZ:3, EOSZ:3, HAS_MODRM:2, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:2, MODRM_BYTE:192, NOMINAL_OPCODE:32, NPREFIXES:1, OUTREG:CR0, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, PREFIX66, REG0:RAX, REG1:CR0, SMODE:2, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00173/cmd b/tests/tests-base/test-00173/cmd new file mode 100644 index 0000000..07cd5b9 --- /dev/null +++ b/tests/tests-base/test-00173/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -16 0f 20 c0 diff --git a/tests/tests-base/test-00173/codes b/tests/tests-base/test-00173/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00173/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00173/retcode.reference b/tests/tests-base/test-00173/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00173/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00173/stderr.reference b/tests/tests-base/test-00173/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00173/stdout.reference b/tests/tests-base/test-00173/stdout.reference new file mode 100644 index 0000000..f18696d --- /dev/null +++ b/tests/tests-base/test-00173/stdout.reference @@ -0,0 +1,20 @@ +Attempting to decode: 0f 20 c0 +iclass MOV_CR category DATAXFER ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 16 +stack-address-width 16 +iform-enum-name MOV_CR_GPR32_CR +iform-enum-name-dispatch (zero based) 2 +iclass-max-iform-dispatch 4 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX EXPLICIT W D 32 4 1 32 INT GPR +1 REG1 REG1=CR0 EXPLICIT R Y 32 4 1 32 INT CR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: RING0 +RING0 only +ISA SET: [I86] diff --git a/tests/tests-base/test-00174/cmd b/tests/tests-base/test-00174/cmd new file mode 100644 index 0000000..b946be4 --- /dev/null +++ b/tests/tests-base/test-00174/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0f 20 c0 diff --git a/tests/tests-base/test-00174/codes b/tests/tests-base/test-00174/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00174/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00174/retcode.reference b/tests/tests-base/test-00174/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00174/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00174/stderr.reference b/tests/tests-base/test-00174/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00174/stdout.reference b/tests/tests-base/test-00174/stdout.reference new file mode 100644 index 0000000..9cfe7f1 --- /dev/null +++ b/tests/tests-base/test-00174/stdout.reference @@ -0,0 +1,20 @@ +Attempting to decode: 0f 20 c0 +iclass MOV_CR category DATAXFER ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOV_CR_GPR32_CR +iform-enum-name-dispatch (zero based) 2 +iclass-max-iform-dispatch 4 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX EXPLICIT W D 32 4 1 32 INT GPR +1 REG1 REG1=CR0 EXPLICIT R Y 32 4 1 32 INT CR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: RING0 +RING0 only +ISA SET: [I86] diff --git a/tests/tests-base/test-00175/cmd b/tests/tests-base/test-00175/cmd new file mode 100644 index 0000000..0e3c893 --- /dev/null +++ b/tests/tests-base/test-00175/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 0f 20 c0 diff --git a/tests/tests-base/test-00175/codes b/tests/tests-base/test-00175/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00175/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00175/retcode.reference b/tests/tests-base/test-00175/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00175/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00175/stderr.reference b/tests/tests-base/test-00175/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00175/stdout.reference b/tests/tests-base/test-00175/stdout.reference new file mode 100644 index 0000000..55ab38f --- /dev/null +++ b/tests/tests-base/test-00175/stdout.reference @@ -0,0 +1,20 @@ +Attempting to decode: 0f 20 c0 +iclass MOV_CR category DATAXFER ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name MOV_CR_GPR64_CR +iform-enum-name-dispatch (zero based) 3 +iclass-max-iform-dispatch 4 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX EXPLICIT W Q 64 8 1 64 INT GPR +1 REG1 REG1=CR0 EXPLICIT R Y 64 8 1 64 INT CR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: RING0 +RING0 only +ISA SET: [I86] diff --git a/tests/tests-base/test-00176/cmd b/tests/tests-base/test-00176/cmd new file mode 100644 index 0000000..b5037a1 --- /dev/null +++ b/tests/tests-base/test-00176/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -16 mov_cr eax cr0 diff --git a/tests/tests-base/test-00176/codes b/tests/tests-base/test-00176/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00176/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00176/retcode.reference b/tests/tests-base/test-00176/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00176/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00176/stderr.reference b/tests/tests-base/test-00176/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00176/stdout.reference b/tests/tests-base/test-00176/stdout.reference new file mode 100644 index 0000000..a0f75a9 --- /dev/null +++ b/tests/tests-base/test-00176/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV_CR REG0:EAX, REG1:CR0, SMODE:1 +OPERAND ORDER: REG0 REG1 + +Encodable! 0F2000 diff --git a/tests/tests-base/test-00177/cmd b/tests/tests-base/test-00177/cmd new file mode 100644 index 0000000..6417b23 --- /dev/null +++ b/tests/tests-base/test-00177/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -32 mov_cr eax cr0 diff --git a/tests/tests-base/test-00177/codes b/tests/tests-base/test-00177/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00177/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00177/retcode.reference b/tests/tests-base/test-00177/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00177/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00177/stderr.reference b/tests/tests-base/test-00177/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00177/stdout.reference b/tests/tests-base/test-00177/stdout.reference new file mode 100644 index 0000000..b86e95f --- /dev/null +++ b/tests/tests-base/test-00177/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV_CR MODE:1, REG0:EAX, REG1:CR0, SMODE:1 +OPERAND ORDER: REG0 REG1 + +Encodable! 0F2000 diff --git a/tests/tests-base/test-00178/cmd b/tests/tests-base/test-00178/cmd new file mode 100644 index 0000000..233f25e --- /dev/null +++ b/tests/tests-base/test-00178/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 mov_cr rax cr0 diff --git a/tests/tests-base/test-00178/codes b/tests/tests-base/test-00178/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00178/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00178/retcode.reference b/tests/tests-base/test-00178/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00178/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00178/stderr.reference b/tests/tests-base/test-00178/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00178/stdout.reference b/tests/tests-base/test-00178/stdout.reference new file mode 100644 index 0000000..a82ff94 --- /dev/null +++ b/tests/tests-base/test-00178/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +MOV_CR MODE:2, REG0:RAX, REG1:CR0, SMODE:2 +OPERAND ORDER: REG0 REG1 + +Encodable! 0F2000 diff --git a/tests/tests-base/test-00179/cmd b/tests/tests-base/test-00179/cmd new file mode 100644 index 0000000..45ab4b5 --- /dev/null +++ b/tests/tests-base/test-00179/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f2 f3 64 67 3e 66 2e 36 65 26 f3 0f 2c 0f diff --git a/tests/tests-base/test-00179/codes b/tests/tests-base/test-00179/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00179/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00179/retcode.reference b/tests/tests-base/test-00179/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00179/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00179/stderr.reference b/tests/tests-base/test-00179/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00179/stdout.reference b/tests/tests-base/test-00179/stdout.reference new file mode 100644 index 0000000..062b41e --- /dev/null +++ b/tests/tests-base/test-00179/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: f2 f3 64 67 3e 66 2e 36 65 26 f3 0f 2c 0f +iclass CVTTSS2SI category CONVERT ISA-extension SSE ISA-set SSE +instruction-length 14 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 64 +iform-enum-name CVTTSS2SI_GPR32d_MEMss +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 4 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=ECX EXPLICIT W D 32 4 1 32 INT GPR +1 MEM0 (see below) EXPLICIT R SS 32 4 1 32 SINGLE INVALID +Memory Operands + 0 read SEG= GS BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +ATTRIBUTES: MXCSR SIMD_SCALAR +F3 PREFIX +67 PREFIX +ANY 66 PREFIX +EXCEPTION TYPE: SSE_TYPE_3 +Number of legacy prefixes: 11 +ISA SET: [SSE] +0 CPUID BIT NAME: [SSE] + Leaf 0x00000001, subleaf 0x00000000, EDX[25] diff --git a/tests/tests-base/test-00180/cmd b/tests/tests-base/test-00180/cmd new file mode 100644 index 0000000..8fe2b56 --- /dev/null +++ b/tests/tests-base/test-00180/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 f2 67 66 2e 64 65 36 3e 26 d0 00 diff --git a/tests/tests-base/test-00180/codes b/tests/tests-base/test-00180/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00180/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00180/retcode.reference b/tests/tests-base/test-00180/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00180/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00180/stderr.reference b/tests/tests-base/test-00180/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00180/stdout.reference b/tests/tests-base/test-00180/stdout.reference new file mode 100644 index 0000000..44e5d2c --- /dev/null +++ b/tests/tests-base/test-00180/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 f2 67 66 2e 64 65 36 3e 26 d0 00 +iclass ROL category ROTATE ISA-extension BASE ISA-set I86 +instruction-length 12 +operand-width 8 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 64 +iform-enum-name ROL_MEMb_ONE +iform-enum-name-dispatch (zero based) 8 +iclass-max-iform-dispatch 12 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) EXPLICIT RW B 8 1 1 8 UINT INVALID +1 IMM0 0x1(8b) IMPLICIT R B 8 1 1 8 UINT INVALID +2 REG0 REG0=RFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read written SEG= GS BASE= EAX/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + must-write-rflags of-mod cf-mod + read: mask=0x0 + written: of cf mask=0x801 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP IMPLICIT_ONE +F2 PREFIX +67 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 10 +ISA SET: [I86] diff --git a/tests/tests-base/test-00181/cmd b/tests/tests-base/test-00181/cmd new file mode 100644 index 0000000..c2e6d5a --- /dev/null +++ b/tests/tests-base/test-00181/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip I286 da c0 diff --git a/tests/tests-base/test-00181/codes b/tests/tests-base/test-00181/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00181/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00181/retcode.reference b/tests/tests-base/test-00181/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00181/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00181/stderr.reference b/tests/tests-base/test-00181/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00181/stdout.reference b/tests/tests-base/test-00181/stdout.reference new file mode 100644 index 0000000..d95cf94 --- /dev/null +++ b/tests/tests-base/test-00181/stdout.reference @@ -0,0 +1,3 @@ +Setting chip to I286 +Attempting to decode: da c0 +The instruction was not valid for the specified chip. diff --git a/tests/tests-base/test-00182/cmd b/tests/tests-base/test-00182/cmd new file mode 100644 index 0000000..a48ddf9 --- /dev/null +++ b/tests/tests-base/test-00182/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO da c0 diff --git a/tests/tests-base/test-00182/codes b/tests/tests-base/test-00182/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00182/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00182/retcode.reference b/tests/tests-base/test-00182/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00182/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00182/stderr.reference b/tests/tests-base/test-00182/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00182/stdout.reference b/tests/tests-base/test-00182/stdout.reference new file mode 100644 index 0000000..02025bb --- /dev/null +++ b/tests/tests-base/test-00182/stdout.reference @@ -0,0 +1,27 @@ +Setting chip to PENTIUMPRO +Attempting to decode: da c0 +iclass FCMOVB category FCMOV ISA-extension X87 ISA-set PPRO +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name FCMOVB_ST0_X87 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=st(0) IMPLICIT CW F80 80 10 1 80 LONGDOUBLE X87 +1 REG1 REG1=st(0) EXPLICIT R F80 80 10 1 80 LONGDOUBLE X87 +2 REG2 REG2=X87STATUS SUPPRESSED W PSEUDO 0 0 1 0 INT PSEUDOX87 +3 REG3 REG3=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags cf-tst fc0-u fc1-mod fc2-u fc3-u + read: cf mask=0x1 + written: fc0 fc1 fc2 fc3 mask=0xf0000000 + undefined: fc0 fc2 fc3 mask=0xd0000000 +ATTRIBUTES: NOTSX +ISA SET: [PPRO] diff --git a/tests/tests-base/test-00183/cmd b/tests/tests-base/test-00183/cmd new file mode 100644 index 0000000..13ba802 --- /dev/null +++ b/tests/tests-base/test-00183/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip SALTWELL da c0 diff --git a/tests/tests-base/test-00183/codes b/tests/tests-base/test-00183/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00183/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00183/retcode.reference b/tests/tests-base/test-00183/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00183/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00183/stderr.reference b/tests/tests-base/test-00183/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00183/stdout.reference b/tests/tests-base/test-00183/stdout.reference new file mode 100644 index 0000000..50c67cf --- /dev/null +++ b/tests/tests-base/test-00183/stdout.reference @@ -0,0 +1,27 @@ +Setting chip to SALTWELL +Attempting to decode: da c0 +iclass FCMOVB category FCMOV ISA-extension X87 ISA-set PPRO +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name FCMOVB_ST0_X87 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=st(0) IMPLICIT CW F80 80 10 1 80 LONGDOUBLE X87 +1 REG1 REG1=st(0) EXPLICIT R F80 80 10 1 80 LONGDOUBLE X87 +2 REG2 REG2=X87STATUS SUPPRESSED W PSEUDO 0 0 1 0 INT PSEUDOX87 +3 REG3 REG3=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags cf-tst fc0-u fc1-mod fc2-u fc3-u + read: cf mask=0x1 + written: fc0 fc1 fc2 fc3 mask=0xf0000000 + undefined: fc0 fc2 fc3 mask=0xd0000000 +ATTRIBUTES: NOTSX +ISA SET: [PPRO] diff --git a/tests/tests-base/test-00184/cmd b/tests/tests-base/test-00184/cmd new file mode 100644 index 0000000..fbf55ca --- /dev/null +++ b/tests/tests-base/test-00184/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex4 -xml f0 00 00 diff --git a/tests/tests-base/test-00184/codes b/tests/tests-base/test-00184/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00184/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00184/retcode.reference b/tests/tests-base/test-00184/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00184/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00184/stderr.reference b/tests/tests-base/test-00184/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00184/stdout.reference b/tests/tests-base/test-00184/stdout.reference new file mode 100644 index 0000000..39cfd80 --- /dev/null +++ b/tests/tests-base/test-00184/stdout.reference @@ -0,0 +1,9 @@ +PARSING BYTES: f0 00 00 +ADD_LOCK ADD_LOCK_MEMb_GPR8 EASZ:2, EOSZ:2, HAS_MODRM:1, LOCK, LZCNT, MAX_BYTES:3, MEM0:ptr DS[EAX], MODE:1, MODRM, NPREFIXES:1, OUTREG:EFLAGS, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, REG0:AL, REG1:EFLAGS, SMODE:1, TZCNT, USING_DEFAULT_SEGMENT0 +0 MEM0/RW/B/EXPLICIT/IMM_CONST/1 +1 REG0/R/B/EXPLICIT/NT_LOOKUP_FN/GPR8_R +2 REG1/W/Y/SUPPRESSED/NT_LOOKUP_FN/RFLAGS +YDIS: lock add byte ptr [eax], al +XED syntax: ADD_LOCK EASZ:2, EOSZ:2, HAS_MODRM:1, LOCK, LZCNT, MAX_BYTES:3, MEM0:ptr DS[EAX], MODE:1, MODRM, NPREFIXES:1, OUTREG:EFLAGS, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, REG0:AL, REG1:EFLAGS, SMODE:1, TZCNT, USING_DEFAULT_SEGMENT0 +ATT syntax: lock addb %al, (%eax) +INTEL syntax: lock add byte ptr [eax], al diff --git a/tests/tests-base/test-00185/cmd b/tests/tests-base/test-00185/cmd new file mode 100644 index 0000000..2368031 --- /dev/null +++ b/tests/tests-base/test-00185/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex4 8B 44 18 00 diff --git a/tests/tests-base/test-00185/codes b/tests/tests-base/test-00185/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00185/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00185/retcode.reference b/tests/tests-base/test-00185/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00185/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00185/stderr.reference b/tests/tests-base/test-00185/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00185/stdout.reference b/tests/tests-base/test-00185/stdout.reference new file mode 100644 index 0000000..c5568ed --- /dev/null +++ b/tests/tests-base/test-00185/stdout.reference @@ -0,0 +1,8 @@ +PARSING BYTES: 8b 44 18 00 +MOV MOV_GPRv_MEMv DISP_WIDTH:8, EASZ:2, EOSZ:2, HAS_SIB, HAS_MODRM:1, LZCNT, MAX_BYTES:4, MEM0:ptr DS[EAX+EBX*1], MOD:1, MODE:1, MODRM, MODRM_BYTE:68, NEED_MEMDISP:8, NOMINAL_OPCODE:139, OUTREG:EAX, P4, POS_SIB:2, POS_DISP:3, POS_MODRM:1, REG0:EAX, RM:4, SIBINDEX:3, SMODE:1, SRM:3, TZCNT, USING_DEFAULT_SEGMENT0 +0 REG0/W/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +1 MEM0/R/V/EXPLICIT/IMM_CONST/1 +YDIS: mov eax, dword ptr [eax+ebx*1] +XED syntax: MOV DISP_WIDTH:8, EASZ:2, EOSZ:2, HAS_SIB, HAS_MODRM:1, LZCNT, MAX_BYTES:4, MEM0:ptr DS[EAX+EBX*1], MOD:1, MODE:1, MODRM, MODRM_BYTE:68, NEED_MEMDISP:8, NOMINAL_OPCODE:139, OUTREG:EAX, P4, POS_SIB:2, POS_DISP:3, POS_MODRM:1, REG0:EAX, RM:4, SIBINDEX:3, SMODE:1, SRM:3, TZCNT, USING_DEFAULT_SEGMENT0 +ATT syntax: movl (%eax,%ebx,1), %eax +INTEL syntax: mov eax, dword ptr [eax+ebx*1] diff --git a/tests/tests-base/test-00186/cmd b/tests/tests-base/test-00186/cmd new file mode 100644 index 0000000..c3a2394 --- /dev/null +++ b/tests/tests-base/test-00186/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex4 -no-unit-scale 8B 44 18 00 diff --git a/tests/tests-base/test-00186/codes b/tests/tests-base/test-00186/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00186/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00186/retcode.reference b/tests/tests-base/test-00186/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00186/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00186/stderr.reference b/tests/tests-base/test-00186/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00186/stdout.reference b/tests/tests-base/test-00186/stdout.reference new file mode 100644 index 0000000..56685c7 --- /dev/null +++ b/tests/tests-base/test-00186/stdout.reference @@ -0,0 +1,8 @@ +PARSING BYTES: 8b 44 18 00 +MOV MOV_GPRv_MEMv DISP_WIDTH:8, EASZ:2, EOSZ:2, HAS_SIB, HAS_MODRM:1, LZCNT, MAX_BYTES:4, MEM0:ptr DS[EAX+EBX*1], MOD:1, MODE:1, MODRM, MODRM_BYTE:68, NEED_MEMDISP:8, NOMINAL_OPCODE:139, OUTREG:EAX, P4, POS_SIB:2, POS_DISP:3, POS_MODRM:1, REG0:EAX, RM:4, SIBINDEX:3, SMODE:1, SRM:3, TZCNT, USING_DEFAULT_SEGMENT0 +0 REG0/W/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +1 MEM0/R/V/EXPLICIT/IMM_CONST/1 +YDIS: mov eax, dword ptr [eax+ebx] +XED syntax: MOV DISP_WIDTH:8, EASZ:2, EOSZ:2, HAS_SIB, HAS_MODRM:1, LZCNT, MAX_BYTES:4, MEM0:ptr DS[EAX+EBX*1], MOD:1, MODE:1, MODRM, MODRM_BYTE:68, NEED_MEMDISP:8, NOMINAL_OPCODE:139, OUTREG:EAX, P4, POS_SIB:2, POS_DISP:3, POS_MODRM:1, REG0:EAX, RM:4, SIBINDEX:3, SMODE:1, SRM:3, TZCNT, USING_DEFAULT_SEGMENT0 +ATT syntax: movl (%eax,%ebx,1), %eax +INTEL syntax: mov eax, dword ptr [eax+ebx] diff --git a/tests/tests-base/test-00187/cmd b/tests/tests-base/test-00187/cmd new file mode 100644 index 0000000..2075e69 --- /dev/null +++ b/tests/tests-base/test-00187/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM a7 diff --git a/tests/tests-base/test-00187/codes b/tests/tests-base/test-00187/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00187/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00187/retcode.reference b/tests/tests-base/test-00187/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00187/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00187/stderr.reference b/tests/tests-base/test-00187/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00187/stdout.reference b/tests/tests-base/test-00187/stdout.reference new file mode 100644 index 0000000..d5d8cef --- /dev/null +++ b/tests/tests-base/test-00187/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: a7 +iclass CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00188/cmd b/tests/tests-base/test-00188/cmd new file mode 100644 index 0000000..c1c75e2 --- /dev/null +++ b/tests/tests-base/test-00188/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 a7 diff --git a/tests/tests-base/test-00188/codes b/tests/tests-base/test-00188/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00188/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00188/retcode.reference b/tests/tests-base/test-00188/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00188/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00188/stderr.reference b/tests/tests-base/test-00188/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00188/stdout.reference b/tests/tests-base/test-00188/stdout.reference new file mode 100644 index 0000000..be67a7f --- /dev/null +++ b/tests/tests-base/test-00188/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUM +Attempting to decode: f3 a7 +iclass REPE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00189/cmd b/tests/tests-base/test-00189/cmd new file mode 100644 index 0000000..7400609 --- /dev/null +++ b/tests/tests-base/test-00189/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 a7 diff --git a/tests/tests-base/test-00189/codes b/tests/tests-base/test-00189/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00189/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00189/retcode.reference b/tests/tests-base/test-00189/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00189/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00189/stderr.reference b/tests/tests-base/test-00189/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00189/stdout.reference b/tests/tests-base/test-00189/stdout.reference new file mode 100644 index 0000000..b34bdb7 --- /dev/null +++ b/tests/tests-base/test-00189/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUM +Attempting to decode: f2 a7 +iclass REPNE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00190/cmd b/tests/tests-base/test-00190/cmd new file mode 100644 index 0000000..263e625 --- /dev/null +++ b/tests/tests-base/test-00190/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 a7 diff --git a/tests/tests-base/test-00190/codes b/tests/tests-base/test-00190/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00190/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00190/retcode.reference b/tests/tests-base/test-00190/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00190/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00190/stderr.reference b/tests/tests-base/test-00190/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00190/stdout.reference b/tests/tests-base/test-00190/stdout.reference new file mode 100644 index 0000000..8792b1f --- /dev/null +++ b/tests/tests-base/test-00190/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUM +Attempting to decode: f2 f3 a7 +iclass REPNE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I386] diff --git a/tests/tests-base/test-00191/cmd b/tests/tests-base/test-00191/cmd new file mode 100644 index 0000000..1c0d666 --- /dev/null +++ b/tests/tests-base/test-00191/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 a7 diff --git a/tests/tests-base/test-00191/codes b/tests/tests-base/test-00191/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00191/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00191/retcode.reference b/tests/tests-base/test-00191/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00191/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00191/stderr.reference b/tests/tests-base/test-00191/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00191/stdout.reference b/tests/tests-base/test-00191/stdout.reference new file mode 100644 index 0000000..b72e2e1 --- /dev/null +++ b/tests/tests-base/test-00191/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUM +Attempting to decode: f3 f2 a7 +iclass REPE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I386] diff --git a/tests/tests-base/test-00192/cmd b/tests/tests-base/test-00192/cmd new file mode 100644 index 0000000..478bfc6 --- /dev/null +++ b/tests/tests-base/test-00192/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO a7 diff --git a/tests/tests-base/test-00192/codes b/tests/tests-base/test-00192/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00192/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00192/retcode.reference b/tests/tests-base/test-00192/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00192/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00192/stderr.reference b/tests/tests-base/test-00192/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00192/stdout.reference b/tests/tests-base/test-00192/stdout.reference new file mode 100644 index 0000000..9829d53 --- /dev/null +++ b/tests/tests-base/test-00192/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: a7 +iclass CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00193/cmd b/tests/tests-base/test-00193/cmd new file mode 100644 index 0000000..8c7bf2a --- /dev/null +++ b/tests/tests-base/test-00193/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 a7 diff --git a/tests/tests-base/test-00193/codes b/tests/tests-base/test-00193/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00193/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00193/retcode.reference b/tests/tests-base/test-00193/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00193/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00193/stderr.reference b/tests/tests-base/test-00193/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00193/stdout.reference b/tests/tests-base/test-00193/stdout.reference new file mode 100644 index 0000000..2886840 --- /dev/null +++ b/tests/tests-base/test-00193/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 a7 +iclass REPE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00194/cmd b/tests/tests-base/test-00194/cmd new file mode 100644 index 0000000..d50b719 --- /dev/null +++ b/tests/tests-base/test-00194/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 a7 diff --git a/tests/tests-base/test-00194/codes b/tests/tests-base/test-00194/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00194/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00194/retcode.reference b/tests/tests-base/test-00194/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00194/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00194/stderr.reference b/tests/tests-base/test-00194/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00194/stdout.reference b/tests/tests-base/test-00194/stdout.reference new file mode 100644 index 0000000..2894f50 --- /dev/null +++ b/tests/tests-base/test-00194/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 a7 +iclass REPNE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00195/cmd b/tests/tests-base/test-00195/cmd new file mode 100644 index 0000000..a0b0702 --- /dev/null +++ b/tests/tests-base/test-00195/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 a7 diff --git a/tests/tests-base/test-00195/codes b/tests/tests-base/test-00195/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00195/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00195/retcode.reference b/tests/tests-base/test-00195/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00195/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00195/stderr.reference b/tests/tests-base/test-00195/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00195/stdout.reference b/tests/tests-base/test-00195/stdout.reference new file mode 100644 index 0000000..953ff48 --- /dev/null +++ b/tests/tests-base/test-00195/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 f3 a7 +iclass REPE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I386] diff --git a/tests/tests-base/test-00196/cmd b/tests/tests-base/test-00196/cmd new file mode 100644 index 0000000..5bf7721 --- /dev/null +++ b/tests/tests-base/test-00196/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 a7 diff --git a/tests/tests-base/test-00196/codes b/tests/tests-base/test-00196/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00196/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00196/retcode.reference b/tests/tests-base/test-00196/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00196/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00196/stderr.reference b/tests/tests-base/test-00196/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00196/stdout.reference b/tests/tests-base/test-00196/stdout.reference new file mode 100644 index 0000000..ba2aab6 --- /dev/null +++ b/tests/tests-base/test-00196/stdout.reference @@ -0,0 +1,35 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 f2 a7 +iclass REPNE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I386] diff --git a/tests/tests-base/test-00197/cmd b/tests/tests-base/test-00197/cmd new file mode 100644 index 0000000..2215d66 --- /dev/null +++ b/tests/tests-base/test-00197/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM e0 aa diff --git a/tests/tests-base/test-00197/codes b/tests/tests-base/test-00197/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00197/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00197/retcode.reference b/tests/tests-base/test-00197/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00197/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00197/stderr.reference b/tests/tests-base/test-00197/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00197/stdout.reference b/tests/tests-base/test-00197/stdout.reference new file mode 100644 index 0000000..0d93a55 --- /dev/null +++ b/tests/tests-base/test-00197/stdout.reference @@ -0,0 +1,28 @@ +Setting chip to PENTIUM +Attempting to decode: e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +ISA SET: [I86] diff --git a/tests/tests-base/test-00198/cmd b/tests/tests-base/test-00198/cmd new file mode 100644 index 0000000..e05cfca --- /dev/null +++ b/tests/tests-base/test-00198/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 e0 aa diff --git a/tests/tests-base/test-00198/codes b/tests/tests-base/test-00198/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00198/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00198/retcode.reference b/tests/tests-base/test-00198/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00198/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00198/stderr.reference b/tests/tests-base/test-00198/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00198/stdout.reference b/tests/tests-base/test-00198/stdout.reference new file mode 100644 index 0000000..556b9a6 --- /dev/null +++ b/tests/tests-base/test-00198/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f2 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00199/cmd b/tests/tests-base/test-00199/cmd new file mode 100644 index 0000000..8a3d913 --- /dev/null +++ b/tests/tests-base/test-00199/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 e0 aa diff --git a/tests/tests-base/test-00199/codes b/tests/tests-base/test-00199/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00199/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00199/retcode.reference b/tests/tests-base/test-00199/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00199/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00199/stderr.reference b/tests/tests-base/test-00199/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00199/stdout.reference b/tests/tests-base/test-00199/stdout.reference new file mode 100644 index 0000000..7216253 --- /dev/null +++ b/tests/tests-base/test-00199/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f3 e0 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00200/cmd b/tests/tests-base/test-00200/cmd new file mode 100644 index 0000000..fb5fdbc --- /dev/null +++ b/tests/tests-base/test-00200/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 e0 aa diff --git a/tests/tests-base/test-00200/codes b/tests/tests-base/test-00200/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00200/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00200/retcode.reference b/tests/tests-base/test-00200/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00200/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00200/stderr.reference b/tests/tests-base/test-00200/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00200/stdout.reference b/tests/tests-base/test-00200/stdout.reference new file mode 100644 index 0000000..03ae015 --- /dev/null +++ b/tests/tests-base/test-00200/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f3 f2 e0 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00201/cmd b/tests/tests-base/test-00201/cmd new file mode 100644 index 0000000..f95f63c --- /dev/null +++ b/tests/tests-base/test-00201/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 e0 aa diff --git a/tests/tests-base/test-00201/codes b/tests/tests-base/test-00201/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00201/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00201/retcode.reference b/tests/tests-base/test-00201/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00201/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00201/stderr.reference b/tests/tests-base/test-00201/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00201/stdout.reference b/tests/tests-base/test-00201/stdout.reference new file mode 100644 index 0000000..64302dc --- /dev/null +++ b/tests/tests-base/test-00201/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f2 f3 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00202/cmd b/tests/tests-base/test-00202/cmd new file mode 100644 index 0000000..3382bd7 --- /dev/null +++ b/tests/tests-base/test-00202/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM e1 aa diff --git a/tests/tests-base/test-00202/codes b/tests/tests-base/test-00202/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00202/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00202/retcode.reference b/tests/tests-base/test-00202/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00202/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00202/stderr.reference b/tests/tests-base/test-00202/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00202/stdout.reference b/tests/tests-base/test-00202/stdout.reference new file mode 100644 index 0000000..e404a6f --- /dev/null +++ b/tests/tests-base/test-00202/stdout.reference @@ -0,0 +1,28 @@ +Setting chip to PENTIUM +Attempting to decode: e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +ISA SET: [I86] diff --git a/tests/tests-base/test-00203/cmd b/tests/tests-base/test-00203/cmd new file mode 100644 index 0000000..9e703f9 --- /dev/null +++ b/tests/tests-base/test-00203/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 e1 aa diff --git a/tests/tests-base/test-00203/codes b/tests/tests-base/test-00203/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00203/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00203/retcode.reference b/tests/tests-base/test-00203/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00203/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00203/stderr.reference b/tests/tests-base/test-00203/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00203/stdout.reference b/tests/tests-base/test-00203/stdout.reference new file mode 100644 index 0000000..7d275b4 --- /dev/null +++ b/tests/tests-base/test-00203/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f2 e1 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00204/cmd b/tests/tests-base/test-00204/cmd new file mode 100644 index 0000000..9a1cc43 --- /dev/null +++ b/tests/tests-base/test-00204/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 e1 aa diff --git a/tests/tests-base/test-00204/codes b/tests/tests-base/test-00204/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00204/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00204/retcode.reference b/tests/tests-base/test-00204/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00204/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00204/stderr.reference b/tests/tests-base/test-00204/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00204/stdout.reference b/tests/tests-base/test-00204/stdout.reference new file mode 100644 index 0000000..2a96288 --- /dev/null +++ b/tests/tests-base/test-00204/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f3 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00205/cmd b/tests/tests-base/test-00205/cmd new file mode 100644 index 0000000..c448bf1 --- /dev/null +++ b/tests/tests-base/test-00205/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f3 f2 e1 aa diff --git a/tests/tests-base/test-00205/codes b/tests/tests-base/test-00205/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00205/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00205/retcode.reference b/tests/tests-base/test-00205/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00205/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00205/stderr.reference b/tests/tests-base/test-00205/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00205/stdout.reference b/tests/tests-base/test-00205/stdout.reference new file mode 100644 index 0000000..b8e15d6 --- /dev/null +++ b/tests/tests-base/test-00205/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f3 f2 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00206/cmd b/tests/tests-base/test-00206/cmd new file mode 100644 index 0000000..6b89b86 --- /dev/null +++ b/tests/tests-base/test-00206/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUM f2 f3 e1 aa diff --git a/tests/tests-base/test-00206/codes b/tests/tests-base/test-00206/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00206/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00206/retcode.reference b/tests/tests-base/test-00206/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00206/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00206/stderr.reference b/tests/tests-base/test-00206/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00206/stdout.reference b/tests/tests-base/test-00206/stdout.reference new file mode 100644 index 0000000..f0978e6 --- /dev/null +++ b/tests/tests-base/test-00206/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUM +Attempting to decode: f2 f3 e1 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00207/cmd b/tests/tests-base/test-00207/cmd new file mode 100644 index 0000000..3cc2f87 --- /dev/null +++ b/tests/tests-base/test-00207/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO e0 aa diff --git a/tests/tests-base/test-00207/codes b/tests/tests-base/test-00207/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00207/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00207/retcode.reference b/tests/tests-base/test-00207/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00207/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00207/stderr.reference b/tests/tests-base/test-00207/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00207/stdout.reference b/tests/tests-base/test-00207/stdout.reference new file mode 100644 index 0000000..55bbdca --- /dev/null +++ b/tests/tests-base/test-00207/stdout.reference @@ -0,0 +1,28 @@ +Setting chip to PENTIUMPRO +Attempting to decode: e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +ISA SET: [I86] diff --git a/tests/tests-base/test-00208/cmd b/tests/tests-base/test-00208/cmd new file mode 100644 index 0000000..40a5179 --- /dev/null +++ b/tests/tests-base/test-00208/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 e0 aa diff --git a/tests/tests-base/test-00208/codes b/tests/tests-base/test-00208/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00208/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00208/retcode.reference b/tests/tests-base/test-00208/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00208/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00208/stderr.reference b/tests/tests-base/test-00208/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00208/stdout.reference b/tests/tests-base/test-00208/stdout.reference new file mode 100644 index 0000000..302acec --- /dev/null +++ b/tests/tests-base/test-00208/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00209/cmd b/tests/tests-base/test-00209/cmd new file mode 100644 index 0000000..2f9e468 --- /dev/null +++ b/tests/tests-base/test-00209/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 e0 aa diff --git a/tests/tests-base/test-00209/codes b/tests/tests-base/test-00209/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00209/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00209/retcode.reference b/tests/tests-base/test-00209/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00209/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00209/stderr.reference b/tests/tests-base/test-00209/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00209/stdout.reference b/tests/tests-base/test-00209/stdout.reference new file mode 100644 index 0000000..d1fa5ea --- /dev/null +++ b/tests/tests-base/test-00209/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00210/cmd b/tests/tests-base/test-00210/cmd new file mode 100644 index 0000000..90f9a54 --- /dev/null +++ b/tests/tests-base/test-00210/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 e0 aa diff --git a/tests/tests-base/test-00210/codes b/tests/tests-base/test-00210/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00210/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00210/retcode.reference b/tests/tests-base/test-00210/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00210/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00210/stderr.reference b/tests/tests-base/test-00210/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00210/stdout.reference b/tests/tests-base/test-00210/stdout.reference new file mode 100644 index 0000000..1a76828 --- /dev/null +++ b/tests/tests-base/test-00210/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 f2 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00211/cmd b/tests/tests-base/test-00211/cmd new file mode 100644 index 0000000..dd2e053 --- /dev/null +++ b/tests/tests-base/test-00211/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 e0 aa diff --git a/tests/tests-base/test-00211/codes b/tests/tests-base/test-00211/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00211/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00211/retcode.reference b/tests/tests-base/test-00211/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00211/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00211/stderr.reference b/tests/tests-base/test-00211/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00211/stdout.reference b/tests/tests-base/test-00211/stdout.reference new file mode 100644 index 0000000..716b15f --- /dev/null +++ b/tests/tests-base/test-00211/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 f3 e0 aa +iclass LOOPNE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPNE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00212/cmd b/tests/tests-base/test-00212/cmd new file mode 100644 index 0000000..56efa26 --- /dev/null +++ b/tests/tests-base/test-00212/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO e1 aa diff --git a/tests/tests-base/test-00212/codes b/tests/tests-base/test-00212/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00212/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00212/retcode.reference b/tests/tests-base/test-00212/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00212/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00212/stderr.reference b/tests/tests-base/test-00212/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00212/stdout.reference b/tests/tests-base/test-00212/stdout.reference new file mode 100644 index 0000000..29e9c74 --- /dev/null +++ b/tests/tests-base/test-00212/stdout.reference @@ -0,0 +1,28 @@ +Setting chip to PENTIUMPRO +Attempting to decode: e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +ISA SET: [I86] diff --git a/tests/tests-base/test-00213/cmd b/tests/tests-base/test-00213/cmd new file mode 100644 index 0000000..27b9a7a --- /dev/null +++ b/tests/tests-base/test-00213/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 e1 aa diff --git a/tests/tests-base/test-00213/codes b/tests/tests-base/test-00213/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00213/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00213/retcode.reference b/tests/tests-base/test-00213/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00213/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00213/stderr.reference b/tests/tests-base/test-00213/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00213/stdout.reference b/tests/tests-base/test-00213/stdout.reference new file mode 100644 index 0000000..c2db4f1 --- /dev/null +++ b/tests/tests-base/test-00213/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00214/cmd b/tests/tests-base/test-00214/cmd new file mode 100644 index 0000000..74dd8a8 --- /dev/null +++ b/tests/tests-base/test-00214/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 e1 aa diff --git a/tests/tests-base/test-00214/codes b/tests/tests-base/test-00214/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00214/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00214/retcode.reference b/tests/tests-base/test-00214/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00214/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00214/stderr.reference b/tests/tests-base/test-00214/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00214/stdout.reference b/tests/tests-base/test-00214/stdout.reference new file mode 100644 index 0000000..d7cda5b --- /dev/null +++ b/tests/tests-base/test-00214/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00215/cmd b/tests/tests-base/test-00215/cmd new file mode 100644 index 0000000..46b8a6a --- /dev/null +++ b/tests/tests-base/test-00215/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f3 f2 e1 aa diff --git a/tests/tests-base/test-00215/codes b/tests/tests-base/test-00215/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00215/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00215/retcode.reference b/tests/tests-base/test-00215/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00215/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00215/stderr.reference b/tests/tests-base/test-00215/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00215/stdout.reference b/tests/tests-base/test-00215/stdout.reference new file mode 100644 index 0000000..34e503f --- /dev/null +++ b/tests/tests-base/test-00215/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f3 f2 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00216/cmd b/tests/tests-base/test-00216/cmd new file mode 100644 index 0000000..c8c6c4b --- /dev/null +++ b/tests/tests-base/test-00216/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENTIUMPRO f2 f3 e1 aa diff --git a/tests/tests-base/test-00216/codes b/tests/tests-base/test-00216/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00216/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00216/retcode.reference b/tests/tests-base/test-00216/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00216/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00216/stderr.reference b/tests/tests-base/test-00216/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00216/stdout.reference b/tests/tests-base/test-00216/stdout.reference new file mode 100644 index 0000000..11443d9 --- /dev/null +++ b/tests/tests-base/test-00216/stdout.reference @@ -0,0 +1,30 @@ +Setting chip to PENTIUMPRO +Attempting to decode: f2 f3 e1 aa +iclass LOOPE category COND_BR ISA-extension BASE ISA-set I86 +instruction-length 4 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LOOPE_RELBRb +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID +1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP +3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + reads-rflags zf-tst + read: zf mask=0x40 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00217/cmd b/tests/tests-base/test-00217/cmd new file mode 100644 index 0000000..9feaea7 --- /dev/null +++ b/tests/tests-base/test-00217/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 lea r13d agen:r13d,-,-,00000000 diff --git a/tests/tests-base/test-00217/codes b/tests/tests-base/test-00217/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00217/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00217/retcode.reference b/tests/tests-base/test-00217/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00217/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00217/stderr.reference b/tests/tests-base/test-00217/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00217/stdout.reference b/tests/tests-base/test-00217/stdout.reference new file mode 100644 index 0000000..272fa2d --- /dev/null +++ b/tests/tests-base/test-00217/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13D], DISP_WIDTH:32, EASZ:2, MODE:2, REG0:R13D, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 67458DAD00000000 diff --git a/tests/tests-base/test-00218/cmd b/tests/tests-base/test-00218/cmd new file mode 100644 index 0000000..053f45e --- /dev/null +++ b/tests/tests-base/test-00218/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 lea r13d agen:r13d diff --git a/tests/tests-base/test-00218/codes b/tests/tests-base/test-00218/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00218/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00218/retcode.reference b/tests/tests-base/test-00218/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00218/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00218/stderr.reference b/tests/tests-base/test-00218/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00218/stdout.reference b/tests/tests-base/test-00218/stdout.reference new file mode 100644 index 0000000..4282793 --- /dev/null +++ b/tests/tests-base/test-00218/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +LEA AGEN:ptr [R13D], EASZ:2, MODE:2, REG0:R13D, SMODE:2 +OPERAND ORDER: REG0 AGEN + +Encodable! 67458D6D00 diff --git a/tests/tests-base/test-00219/cmd b/tests/tests-base/test-00219/cmd new file mode 100644 index 0000000..bc0bbba --- /dev/null +++ b/tests/tests-base/test-00219/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c5 1d 0000 0000 diff --git a/tests/tests-base/test-00219/codes b/tests/tests-base/test-00219/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00219/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00219/retcode.reference b/tests/tests-base/test-00219/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00219/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00219/stderr.reference b/tests/tests-base/test-00219/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00219/stdout.reference b/tests/tests-base/test-00219/stdout.reference new file mode 100644 index 0000000..3ee8d5e --- /dev/null +++ b/tests/tests-base/test-00219/stdout.reference @@ -0,0 +1,3 @@ +C51D00000000 +ICLASS: LDS CATEGORY: SEGOP EXTENSION: BASE IFORM: LDS_GPRz_MEMp ISA_SET: I86 +SHORT: lds ebx, ptr [0x0] diff --git a/tests/tests-base/test-00220/cmd b/tests/tests-base/test-00220/cmd new file mode 100644 index 0000000..18afc8c --- /dev/null +++ b/tests/tests-base/test-00220/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 66 c5 1d 0000 0000 diff --git a/tests/tests-base/test-00220/codes b/tests/tests-base/test-00220/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00220/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00220/retcode.reference b/tests/tests-base/test-00220/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00220/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00220/stderr.reference b/tests/tests-base/test-00220/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00220/stdout.reference b/tests/tests-base/test-00220/stdout.reference new file mode 100644 index 0000000..905f864 --- /dev/null +++ b/tests/tests-base/test-00220/stdout.reference @@ -0,0 +1,3 @@ +66C51D00000000 +ICLASS: LDS CATEGORY: SEGOP EXTENSION: BASE IFORM: LDS_GPRz_MEMp ISA_SET: I86 +SHORT: lds bx, dword ptr [0x0] diff --git a/tests/tests-base/test-00221/cmd b/tests/tests-base/test-00221/cmd new file mode 100644 index 0000000..42413ee --- /dev/null +++ b/tests/tests-base/test-00221/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 1d 0000 0000 diff --git a/tests/tests-base/test-00221/codes b/tests/tests-base/test-00221/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00221/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00221/retcode.reference b/tests/tests-base/test-00221/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00221/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00221/stderr.reference b/tests/tests-base/test-00221/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00221/stdout.reference b/tests/tests-base/test-00221/stdout.reference new file mode 100644 index 0000000..6dcb62a --- /dev/null +++ b/tests/tests-base/test-00221/stdout.reference @@ -0,0 +1,3 @@ +C41D00000000 +ICLASS: LES CATEGORY: SEGOP EXTENSION: BASE IFORM: LES_GPRz_MEMp ISA_SET: I86 +SHORT: les ebx, ptr [0x0] diff --git a/tests/tests-base/test-00222/cmd b/tests/tests-base/test-00222/cmd new file mode 100644 index 0000000..4d94b46 --- /dev/null +++ b/tests/tests-base/test-00222/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 66 c4 1d 0000 0000 diff --git a/tests/tests-base/test-00222/codes b/tests/tests-base/test-00222/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00222/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00222/retcode.reference b/tests/tests-base/test-00222/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00222/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00222/stderr.reference b/tests/tests-base/test-00222/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00222/stdout.reference b/tests/tests-base/test-00222/stdout.reference new file mode 100644 index 0000000..d0278da --- /dev/null +++ b/tests/tests-base/test-00222/stdout.reference @@ -0,0 +1,3 @@ +66C41D00000000 +ICLASS: LES CATEGORY: SEGOP EXTENSION: BASE IFORM: LES_GPRz_MEMp ISA_SET: I86 +SHORT: les bx, dword ptr [0x0] diff --git a/tests/tests-base/test-00223/cmd b/tests/tests-base/test-00223/cmd new file mode 100644 index 0000000..98e16ac --- /dev/null +++ b/tests/tests-base/test-00223/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -b 0xfffffff0 -16 -d e9 0d00 diff --git a/tests/tests-base/test-00223/codes b/tests/tests-base/test-00223/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00223/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00223/retcode.reference b/tests/tests-base/test-00223/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00223/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00223/stderr.reference b/tests/tests-base/test-00223/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00223/stdout.reference b/tests/tests-base/test-00223/stdout.reference new file mode 100644 index 0000000..ab7fca3 --- /dev/null +++ b/tests/tests-base/test-00223/stdout.reference @@ -0,0 +1,4 @@ +ASSUMED BASE = fffffff0 +E90D00 +ICLASS: JMP CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_RELBRz ISA_SET: I86 +SHORT: jmp 0x0 diff --git a/tests/tests-base/test-00224/cmd b/tests/tests-base/test-00224/cmd new file mode 100644 index 0000000..212566c --- /dev/null +++ b/tests/tests-base/test-00224/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 xor ah bh diff --git a/tests/tests-base/test-00224/codes b/tests/tests-base/test-00224/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00224/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00224/retcode.reference b/tests/tests-base/test-00224/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00224/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00224/stderr.reference b/tests/tests-base/test-00224/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00224/stdout.reference b/tests/tests-base/test-00224/stdout.reference new file mode 100644 index 0000000..741c490 --- /dev/null +++ b/tests/tests-base/test-00224/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +XOR MODE:2, REG0:AH, REG1:BH, SMODE:2 +OPERAND ORDER: REG0 REG1 + +Encodable! 30FC diff --git a/tests/tests-base/test-00225/cmd b/tests/tests-base/test-00225/cmd new file mode 100644 index 0000000..50e9d1c --- /dev/null +++ b/tests/tests-base/test-00225/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 xor ah al diff --git a/tests/tests-base/test-00225/codes b/tests/tests-base/test-00225/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00225/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00225/retcode.reference b/tests/tests-base/test-00225/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00225/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00225/stderr.reference b/tests/tests-base/test-00225/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00225/stdout.reference b/tests/tests-base/test-00225/stdout.reference new file mode 100644 index 0000000..e84a657 --- /dev/null +++ b/tests/tests-base/test-00225/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +XOR MODE:2, REG0:AH, REG1:AL, SMODE:2 +OPERAND ORDER: REG0 REG1 + +Encodable! 30C4 diff --git a/tests/tests-base/test-00226/cmd b/tests/tests-base/test-00226/cmd new file mode 100644 index 0000000..95a6a34 --- /dev/null +++ b/tests/tests-base/test-00226/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 xor al bl diff --git a/tests/tests-base/test-00226/codes b/tests/tests-base/test-00226/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00226/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00226/retcode.reference b/tests/tests-base/test-00226/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00226/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00226/stderr.reference b/tests/tests-base/test-00226/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00226/stdout.reference b/tests/tests-base/test-00226/stdout.reference new file mode 100644 index 0000000..2856b05 --- /dev/null +++ b/tests/tests-base/test-00226/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +XOR MODE:2, REG0:AL, REG1:BL, SMODE:2 +OPERAND ORDER: REG0 REG1 + +Encodable! 30D8 diff --git a/tests/tests-base/test-00227/cmd b/tests/tests-base/test-00227/cmd new file mode 100644 index 0000000..a0481ad --- /dev/null +++ b/tests/tests-base/test-00227/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 xor sil al diff --git a/tests/tests-base/test-00227/codes b/tests/tests-base/test-00227/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00227/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00227/retcode.reference b/tests/tests-base/test-00227/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00227/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00227/stderr.reference b/tests/tests-base/test-00227/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00227/stdout.reference b/tests/tests-base/test-00227/stdout.reference new file mode 100644 index 0000000..5b8e8be --- /dev/null +++ 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b/tests/tests-base/test-00245/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00245/retcode.reference b/tests/tests-base/test-00245/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00245/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00245/stderr.reference b/tests/tests-base/test-00245/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00245/stdout.reference b/tests/tests-base/test-00245/stdout.reference new file mode 100644 index 0000000..d2875cb --- /dev/null +++ b/tests/tests-base/test-00245/stdout.reference @@ -0,0 +1,4 @@ +Encode request: +SYSRET EOSZ:3, MODE:2, SMODE:2 + +Encodable! 480F07 diff --git a/tests/tests-base/test-00246/cmd b/tests/tests-base/test-00246/cmd new file mode 100644 index 0000000..6bc5f83 --- /dev/null +++ b/tests/tests-base/test-00246/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -32 sysret diff --git a/tests/tests-base/test-00246/codes b/tests/tests-base/test-00246/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00246/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00246/retcode.reference b/tests/tests-base/test-00246/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00246/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00246/stderr.reference b/tests/tests-base/test-00246/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00246/stdout.reference b/tests/tests-base/test-00246/stdout.reference new file mode 100644 index 0000000..f2114c7 --- /dev/null +++ b/tests/tests-base/test-00246/stdout.reference @@ -0,0 +1,4 @@ +Encode request: +SYSRET MODE:1, SMODE:1 + +Could not encode diff --git a/tests/tests-base/test-00247/cmd b/tests/tests-base/test-00247/cmd new file mode 100644 index 0000000..ecfde42 --- /dev/null +++ b/tests/tests-base/test-00247/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -32 sysret_amd diff --git a/tests/tests-base/test-00247/codes b/tests/tests-base/test-00247/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00247/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00247/retcode.reference b/tests/tests-base/test-00247/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00247/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00247/stderr.reference b/tests/tests-base/test-00247/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00247/stdout.reference b/tests/tests-base/test-00247/stdout.reference new file mode 100644 index 0000000..16d1e56 --- /dev/null +++ b/tests/tests-base/test-00247/stdout.reference @@ -0,0 +1,4 @@ +Encode request: +SYSRET_AMD MODE:1, SMODE:1 + +Encodable! 0F07 diff --git a/tests/tests-base/test-00248/cmd b/tests/tests-base/test-00248/cmd new file mode 100644 index 0000000..a742951 --- /dev/null +++ b/tests/tests-base/test-00248/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 66 36 64 2e f0 67 f2 26 3e f3 65 0f 16 8d 4b diff --git a/tests/tests-base/test-00248/codes b/tests/tests-base/test-00248/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00248/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00248/retcode.reference b/tests/tests-base/test-00248/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00248/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00248/stderr.reference b/tests/tests-base/test-00248/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00248/stdout.reference b/tests/tests-base/test-00248/stdout.reference new file mode 100644 index 0000000..d37f7a3 --- /dev/null +++ b/tests/tests-base/test-00248/stdout.reference @@ -0,0 +1,2 @@ +6636642EF067F2263EF3650F168D4B +ERROR: INSTR_TOO_LONG Could not decode at offset: 0x0 PC: 0x0: [6636642EF067F2263EF3650F168D4B] diff --git a/tests/tests-base/test-00249/cmd b/tests/tests-base/test-00249/cmd new file mode 100644 index 0000000..627b5cf --- /dev/null +++ b/tests/tests-base/test-00249/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 66 36 64 2e f0 67 f2 26 3e f3 65 0f 16 8d diff --git a/tests/tests-base/test-00249/codes b/tests/tests-base/test-00249/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00249/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00249/retcode.reference b/tests/tests-base/test-00249/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00249/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00249/stderr.reference b/tests/tests-base/test-00249/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00249/stdout.reference b/tests/tests-base/test-00249/stdout.reference new file mode 100644 index 0000000..e1e89ac --- /dev/null +++ b/tests/tests-base/test-00249/stdout.reference @@ -0,0 +1,2 @@ +6636642EF067F2263EF3650F168D +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [6636642EF067F2263EF3650F168D00] diff --git a/tests/tests-base/test-00250/cmd b/tests/tests-base/test-00250/cmd new file mode 100644 index 0000000..00a622d --- /dev/null +++ b/tests/tests-base/test-00250/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 0fb20000 diff --git a/tests/tests-base/test-00250/codes b/tests/tests-base/test-00250/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00250/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00250/retcode.reference b/tests/tests-base/test-00250/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00250/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00250/stderr.reference b/tests/tests-base/test-00250/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00250/stdout.reference b/tests/tests-base/test-00250/stdout.reference new file mode 100644 index 0000000..af74267 --- /dev/null +++ b/tests/tests-base/test-00250/stdout.reference @@ -0,0 +1,21 @@ +Attempting to decode: 0f b2 00 00 +iclass LSS category SEGOP ISA-extension BASE ISA-set I386 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 64 +stack-address-width 64 +iform-enum-name LSS_GPRv_MEMp2 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX EXPLICIT W V 32 4 1 32 INT GPR +1 MEM0 (see below) EXPLICIT R P2 48 6 1 48 STRUCT INVALID +2 REG1 REG1=SS SUPPRESSED W W 16 2 1 16 INT SR +Memory Operands + 0 read BASE= RAX/GPR ASZ0=64 + MemopBytes = 6 +ATTRIBUTES: NOTSX SCALABLE +ISA SET: [I386] diff --git a/tests/tests-base/test-00251/cmd b/tests/tests-base/test-00251/cmd new file mode 100644 index 0000000..7156672 --- /dev/null +++ b/tests/tests-base/test-00251/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 ff18 diff --git a/tests/tests-base/test-00251/codes b/tests/tests-base/test-00251/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00251/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00251/retcode.reference b/tests/tests-base/test-00251/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00251/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00251/stderr.reference b/tests/tests-base/test-00251/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00251/stdout.reference b/tests/tests-base/test-00251/stdout.reference new file mode 100644 index 0000000..0b15ca4 --- /dev/null +++ b/tests/tests-base/test-00251/stdout.reference @@ -0,0 +1,24 @@ +Attempting to decode: ff 18 +iclass CALL_FAR category CALL ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 64 +stack-address-width 64 +iform-enum-name CALL_FAR_MEMp2 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) EXPLICIT R P2 48 6 1 48 STRUCT INVALID +1 REG0 REG0=STACKPUSH SUPPRESSED W SPW2 64 8 1 64 INT PSEUDO +2 REG1 REG1=RIP SUPPRESSED W V 32 4 1 32 INT IP +3 MEM1 (see below) SUPPRESSED W SPW2 64 8 1 64 INT INVALID +4 BASE1 BASE1=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR +Memory Operands + 0 read BASE= RAX/GPR ASZ0=64 + 1 written BASE= RSP/GPR ASZ1=64 + MemopBytes = 6 +ATTRIBUTES: FAR_XFER FIXED_BASE1 NOTSX SCALABLE STACKPUSH1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00252/cmd b/tests/tests-base/test-00252/cmd new file mode 100644 index 0000000..2ba6f23 --- /dev/null +++ b/tests/tests-base/test-00252/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48ff18 diff --git a/tests/tests-base/test-00252/codes b/tests/tests-base/test-00252/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00252/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00252/retcode.reference b/tests/tests-base/test-00252/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00252/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00252/stderr.reference b/tests/tests-base/test-00252/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00252/stdout.reference b/tests/tests-base/test-00252/stdout.reference new file mode 100644 index 0000000..fc3b1f2 --- /dev/null +++ b/tests/tests-base/test-00252/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 48 ff 18 +iclass CALL_FAR category CALL ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name CALL_FAR_MEMp2 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) EXPLICIT R P2 80 10 1 80 STRUCT INVALID +1 REG0 REG0=STACKPUSH SUPPRESSED W SPW2 128 16 1 128 INT PSEUDO +2 REG1 REG1=RIP SUPPRESSED W V 64 8 1 64 INT IP +3 MEM1 (see below) SUPPRESSED W SPW2 128 16 1 128 INT INVALID +4 BASE1 BASE1=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR +Memory Operands + 0 read BASE= RAX/GPR ASZ0=64 + 1 written BASE= RSP/GPR ASZ1=64 + MemopBytes = 10 +ATTRIBUTES: FAR_XFER FIXED_BASE1 NOTSX SCALABLE STACKPUSH1 +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00253/cmd b/tests/tests-base/test-00253/cmd new file mode 100644 index 0000000..d299d64 --- /dev/null +++ b/tests/tests-base/test-00253/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0f01c8 diff --git a/tests/tests-base/test-00253/codes b/tests/tests-base/test-00253/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00253/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00253/retcode.reference b/tests/tests-base/test-00253/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00253/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00253/stderr.reference b/tests/tests-base/test-00253/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00253/stdout.reference b/tests/tests-base/test-00253/stdout.reference new file mode 100644 index 0000000..9a5560c --- /dev/null +++ b/tests/tests-base/test-00253/stdout.reference @@ -0,0 +1,23 @@ +Attempting to decode: 0f 01 c8 +iclass MONITOR category MISC ISA-extension SSE3 ISA-set SSE3 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MONITOR +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +1 REG1 REG1=ECX SUPPRESSED R D 32 4 1 32 INT GPR +2 REG2 REG2=EDX SUPPRESSED R D 32 4 1 32 INT GPR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: NOTSX RING0 +RING0 only +ISA SET: [SSE3] +0 CPUID BIT NAME: [SSE3] + Leaf 0x00000001, subleaf 0x00000000, ECX[0] diff --git a/tests/tests-base/test-00254/cmd b/tests/tests-base/test-00254/cmd new file mode 100644 index 0000000..eb17cd4 --- /dev/null +++ b/tests/tests-base/test-00254/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0f01c9 diff --git a/tests/tests-base/test-00254/codes b/tests/tests-base/test-00254/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00254/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00254/retcode.reference b/tests/tests-base/test-00254/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00254/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00254/stderr.reference b/tests/tests-base/test-00254/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00254/stdout.reference b/tests/tests-base/test-00254/stdout.reference new file mode 100644 index 0000000..88019a2 --- /dev/null +++ b/tests/tests-base/test-00254/stdout.reference @@ -0,0 +1,22 @@ +Attempting to decode: 0f 01 c9 +iclass MWAIT category MISC ISA-extension SSE3 ISA-set SSE3 +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MWAIT +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED RW D 32 4 1 32 INT GPR +1 REG1 REG1=ECX SUPPRESSED R D 32 4 1 32 INT GPR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: NOTSX RING0 +RING0 only +ISA SET: [SSE3] +0 CPUID BIT NAME: [SSE3] + Leaf 0x00000001, subleaf 0x00000000, ECX[0] diff --git a/tests/tests-base/test-00255/cmd b/tests/tests-base/test-00255/cmd new file mode 100644 index 0000000..15a5e9f --- /dev/null +++ b/tests/tests-base/test-00255/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66 0f 38 10 ff diff --git a/tests/tests-base/test-00255/codes b/tests/tests-base/test-00255/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00255/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00255/retcode.reference b/tests/tests-base/test-00255/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00255/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00255/stderr.reference b/tests/tests-base/test-00255/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00255/stdout.reference b/tests/tests-base/test-00255/stdout.reference new file mode 100644 index 0000000..be3b4b4 --- /dev/null +++ b/tests/tests-base/test-00255/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 66 0f 38 10 ff +iclass PBLENDVB category SSE ISA-extension SSE4 ISA-set SSE4 +instruction-length 5 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PBLENDVB_XMMdq_XMMdq +iform-enum-name-dispatch (zero based) 1 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=XMM7 EXPLICIT RW DQ 128 16 4 32 INT XMM +1 REG1 REG1=XMM7 EXPLICIT R DQ 128 16 4 32 INT XMM +2 REG2 REG2=XMM0 SUPPRESSED R DQ 128 16 4 32 INT XMM +Memory Operands + MemopBytes = 0 +ATTRIBUTES: REQUIRES_ALIGNMENT +ANY 66 PREFIX +EXCEPTION TYPE: SSE_TYPE_4 +Number of legacy prefixes: 1 +ISA SET: [SSE4] +0 CPUID BIT NAME: [SSE4] + Leaf 0x00000001, subleaf 0x00000000, ECX[19] diff --git a/tests/tests-base/test-00256/cmd b/tests/tests-base/test-00256/cmd new file mode 100644 index 0000000..5a2c6c4 --- /dev/null +++ b/tests/tests-base/test-00256/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66 0f 38 14 ff diff --git a/tests/tests-base/test-00256/codes b/tests/tests-base/test-00256/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00256/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00256/retcode.reference b/tests/tests-base/test-00256/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00256/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00256/stderr.reference b/tests/tests-base/test-00256/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00256/stdout.reference b/tests/tests-base/test-00256/stdout.reference new file mode 100644 index 0000000..da70c64 --- /dev/null +++ b/tests/tests-base/test-00256/stdout.reference @@ -0,0 +1,25 @@ +Attempting to decode: 66 0f 38 14 ff +iclass BLENDVPS category SSE ISA-extension SSE4 ISA-set SSE4 +instruction-length 5 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name BLENDVPS_XMMdq_XMMdq +iform-enum-name-dispatch (zero based) 1 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=XMM7 EXPLICIT RW DQ 128 16 4 32 SINGLE XMM +1 REG1 REG1=XMM7 EXPLICIT R DQ 128 16 4 32 SINGLE XMM +2 REG2 REG2=XMM0 SUPPRESSED R DQ 128 16 4 32 UINT XMM +Memory Operands + MemopBytes = 0 +ATTRIBUTES: REQUIRES_ALIGNMENT +ANY 66 PREFIX +EXCEPTION TYPE: SSE_TYPE_4 +Number of legacy prefixes: 1 +ISA SET: [SSE4] +0 CPUID BIT NAME: [SSE4] + Leaf 0x00000001, subleaf 0x00000000, ECX[19] diff --git a/tests/tests-base/test-00257/cmd b/tests/tests-base/test-00257/cmd new file mode 100644 index 0000000..1fd62b9 --- /dev/null +++ b/tests/tests-base/test-00257/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de ff 10 diff --git a/tests/tests-base/test-00257/codes b/tests/tests-base/test-00257/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00257/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00257/retcode.reference b/tests/tests-base/test-00257/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00257/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00257/stderr.reference b/tests/tests-base/test-00257/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00257/stdout.reference b/tests/tests-base/test-00257/stdout.reference new file mode 100644 index 0000000..d3f3ecb --- /dev/null +++ b/tests/tests-base/test-00257/stdout.reference @@ -0,0 +1,5 @@ +FF10 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_MEMv ISA_SET: I86 +SHORT: call qword ptr [rax] +Encodable! FF10 +Identical re-encoding diff --git a/tests/tests-base/test-00258/cmd b/tests/tests-base/test-00258/cmd new file mode 100644 index 0000000..eadbd44 --- /dev/null +++ b/tests/tests-base/test-00258/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de ff 10 diff --git a/tests/tests-base/test-00258/codes b/tests/tests-base/test-00258/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00258/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00258/retcode.reference b/tests/tests-base/test-00258/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00258/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00258/stderr.reference b/tests/tests-base/test-00258/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00258/stdout.reference b/tests/tests-base/test-00258/stdout.reference new file mode 100644 index 0000000..e379577 --- /dev/null +++ b/tests/tests-base/test-00258/stdout.reference @@ -0,0 +1,5 @@ +FF10 +ICLASS: CALL_NEAR CATEGORY: CALL EXTENSION: BASE IFORM: CALL_NEAR_MEMv ISA_SET: I86 +SHORT: call dword ptr [eax] +Encodable! FF10 +Identical re-encoding diff --git a/tests/tests-base/test-00259/cmd b/tests/tests-base/test-00259/cmd new file mode 100644 index 0000000..0593fdb --- /dev/null +++ b/tests/tests-base/test-00259/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de ff e0 diff --git a/tests/tests-base/test-00259/codes b/tests/tests-base/test-00259/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00259/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00259/retcode.reference b/tests/tests-base/test-00259/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00259/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00259/stderr.reference b/tests/tests-base/test-00259/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00259/stdout.reference b/tests/tests-base/test-00259/stdout.reference new file mode 100644 index 0000000..45fcd75 --- /dev/null +++ b/tests/tests-base/test-00259/stdout.reference @@ -0,0 +1,5 @@ +FFE0 +ICLASS: JMP CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_GPRv ISA_SET: I86 +SHORT: jmp eax +Encodable! FFE0 +Identical re-encoding diff --git a/tests/tests-base/test-00260/cmd b/tests/tests-base/test-00260/cmd new file mode 100644 index 0000000..fe39a66 --- /dev/null +++ b/tests/tests-base/test-00260/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 66 ff e0 diff --git a/tests/tests-base/test-00260/codes b/tests/tests-base/test-00260/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00260/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00260/retcode.reference b/tests/tests-base/test-00260/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00260/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00260/stderr.reference b/tests/tests-base/test-00260/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00260/stdout.reference b/tests/tests-base/test-00260/stdout.reference new file mode 100644 index 0000000..5c90fcd --- /dev/null +++ b/tests/tests-base/test-00260/stdout.reference @@ -0,0 +1,5 @@ +66FFE0 +ICLASS: JMP CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_GPRv ISA_SET: I86 +SHORT: jmp ax +Encodable! 66FFE0 +Identical re-encoding diff --git a/tests/tests-base/test-00261/cmd b/tests/tests-base/test-00261/cmd new file mode 100644 index 0000000..d7896e0 --- /dev/null +++ b/tests/tests-base/test-00261/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de ff e0 diff --git a/tests/tests-base/test-00261/codes b/tests/tests-base/test-00261/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00261/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00261/retcode.reference b/tests/tests-base/test-00261/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00261/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00261/stderr.reference b/tests/tests-base/test-00261/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00261/stdout.reference b/tests/tests-base/test-00261/stdout.reference new file mode 100644 index 0000000..aa06f6b --- /dev/null +++ b/tests/tests-base/test-00261/stdout.reference @@ -0,0 +1,5 @@ +FFE0 +ICLASS: JMP CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_GPRv ISA_SET: I86 +SHORT: jmp rax +Encodable! FFE0 +Identical re-encoding diff --git a/tests/tests-base/test-00262/cmd b/tests/tests-base/test-00262/cmd new file mode 100644 index 0000000..c588461 --- /dev/null +++ b/tests/tests-base/test-00262/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 66 ff e0 diff --git a/tests/tests-base/test-00262/codes b/tests/tests-base/test-00262/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00262/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00262/retcode.reference b/tests/tests-base/test-00262/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00262/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00262/stderr.reference b/tests/tests-base/test-00262/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00262/stdout.reference b/tests/tests-base/test-00262/stdout.reference new file mode 100644 index 0000000..7b67abf --- /dev/null +++ b/tests/tests-base/test-00262/stdout.reference @@ -0,0 +1,11 @@ +66FFE0 +ICLASS: JMP CATEGORY: UNCOND_BR EXTENSION: BASE IFORM: JMP_GPRv ISA_SET: I86 +SHORT: jmp rax +Encodable! FFE0 +Discrepenacy after re-encoding. dec_len= 3 [66FFE0] enc_olen= 2 [FFE0] for instruction: JMP JMP_GPRv DF64, EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:224, NOMINAL_OPCODE:255, NPREFIXES:1, OUTREG:RAX, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, PREFIX66, REG:4, REG0:RAX, REG1:RIP, SMODE:2, SRM:7, TZCNT +0 REG0/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_B +1 REG1/W/V/SUPPRESSED/NT_LOOKUP_FN/RIP +YDIS: jmp rax +vs Encode request: JMP DF64, EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:224, NOMINAL_OPCODE:255, NPREFIXES:1, OUTREG:RAX, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, PREFIX66, REG:4, REG0:RAX, REG1:RIP, SMODE:2, SRM:7, TZCNT +OPERAND ORDER: REG0 + diff --git a/tests/tests-base/test-00263/cmd b/tests/tests-base/test-00263/cmd new file mode 100644 index 0000000..6fc1b32 --- /dev/null +++ b/tests/tests-base/test-00263/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex6 -64 64 67 f0 48 81 24 e5 1c 68 48 43 5f a6 b7 cd diff --git a/tests/tests-base/test-00263/codes b/tests/tests-base/test-00263/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00263/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00263/retcode.reference b/tests/tests-base/test-00263/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00263/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00263/stderr.reference b/tests/tests-base/test-00263/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00263/stdout.reference b/tests/tests-base/test-00263/stdout.reference new file mode 100644 index 0000000..1f2e103 --- /dev/null +++ b/tests/tests-base/test-00263/stdout.reference @@ -0,0 +1,14 @@ +PARSING BYTES: 64 67 f0 48 81 24 e5 1c 68 48 43 5f a6 b7 cd +AND_LOCK AND_LOCK_MEMv_IMMz ASZ, DISP_WIDTH:32, EASZ:2, EOSZ:3, HAS_SIB, HAS_MODRM:1, ILD_SEG:100, IMM_WIDTH:32, IMM0SIGNED, IMM0:0xcdb7a65f, LOCK, LZCNT, MAX_BYTES:15, MEM0:ptr FS[0x4348681c], MODE:2, MODRM, MODRM_BYTE:36, NEED_MEMDISP:32, NOMINAL_OPCODE:129, NPREFIXES:4, NREXES:1, NSEG_PREFIXES:1, OUTREG:RFLAGS, P4, POS_SIB:6, POS_DISP:7, POS_IMM:11, POS_NOMINAL_OPCODE:4, POS_MODRM:5, REG:4, REG0:RFLAGS, REX, REXW, RM:4, SEG_OVD:4, SIBBASE:5, SIBINDEX:4, SIBSCALE:3, SMODE:2, SRM:1, TZCNT +0 MEM0/RW/V/EXPLICIT/IMM_CONST/1 +1 IMM0/R/Z/EXPLICIT/IMM_CONST/1 +2 REG0/W/Y/SUPPRESSED/NT_LOOKUP_FN/RFLAGS +YDIS: lock and qword ptr fs:[0x4348681c], 0xffffffffcdb7a65f +XED syntax: AND_LOCK ASZ, DISP_WIDTH:32, EASZ:2, EOSZ:3, HAS_SIB, HAS_MODRM:1, ILD_SEG:100, IMM_WIDTH:32, IMM0SIGNED, IMM0:0xcdb7a65f, LOCK, LZCNT, MAX_BYTES:15, MEM0:ptr FS[0x4348681c], MODE:2, MODRM, MODRM_BYTE:36, NEED_MEMDISP:32, NOMINAL_OPCODE:129, NPREFIXES:4, NREXES:1, NSEG_PREFIXES:1, OUTREG:RFLAGS, P4, POS_SIB:6, POS_DISP:7, POS_IMM:11, POS_NOMINAL_OPCODE:4, POS_MODRM:5, REG:4, REG0:RFLAGS, REX, REXW, RM:4, SEG_OVD:4, SIBBASE:5, SIBINDEX:4, SIBSCALE:3, SMODE:2, SRM:1, TZCNT +ATT syntax: lock andq $0xffffffffcdb7a65f, %fs:0x4348681c +INTEL syntax: lock and qword ptr fs:[0x4348681c], 0xffffffffcdb7a65f + + +Preparing to encode ... +Encoding... +Encodable: 67f064488124251c6848435fa6b7cd diff --git a/tests/tests-base/test-00264/cmd b/tests/tests-base/test-00264/cmd new file mode 100644 index 0000000..54e1090 --- /dev/null +++ b/tests/tests-base/test-00264/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip SALTWELL 0f 0d 08 diff --git a/tests/tests-base/test-00264/codes b/tests/tests-base/test-00264/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00264/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00264/retcode.reference b/tests/tests-base/test-00264/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00264/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00264/stderr.reference b/tests/tests-base/test-00264/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00264/stdout.reference b/tests/tests-base/test-00264/stdout.reference new file mode 100644 index 0000000..b23ac13 --- /dev/null +++ b/tests/tests-base/test-00264/stdout.reference @@ -0,0 +1,20 @@ +Setting chip to SALTWELL +Attempting to decode: 0f 0d 08 +iclass PREFETCHW category PREFETCH ISA-extension 3DNOW ISA-set PREFETCH_NOP +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PREFETCHW_0F0Dr1 +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 2 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) EXPLICIT R MPREFETCH 512 64 8 64 INT INVALID +Memory Operands + 0 read SEG= DS BASE= EAX/GPR ASZ0=32 + MemopBytes = 64 +ATTRIBUTES: PREFETCH +ISA SET: [PREFETCH_NOP] diff --git a/tests/tests-base/test-00265/cmd b/tests/tests-base/test-00265/cmd new file mode 100644 index 0000000..afcabba --- /dev/null +++ b/tests/tests-base/test-00265/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip PENRYN_E 0f 01 d0 diff --git a/tests/tests-base/test-00265/codes b/tests/tests-base/test-00265/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00265/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00265/retcode.reference b/tests/tests-base/test-00265/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00265/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00265/stderr.reference b/tests/tests-base/test-00265/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00265/stdout.reference b/tests/tests-base/test-00265/stdout.reference new file mode 100644 index 0000000..5128cbe --- /dev/null +++ b/tests/tests-base/test-00265/stdout.reference @@ -0,0 +1,26 @@ +Setting chip to PENRYN_E +Attempting to decode: 0f 01 d0 +iclass XGETBV category XSAVE ISA-extension XSAVE ISA-set XSAVE +instruction-length 3 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name XGETBV +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=ECX SUPPRESSED R D 32 4 1 32 INT GPR +1 REG1 REG1=EDX SUPPRESSED W D 32 4 1 32 INT GPR +2 REG2 REG2=EAX SUPPRESSED W D 32 4 1 32 INT GPR +3 REG3 REG3=XCR0 SUPPRESSED R Q 64 8 1 64 INT XCR +Memory Operands + MemopBytes = 0 +ATTRIBUTES: +ISA SET: [XSAVE] +0 CPUID BIT NAME: [XSAVE] + Leaf 0x00000001, subleaf 0x00000000, ECX[26] +1 CPUID BIT NAME: [OSXSAVE] + Leaf 0x00000001, subleaf 0x00000000, ECX[27] diff --git a/tests/tests-base/test-00266/cmd b/tests/tests-base/test-00266/cmd new file mode 100644 index 0000000..ebf58fa --- /dev/null +++ b/tests/tests-base/test-00266/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -chip NEHALEM 0f 01 d0 diff --git a/tests/tests-base/test-00266/codes b/tests/tests-base/test-00266/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00266/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00266/retcode.reference b/tests/tests-base/test-00266/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00266/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00266/stderr.reference b/tests/tests-base/test-00266/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00266/stdout.reference b/tests/tests-base/test-00266/stdout.reference new file mode 100644 index 0000000..6846606 --- /dev/null +++ b/tests/tests-base/test-00266/stdout.reference @@ -0,0 +1,3 @@ +Setting chip to NEHALEM +Attempting to decode: 0f 01 d0 +The instruction was not valid for the specified chip. diff --git a/tests/tests-base/test-00267/cmd b/tests/tests-base/test-00267/cmd new file mode 100644 index 0000000..1dd5155 --- /dev/null +++ b/tests/tests-base/test-00267/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -A -d a1 00 70 70 c1 diff --git a/tests/tests-base/test-00267/codes b/tests/tests-base/test-00267/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00267/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00267/retcode.reference b/tests/tests-base/test-00267/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00267/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00267/stderr.reference b/tests/tests-base/test-00267/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00267/stdout.reference b/tests/tests-base/test-00267/stdout.reference new file mode 100644 index 0000000..bb09516 --- /dev/null +++ b/tests/tests-base/test-00267/stdout.reference @@ -0,0 +1,3 @@ +A1007070C1 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_OrAX_MEMv ISA_SET: I86 +SHORT: movl 0xc1707000, %eax diff --git a/tests/tests-base/test-00268/cmd b/tests/tests-base/test-00268/cmd new file mode 100644 index 0000000..2a07130 --- /dev/null +++ b/tests/tests-base/test-00268/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -A -d 00 80 00 70 70 c1 diff --git a/tests/tests-base/test-00268/codes b/tests/tests-base/test-00268/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00268/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00268/retcode.reference b/tests/tests-base/test-00268/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00268/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00268/stderr.reference b/tests/tests-base/test-00268/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00268/stdout.reference b/tests/tests-base/test-00268/stdout.reference new file mode 100644 index 0000000..14b27eb --- /dev/null +++ b/tests/tests-base/test-00268/stdout.reference @@ -0,0 +1,3 @@ +0080007070C1 +ICLASS: ADD CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_MEMb_GPR8 ISA_SET: I86 +SHORT: addb %al, -0x3e8f9000(%eax) diff --git a/tests/tests-base/test-00269/cmd b/tests/tests-base/test-00269/cmd new file mode 100644 index 0000000..3f519a8 --- /dev/null +++ b/tests/tests-base/test-00269/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 e2 f1 92 64 40 11 diff --git a/tests/tests-base/test-00269/codes b/tests/tests-base/test-00269/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00269/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00269/retcode.reference b/tests/tests-base/test-00269/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00269/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00269/stderr.reference b/tests/tests-base/test-00269/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00269/stdout.reference b/tests/tests-base/test-00269/stdout.reference new file mode 100644 index 0000000..94f15aa --- /dev/null +++ b/tests/tests-base/test-00269/stdout.reference @@ -0,0 +1,3 @@ +C4E2F192644011 +ICLASS: VGATHERDPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherdpd xmm4, xmmword ptr [eax+xmm0*2+0x11], xmm1 diff --git a/tests/tests-base/test-00270/cmd b/tests/tests-base/test-00270/cmd new file mode 100644 index 0000000..b5813c0 --- /dev/null +++ b/tests/tests-base/test-00270/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de c4 e2 f1 92 64 40 11 diff --git a/tests/tests-base/test-00270/codes b/tests/tests-base/test-00270/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00270/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00270/retcode.reference b/tests/tests-base/test-00270/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00270/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00270/stderr.reference b/tests/tests-base/test-00270/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00270/stdout.reference b/tests/tests-base/test-00270/stdout.reference new file mode 100644 index 0000000..5edb31a --- /dev/null +++ b/tests/tests-base/test-00270/stdout.reference @@ -0,0 +1,5 @@ +C4E2F192644011 +ICLASS: VGATHERDPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherdpd xmm4, xmmword ptr [eax+xmm0*2+0x11], xmm1 +Encodable! C4E2F192644011 +Identical re-encoding diff --git a/tests/tests-base/test-00271/cmd b/tests/tests-base/test-00271/cmd new file mode 100644 index 0000000..886917d --- /dev/null +++ b/tests/tests-base/test-00271/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERDPS xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00271/codes b/tests/tests-base/test-00271/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00271/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00271/retcode.reference b/tests/tests-base/test-00271/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00271/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00271/stderr.reference b/tests/tests-base/test-00271/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00271/stdout.reference b/tests/tests-base/test-00271/stdout.reference new file mode 100644 index 0000000..ee56460 --- /dev/null +++ b/tests/tests-base/test-00271/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPS MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E269920408 diff --git a/tests/tests-base/test-00272/cmd b/tests/tests-base/test-00272/cmd new file mode 100644 index 0000000..72e3014 --- /dev/null +++ b/tests/tests-base/test-00272/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERDPS ymm0 MEM32:rax,ymm1,1 ymm2 diff --git a/tests/tests-base/test-00272/codes b/tests/tests-base/test-00272/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00272/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00272/retcode.reference b/tests/tests-base/test-00272/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00272/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00272/stderr.reference b/tests/tests-base/test-00272/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00272/stdout.reference b/tests/tests-base/test-00272/stdout.reference new file mode 100644 index 0000000..ab175c2 --- /dev/null +++ b/tests/tests-base/test-00272/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPS MEM_WIDTH:32, MEM0:ymmword ptr [RAX+YMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E26D920408 diff --git a/tests/tests-base/test-00273/cmd b/tests/tests-base/test-00273/cmd new file mode 100644 index 0000000..5ce7978 --- /dev/null +++ b/tests/tests-base/test-00273/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERDD xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00273/codes b/tests/tests-base/test-00273/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00273/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00273/retcode.reference b/tests/tests-base/test-00273/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00273/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00273/stderr.reference b/tests/tests-base/test-00273/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00273/stdout.reference b/tests/tests-base/test-00273/stdout.reference new file mode 100644 index 0000000..0264da9 --- /dev/null +++ b/tests/tests-base/test-00273/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERDD MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E269900408 diff --git a/tests/tests-base/test-00274/cmd b/tests/tests-base/test-00274/cmd new file mode 100644 index 0000000..684ca2f --- /dev/null +++ b/tests/tests-base/test-00274/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERDD ymm0 MEM32:rax,xmm1,1 ymm2 diff --git a/tests/tests-base/test-00274/codes b/tests/tests-base/test-00274/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00274/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00274/retcode.reference b/tests/tests-base/test-00274/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00274/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00274/stderr.reference b/tests/tests-base/test-00274/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00274/stdout.reference b/tests/tests-base/test-00274/stdout.reference new file mode 100644 index 0000000..97d86b2 --- /dev/null +++ b/tests/tests-base/test-00274/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERDD MEM_WIDTH:32, MEM0:ymmword ptr [RAX+XMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Could not encode diff --git a/tests/tests-base/test-00275/cmd b/tests/tests-base/test-00275/cmd new file mode 100644 index 0000000..ae82df5 --- /dev/null +++ b/tests/tests-base/test-00275/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERDQ xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00275/codes b/tests/tests-base/test-00275/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00275/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00275/retcode.reference b/tests/tests-base/test-00275/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00275/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00275/stderr.reference b/tests/tests-base/test-00275/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00275/stdout.reference b/tests/tests-base/test-00275/stdout.reference new file mode 100644 index 0000000..d2926bd --- /dev/null +++ b/tests/tests-base/test-00275/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERDQ MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2E9900408 diff --git a/tests/tests-base/test-00276/cmd b/tests/tests-base/test-00276/cmd new file mode 100644 index 0000000..67385ea --- /dev/null +++ b/tests/tests-base/test-00276/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERDQ ymm0 MEM32:rax,xmm1,1 ymm2 diff --git a/tests/tests-base/test-00276/codes b/tests/tests-base/test-00276/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00276/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00276/retcode.reference b/tests/tests-base/test-00276/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00276/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00276/stderr.reference b/tests/tests-base/test-00276/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00276/stdout.reference b/tests/tests-base/test-00276/stdout.reference new file mode 100644 index 0000000..e5f0412 --- /dev/null +++ b/tests/tests-base/test-00276/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERDQ MEM_WIDTH:32, MEM0:ymmword ptr [RAX+XMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2ED900408 diff --git a/tests/tests-base/test-00277/cmd b/tests/tests-base/test-00277/cmd new file mode 100644 index 0000000..bcce018 --- /dev/null +++ b/tests/tests-base/test-00277/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERDPD xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00277/codes b/tests/tests-base/test-00277/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00277/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00277/retcode.reference b/tests/tests-base/test-00277/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00277/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00277/stderr.reference b/tests/tests-base/test-00277/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00277/stdout.reference b/tests/tests-base/test-00277/stdout.reference new file mode 100644 index 0000000..1eece94 --- /dev/null +++ b/tests/tests-base/test-00277/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPD MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2E9920408 diff --git a/tests/tests-base/test-00278/cmd b/tests/tests-base/test-00278/cmd new file mode 100644 index 0000000..eef7627 --- /dev/null +++ b/tests/tests-base/test-00278/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERDPD ymm0 MEM32:rax,xmm1,1 ymm2 diff --git a/tests/tests-base/test-00278/codes b/tests/tests-base/test-00278/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00278/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00278/retcode.reference b/tests/tests-base/test-00278/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00278/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00278/stderr.reference b/tests/tests-base/test-00278/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00278/stdout.reference b/tests/tests-base/test-00278/stdout.reference new file mode 100644 index 0000000..f2a4eb3 --- /dev/null +++ b/tests/tests-base/test-00278/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPD MEM_WIDTH:32, MEM0:ymmword ptr [RAX+XMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2ED920408 diff --git a/tests/tests-base/test-00279/cmd b/tests/tests-base/test-00279/cmd new file mode 100644 index 0000000..a507571 --- /dev/null +++ b/tests/tests-base/test-00279/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERQPS xmm0 MEM8:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00279/codes b/tests/tests-base/test-00279/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00279/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00279/retcode.reference b/tests/tests-base/test-00279/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00279/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00279/stderr.reference b/tests/tests-base/test-00279/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00279/stdout.reference b/tests/tests-base/test-00279/stdout.reference new file mode 100644 index 0000000..37db407 --- /dev/null +++ b/tests/tests-base/test-00279/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERQPS MEM_WIDTH:8, MEM0:qword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E269930408 diff --git a/tests/tests-base/test-00280/cmd b/tests/tests-base/test-00280/cmd new file mode 100644 index 0000000..9a322fc --- /dev/null +++ b/tests/tests-base/test-00280/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERQPS xmm0 MEM16:rax,ymm1,1 xmm2 diff --git a/tests/tests-base/test-00280/codes b/tests/tests-base/test-00280/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00280/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00280/retcode.reference b/tests/tests-base/test-00280/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00280/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00280/stderr.reference b/tests/tests-base/test-00280/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00280/stdout.reference b/tests/tests-base/test-00280/stdout.reference new file mode 100644 index 0000000..daf6c4b --- /dev/null +++ b/tests/tests-base/test-00280/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERQPS MEM_WIDTH:16, MEM0:xmmword ptr [RAX+YMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E26D930408 diff --git a/tests/tests-base/test-00281/cmd b/tests/tests-base/test-00281/cmd new file mode 100644 index 0000000..fee622f --- /dev/null +++ b/tests/tests-base/test-00281/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERQPD xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00281/codes b/tests/tests-base/test-00281/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00281/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00281/retcode.reference b/tests/tests-base/test-00281/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00281/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00281/stderr.reference b/tests/tests-base/test-00281/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00281/stdout.reference b/tests/tests-base/test-00281/stdout.reference new file mode 100644 index 0000000..8a88ba9 --- /dev/null +++ b/tests/tests-base/test-00281/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERQPD MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2E9930408 diff --git a/tests/tests-base/test-00282/cmd b/tests/tests-base/test-00282/cmd new file mode 100644 index 0000000..8744796 --- /dev/null +++ b/tests/tests-base/test-00282/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VGATHERQPD ymm0 MEM32:rax,ymm1,1 ymm2 diff --git a/tests/tests-base/test-00282/codes b/tests/tests-base/test-00282/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00282/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00282/retcode.reference b/tests/tests-base/test-00282/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00282/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00282/stderr.reference b/tests/tests-base/test-00282/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00282/stdout.reference b/tests/tests-base/test-00282/stdout.reference new file mode 100644 index 0000000..cd213e2 --- /dev/null +++ b/tests/tests-base/test-00282/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERQPD MEM_WIDTH:32, MEM0:ymmword ptr [RAX+YMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2ED930408 diff --git a/tests/tests-base/test-00283/cmd b/tests/tests-base/test-00283/cmd new file mode 100644 index 0000000..cc7e4c9 --- /dev/null +++ b/tests/tests-base/test-00283/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERQD xmm0 MEM8:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00283/codes b/tests/tests-base/test-00283/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00283/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00283/retcode.reference b/tests/tests-base/test-00283/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00283/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00283/stderr.reference b/tests/tests-base/test-00283/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00283/stdout.reference b/tests/tests-base/test-00283/stdout.reference new file mode 100644 index 0000000..7ed0b38 --- /dev/null +++ b/tests/tests-base/test-00283/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERQD MEM_WIDTH:8, MEM0:qword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E269910408 diff --git a/tests/tests-base/test-00284/cmd b/tests/tests-base/test-00284/cmd new file mode 100644 index 0000000..f2f71ab --- /dev/null +++ b/tests/tests-base/test-00284/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERQD xmm0 MEM16:rax,ymm1,1 xmm2 diff --git a/tests/tests-base/test-00284/codes b/tests/tests-base/test-00284/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00284/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00284/retcode.reference b/tests/tests-base/test-00284/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00284/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00284/stderr.reference b/tests/tests-base/test-00284/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00284/stdout.reference b/tests/tests-base/test-00284/stdout.reference new file mode 100644 index 0000000..b4de4fa --- /dev/null +++ b/tests/tests-base/test-00284/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERQD MEM_WIDTH:16, MEM0:xmmword ptr [RAX+YMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E26D910408 diff --git a/tests/tests-base/test-00285/cmd b/tests/tests-base/test-00285/cmd new file mode 100644 index 0000000..50b78ed --- /dev/null +++ b/tests/tests-base/test-00285/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERQQ xmm0 MEM16:rax,xmm1,1 xmm2 diff --git a/tests/tests-base/test-00285/codes b/tests/tests-base/test-00285/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00285/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00285/retcode.reference b/tests/tests-base/test-00285/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00285/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00285/stderr.reference b/tests/tests-base/test-00285/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00285/stdout.reference b/tests/tests-base/test-00285/stdout.reference new file mode 100644 index 0000000..a6d8da0 --- /dev/null +++ b/tests/tests-base/test-00285/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERQQ MEM_WIDTH:16, MEM0:xmmword ptr [RAX+XMM1*1], MODE:2, REG0:XMM0, REG1:XMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2E9910408 diff --git a/tests/tests-base/test-00286/cmd b/tests/tests-base/test-00286/cmd new file mode 100644 index 0000000..e9b3a69 --- /dev/null +++ b/tests/tests-base/test-00286/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 VPGATHERQQ ymm0 MEM32:rax,ymm1,1 ymm2 diff --git a/tests/tests-base/test-00286/codes b/tests/tests-base/test-00286/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00286/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00286/retcode.reference b/tests/tests-base/test-00286/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00286/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00286/stderr.reference b/tests/tests-base/test-00286/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00286/stdout.reference b/tests/tests-base/test-00286/stdout.reference new file mode 100644 index 0000000..831b2f5 --- /dev/null +++ b/tests/tests-base/test-00286/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPGATHERQQ MEM_WIDTH:32, MEM0:ymmword ptr [RAX+YMM1*1], MODE:2, REG0:YMM0, REG1:YMM2, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E2ED910408 diff --git a/tests/tests-base/test-00287/cmd b/tests/tests-base/test-00287/cmd new file mode 100644 index 0000000..b2a3d57 --- /dev/null +++ b/tests/tests-base/test-00287/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E269920408 diff --git a/tests/tests-base/test-00287/codes b/tests/tests-base/test-00287/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00287/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00287/retcode.reference b/tests/tests-base/test-00287/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00287/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00287/stderr.reference b/tests/tests-base/test-00287/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00287/stdout.reference b/tests/tests-base/test-00287/stdout.reference new file mode 100644 index 0000000..92bd733 --- /dev/null +++ b/tests/tests-base/test-00287/stdout.reference @@ -0,0 +1,5 @@ +C4E269920408 +ICLASS: VGATHERDPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPS_XMMf32_MEMdq_XMMi32_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherdps xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E269920408 +Identical re-encoding diff --git a/tests/tests-base/test-00288/cmd b/tests/tests-base/test-00288/cmd new file mode 100644 index 0000000..14ff2a4 --- /dev/null +++ b/tests/tests-base/test-00288/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E26D920408 diff --git a/tests/tests-base/test-00288/codes b/tests/tests-base/test-00288/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00288/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00288/retcode.reference b/tests/tests-base/test-00288/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00288/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00288/stderr.reference b/tests/tests-base/test-00288/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00288/stdout.reference b/tests/tests-base/test-00288/stdout.reference new file mode 100644 index 0000000..5c9ba29 --- /dev/null +++ b/tests/tests-base/test-00288/stdout.reference @@ -0,0 +1,5 @@ +C4E26D920408 +ICLASS: VGATHERDPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPS_YMMf32_MEMqq_YMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherdps ymm0, ymmword ptr [rax+ymm1*1], ymm2 +Encodable! C4E26D920408 +Identical re-encoding diff --git a/tests/tests-base/test-00289/cmd b/tests/tests-base/test-00289/cmd new file mode 100644 index 0000000..aff57bf --- /dev/null +++ b/tests/tests-base/test-00289/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E269900408 diff --git a/tests/tests-base/test-00289/codes b/tests/tests-base/test-00289/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00289/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00289/retcode.reference b/tests/tests-base/test-00289/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00289/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00289/stderr.reference b/tests/tests-base/test-00289/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00289/stdout.reference b/tests/tests-base/test-00289/stdout.reference new file mode 100644 index 0000000..4306f13 --- /dev/null +++ b/tests/tests-base/test-00289/stdout.reference @@ -0,0 +1,5 @@ +C4E269900408 +ICLASS: VPGATHERDD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERDD_XMMu32_MEMdq_XMMi32_VL128 ISA_SET: AVX2GATHER +SHORT: vpgatherdd xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E269900408 +Identical re-encoding diff --git a/tests/tests-base/test-00290/cmd b/tests/tests-base/test-00290/cmd new file mode 100644 index 0000000..81ef43c --- /dev/null +++ b/tests/tests-base/test-00290/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E26D900408 diff --git a/tests/tests-base/test-00290/codes b/tests/tests-base/test-00290/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00290/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00290/retcode.reference b/tests/tests-base/test-00290/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00290/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00290/stderr.reference b/tests/tests-base/test-00290/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00290/stdout.reference b/tests/tests-base/test-00290/stdout.reference new file mode 100644 index 0000000..22edba1 --- /dev/null +++ b/tests/tests-base/test-00290/stdout.reference @@ -0,0 +1,5 @@ +C4E26D900408 +ICLASS: VPGATHERDD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERDD_YMMu32_MEMqq_YMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherdd ymm0, ymmword ptr [rax+ymm1*1], ymm2 +Encodable! C4E26D900408 +Identical re-encoding diff --git a/tests/tests-base/test-00291/cmd b/tests/tests-base/test-00291/cmd new file mode 100644 index 0000000..6873a3a --- /dev/null +++ b/tests/tests-base/test-00291/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2E9900408 diff --git a/tests/tests-base/test-00291/codes b/tests/tests-base/test-00291/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00291/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00291/retcode.reference b/tests/tests-base/test-00291/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00291/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00291/stderr.reference b/tests/tests-base/test-00291/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00291/stdout.reference b/tests/tests-base/test-00291/stdout.reference new file mode 100644 index 0000000..28fcb5a --- /dev/null +++ b/tests/tests-base/test-00291/stdout.reference @@ -0,0 +1,5 @@ +C4E2E9900408 +ICLASS: VPGATHERDQ CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERDQ_XMMu64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vpgatherdq xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E2E9900408 +Identical re-encoding diff --git a/tests/tests-base/test-00292/cmd b/tests/tests-base/test-00292/cmd new file mode 100644 index 0000000..e9ab0b2 --- /dev/null +++ b/tests/tests-base/test-00292/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2ED900408 diff --git a/tests/tests-base/test-00292/codes b/tests/tests-base/test-00292/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00292/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00292/retcode.reference b/tests/tests-base/test-00292/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00292/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00292/stderr.reference b/tests/tests-base/test-00292/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00292/stdout.reference b/tests/tests-base/test-00292/stdout.reference new file mode 100644 index 0000000..98a667c --- /dev/null +++ b/tests/tests-base/test-00292/stdout.reference @@ -0,0 +1,5 @@ +C4E2ED900408 +ICLASS: VPGATHERDQ CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERDQ_YMMu64_MEMqq_YMMi64_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherdq ymm0, ymmword ptr [rax+xmm1*1], ymm2 +Encodable! C4E2ED900408 +Identical re-encoding diff --git a/tests/tests-base/test-00293/cmd b/tests/tests-base/test-00293/cmd new file mode 100644 index 0000000..96920e2 --- /dev/null +++ b/tests/tests-base/test-00293/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2E9920408 diff --git a/tests/tests-base/test-00293/codes b/tests/tests-base/test-00293/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00293/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00293/retcode.reference b/tests/tests-base/test-00293/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00293/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00293/stderr.reference b/tests/tests-base/test-00293/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00293/stdout.reference b/tests/tests-base/test-00293/stdout.reference new file mode 100644 index 0000000..68e45e7 --- /dev/null +++ b/tests/tests-base/test-00293/stdout.reference @@ -0,0 +1,5 @@ +C4E2E9920408 +ICLASS: VGATHERDPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherdpd xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E2E9920408 +Identical re-encoding diff --git a/tests/tests-base/test-00294/cmd b/tests/tests-base/test-00294/cmd new file mode 100644 index 0000000..14d5008 --- /dev/null +++ b/tests/tests-base/test-00294/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2ED920408 diff --git a/tests/tests-base/test-00294/codes b/tests/tests-base/test-00294/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00294/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00294/retcode.reference b/tests/tests-base/test-00294/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00294/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00294/stderr.reference b/tests/tests-base/test-00294/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00294/stdout.reference b/tests/tests-base/test-00294/stdout.reference new file mode 100644 index 0000000..a1946dd --- /dev/null +++ b/tests/tests-base/test-00294/stdout.reference @@ -0,0 +1,5 @@ +C4E2ED920408 +ICLASS: VGATHERDPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERDPD_YMMf64_MEMqq_YMMi64_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherdpd ymm0, ymmword ptr [rax+xmm1*1], ymm2 +Encodable! C4E2ED920408 +Identical re-encoding diff --git a/tests/tests-base/test-00295/cmd b/tests/tests-base/test-00295/cmd new file mode 100644 index 0000000..ae997f1 --- /dev/null +++ b/tests/tests-base/test-00295/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E269930408 diff --git a/tests/tests-base/test-00295/codes b/tests/tests-base/test-00295/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00295/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00295/retcode.reference b/tests/tests-base/test-00295/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00295/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00295/stderr.reference b/tests/tests-base/test-00295/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00295/stdout.reference b/tests/tests-base/test-00295/stdout.reference new file mode 100644 index 0000000..02d00c6 --- /dev/null +++ b/tests/tests-base/test-00295/stdout.reference @@ -0,0 +1,5 @@ +C4E269930408 +ICLASS: VGATHERQPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPS_XMMf32_MEMq_XMMi32_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherqps xmm0, qword ptr [rax+xmm1*1], xmm2 +Encodable! C4E269930408 +Identical re-encoding diff --git a/tests/tests-base/test-00296/cmd b/tests/tests-base/test-00296/cmd new file mode 100644 index 0000000..299f1ea --- /dev/null +++ b/tests/tests-base/test-00296/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E26D930408 diff --git a/tests/tests-base/test-00296/codes b/tests/tests-base/test-00296/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00296/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00296/retcode.reference b/tests/tests-base/test-00296/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00296/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00296/stderr.reference b/tests/tests-base/test-00296/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00296/stdout.reference b/tests/tests-base/test-00296/stdout.reference new file mode 100644 index 0000000..a55c374 --- /dev/null +++ b/tests/tests-base/test-00296/stdout.reference @@ -0,0 +1,5 @@ +C4E26D930408 +ICLASS: VGATHERQPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherqps xmm0, xmmword ptr [rax+ymm1*1], xmm2 +Encodable! C4E26D930408 +Identical re-encoding diff --git a/tests/tests-base/test-00297/cmd b/tests/tests-base/test-00297/cmd new file mode 100644 index 0000000..e7c1bc8 --- /dev/null +++ b/tests/tests-base/test-00297/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2E9930408 diff --git a/tests/tests-base/test-00297/codes b/tests/tests-base/test-00297/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00297/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00297/retcode.reference b/tests/tests-base/test-00297/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00297/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00297/stderr.reference b/tests/tests-base/test-00297/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00297/stdout.reference b/tests/tests-base/test-00297/stdout.reference new file mode 100644 index 0000000..16082e8 --- /dev/null +++ b/tests/tests-base/test-00297/stdout.reference @@ -0,0 +1,5 @@ +C4E2E9930408 +ICLASS: VGATHERQPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPD_XMMf64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vgatherqpd xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E2E9930408 +Identical re-encoding diff --git a/tests/tests-base/test-00298/cmd b/tests/tests-base/test-00298/cmd new file mode 100644 index 0000000..03d376b --- /dev/null +++ b/tests/tests-base/test-00298/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2ED930408 diff --git a/tests/tests-base/test-00298/codes b/tests/tests-base/test-00298/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00298/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00298/retcode.reference b/tests/tests-base/test-00298/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00298/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00298/stderr.reference b/tests/tests-base/test-00298/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00298/stdout.reference b/tests/tests-base/test-00298/stdout.reference new file mode 100644 index 0000000..f229e9f --- /dev/null +++ b/tests/tests-base/test-00298/stdout.reference @@ -0,0 +1,5 @@ +C4E2ED930408 +ICLASS: VGATHERQPD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPD_YMMf64_MEMqq_YMMi64_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherqpd ymm0, ymmword ptr [rax+ymm1*1], ymm2 +Encodable! C4E2ED930408 +Identical re-encoding diff --git a/tests/tests-base/test-00299/cmd b/tests/tests-base/test-00299/cmd new file mode 100644 index 0000000..c1db28f --- /dev/null +++ b/tests/tests-base/test-00299/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E26D910408 diff --git a/tests/tests-base/test-00299/codes b/tests/tests-base/test-00299/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00299/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00299/retcode.reference b/tests/tests-base/test-00299/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00299/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00299/stderr.reference b/tests/tests-base/test-00299/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00299/stdout.reference b/tests/tests-base/test-00299/stdout.reference new file mode 100644 index 0000000..57da0cd --- /dev/null +++ b/tests/tests-base/test-00299/stdout.reference @@ -0,0 +1,5 @@ +C4E26D910408 +ICLASS: VPGATHERQD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherqd xmm0, xmmword ptr [rax+ymm1*1], xmm2 +Encodable! C4E26D910408 +Identical re-encoding diff --git a/tests/tests-base/test-00300/cmd b/tests/tests-base/test-00300/cmd new file mode 100644 index 0000000..1ac0871 --- /dev/null +++ b/tests/tests-base/test-00300/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E269910408 diff --git a/tests/tests-base/test-00300/codes b/tests/tests-base/test-00300/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00300/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00300/retcode.reference b/tests/tests-base/test-00300/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00300/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00300/stderr.reference b/tests/tests-base/test-00300/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00300/stdout.reference b/tests/tests-base/test-00300/stdout.reference new file mode 100644 index 0000000..8bc40d9 --- /dev/null +++ b/tests/tests-base/test-00300/stdout.reference @@ -0,0 +1,5 @@ +C4E269910408 +ICLASS: VPGATHERQD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQD_XMMu32_MEMq_XMMi32_VL128 ISA_SET: AVX2GATHER +SHORT: vpgatherqd xmm0, qword ptr [rax+xmm1*1], xmm2 +Encodable! C4E269910408 +Identical re-encoding diff --git a/tests/tests-base/test-00301/cmd b/tests/tests-base/test-00301/cmd new file mode 100644 index 0000000..500ec02 --- /dev/null +++ b/tests/tests-base/test-00301/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2E9910408 diff --git a/tests/tests-base/test-00301/codes b/tests/tests-base/test-00301/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00301/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00301/retcode.reference b/tests/tests-base/test-00301/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00301/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00301/stderr.reference b/tests/tests-base/test-00301/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00301/stdout.reference b/tests/tests-base/test-00301/stdout.reference new file mode 100644 index 0000000..83e1079 --- /dev/null +++ b/tests/tests-base/test-00301/stdout.reference @@ -0,0 +1,5 @@ +C4E2E9910408 +ICLASS: VPGATHERQQ CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQQ_XMMu64_MEMdq_XMMi64_VL128 ISA_SET: AVX2GATHER +SHORT: vpgatherqq xmm0, xmmword ptr [rax+xmm1*1], xmm2 +Encodable! C4E2E9910408 +Identical re-encoding diff --git a/tests/tests-base/test-00302/cmd b/tests/tests-base/test-00302/cmd new file mode 100644 index 0000000..7c75d28 --- /dev/null +++ b/tests/tests-base/test-00302/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C4E2ED910408 diff --git a/tests/tests-base/test-00302/codes b/tests/tests-base/test-00302/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00302/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00302/retcode.reference b/tests/tests-base/test-00302/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00302/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00302/stderr.reference b/tests/tests-base/test-00302/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00302/stdout.reference b/tests/tests-base/test-00302/stdout.reference new file mode 100644 index 0000000..094a308 --- /dev/null +++ b/tests/tests-base/test-00302/stdout.reference @@ -0,0 +1,5 @@ +C4E2ED910408 +ICLASS: VPGATHERQQ CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQQ_YMMu64_MEMqq_YMMi64_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherqq ymm0, ymmword ptr [rax+ymm1*1], ymm2 +Encodable! C4E2ED910408 +Identical re-encoding diff --git a/tests/tests-base/test-00303/cmd b/tests/tests-base/test-00303/cmd new file mode 100644 index 0000000..18a45c9 --- /dev/null +++ b/tests/tests-base/test-00303/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex-ild2 -64 8f e9 78 81 ca diff --git a/tests/tests-base/test-00303/codes b/tests/tests-base/test-00303/codes new file mode 100644 index 0000000..37fab49 --- /dev/null +++ b/tests/tests-base/test-00303/codes @@ -0,0 +1 @@ +DEC XOP diff --git a/tests/tests-base/test-00303/retcode.reference b/tests/tests-base/test-00303/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00303/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00303/stderr.reference b/tests/tests-base/test-00303/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00303/stdout.reference b/tests/tests-base/test-00303/stdout.reference new file mode 100644 index 0000000..b17b240 --- /dev/null +++ b/tests/tests-base/test-00303/stdout.reference @@ -0,0 +1,5 @@ +Attempting to decode: 8fe97881ca + chip = INVALID +ILD length = 5 +Traditional length = 5 +Length matched diff --git a/tests/tests-base/test-00304/cmd b/tests/tests-base/test-00304/cmd new file mode 100644 index 0000000..67c200e --- /dev/null +++ b/tests/tests-base/test-00304/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex-ild2 -64 -chip WESTMERE 8f e9 78 81 ca diff --git a/tests/tests-base/test-00304/codes b/tests/tests-base/test-00304/codes new file mode 100644 index 0000000..37fab49 --- /dev/null +++ b/tests/tests-base/test-00304/codes @@ -0,0 +1 @@ +DEC XOP diff --git a/tests/tests-base/test-00304/retcode.reference b/tests/tests-base/test-00304/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00304/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00304/stderr.reference b/tests/tests-base/test-00304/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00304/stdout.reference b/tests/tests-base/test-00304/stdout.reference new file mode 100644 index 0000000..9ce89c6 --- /dev/null +++ b/tests/tests-base/test-00304/stdout.reference @@ -0,0 +1,5 @@ +Setting chip to WESTMERE +Attempting to decode: 8fe97881ca + chip = WESTMERE +ILD length = 2 +Could not decode given input. diff --git a/tests/tests-base/test-00305/cmd b/tests/tests-base/test-00305/cmd new file mode 100644 index 0000000..0e2291f --- /dev/null +++ b/tests/tests-base/test-00305/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f1aff diff --git a/tests/tests-base/test-00305/codes b/tests/tests-base/test-00305/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00305/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00305/retcode.reference b/tests/tests-base/test-00305/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00305/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00305/stderr.reference b/tests/tests-base/test-00305/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00305/stdout.reference b/tests/tests-base/test-00305/stdout.reference new file mode 100644 index 0000000..a764e24 --- /dev/null +++ b/tests/tests-base/test-00305/stdout.reference @@ -0,0 +1,5 @@ +0F1AFF +ICLASS: NOP CATEGORY: WIDENOP EXTENSION: BASE IFORM: NOP_GPRv_GPRv_0F1A ISA_SET: PPRO +SHORT: nop edi, edi +Encodable! 0F1AFF +Identical re-encoding diff --git a/tests/tests-base/test-00306/cmd b/tests/tests-base/test-00306/cmd new file mode 100644 index 0000000..56ed039 --- /dev/null +++ b/tests/tests-base/test-00306/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f1bff diff --git a/tests/tests-base/test-00306/codes b/tests/tests-base/test-00306/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00306/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00306/retcode.reference b/tests/tests-base/test-00306/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00306/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00306/stderr.reference b/tests/tests-base/test-00306/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00306/stdout.reference b/tests/tests-base/test-00306/stdout.reference new file mode 100644 index 0000000..3c794b3 --- /dev/null +++ b/tests/tests-base/test-00306/stdout.reference @@ -0,0 +1,11 @@ +0F1BFF +ICLASS: NOP CATEGORY: WIDENOP EXTENSION: BASE IFORM: NOP_GPRv_GPRv_0F1B ISA_SET: PPRO +SHORT: nop edi, edi +Encodable! 0F1AFF +Discrepenacy after re-encoding. dec_len= 3 [0F1BFF] enc_olen= 3 [0F1AFF] for instruction: NOP NOP_GPRv_GPRv_0F1B EASZ:3, EOSZ:2, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:255, NOMINAL_OPCODE:27, OUTREG:EDI, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, REG:7, REG0:EDI, REG1:EDI, RM:7, SMODE:2, SRM:3, TZCNT +0 REG0/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_B +1 REG1/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +YDIS: nop edi, edi +vs Encode request: NOP EASZ:3, EOSZ:2, HAS_MODRM:1, LZCNT, MAP:1, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:255, NOMINAL_OPCODE:27, OUTREG:EDI, P4, POS_NOMINAL_OPCODE:1, POS_MODRM:2, REG:7, REG0:EDI, REG1:EDI, RM:7, SMODE:2, SRM:3, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00307/cmd b/tests/tests-base/test-00307/cmd new file mode 100644 index 0000000..a9aaa9c --- /dev/null +++ b/tests/tests-base/test-00307/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de f30f1bff diff --git a/tests/tests-base/test-00307/codes b/tests/tests-base/test-00307/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00307/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00307/retcode.reference b/tests/tests-base/test-00307/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00307/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00307/stderr.reference b/tests/tests-base/test-00307/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00307/stdout.reference b/tests/tests-base/test-00307/stdout.reference new file mode 100644 index 0000000..52a681a --- /dev/null +++ b/tests/tests-base/test-00307/stdout.reference @@ -0,0 +1,11 @@ +F30F1BFF +ICLASS: NOP CATEGORY: WIDENOP EXTENSION: BASE IFORM: NOP_GPRv_GPRv_0F1B ISA_SET: PPRO +SHORT: nop edi, edi +Encodable! F30F1AFF +Discrepenacy after re-encoding. dec_len= 4 [F30F1BFF] enc_olen= 4 [F30F1AFF] for instruction: NOP NOP_GPRv_GPRv_0F1B EASZ:3, EOSZ:2, FIRST_F2F3:3, HAS_MODRM:1, ILD_F3, LAST_F2F3:3, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:2, MODRM_BYTE:255, NOMINAL_OPCODE:27, NPREFIXES:1, OUTREG:EDI, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, REG:7, REG0:EDI, REG1:EDI, REP:3, RM:7, SMODE:2, SRM:3, TZCNT +0 REG0/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_B +1 REG1/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_R +YDIS: nop edi, edi +vs Encode request: NOP EASZ:3, EOSZ:2, FIRST_F2F3:3, HAS_MODRM:1, ILD_F3, LAST_F2F3:3, LZCNT, MAP:1, MAX_BYTES:4, MOD:3, MODE:2, MODRM_BYTE:255, NOMINAL_OPCODE:27, NPREFIXES:1, OUTREG:EDI, P4, POS_NOMINAL_OPCODE:2, POS_MODRM:3, REG:7, REG0:EDI, REG1:EDI, REP:3, RM:7, SMODE:2, SRM:3, TZCNT +OPERAND ORDER: REG0 REG1 + diff --git a/tests/tests-base/test-00308/cmd b/tests/tests-base/test-00308/cmd new file mode 100644 index 0000000..7f4ecb1 --- /dev/null +++ b/tests/tests-base/test-00308/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -d c4 c3 bd 79 f2 45 diff --git a/tests/tests-base/test-00308/codes b/tests/tests-base/test-00308/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00308/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00308/retcode.reference b/tests/tests-base/test-00308/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00308/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00308/stderr.reference b/tests/tests-base/test-00308/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00308/stdout.reference b/tests/tests-base/test-00308/stdout.reference new file mode 100644 index 0000000..78e166c --- /dev/null +++ b/tests/tests-base/test-00308/stdout.reference @@ -0,0 +1,3 @@ +C4C3BD79F245 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq ISA_SET: FMA4 +SHORT: vfnmaddpd ymm6, ymm0, ymm4, ymm2 diff --git a/tests/tests-base/test-00309/cmd b/tests/tests-base/test-00309/cmd new file mode 100644 index 0000000..fdfd3ab --- /dev/null +++ b/tests/tests-base/test-00309/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 c3 bd 79 f2 45 diff --git a/tests/tests-base/test-00309/codes b/tests/tests-base/test-00309/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00309/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00309/retcode.reference b/tests/tests-base/test-00309/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00309/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00309/stderr.reference b/tests/tests-base/test-00309/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00309/stdout.reference b/tests/tests-base/test-00309/stdout.reference new file mode 100644 index 0000000..4f3f15a --- /dev/null +++ b/tests/tests-base/test-00309/stdout.reference @@ -0,0 +1,3 @@ +C4C3BD79F245 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq ISA_SET: FMA4 +SHORT: vfnmaddpd ymm6, ymm8, ymm4, ymm10 diff --git a/tests/tests-base/test-00310/cmd b/tests/tests-base/test-00310/cmd new file mode 100644 index 0000000..0ad360d --- /dev/null +++ b/tests/tests-base/test-00310/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -d c4 c3 b9 79 f2 45 diff --git a/tests/tests-base/test-00310/codes b/tests/tests-base/test-00310/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00310/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00310/retcode.reference b/tests/tests-base/test-00310/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00310/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00310/stderr.reference b/tests/tests-base/test-00310/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00310/stdout.reference b/tests/tests-base/test-00310/stdout.reference new file mode 100644 index 0000000..609c6ca --- /dev/null +++ b/tests/tests-base/test-00310/stdout.reference @@ -0,0 +1,3 @@ +C4C3B979F245 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq ISA_SET: FMA4 +SHORT: vfnmaddpd xmm6, xmm0, xmm4, xmm2 diff --git a/tests/tests-base/test-00311/cmd b/tests/tests-base/test-00311/cmd new file mode 100644 index 0000000..6367665 --- /dev/null +++ b/tests/tests-base/test-00311/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de c4 c3 39 79 f2 45 diff --git a/tests/tests-base/test-00311/codes b/tests/tests-base/test-00311/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00311/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00311/retcode.reference b/tests/tests-base/test-00311/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00311/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00311/stderr.reference b/tests/tests-base/test-00311/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00311/stdout.reference b/tests/tests-base/test-00311/stdout.reference new file mode 100644 index 0000000..54c0e50 --- /dev/null +++ b/tests/tests-base/test-00311/stdout.reference @@ -0,0 +1,5 @@ +C4C33979F245 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq ISA_SET: FMA4 +SHORT: vfnmaddpd xmm6, xmm8, xmm10, xmm4 +Encodable! C4C33979F245 +Identical re-encoding diff --git a/tests/tests-base/test-00312/cmd b/tests/tests-base/test-00312/cmd new file mode 100644 index 0000000..5276f1c --- /dev/null +++ b/tests/tests-base/test-00312/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c5 fd 57 c0 diff --git a/tests/tests-base/test-00312/codes b/tests/tests-base/test-00312/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00312/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00312/retcode.reference b/tests/tests-base/test-00312/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00312/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00312/stderr.reference b/tests/tests-base/test-00312/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00312/stdout.reference b/tests/tests-base/test-00312/stdout.reference new file mode 100644 index 0000000..28f2df3 --- /dev/null +++ b/tests/tests-base/test-00312/stdout.reference @@ -0,0 +1,3 @@ +C5FD57C0 +ICLASS: VXORPD CATEGORY: LOGICAL_FP EXTENSION: AVX IFORM: VXORPD_YMMqq_YMMqq_YMMqq ISA_SET: AVX +SHORT: vxorpd ymm0, ymm0, ymm0 diff --git a/tests/tests-base/test-00313/cmd b/tests/tests-base/test-00313/cmd new file mode 100644 index 0000000..de204ac --- /dev/null +++ b/tests/tests-base/test-00313/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de c5 fd 57 c0 diff --git a/tests/tests-base/test-00313/codes b/tests/tests-base/test-00313/codes new file mode 100644 index 0000000..02c1b7e --- /dev/null +++ b/tests/tests-base/test-00313/codes @@ -0,0 +1 @@ +DEC ENC AVX diff --git a/tests/tests-base/test-00313/retcode.reference b/tests/tests-base/test-00313/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00313/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00313/stderr.reference b/tests/tests-base/test-00313/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00313/stdout.reference b/tests/tests-base/test-00313/stdout.reference new file mode 100644 index 0000000..9d55e52 --- /dev/null +++ b/tests/tests-base/test-00313/stdout.reference @@ -0,0 +1,5 @@ +C5FD57C0 +ICLASS: VXORPD CATEGORY: LOGICAL_FP EXTENSION: AVX IFORM: VXORPD_YMMqq_YMMqq_YMMqq ISA_SET: AVX +SHORT: vxorpd ymm0, ymm0, ymm0 +Encodable! C5FD57C0 +Identical re-encoding diff --git a/tests/tests-base/test-00314/cmd b/tests/tests-base/test-00314/cmd new file mode 100644 index 0000000..cbe652d --- /dev/null +++ b/tests/tests-base/test-00314/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vxorpd ymm0 ymm0 ymm0 diff --git a/tests/tests-base/test-00314/codes b/tests/tests-base/test-00314/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00314/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00314/retcode.reference b/tests/tests-base/test-00314/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00314/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00314/stderr.reference b/tests/tests-base/test-00314/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00314/stdout.reference b/tests/tests-base/test-00314/stdout.reference new file mode 100644 index 0000000..f8824b4 --- /dev/null +++ b/tests/tests-base/test-00314/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VXORPD MODE:2, REG0:YMM0, REG1:YMM0, REG2:YMM0, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 + +Encodable! C5FD57C0 diff --git a/tests/tests-base/test-00315/cmd b/tests/tests-base/test-00315/cmd new file mode 100644 index 0000000..3a2620f --- /dev/null +++ b/tests/tests-base/test-00315/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 vxorpd ymm0 ymm0 ymm0 diff --git a/tests/tests-base/test-00315/codes b/tests/tests-base/test-00315/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00315/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00315/retcode.reference b/tests/tests-base/test-00315/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00315/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00315/stderr.reference b/tests/tests-base/test-00315/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00315/stdout.reference b/tests/tests-base/test-00315/stdout.reference new file mode 100644 index 0000000..f27facd --- /dev/null +++ b/tests/tests-base/test-00315/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VXORPD MODE:1, REG0:YMM0, REG1:YMM0, REG2:YMM0, SMODE:1 +OPERAND ORDER: REG0 REG1 REG2 + +Encodable! C5FD57C0 diff --git a/tests/tests-base/test-00316/cmd b/tests/tests-base/test-00316/cmd new file mode 100644 index 0000000..cf9addc --- /dev/null +++ b/tests/tests-base/test-00316/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -d c4 e3 fd 79 42 45 93 diff --git a/tests/tests-base/test-00316/codes b/tests/tests-base/test-00316/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00316/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00316/retcode.reference b/tests/tests-base/test-00316/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00316/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00316/stderr.reference b/tests/tests-base/test-00316/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00316/stdout.reference b/tests/tests-base/test-00316/stdout.reference new file mode 100644 index 0000000..a886f37 --- /dev/null +++ b/tests/tests-base/test-00316/stdout.reference @@ -0,0 +1,3 @@ +C4E3FD79424593 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq ISA_SET: FMA4 +SHORT: vfnmaddpd ymm0, ymm0, ymm1, ymmword ptr [edx+0x45] diff --git a/tests/tests-base/test-00317/cmd b/tests/tests-base/test-00317/cmd new file mode 100644 index 0000000..1bb9c61 --- /dev/null +++ b/tests/tests-base/test-00317/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 e3 fd 79 42 45 93 diff --git a/tests/tests-base/test-00317/codes b/tests/tests-base/test-00317/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00317/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00317/retcode.reference b/tests/tests-base/test-00317/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00317/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00317/stderr.reference b/tests/tests-base/test-00317/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00317/stdout.reference b/tests/tests-base/test-00317/stdout.reference new file mode 100644 index 0000000..fc2ff3b --- /dev/null +++ b/tests/tests-base/test-00317/stdout.reference @@ -0,0 +1,3 @@ +C4E3FD79424593 +ICLASS: VFNMADDPD CATEGORY: FMA4 EXTENSION: FMA4 IFORM: VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq ISA_SET: FMA4 +SHORT: vfnmaddpd ymm0, ymm0, ymm9, ymmword ptr [rdx+0x45] diff --git a/tests/tests-base/test-00318/cmd b/tests/tests-base/test-00318/cmd new file mode 100644 index 0000000..813ac83 --- /dev/null +++ b/tests/tests-base/test-00318/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 8F 43 24 diff --git a/tests/tests-base/test-00318/codes b/tests/tests-base/test-00318/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00318/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00318/retcode.reference b/tests/tests-base/test-00318/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00318/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00318/stderr.reference b/tests/tests-base/test-00318/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00318/stdout.reference b/tests/tests-base/test-00318/stdout.reference new file mode 100644 index 0000000..29e7d50 --- /dev/null +++ b/tests/tests-base/test-00318/stdout.reference @@ -0,0 +1,3 @@ +8F4324 +ICLASS: POP CATEGORY: POP EXTENSION: BASE IFORM: POP_MEMv ISA_SET: I86 +SHORT: pop qword ptr [rbx+0x24] diff --git a/tests/tests-base/test-00319/cmd b/tests/tests-base/test-00319/cmd new file mode 100644 index 0000000..7952b99 --- /dev/null +++ b/tests/tests-base/test-00319/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 03 f1 49 fe 0f diff --git a/tests/tests-base/test-00319/codes b/tests/tests-base/test-00319/codes new file mode 100644 index 0000000..4e6cee1 --- /dev/null +++ b/tests/tests-base/test-00319/codes @@ -0,0 +1 @@ +DEC AVX XOP diff --git a/tests/tests-base/test-00319/retcode.reference b/tests/tests-base/test-00319/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00319/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00319/stderr.reference b/tests/tests-base/test-00319/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00319/stdout.reference b/tests/tests-base/test-00319/stdout.reference new file mode 100644 index 0000000..04a27cb --- /dev/null +++ b/tests/tests-base/test-00319/stdout.reference @@ -0,0 +1,3 @@ +C403F149FE0F +ICLASS: VPERMIL2PD CATEGORY: XOP EXTENSION: XOP IFORM: VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb ISA_SET: XOP +SHORT: vpermil2pd xmm15, xmm1, xmm0, xmm14, 0xf diff --git a/tests/tests-base/test-00320/cmd b/tests/tests-base/test-00320/cmd new file mode 100644 index 0000000..772ec08 --- /dev/null +++ b/tests/tests-base/test-00320/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 03 71 49 fe 0f diff --git a/tests/tests-base/test-00320/codes b/tests/tests-base/test-00320/codes new file mode 100644 index 0000000..4e6cee1 --- /dev/null +++ b/tests/tests-base/test-00320/codes @@ -0,0 +1 @@ +DEC AVX XOP diff --git a/tests/tests-base/test-00320/retcode.reference b/tests/tests-base/test-00320/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00320/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00320/stderr.reference b/tests/tests-base/test-00320/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00320/stdout.reference b/tests/tests-base/test-00320/stdout.reference new file mode 100644 index 0000000..f4eb48a --- /dev/null +++ b/tests/tests-base/test-00320/stdout.reference @@ -0,0 +1,3 @@ +C4037149FE0F +ICLASS: VPERMIL2PD CATEGORY: XOP EXTENSION: XOP IFORM: VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb ISA_SET: XOP +SHORT: vpermil2pd xmm15, xmm1, xmm14, xmm0, 0xf diff --git a/tests/tests-base/test-00321/cmd b/tests/tests-base/test-00321/cmd new file mode 100644 index 0000000..62369ac --- /dev/null +++ b/tests/tests-base/test-00321/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 83 f1 48 fe 0f diff --git a/tests/tests-base/test-00321/codes b/tests/tests-base/test-00321/codes new file mode 100644 index 0000000..4e6cee1 --- /dev/null +++ b/tests/tests-base/test-00321/codes @@ -0,0 +1 @@ +DEC AVX XOP diff --git a/tests/tests-base/test-00321/retcode.reference b/tests/tests-base/test-00321/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00321/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00321/stderr.reference b/tests/tests-base/test-00321/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00321/stdout.reference b/tests/tests-base/test-00321/stdout.reference new file mode 100644 index 0000000..ae25bac --- /dev/null +++ b/tests/tests-base/test-00321/stdout.reference @@ -0,0 +1,3 @@ +C483F148FE0F +ICLASS: VPERMIL2PS CATEGORY: XOP EXTENSION: XOP IFORM: VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb ISA_SET: XOP +SHORT: vpermil2ps xmm7, xmm1, xmm0, xmm14, 0xf diff --git a/tests/tests-base/test-00322/cmd b/tests/tests-base/test-00322/cmd new file mode 100644 index 0000000..2925d60 --- /dev/null +++ b/tests/tests-base/test-00322/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 03 f1 49 7e 0f 00 diff --git a/tests/tests-base/test-00322/codes b/tests/tests-base/test-00322/codes new file mode 100644 index 0000000..4e6cee1 --- /dev/null +++ b/tests/tests-base/test-00322/codes @@ -0,0 +1 @@ +DEC AVX XOP diff --git a/tests/tests-base/test-00322/retcode.reference b/tests/tests-base/test-00322/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00322/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00322/stderr.reference b/tests/tests-base/test-00322/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00322/stdout.reference b/tests/tests-base/test-00322/stdout.reference new file mode 100644 index 0000000..e61ea07 --- /dev/null +++ b/tests/tests-base/test-00322/stdout.reference @@ -0,0 +1,3 @@ +C403F1497E0F00 +ICLASS: VPERMIL2PD CATEGORY: XOP EXTENSION: XOP IFORM: VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb ISA_SET: XOP +SHORT: vpermil2pd xmm15, xmm1, xmm0, xmmword ptr [r14+0xf], 0x0 diff --git a/tests/tests-base/test-00323/cmd b/tests/tests-base/test-00323/cmd new file mode 100644 index 0000000..02e16fc --- /dev/null +++ b/tests/tests-base/test-00323/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 03 71 49 7e 7f ff diff --git a/tests/tests-base/test-00323/codes b/tests/tests-base/test-00323/codes new file mode 100644 index 0000000..4e6cee1 --- /dev/null +++ b/tests/tests-base/test-00323/codes @@ -0,0 +1 @@ +DEC AVX XOP diff --git a/tests/tests-base/test-00323/retcode.reference b/tests/tests-base/test-00323/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00323/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00323/stderr.reference b/tests/tests-base/test-00323/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00323/stdout.reference b/tests/tests-base/test-00323/stdout.reference new file mode 100644 index 0000000..f5d2b1c --- /dev/null +++ b/tests/tests-base/test-00323/stdout.reference @@ -0,0 +1,3 @@ +C40371497E7FFF +ICLASS: VPERMIL2PD CATEGORY: XOP EXTENSION: XOP IFORM: VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb ISA_SET: XOP +SHORT: vpermil2pd xmm15, xmm1, xmmword ptr [r14+0x7f], xmm15, 0xff diff --git a/tests/tests-base/test-00324/cmd b/tests/tests-base/test-00324/cmd new file mode 100644 index 0000000..934bc32 --- /dev/null +++ b/tests/tests-base/test-00324/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d c4 dc 9b c3 72 d7 68 3e diff --git a/tests/tests-base/test-00324/codes b/tests/tests-base/test-00324/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00324/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00324/retcode.reference b/tests/tests-base/test-00324/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00324/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00324/stderr.reference b/tests/tests-base/test-00324/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00324/stdout.reference b/tests/tests-base/test-00324/stdout.reference new file mode 100644 index 0000000..19c8ed5 --- /dev/null +++ b/tests/tests-base/test-00324/stdout.reference @@ -0,0 +1,2 @@ +C4DC9BC372D7683E +ERROR: GENERAL_ERROR Could not decode at offset: 0x0 PC: 0x0: [C4DC9BC372D7683E00000000000000] diff --git a/tests/tests-base/test-00325/cmd b/tests/tests-base/test-00325/cmd new file mode 100644 index 0000000..27d9aa8 --- /dev/null +++ b/tests/tests-base/test-00325/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 4d c4 12 bd 79 f2 45 diff --git a/tests/tests-base/test-00325/codes b/tests/tests-base/test-00325/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00325/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00325/retcode.reference b/tests/tests-base/test-00325/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00325/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00325/stderr.reference b/tests/tests-base/test-00325/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00325/stdout.reference b/tests/tests-base/test-00325/stdout.reference new file mode 100644 index 0000000..649298d --- /dev/null +++ b/tests/tests-base/test-00325/stdout.reference @@ -0,0 +1,2 @@ +4DC412BD79F245 +ERROR: BAD_REX_PREFIX Could not decode at offset: 0x0 PC: 0x0: [4DC412BD79F2450000000000000000] diff --git a/tests/tests-base/test-00326/cmd b/tests/tests-base/test-00326/cmd new file mode 100644 index 0000000..774c8aa --- /dev/null +++ b/tests/tests-base/test-00326/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d a0 11 22 33 44 55 66 77 88 diff --git a/tests/tests-base/test-00326/codes b/tests/tests-base/test-00326/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00326/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00326/retcode.reference b/tests/tests-base/test-00326/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00326/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00326/stderr.reference b/tests/tests-base/test-00326/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00326/stdout.reference b/tests/tests-base/test-00326/stdout.reference new file mode 100644 index 0000000..c30c1bf --- /dev/null +++ b/tests/tests-base/test-00326/stdout.reference @@ -0,0 +1,3 @@ +A01122334455667788 +ICLASS: MOV CATEGORY: DATAXFER EXTENSION: BASE IFORM: MOV_AL_MEMb ISA_SET: I86 +SHORT: mov al, byte ptr [0x8877665544332211] diff --git a/tests/tests-base/test-00327/cmd b/tests/tests-base/test-00327/cmd new file mode 100644 index 0000000..0c047e1 --- /dev/null +++ b/tests/tests-base/test-00327/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 65 66 41 0F diff --git a/tests/tests-base/test-00327/codes b/tests/tests-base/test-00327/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00327/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00327/retcode.reference b/tests/tests-base/test-00327/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00327/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00327/stderr.reference b/tests/tests-base/test-00327/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00327/stdout.reference b/tests/tests-base/test-00327/stdout.reference new file mode 100644 index 0000000..9b9306f --- /dev/null +++ b/tests/tests-base/test-00327/stdout.reference @@ -0,0 +1,2 @@ +6566410F +ERROR: BUFFER_TOO_SHORT Could not decode at offset: 0x0 PC: 0x0: [6566410F0000000000000000000000] diff --git a/tests/tests-base/test-00328/cmd b/tests/tests-base/test-00328/cmd new file mode 100644 index 0000000..a815767 --- /dev/null +++ b/tests/tests-base/test-00328/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 e2 f1 92 44 40 11 diff --git a/tests/tests-base/test-00328/codes b/tests/tests-base/test-00328/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00328/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00328/retcode.reference b/tests/tests-base/test-00328/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00328/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00328/stderr.reference b/tests/tests-base/test-00328/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00328/stdout.reference b/tests/tests-base/test-00328/stdout.reference new file mode 100644 index 0000000..bcf15b7 --- /dev/null +++ b/tests/tests-base/test-00328/stdout.reference @@ -0,0 +1,2 @@ +C4E2F192444011 +ERROR: GATHER_REGS Could not decode at offset: 0x0 PC: 0x0: [C4E2F1924440110000000000000000] diff --git a/tests/tests-base/test-00329/cmd b/tests/tests-base/test-00329/cmd new file mode 100644 index 0000000..32f5a16 --- /dev/null +++ b/tests/tests-base/test-00329/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 e2 f9 92 64 40 11 diff --git a/tests/tests-base/test-00329/codes b/tests/tests-base/test-00329/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00329/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00329/retcode.reference b/tests/tests-base/test-00329/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00329/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00329/stderr.reference b/tests/tests-base/test-00329/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00329/stdout.reference b/tests/tests-base/test-00329/stdout.reference new file mode 100644 index 0000000..581de14 --- /dev/null +++ b/tests/tests-base/test-00329/stdout.reference @@ -0,0 +1,2 @@ +C4E2F992644011 +ERROR: GATHER_REGS Could not decode at offset: 0x0 PC: 0x0: [C4E2F9926440110000000000000000] diff --git a/tests/tests-base/test-00330/cmd b/tests/tests-base/test-00330/cmd new file mode 100644 index 0000000..e2f3189 --- /dev/null +++ b/tests/tests-base/test-00330/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 e2 d9 92 64 40 11 diff --git a/tests/tests-base/test-00330/codes b/tests/tests-base/test-00330/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00330/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00330/retcode.reference b/tests/tests-base/test-00330/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00330/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00330/stderr.reference b/tests/tests-base/test-00330/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00330/stdout.reference b/tests/tests-base/test-00330/stdout.reference new file mode 100644 index 0000000..5d78aa6 --- /dev/null +++ b/tests/tests-base/test-00330/stdout.reference @@ -0,0 +1,2 @@ +C4E2D992644011 +ERROR: GATHER_REGS Could not decode at offset: 0x0 PC: 0x0: [C4E2D9926440110000000000000000] diff --git a/tests/tests-base/test-00331/cmd b/tests/tests-base/test-00331/cmd new file mode 100644 index 0000000..ad798ca --- /dev/null +++ b/tests/tests-base/test-00331/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e INSB diff --git a/tests/tests-base/test-00331/codes b/tests/tests-base/test-00331/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00331/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00331/retcode.reference b/tests/tests-base/test-00331/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00331/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00331/stderr.reference b/tests/tests-base/test-00331/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00331/stdout.reference b/tests/tests-base/test-00331/stdout.reference new file mode 100644 index 0000000..cc163c7 --- /dev/null +++ b/tests/tests-base/test-00331/stdout.reference @@ -0,0 +1,3 @@ +Request: INSB MODE:1, SMODE:1 +Encodable! 6C +.byte 0x6c diff --git a/tests/tests-base/test-00332/cmd b/tests/tests-base/test-00332/cmd new file mode 100644 index 0000000..8d121cf --- /dev/null +++ b/tests/tests-base/test-00332/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e INSW/16 diff --git a/tests/tests-base/test-00332/codes b/tests/tests-base/test-00332/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00332/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00332/retcode.reference b/tests/tests-base/test-00332/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00332/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00332/stderr.reference b/tests/tests-base/test-00332/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00332/stdout.reference b/tests/tests-base/test-00332/stdout.reference new file mode 100644 index 0000000..7d88b2e --- /dev/null +++ b/tests/tests-base/test-00332/stdout.reference @@ -0,0 +1,3 @@ +Request: INSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 666D +.byte 0x66,0x6d diff --git a/tests/tests-base/test-00333/cmd b/tests/tests-base/test-00333/cmd new file mode 100644 index 0000000..09131c2 --- /dev/null +++ b/tests/tests-base/test-00333/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e INSD diff --git a/tests/tests-base/test-00333/codes b/tests/tests-base/test-00333/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00333/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00333/retcode.reference b/tests/tests-base/test-00333/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00333/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00333/stderr.reference b/tests/tests-base/test-00333/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00333/stdout.reference b/tests/tests-base/test-00333/stdout.reference new file mode 100644 index 0000000..c669fd3 --- /dev/null +++ b/tests/tests-base/test-00333/stdout.reference @@ -0,0 +1,3 @@ +Request: INSD MODE:1, SMODE:1 +Encodable! 6D +.byte 0x6d diff --git a/tests/tests-base/test-00334/cmd b/tests/tests-base/test-00334/cmd new file mode 100644 index 0000000..09131c2 --- /dev/null +++ b/tests/tests-base/test-00334/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e INSD diff --git a/tests/tests-base/test-00334/codes b/tests/tests-base/test-00334/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00334/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00334/retcode.reference b/tests/tests-base/test-00334/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00334/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00334/stderr.reference b/tests/tests-base/test-00334/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00334/stdout.reference b/tests/tests-base/test-00334/stdout.reference new file mode 100644 index 0000000..c669fd3 --- /dev/null +++ b/tests/tests-base/test-00334/stdout.reference @@ -0,0 +1,3 @@ +Request: INSD MODE:1, SMODE:1 +Encodable! 6D +.byte 0x6d diff --git a/tests/tests-base/test-00335/cmd b/tests/tests-base/test-00335/cmd new file mode 100644 index 0000000..78c7690 --- /dev/null +++ b/tests/tests-base/test-00335/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e OUTSB diff --git a/tests/tests-base/test-00335/codes b/tests/tests-base/test-00335/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00335/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00335/retcode.reference b/tests/tests-base/test-00335/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00335/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00335/stderr.reference b/tests/tests-base/test-00335/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00335/stdout.reference b/tests/tests-base/test-00335/stdout.reference new file mode 100644 index 0000000..9759d1a --- /dev/null +++ b/tests/tests-base/test-00335/stdout.reference @@ -0,0 +1,3 @@ +Request: OUTSB MODE:1, SMODE:1 +Encodable! 6E +.byte 0x6e diff --git a/tests/tests-base/test-00336/cmd b/tests/tests-base/test-00336/cmd new file mode 100644 index 0000000..481128c --- /dev/null +++ b/tests/tests-base/test-00336/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e OUTSW/16 diff --git a/tests/tests-base/test-00336/codes b/tests/tests-base/test-00336/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00336/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00336/retcode.reference b/tests/tests-base/test-00336/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00336/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00336/stderr.reference b/tests/tests-base/test-00336/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00336/stdout.reference b/tests/tests-base/test-00336/stdout.reference new file mode 100644 index 0000000..b11b4ed --- /dev/null +++ b/tests/tests-base/test-00336/stdout.reference @@ -0,0 +1,3 @@ +Request: OUTSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 666F +.byte 0x66,0x6f diff --git a/tests/tests-base/test-00337/cmd b/tests/tests-base/test-00337/cmd new file mode 100644 index 0000000..992168c --- /dev/null +++ b/tests/tests-base/test-00337/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e OUTSD diff --git a/tests/tests-base/test-00337/codes b/tests/tests-base/test-00337/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00337/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00337/retcode.reference b/tests/tests-base/test-00337/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00337/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00337/stderr.reference b/tests/tests-base/test-00337/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00337/stdout.reference b/tests/tests-base/test-00337/stdout.reference new file mode 100644 index 0000000..07f3ade --- /dev/null +++ b/tests/tests-base/test-00337/stdout.reference @@ -0,0 +1,3 @@ +Request: OUTSD MODE:1, SMODE:1 +Encodable! 6F +.byte 0x6f diff --git a/tests/tests-base/test-00338/cmd b/tests/tests-base/test-00338/cmd new file mode 100644 index 0000000..992168c --- /dev/null +++ b/tests/tests-base/test-00338/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e OUTSD diff --git a/tests/tests-base/test-00338/codes b/tests/tests-base/test-00338/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00338/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00338/retcode.reference b/tests/tests-base/test-00338/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00338/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00338/stderr.reference b/tests/tests-base/test-00338/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00338/stdout.reference b/tests/tests-base/test-00338/stdout.reference new file mode 100644 index 0000000..07f3ade --- /dev/null +++ b/tests/tests-base/test-00338/stdout.reference @@ -0,0 +1,3 @@ +Request: OUTSD MODE:1, SMODE:1 +Encodable! 6F +.byte 0x6f diff --git a/tests/tests-base/test-00339/cmd b/tests/tests-base/test-00339/cmd new file mode 100644 index 0000000..d95e7dd --- /dev/null +++ b/tests/tests-base/test-00339/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e PUSHF/16 diff --git a/tests/tests-base/test-00339/codes b/tests/tests-base/test-00339/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00339/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00339/retcode.reference b/tests/tests-base/test-00339/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00339/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00339/stderr.reference b/tests/tests-base/test-00339/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00339/stdout.reference b/tests/tests-base/test-00339/stdout.reference new file mode 100644 index 0000000..0bd7802 --- /dev/null +++ b/tests/tests-base/test-00339/stdout.reference @@ -0,0 +1,3 @@ +Request: PUSHF EOSZ:1, MODE:1, SMODE:1 +Encodable! 669C +.byte 0x66,0x9c diff --git a/tests/tests-base/test-00340/cmd b/tests/tests-base/test-00340/cmd new file mode 100644 index 0000000..930ba36 --- /dev/null +++ b/tests/tests-base/test-00340/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e PUSHFD diff --git a/tests/tests-base/test-00340/codes b/tests/tests-base/test-00340/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00340/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00340/retcode.reference b/tests/tests-base/test-00340/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00340/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00340/stderr.reference b/tests/tests-base/test-00340/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00340/stdout.reference b/tests/tests-base/test-00340/stdout.reference new file mode 100644 index 0000000..8521276 --- /dev/null +++ b/tests/tests-base/test-00340/stdout.reference @@ -0,0 +1,3 @@ +Request: PUSHFD MODE:1, SMODE:1 +Encodable! 9C +.byte 0x9c diff --git a/tests/tests-base/test-00341/cmd b/tests/tests-base/test-00341/cmd new file mode 100644 index 0000000..f94943a --- /dev/null +++ b/tests/tests-base/test-00341/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e PUSHFQ/64 diff --git a/tests/tests-base/test-00341/codes b/tests/tests-base/test-00341/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00341/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00341/retcode.reference b/tests/tests-base/test-00341/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00341/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00341/stderr.reference b/tests/tests-base/test-00341/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00341/stdout.reference b/tests/tests-base/test-00341/stdout.reference new file mode 100644 index 0000000..f6fca89 --- /dev/null +++ b/tests/tests-base/test-00341/stdout.reference @@ -0,0 +1,3 @@ +Request: PUSHFQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 9C +.byte 0x9c diff --git a/tests/tests-base/test-00342/cmd b/tests/tests-base/test-00342/cmd new file mode 100644 index 0000000..e4143bd --- /dev/null +++ b/tests/tests-base/test-00342/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e POPF/16 diff --git a/tests/tests-base/test-00342/codes b/tests/tests-base/test-00342/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00342/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00342/retcode.reference b/tests/tests-base/test-00342/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00342/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00342/stderr.reference b/tests/tests-base/test-00342/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00342/stdout.reference b/tests/tests-base/test-00342/stdout.reference new file mode 100644 index 0000000..947e33d --- /dev/null +++ b/tests/tests-base/test-00342/stdout.reference @@ -0,0 +1,3 @@ +Request: POPF EOSZ:1, MODE:1, SMODE:1 +Encodable! 669D +.byte 0x66,0x9d diff --git a/tests/tests-base/test-00343/cmd b/tests/tests-base/test-00343/cmd new file mode 100644 index 0000000..55c1a58 --- /dev/null +++ b/tests/tests-base/test-00343/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e POPFD diff --git a/tests/tests-base/test-00343/codes b/tests/tests-base/test-00343/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00343/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00343/retcode.reference b/tests/tests-base/test-00343/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00343/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00343/stderr.reference b/tests/tests-base/test-00343/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00343/stdout.reference b/tests/tests-base/test-00343/stdout.reference new file mode 100644 index 0000000..2d8aef1 --- /dev/null +++ b/tests/tests-base/test-00343/stdout.reference @@ -0,0 +1,3 @@ +Request: POPFD MODE:1, SMODE:1 +Encodable! 9D +.byte 0x9d diff --git a/tests/tests-base/test-00344/cmd b/tests/tests-base/test-00344/cmd new file mode 100644 index 0000000..2fdf0f7 --- /dev/null +++ b/tests/tests-base/test-00344/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e POPFQ/64 diff --git a/tests/tests-base/test-00344/codes b/tests/tests-base/test-00344/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00344/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00344/retcode.reference b/tests/tests-base/test-00344/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00344/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00344/stderr.reference b/tests/tests-base/test-00344/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00344/stdout.reference b/tests/tests-base/test-00344/stdout.reference new file mode 100644 index 0000000..0c8769a --- /dev/null +++ b/tests/tests-base/test-00344/stdout.reference @@ -0,0 +1,3 @@ +Request: POPFQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 9D +.byte 0x9d diff --git a/tests/tests-base/test-00345/cmd b/tests/tests-base/test-00345/cmd new file mode 100644 index 0000000..5b8fccd --- /dev/null +++ b/tests/tests-base/test-00345/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e MOVSB diff --git a/tests/tests-base/test-00345/codes b/tests/tests-base/test-00345/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00345/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00345/retcode.reference b/tests/tests-base/test-00345/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00345/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00345/stderr.reference b/tests/tests-base/test-00345/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00345/stdout.reference b/tests/tests-base/test-00345/stdout.reference new file mode 100644 index 0000000..dfaf092 --- /dev/null +++ b/tests/tests-base/test-00345/stdout.reference @@ -0,0 +1,3 @@ +Request: MOVSB MODE:1, SMODE:1 +Encodable! A4 +.byte 0xa4 diff --git a/tests/tests-base/test-00346/cmd b/tests/tests-base/test-00346/cmd new file mode 100644 index 0000000..9fb1572 --- /dev/null +++ b/tests/tests-base/test-00346/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e MOVSW/16 diff --git a/tests/tests-base/test-00346/codes b/tests/tests-base/test-00346/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00346/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00346/retcode.reference b/tests/tests-base/test-00346/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00346/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00346/stderr.reference b/tests/tests-base/test-00346/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00346/stdout.reference b/tests/tests-base/test-00346/stdout.reference new file mode 100644 index 0000000..4bec70f --- /dev/null +++ b/tests/tests-base/test-00346/stdout.reference @@ -0,0 +1,3 @@ +Request: MOVSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 66A5 +.byte 0x66,0xa5 diff --git a/tests/tests-base/test-00347/cmd b/tests/tests-base/test-00347/cmd new file mode 100644 index 0000000..525bc9e --- /dev/null +++ b/tests/tests-base/test-00347/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e MOVSD diff --git a/tests/tests-base/test-00347/codes b/tests/tests-base/test-00347/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00347/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00347/retcode.reference b/tests/tests-base/test-00347/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00347/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00347/stderr.reference b/tests/tests-base/test-00347/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00347/stdout.reference b/tests/tests-base/test-00347/stdout.reference new file mode 100644 index 0000000..41cb580 --- /dev/null +++ b/tests/tests-base/test-00347/stdout.reference @@ -0,0 +1,3 @@ +Request: MOVSD MODE:1, SMODE:1 +Encodable! A5 +.byte 0xa5 diff --git a/tests/tests-base/test-00348/cmd b/tests/tests-base/test-00348/cmd new file mode 100644 index 0000000..0610be7 --- /dev/null +++ b/tests/tests-base/test-00348/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e MOVSQ/64 diff --git a/tests/tests-base/test-00348/codes b/tests/tests-base/test-00348/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00348/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00348/retcode.reference b/tests/tests-base/test-00348/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00348/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00348/stderr.reference b/tests/tests-base/test-00348/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00348/stdout.reference b/tests/tests-base/test-00348/stdout.reference new file mode 100644 index 0000000..a8b3e32 --- /dev/null +++ b/tests/tests-base/test-00348/stdout.reference @@ -0,0 +1,3 @@ +Request: MOVSQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48A5 +.byte 0x48,0xa5 diff --git a/tests/tests-base/test-00349/cmd b/tests/tests-base/test-00349/cmd new file mode 100644 index 0000000..3e51088 --- /dev/null +++ b/tests/tests-base/test-00349/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e CMPSB diff --git a/tests/tests-base/test-00349/codes b/tests/tests-base/test-00349/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00349/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00349/retcode.reference b/tests/tests-base/test-00349/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00349/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00349/stderr.reference b/tests/tests-base/test-00349/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00349/stdout.reference b/tests/tests-base/test-00349/stdout.reference new file mode 100644 index 0000000..b57d8e0 --- /dev/null +++ b/tests/tests-base/test-00349/stdout.reference @@ -0,0 +1,3 @@ +Request: CMPSB MODE:1, SMODE:1 +Encodable! A6 +.byte 0xa6 diff --git a/tests/tests-base/test-00350/cmd b/tests/tests-base/test-00350/cmd new file mode 100644 index 0000000..242bcfb --- /dev/null +++ b/tests/tests-base/test-00350/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e CMPSW/16 diff --git a/tests/tests-base/test-00350/codes b/tests/tests-base/test-00350/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00350/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00350/retcode.reference b/tests/tests-base/test-00350/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00350/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00350/stderr.reference b/tests/tests-base/test-00350/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00350/stdout.reference b/tests/tests-base/test-00350/stdout.reference new file mode 100644 index 0000000..846d5b6 --- /dev/null +++ b/tests/tests-base/test-00350/stdout.reference @@ -0,0 +1,3 @@ +Request: CMPSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 66A7 +.byte 0x66,0xa7 diff --git a/tests/tests-base/test-00351/cmd b/tests/tests-base/test-00351/cmd new file mode 100644 index 0000000..d991dcf --- /dev/null +++ b/tests/tests-base/test-00351/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e CMPSD diff --git a/tests/tests-base/test-00351/codes b/tests/tests-base/test-00351/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00351/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00351/retcode.reference b/tests/tests-base/test-00351/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00351/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00351/stderr.reference b/tests/tests-base/test-00351/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00351/stdout.reference b/tests/tests-base/test-00351/stdout.reference new file mode 100644 index 0000000..a2b0da0 --- /dev/null +++ b/tests/tests-base/test-00351/stdout.reference @@ -0,0 +1,3 @@ +Request: CMPSD MODE:1, SMODE:1 +Encodable! A7 +.byte 0xa7 diff --git a/tests/tests-base/test-00352/cmd b/tests/tests-base/test-00352/cmd new file mode 100644 index 0000000..6c067cd --- /dev/null +++ b/tests/tests-base/test-00352/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e CMPSQ/64 diff --git a/tests/tests-base/test-00352/codes b/tests/tests-base/test-00352/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00352/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00352/retcode.reference b/tests/tests-base/test-00352/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00352/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00352/stderr.reference b/tests/tests-base/test-00352/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00352/stdout.reference b/tests/tests-base/test-00352/stdout.reference new file mode 100644 index 0000000..6f0dc3f --- /dev/null +++ b/tests/tests-base/test-00352/stdout.reference @@ -0,0 +1,3 @@ +Request: CMPSQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48A7 +.byte 0x48,0xa7 diff --git a/tests/tests-base/test-00353/cmd b/tests/tests-base/test-00353/cmd new file mode 100644 index 0000000..57625aa --- /dev/null +++ b/tests/tests-base/test-00353/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e STOSB diff --git a/tests/tests-base/test-00353/codes b/tests/tests-base/test-00353/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00353/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00353/retcode.reference b/tests/tests-base/test-00353/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00353/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00353/stderr.reference b/tests/tests-base/test-00353/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00353/stdout.reference b/tests/tests-base/test-00353/stdout.reference new file mode 100644 index 0000000..a44bd0a --- /dev/null +++ b/tests/tests-base/test-00353/stdout.reference @@ -0,0 +1,3 @@ +Request: STOSB MODE:1, SMODE:1 +Encodable! AA +.byte 0xaa diff --git a/tests/tests-base/test-00354/cmd b/tests/tests-base/test-00354/cmd new file mode 100644 index 0000000..9dc9404 --- /dev/null +++ b/tests/tests-base/test-00354/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e STOSW/16 diff --git a/tests/tests-base/test-00354/codes b/tests/tests-base/test-00354/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00354/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00354/retcode.reference b/tests/tests-base/test-00354/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00354/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00354/stderr.reference b/tests/tests-base/test-00354/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00354/stdout.reference b/tests/tests-base/test-00354/stdout.reference new file mode 100644 index 0000000..48b41bc --- /dev/null +++ b/tests/tests-base/test-00354/stdout.reference @@ -0,0 +1,3 @@ +Request: STOSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 66AB +.byte 0x66,0xab diff --git a/tests/tests-base/test-00355/cmd b/tests/tests-base/test-00355/cmd new file mode 100644 index 0000000..41d9358 --- /dev/null +++ b/tests/tests-base/test-00355/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e STOSD diff --git a/tests/tests-base/test-00355/codes b/tests/tests-base/test-00355/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00355/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00355/retcode.reference b/tests/tests-base/test-00355/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00355/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00355/stderr.reference b/tests/tests-base/test-00355/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00355/stdout.reference b/tests/tests-base/test-00355/stdout.reference new file mode 100644 index 0000000..c4a6bbb --- /dev/null +++ b/tests/tests-base/test-00355/stdout.reference @@ -0,0 +1,3 @@ +Request: STOSD MODE:1, SMODE:1 +Encodable! AB +.byte 0xab diff --git a/tests/tests-base/test-00356/cmd b/tests/tests-base/test-00356/cmd new file mode 100644 index 0000000..9505e54 --- /dev/null +++ b/tests/tests-base/test-00356/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e STOSQ/64 diff --git a/tests/tests-base/test-00356/codes b/tests/tests-base/test-00356/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00356/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00356/retcode.reference b/tests/tests-base/test-00356/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00356/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00356/stderr.reference b/tests/tests-base/test-00356/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00356/stdout.reference b/tests/tests-base/test-00356/stdout.reference new file mode 100644 index 0000000..b4769fe --- /dev/null +++ b/tests/tests-base/test-00356/stdout.reference @@ -0,0 +1,3 @@ +Request: STOSQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48AB +.byte 0x48,0xab diff --git a/tests/tests-base/test-00357/cmd b/tests/tests-base/test-00357/cmd new file mode 100644 index 0000000..07a686c --- /dev/null +++ b/tests/tests-base/test-00357/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e LODSB diff --git a/tests/tests-base/test-00357/codes b/tests/tests-base/test-00357/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00357/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00357/retcode.reference b/tests/tests-base/test-00357/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00357/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00357/stderr.reference b/tests/tests-base/test-00357/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00357/stdout.reference b/tests/tests-base/test-00357/stdout.reference new file mode 100644 index 0000000..5f21d48 --- /dev/null +++ b/tests/tests-base/test-00357/stdout.reference @@ -0,0 +1,3 @@ +Request: LODSB MODE:1, SMODE:1 +Encodable! AC +.byte 0xac diff --git a/tests/tests-base/test-00358/cmd b/tests/tests-base/test-00358/cmd new file mode 100644 index 0000000..4a33b03 --- /dev/null +++ b/tests/tests-base/test-00358/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e LODSW/16 diff --git a/tests/tests-base/test-00358/codes b/tests/tests-base/test-00358/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00358/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00358/retcode.reference b/tests/tests-base/test-00358/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00358/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00358/stderr.reference b/tests/tests-base/test-00358/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00358/stdout.reference b/tests/tests-base/test-00358/stdout.reference new file mode 100644 index 0000000..6f79278 --- /dev/null +++ b/tests/tests-base/test-00358/stdout.reference @@ -0,0 +1,3 @@ +Request: LODSW EOSZ:1, MODE:1, SMODE:1 +Encodable! 66AD +.byte 0x66,0xad diff --git a/tests/tests-base/test-00359/cmd b/tests/tests-base/test-00359/cmd new file mode 100644 index 0000000..795c694 --- /dev/null +++ b/tests/tests-base/test-00359/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e LODSD diff --git a/tests/tests-base/test-00359/codes b/tests/tests-base/test-00359/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00359/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00359/retcode.reference b/tests/tests-base/test-00359/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00359/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00359/stderr.reference b/tests/tests-base/test-00359/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00359/stdout.reference b/tests/tests-base/test-00359/stdout.reference new file mode 100644 index 0000000..9703539 --- /dev/null +++ b/tests/tests-base/test-00359/stdout.reference @@ -0,0 +1,3 @@ +Request: LODSD MODE:1, SMODE:1 +Encodable! AD +.byte 0xad diff --git a/tests/tests-base/test-00360/cmd b/tests/tests-base/test-00360/cmd new file mode 100644 index 0000000..bb1d75b --- /dev/null +++ b/tests/tests-base/test-00360/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e LODSQ/64 diff --git a/tests/tests-base/test-00360/codes b/tests/tests-base/test-00360/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00360/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00360/retcode.reference b/tests/tests-base/test-00360/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00360/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00360/stderr.reference b/tests/tests-base/test-00360/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00360/stdout.reference b/tests/tests-base/test-00360/stdout.reference new file mode 100644 index 0000000..64f1ff2 --- /dev/null +++ b/tests/tests-base/test-00360/stdout.reference @@ -0,0 +1,3 @@ +Request: LODSQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48AD +.byte 0x48,0xad diff --git a/tests/tests-base/test-00361/cmd b/tests/tests-base/test-00361/cmd new file mode 100644 index 0000000..e3d2ac5 --- /dev/null +++ b/tests/tests-base/test-00361/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e SCASB diff --git a/tests/tests-base/test-00361/codes b/tests/tests-base/test-00361/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00361/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00361/retcode.reference b/tests/tests-base/test-00361/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00361/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00361/stderr.reference b/tests/tests-base/test-00361/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00361/stdout.reference b/tests/tests-base/test-00361/stdout.reference new file mode 100644 index 0000000..fcef208 --- /dev/null +++ b/tests/tests-base/test-00361/stdout.reference @@ -0,0 +1,3 @@ +Request: SCASB MODE:1, SMODE:1 +Encodable! AE +.byte 0xae diff --git a/tests/tests-base/test-00362/cmd b/tests/tests-base/test-00362/cmd new file mode 100644 index 0000000..d8f4d6f --- /dev/null +++ b/tests/tests-base/test-00362/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e SCASW/16 diff --git a/tests/tests-base/test-00362/codes b/tests/tests-base/test-00362/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00362/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00362/retcode.reference b/tests/tests-base/test-00362/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00362/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00362/stderr.reference b/tests/tests-base/test-00362/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00362/stdout.reference b/tests/tests-base/test-00362/stdout.reference new file mode 100644 index 0000000..acc2adf --- /dev/null +++ b/tests/tests-base/test-00362/stdout.reference @@ -0,0 +1,3 @@ +Request: SCASW EOSZ:1, MODE:1, SMODE:1 +Encodable! 66AF +.byte 0x66,0xaf diff --git a/tests/tests-base/test-00363/cmd b/tests/tests-base/test-00363/cmd new file mode 100644 index 0000000..584c7f4 --- /dev/null +++ b/tests/tests-base/test-00363/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e SCASD diff --git a/tests/tests-base/test-00363/codes b/tests/tests-base/test-00363/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00363/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00363/retcode.reference b/tests/tests-base/test-00363/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00363/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00363/stderr.reference b/tests/tests-base/test-00363/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00363/stdout.reference b/tests/tests-base/test-00363/stdout.reference new file mode 100644 index 0000000..c1b2e7a --- /dev/null +++ b/tests/tests-base/test-00363/stdout.reference @@ -0,0 +1,3 @@ +Request: SCASD MODE:1, SMODE:1 +Encodable! AF +.byte 0xaf diff --git a/tests/tests-base/test-00364/cmd b/tests/tests-base/test-00364/cmd new file mode 100644 index 0000000..ac852cd --- /dev/null +++ b/tests/tests-base/test-00364/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e SCASQ/64 diff --git a/tests/tests-base/test-00364/codes b/tests/tests-base/test-00364/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00364/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00364/retcode.reference b/tests/tests-base/test-00364/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00364/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00364/stderr.reference b/tests/tests-base/test-00364/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00364/stdout.reference b/tests/tests-base/test-00364/stdout.reference new file mode 100644 index 0000000..6c7c770 --- /dev/null +++ b/tests/tests-base/test-00364/stdout.reference @@ -0,0 +1,3 @@ +Request: SCASQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48AF +.byte 0x48,0xaf diff --git a/tests/tests-base/test-00365/cmd b/tests/tests-base/test-00365/cmd new file mode 100644 index 0000000..3fa3939 --- /dev/null +++ b/tests/tests-base/test-00365/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e IRET/16 diff --git a/tests/tests-base/test-00365/codes b/tests/tests-base/test-00365/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00365/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00365/retcode.reference b/tests/tests-base/test-00365/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00365/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00365/stderr.reference b/tests/tests-base/test-00365/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00365/stdout.reference b/tests/tests-base/test-00365/stdout.reference new file mode 100644 index 0000000..a2a26a4 --- /dev/null +++ b/tests/tests-base/test-00365/stdout.reference @@ -0,0 +1,3 @@ +Request: IRET EOSZ:1, MODE:1, SMODE:1 +Encodable! 66CF +.byte 0x66,0xcf diff --git a/tests/tests-base/test-00366/cmd b/tests/tests-base/test-00366/cmd new file mode 100644 index 0000000..fe8cc63 --- /dev/null +++ b/tests/tests-base/test-00366/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e IRETD diff --git a/tests/tests-base/test-00366/codes b/tests/tests-base/test-00366/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00366/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00366/retcode.reference b/tests/tests-base/test-00366/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00366/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00366/stderr.reference b/tests/tests-base/test-00366/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00366/stdout.reference b/tests/tests-base/test-00366/stdout.reference new file mode 100644 index 0000000..f54f32a --- /dev/null +++ b/tests/tests-base/test-00366/stdout.reference @@ -0,0 +1,3 @@ +Request: IRETD MODE:1, SMODE:1 +Encodable! CF +.byte 0xcf diff --git a/tests/tests-base/test-00367/cmd b/tests/tests-base/test-00367/cmd new file mode 100644 index 0000000..a44459f --- /dev/null +++ b/tests/tests-base/test-00367/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e IRETQ/64 diff --git a/tests/tests-base/test-00367/codes b/tests/tests-base/test-00367/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00367/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00367/retcode.reference b/tests/tests-base/test-00367/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00367/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00367/stderr.reference b/tests/tests-base/test-00367/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00367/stdout.reference b/tests/tests-base/test-00367/stdout.reference new file mode 100644 index 0000000..8fa2fff --- /dev/null +++ b/tests/tests-base/test-00367/stdout.reference @@ -0,0 +1,3 @@ +Request: IRETQ EOSZ:3, MODE:2, SMODE:2 +Encodable! 48CF +.byte 0x48,0xcf diff --git a/tests/tests-base/test-00368/cmd b/tests/tests-base/test-00368/cmd new file mode 100644 index 0000000..1fd3848 --- /dev/null +++ b/tests/tests-base/test-00368/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e CLD diff --git a/tests/tests-base/test-00368/codes b/tests/tests-base/test-00368/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00368/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00368/retcode.reference b/tests/tests-base/test-00368/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00368/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00368/stderr.reference b/tests/tests-base/test-00368/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00368/stdout.reference b/tests/tests-base/test-00368/stdout.reference new file mode 100644 index 0000000..d2588a8 --- /dev/null +++ b/tests/tests-base/test-00368/stdout.reference @@ -0,0 +1,3 @@ +Request: CLD MODE:1, SMODE:1 +Encodable! FC +.byte 0xfc diff --git a/tests/tests-base/test-00369/cmd b/tests/tests-base/test-00369/cmd new file mode 100644 index 0000000..971ee6d --- /dev/null +++ b/tests/tests-base/test-00369/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e STD diff --git a/tests/tests-base/test-00369/codes b/tests/tests-base/test-00369/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00369/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00369/retcode.reference b/tests/tests-base/test-00369/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00369/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00369/stderr.reference b/tests/tests-base/test-00369/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00369/stdout.reference b/tests/tests-base/test-00369/stdout.reference new file mode 100644 index 0000000..7c55ddb --- /dev/null +++ b/tests/tests-base/test-00369/stdout.reference @@ -0,0 +1,3 @@ +Request: STD MODE:1, SMODE:1 +Encodable! FD +.byte 0xfd diff --git a/tests/tests-base/test-00370/cmd b/tests/tests-base/test-00370/cmd new file mode 100644 index 0000000..be1f21f --- /dev/null +++ b/tests/tests-base/test-00370/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e SYSCALL/64 diff --git a/tests/tests-base/test-00370/codes b/tests/tests-base/test-00370/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00370/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00370/retcode.reference b/tests/tests-base/test-00370/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00370/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00370/stderr.reference b/tests/tests-base/test-00370/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00370/stdout.reference b/tests/tests-base/test-00370/stdout.reference new file mode 100644 index 0000000..24c66de --- /dev/null +++ b/tests/tests-base/test-00370/stdout.reference @@ -0,0 +1,3 @@ +Request: SYSCALL EOSZ:3, MODE:2, SMODE:2 +Encodable! 0F05 +.byte 0x0f,0x05 diff --git a/tests/tests-base/test-00371/cmd b/tests/tests-base/test-00371/cmd new file mode 100644 index 0000000..68dd522 --- /dev/null +++ b/tests/tests-base/test-00371/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e SYSRET/64 diff --git a/tests/tests-base/test-00371/codes b/tests/tests-base/test-00371/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00371/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00371/retcode.reference b/tests/tests-base/test-00371/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00371/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00371/stderr.reference b/tests/tests-base/test-00371/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00371/stdout.reference b/tests/tests-base/test-00371/stdout.reference new file mode 100644 index 0000000..e4d8aff --- /dev/null +++ b/tests/tests-base/test-00371/stdout.reference @@ -0,0 +1,3 @@ +Request: SYSRET EOSZ:3, MODE:2, SMODE:2 +Encodable! 480F07 +.byte 0x48,0x0f,0x07 diff --git a/tests/tests-base/test-00372/cmd b/tests/tests-base/test-00372/cmd new file mode 100644 index 0000000..a20a52b --- /dev/null +++ b/tests/tests-base/test-00372/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e RSM diff --git a/tests/tests-base/test-00372/codes b/tests/tests-base/test-00372/codes new file mode 100644 index 0000000..97af984 --- /dev/null +++ b/tests/tests-base/test-00372/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00372/retcode.reference b/tests/tests-base/test-00372/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00372/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00372/stderr.reference b/tests/tests-base/test-00372/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00372/stdout.reference b/tests/tests-base/test-00372/stdout.reference new file mode 100644 index 0000000..3b77bae --- /dev/null +++ b/tests/tests-base/test-00372/stdout.reference @@ -0,0 +1,3 @@ +Request: RSM MODE:1, SMODE:1 +Encodable! 0FAA +.byte 0x0f,0xaa diff --git a/tests/tests-base/test-00373/cmd b/tests/tests-base/test-00373/cmd new file mode 100644 index 0000000..95adf21 --- /dev/null +++ b/tests/tests-base/test-00373/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6C diff --git a/tests/tests-base/test-00373/codes b/tests/tests-base/test-00373/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00373/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00373/retcode.reference b/tests/tests-base/test-00373/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00373/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00373/stderr.reference b/tests/tests-base/test-00373/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00373/stdout.reference b/tests/tests-base/test-00373/stdout.reference new file mode 100644 index 0000000..28d277d --- /dev/null +++ b/tests/tests-base/test-00373/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6c +iclass INSB category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name INSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 NOTSX +ISA SET: [I186] diff --git a/tests/tests-base/test-00374/cmd b/tests/tests-base/test-00374/cmd new file mode 100644 index 0000000..c045c25 --- /dev/null +++ b/tests/tests-base/test-00374/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 666D diff --git a/tests/tests-base/test-00374/codes b/tests/tests-base/test-00374/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00374/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00374/retcode.reference b/tests/tests-base/test-00374/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00374/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00374/stderr.reference b/tests/tests-base/test-00374/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00374/stdout.reference b/tests/tests-base/test-00374/stdout.reference new file mode 100644 index 0000000..1d22129 --- /dev/null +++ b/tests/tests-base/test-00374/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 6d +iclass INSW category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name INSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I186] diff --git a/tests/tests-base/test-00375/cmd b/tests/tests-base/test-00375/cmd new file mode 100644 index 0000000..fd24a86 --- /dev/null +++ b/tests/tests-base/test-00375/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6D diff --git a/tests/tests-base/test-00375/codes b/tests/tests-base/test-00375/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00375/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00375/retcode.reference b/tests/tests-base/test-00375/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00375/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00375/stderr.reference b/tests/tests-base/test-00375/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00375/stdout.reference b/tests/tests-base/test-00375/stdout.reference new file mode 100644 index 0000000..b4bd25f --- /dev/null +++ b/tests/tests-base/test-00375/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6d +iclass INSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name INSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +ISA SET: [I386] diff --git a/tests/tests-base/test-00376/cmd b/tests/tests-base/test-00376/cmd new file mode 100644 index 0000000..fd24a86 --- /dev/null +++ b/tests/tests-base/test-00376/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6D diff --git a/tests/tests-base/test-00376/codes b/tests/tests-base/test-00376/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00376/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00376/retcode.reference b/tests/tests-base/test-00376/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00376/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00376/stderr.reference b/tests/tests-base/test-00376/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00376/stdout.reference b/tests/tests-base/test-00376/stdout.reference new file mode 100644 index 0000000..b4bd25f --- /dev/null +++ b/tests/tests-base/test-00376/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6d +iclass INSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name INSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +ISA SET: [I386] diff --git a/tests/tests-base/test-00377/cmd b/tests/tests-base/test-00377/cmd new file mode 100644 index 0000000..76d17e7 --- /dev/null +++ b/tests/tests-base/test-00377/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6E diff --git a/tests/tests-base/test-00377/codes b/tests/tests-base/test-00377/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00377/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00377/retcode.reference b/tests/tests-base/test-00377/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00377/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00377/stderr.reference b/tests/tests-base/test-00377/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00377/stdout.reference b/tests/tests-base/test-00377/stdout.reference new file mode 100644 index 0000000..7f03648 --- /dev/null +++ b/tests/tests-base/test-00377/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6e +iclass OUTSB category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OUTSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 NOTSX +ISA SET: [I186] diff --git a/tests/tests-base/test-00378/cmd b/tests/tests-base/test-00378/cmd new file mode 100644 index 0000000..3e94219 --- /dev/null +++ b/tests/tests-base/test-00378/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 666F diff --git a/tests/tests-base/test-00378/codes b/tests/tests-base/test-00378/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00378/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00378/retcode.reference b/tests/tests-base/test-00378/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00378/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00378/stderr.reference b/tests/tests-base/test-00378/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00378/stdout.reference b/tests/tests-base/test-00378/stdout.reference new file mode 100644 index 0000000..e3026fd --- /dev/null +++ b/tests/tests-base/test-00378/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 6f +iclass OUTSW category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OUTSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I186] diff --git a/tests/tests-base/test-00379/cmd b/tests/tests-base/test-00379/cmd new file mode 100644 index 0000000..556ec49 --- /dev/null +++ b/tests/tests-base/test-00379/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6F diff --git a/tests/tests-base/test-00379/codes b/tests/tests-base/test-00379/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00379/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00379/retcode.reference b/tests/tests-base/test-00379/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00379/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00379/stderr.reference b/tests/tests-base/test-00379/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00379/stdout.reference b/tests/tests-base/test-00379/stdout.reference new file mode 100644 index 0000000..fb8d46e --- /dev/null +++ b/tests/tests-base/test-00379/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6f +iclass OUTSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OUTSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +ISA SET: [I386] diff --git a/tests/tests-base/test-00380/cmd b/tests/tests-base/test-00380/cmd new file mode 100644 index 0000000..556ec49 --- /dev/null +++ b/tests/tests-base/test-00380/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 6F diff --git a/tests/tests-base/test-00380/codes b/tests/tests-base/test-00380/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00380/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00380/retcode.reference b/tests/tests-base/test-00380/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00380/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00380/stderr.reference b/tests/tests-base/test-00380/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00380/stdout.reference b/tests/tests-base/test-00380/stdout.reference new file mode 100644 index 0000000..fb8d46e --- /dev/null +++ b/tests/tests-base/test-00380/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 6f +iclass OUTSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name OUTSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX +ISA SET: [I386] diff --git a/tests/tests-base/test-00381/cmd b/tests/tests-base/test-00381/cmd new file mode 100644 index 0000000..00224db --- /dev/null +++ b/tests/tests-base/test-00381/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 669C diff --git a/tests/tests-base/test-00381/codes b/tests/tests-base/test-00381/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00381/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00381/retcode.reference b/tests/tests-base/test-00381/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00381/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00381/stderr.reference b/tests/tests-base/test-00381/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00381/stdout.reference b/tests/tests-base/test-00381/stdout.reference new file mode 100644 index 0000000..bba3414 --- /dev/null +++ b/tests/tests-base/test-00381/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: 66 9c +iclass PUSHF category PUSH ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PUSHF +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPUSH SUPPRESSED W W 16 2 1 16 INT PSEUDO +1 MEM0 (see below) SUPPRESSED W W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst + read: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 STACKPUSH0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00382/cmd b/tests/tests-base/test-00382/cmd new file mode 100644 index 0000000..bad0473 --- /dev/null +++ b/tests/tests-base/test-00382/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 9C diff --git a/tests/tests-base/test-00382/codes b/tests/tests-base/test-00382/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00382/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00382/retcode.reference b/tests/tests-base/test-00382/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00382/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00382/stderr.reference b/tests/tests-base/test-00382/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00382/stdout.reference b/tests/tests-base/test-00382/stdout.reference new file mode 100644 index 0000000..6245c16 --- /dev/null +++ b/tests/tests-base/test-00382/stdout.reference @@ -0,0 +1,28 @@ +Attempting to decode: 9c +iclass PUSHFD category PUSH ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name PUSHFD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPUSH SUPPRESSED W D 32 4 1 32 INT PSEUDO +1 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst + read: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 STACKPUSH0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00383/cmd b/tests/tests-base/test-00383/cmd new file mode 100644 index 0000000..a5b09ff --- /dev/null +++ b/tests/tests-base/test-00383/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 9C diff --git a/tests/tests-base/test-00383/codes b/tests/tests-base/test-00383/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00383/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00383/retcode.reference b/tests/tests-base/test-00383/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00383/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00383/stderr.reference b/tests/tests-base/test-00383/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00383/stdout.reference b/tests/tests-base/test-00383/stdout.reference new file mode 100644 index 0000000..d638b05 --- /dev/null +++ b/tests/tests-base/test-00383/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 9c +iclass PUSHFQ category PUSH ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 1 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name PUSHFQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPUSH SUPPRESSED W Q 64 8 1 64 INT PSEUDO +1 MEM0 (see below) SUPPRESSED W Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR +3 REG1 REG1=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 written BASE= RSP/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst + read: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + written: mask=0x0 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 STACKPUSH0 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00384/cmd b/tests/tests-base/test-00384/cmd new file mode 100644 index 0000000..b6d6d62 --- /dev/null +++ b/tests/tests-base/test-00384/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 669D diff --git a/tests/tests-base/test-00384/codes b/tests/tests-base/test-00384/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00384/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00384/retcode.reference b/tests/tests-base/test-00384/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00384/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00384/stderr.reference b/tests/tests-base/test-00384/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00384/stdout.reference b/tests/tests-base/test-00384/stdout.reference new file mode 100644 index 0000000..b5764a0 --- /dev/null +++ b/tests/tests-base/test-00384/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 9d +iclass POPF category POP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name POPF +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R W 16 2 1 16 INT PSEUDO +1 MEM0 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm vip mask=0x123000 + written: of sf zf af pf cf df vif iopl if ac rf nt tf id mask=0x2d7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX STACKPOP0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00385/cmd b/tests/tests-base/test-00385/cmd new file mode 100644 index 0000000..9376b7c --- /dev/null +++ b/tests/tests-base/test-00385/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 9D diff --git a/tests/tests-base/test-00385/codes b/tests/tests-base/test-00385/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00385/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00385/retcode.reference b/tests/tests-base/test-00385/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00385/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00385/stderr.reference b/tests/tests-base/test-00385/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00385/stdout.reference b/tests/tests-base/test-00385/stdout.reference new file mode 100644 index 0000000..f4a1012 --- /dev/null +++ b/tests/tests-base/test-00385/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: 9d +iclass POPFD category POP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name POPFD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R D 32 4 1 32 INT PSEUDO +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm vip mask=0x123000 + written: of sf zf af pf cf df vif iopl if ac rf nt tf id mask=0x2d7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX STACKPOP0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00386/cmd b/tests/tests-base/test-00386/cmd new file mode 100644 index 0000000..335433b --- /dev/null +++ b/tests/tests-base/test-00386/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 9D diff --git a/tests/tests-base/test-00386/codes b/tests/tests-base/test-00386/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00386/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00386/retcode.reference b/tests/tests-base/test-00386/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00386/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00386/stderr.reference b/tests/tests-base/test-00386/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00386/stdout.reference b/tests/tests-base/test-00386/stdout.reference new file mode 100644 index 0000000..02faa42 --- /dev/null +++ b/tests/tests-base/test-00386/stdout.reference @@ -0,0 +1,29 @@ +Attempting to decode: 9d +iclass POPFQ category POP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 1 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name POPFQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R Q 64 8 1 64 INT PSEUDO +1 MEM0 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR +3 REG1 REG1=RFLAGS SUPPRESSED RW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSP/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm vip mask=0x123000 + written: of sf zf af pf cf df vif iopl if ac rf nt tf id mask=0x2d7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX STACKPOP0 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00387/cmd b/tests/tests-base/test-00387/cmd new file mode 100644 index 0000000..abd9982 --- /dev/null +++ b/tests/tests-base/test-00387/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 A4 diff --git a/tests/tests-base/test-00387/codes b/tests/tests-base/test-00387/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00387/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00387/retcode.reference b/tests/tests-base/test-00387/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00387/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00387/stderr.reference b/tests/tests-base/test-00387/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00387/stdout.reference b/tests/tests-base/test-00387/stdout.reference new file mode 100644 index 0000000..82c9b80 --- /dev/null +++ b/tests/tests-base/test-00387/stdout.reference @@ -0,0 +1,29 @@ +Attempting to decode: a4 +iclass MOVSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOVSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00388/cmd b/tests/tests-base/test-00388/cmd new file mode 100644 index 0000000..843e29b --- /dev/null +++ b/tests/tests-base/test-00388/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66A5 diff --git a/tests/tests-base/test-00388/codes b/tests/tests-base/test-00388/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00388/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00388/retcode.reference b/tests/tests-base/test-00388/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00388/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00388/stderr.reference b/tests/tests-base/test-00388/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00388/stdout.reference b/tests/tests-base/test-00388/stdout.reference new file mode 100644 index 0000000..da5521c --- /dev/null +++ b/tests/tests-base/test-00388/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: 66 a5 +iclass MOVSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOVSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00389/cmd b/tests/tests-base/test-00389/cmd new file mode 100644 index 0000000..461cc13 --- /dev/null +++ b/tests/tests-base/test-00389/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 A5 diff --git a/tests/tests-base/test-00389/codes b/tests/tests-base/test-00389/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00389/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00389/retcode.reference b/tests/tests-base/test-00389/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00389/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00389/stderr.reference b/tests/tests-base/test-00389/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00389/stdout.reference b/tests/tests-base/test-00389/stdout.reference new file mode 100644 index 0000000..47400eb --- /dev/null +++ b/tests/tests-base/test-00389/stdout.reference @@ -0,0 +1,29 @@ +Attempting to decode: a5 +iclass MOVSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name MOVSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00390/cmd b/tests/tests-base/test-00390/cmd new file mode 100644 index 0000000..50b844c --- /dev/null +++ b/tests/tests-base/test-00390/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48A5 diff --git a/tests/tests-base/test-00390/codes b/tests/tests-base/test-00390/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00390/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00390/retcode.reference b/tests/tests-base/test-00390/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00390/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00390/stderr.reference b/tests/tests-base/test-00390/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00390/stdout.reference b/tests/tests-base/test-00390/stdout.reference new file mode 100644 index 0000000..a3ae0c9 --- /dev/null +++ b/tests/tests-base/test-00390/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: 48 a5 +iclass MOVSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name MOVSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RDI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +2 MEM1 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +3 BASE1 BASE1=RSI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +4 REG0 REG0=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 written BASE= RDI/GPR ASZ0=64 + 1 read BASE= RSI/GPR ASZ1=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00391/cmd b/tests/tests-base/test-00391/cmd new file mode 100644 index 0000000..0908b03 --- /dev/null +++ b/tests/tests-base/test-00391/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 A6 diff --git a/tests/tests-base/test-00391/codes b/tests/tests-base/test-00391/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00391/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00391/retcode.reference b/tests/tests-base/test-00391/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00391/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00391/stderr.reference b/tests/tests-base/test-00391/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00391/stdout.reference b/tests/tests-base/test-00391/stdout.reference new file mode 100644 index 0000000..a239e6e --- /dev/null +++ b/tests/tests-base/test-00391/stdout.reference @@ -0,0 +1,29 @@ +Attempting to decode: a6 +iclass CMPSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00392/cmd b/tests/tests-base/test-00392/cmd new file mode 100644 index 0000000..291b289 --- /dev/null +++ b/tests/tests-base/test-00392/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66A7 diff --git a/tests/tests-base/test-00392/codes b/tests/tests-base/test-00392/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00392/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00392/retcode.reference b/tests/tests-base/test-00392/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00392/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00392/stderr.reference b/tests/tests-base/test-00392/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00392/stdout.reference b/tests/tests-base/test-00392/stdout.reference new file mode 100644 index 0000000..4b44e58 --- /dev/null +++ b/tests/tests-base/test-00392/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: 66 a7 +iclass CMPSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00393/cmd b/tests/tests-base/test-00393/cmd new file mode 100644 index 0000000..fed6a51 --- /dev/null +++ b/tests/tests-base/test-00393/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 A7 diff --git a/tests/tests-base/test-00393/codes b/tests/tests-base/test-00393/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00393/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00393/retcode.reference b/tests/tests-base/test-00393/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00393/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00393/stderr.reference b/tests/tests-base/test-00393/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00393/stdout.reference b/tests/tests-base/test-00393/stdout.reference new file mode 100644 index 0000000..0d91fbe --- /dev/null +++ b/tests/tests-base/test-00393/stdout.reference @@ -0,0 +1,29 @@ +Attempting to decode: a7 +iclass CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00394/cmd b/tests/tests-base/test-00394/cmd new file mode 100644 index 0000000..68e5207 --- /dev/null +++ b/tests/tests-base/test-00394/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48A7 diff --git a/tests/tests-base/test-00394/codes b/tests/tests-base/test-00394/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00394/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00394/retcode.reference b/tests/tests-base/test-00394/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00394/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00394/stderr.reference b/tests/tests-base/test-00394/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00394/stdout.reference b/tests/tests-base/test-00394/stdout.reference new file mode 100644 index 0000000..feb2edf --- /dev/null +++ b/tests/tests-base/test-00394/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: 48 a7 +iclass CMPSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name CMPSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RSI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +2 MEM1 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +3 BASE1 BASE1=RDI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +4 REG0 REG0=RFLAGS SUPPRESSED RW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSI/GPR ASZ0=64 + 1 read BASE= RDI/GPR ASZ1=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00395/cmd b/tests/tests-base/test-00395/cmd new file mode 100644 index 0000000..e4b9c4d --- /dev/null +++ b/tests/tests-base/test-00395/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AA diff --git a/tests/tests-base/test-00395/codes b/tests/tests-base/test-00395/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00395/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00395/retcode.reference b/tests/tests-base/test-00395/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00395/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00395/stderr.reference b/tests/tests-base/test-00395/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00395/stdout.reference b/tests/tests-base/test-00395/stdout.reference new file mode 100644 index 0000000..012696a --- /dev/null +++ b/tests/tests-base/test-00395/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: aa +iclass STOSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name STOSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=AL SUPPRESSED R B 8 1 1 8 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 +ISA SET: [I86] diff --git a/tests/tests-base/test-00396/cmd b/tests/tests-base/test-00396/cmd new file mode 100644 index 0000000..ed1e697 --- /dev/null +++ b/tests/tests-base/test-00396/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66AB diff --git a/tests/tests-base/test-00396/codes b/tests/tests-base/test-00396/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00396/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00396/retcode.reference b/tests/tests-base/test-00396/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00396/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00396/stderr.reference b/tests/tests-base/test-00396/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00396/stdout.reference b/tests/tests-base/test-00396/stdout.reference new file mode 100644 index 0000000..7fc6802 --- /dev/null +++ b/tests/tests-base/test-00396/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 ab +iclass STOSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name STOSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=AX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00397/cmd b/tests/tests-base/test-00397/cmd new file mode 100644 index 0000000..0b1bf36 --- /dev/null +++ b/tests/tests-base/test-00397/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AB diff --git a/tests/tests-base/test-00397/codes b/tests/tests-base/test-00397/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00397/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00397/retcode.reference b/tests/tests-base/test-00397/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00397/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00397/stderr.reference b/tests/tests-base/test-00397/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00397/stdout.reference b/tests/tests-base/test-00397/stdout.reference new file mode 100644 index 0000000..b82d871 --- /dev/null +++ b/tests/tests-base/test-00397/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: ab +iclass STOSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name STOSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00398/cmd b/tests/tests-base/test-00398/cmd new file mode 100644 index 0000000..cd1d1cb --- /dev/null +++ b/tests/tests-base/test-00398/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48AB diff --git a/tests/tests-base/test-00398/codes b/tests/tests-base/test-00398/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00398/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00398/retcode.reference b/tests/tests-base/test-00398/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00398/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00398/stderr.reference b/tests/tests-base/test-00398/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00398/stdout.reference b/tests/tests-base/test-00398/stdout.reference new file mode 100644 index 0000000..48e6161 --- /dev/null +++ b/tests/tests-base/test-00398/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 48 ab +iclass STOSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name STOSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED W Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RDI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +2 REG0 REG0=RAX SUPPRESSED R Q 64 8 1 64 INT GPR +3 REG1 REG1=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 written BASE= RDI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00399/cmd b/tests/tests-base/test-00399/cmd new file mode 100644 index 0000000..2c5e110 --- /dev/null +++ b/tests/tests-base/test-00399/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AC diff --git a/tests/tests-base/test-00399/codes b/tests/tests-base/test-00399/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00399/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00399/retcode.reference b/tests/tests-base/test-00399/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00399/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00399/stderr.reference b/tests/tests-base/test-00399/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00399/stdout.reference b/tests/tests-base/test-00399/stdout.reference new file mode 100644 index 0000000..ca7e9b1 --- /dev/null +++ b/tests/tests-base/test-00399/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: ac +iclass LODSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LODSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL SUPPRESSED W B 8 1 1 8 INT GPR +1 MEM0 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 +ISA SET: [I86] diff --git a/tests/tests-base/test-00400/cmd b/tests/tests-base/test-00400/cmd new file mode 100644 index 0000000..0d5840b --- /dev/null +++ b/tests/tests-base/test-00400/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66AD diff --git a/tests/tests-base/test-00400/codes b/tests/tests-base/test-00400/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00400/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00400/retcode.reference b/tests/tests-base/test-00400/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00400/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00400/stderr.reference b/tests/tests-base/test-00400/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00400/stdout.reference b/tests/tests-base/test-00400/stdout.reference new file mode 100644 index 0000000..2ffb4f1 --- /dev/null +++ b/tests/tests-base/test-00400/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 ad +iclass LODSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LODSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AX SUPPRESSED W W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00401/cmd b/tests/tests-base/test-00401/cmd new file mode 100644 index 0000000..b7fddcc --- /dev/null +++ b/tests/tests-base/test-00401/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AD diff --git a/tests/tests-base/test-00401/codes b/tests/tests-base/test-00401/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00401/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00401/retcode.reference b/tests/tests-base/test-00401/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00401/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00401/stderr.reference b/tests/tests-base/test-00401/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00401/stdout.reference b/tests/tests-base/test-00401/stdout.reference new file mode 100644 index 0000000..48bbf31 --- /dev/null +++ b/tests/tests-base/test-00401/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: ad +iclass LODSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name LODSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED W D 32 4 1 32 INT GPR +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00402/cmd b/tests/tests-base/test-00402/cmd new file mode 100644 index 0000000..e79594d --- /dev/null +++ b/tests/tests-base/test-00402/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48AD diff --git a/tests/tests-base/test-00402/codes b/tests/tests-base/test-00402/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00402/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00402/retcode.reference b/tests/tests-base/test-00402/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00402/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00402/stderr.reference b/tests/tests-base/test-00402/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00402/stdout.reference b/tests/tests-base/test-00402/stdout.reference new file mode 100644 index 0000000..7f8ac87 --- /dev/null +++ b/tests/tests-base/test-00402/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 48 ad +iclass LODSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name LODSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX SUPPRESSED W Q 64 8 1 64 INT GPR +1 MEM0 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RSI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +3 REG1 REG1=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00403/cmd b/tests/tests-base/test-00403/cmd new file mode 100644 index 0000000..0b583e7 --- /dev/null +++ b/tests/tests-base/test-00403/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AE diff --git a/tests/tests-base/test-00403/codes b/tests/tests-base/test-00403/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00403/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00403/retcode.reference b/tests/tests-base/test-00403/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00403/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00403/stderr.reference b/tests/tests-base/test-00403/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00403/stdout.reference b/tests/tests-base/test-00403/stdout.reference new file mode 100644 index 0000000..72e07e1 --- /dev/null +++ b/tests/tests-base/test-00403/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: ae +iclass SCASB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name SCASB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL SUPPRESSED R B 8 1 1 8 INT GPR +1 MEM0 (see below) SUPPRESSED R B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 +ISA SET: [I86] diff --git a/tests/tests-base/test-00404/cmd b/tests/tests-base/test-00404/cmd new file mode 100644 index 0000000..b6b044d --- /dev/null +++ b/tests/tests-base/test-00404/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66AF diff --git a/tests/tests-base/test-00404/codes b/tests/tests-base/test-00404/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00404/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00404/retcode.reference b/tests/tests-base/test-00404/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00404/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00404/stderr.reference b/tests/tests-base/test-00404/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00404/stdout.reference b/tests/tests-base/test-00404/stdout.reference new file mode 100644 index 0000000..055afdd --- /dev/null +++ b/tests/tests-base/test-00404/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 66 af +iclass SCASW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name SCASW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED R W 16 2 1 16 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00405/cmd b/tests/tests-base/test-00405/cmd new file mode 100644 index 0000000..03b62ec --- /dev/null +++ b/tests/tests-base/test-00405/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 AF diff --git a/tests/tests-base/test-00405/codes b/tests/tests-base/test-00405/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00405/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00405/retcode.reference b/tests/tests-base/test-00405/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00405/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00405/stderr.reference b/tests/tests-base/test-00405/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00405/stdout.reference b/tests/tests-base/test-00405/stdout.reference new file mode 100644 index 0000000..3a4d11b --- /dev/null +++ b/tests/tests-base/test-00405/stdout.reference @@ -0,0 +1,27 @@ +Attempting to decode: af +iclass SCASD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name SCASD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +1 MEM0 (see below) SUPPRESSED R D 32 4 1 32 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00406/cmd b/tests/tests-base/test-00406/cmd new file mode 100644 index 0000000..51a84ee --- /dev/null +++ b/tests/tests-base/test-00406/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48AF diff --git a/tests/tests-base/test-00406/codes b/tests/tests-base/test-00406/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00406/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00406/retcode.reference b/tests/tests-base/test-00406/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00406/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00406/stderr.reference b/tests/tests-base/test-00406/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00406/stdout.reference b/tests/tests-base/test-00406/stdout.reference new file mode 100644 index 0000000..114b06a --- /dev/null +++ b/tests/tests-base/test-00406/stdout.reference @@ -0,0 +1,30 @@ +Attempting to decode: 48 af +iclass SCASQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name SCASQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX SUPPRESSED R Q 64 8 1 64 INT GPR +1 MEM0 (see below) SUPPRESSED R Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RDI SUPPRESSED RW ASZ 64 8 1 64 INT GPR +3 REG1 REG1=RFLAGS SUPPRESSED RW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RDI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod + read: df mask=0x400 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00407/cmd b/tests/tests-base/test-00407/cmd new file mode 100644 index 0000000..359a2df --- /dev/null +++ b/tests/tests-base/test-00407/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 66CF diff --git a/tests/tests-base/test-00407/codes b/tests/tests-base/test-00407/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00407/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00407/retcode.reference b/tests/tests-base/test-00407/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00407/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00407/stderr.reference b/tests/tests-base/test-00407/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00407/stdout.reference b/tests/tests-base/test-00407/stdout.reference new file mode 100644 index 0000000..9b09915 --- /dev/null +++ b/tests/tests-base/test-00407/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: 66 cf +iclass IRET category RET ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name IRET +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R SPW3 48 6 1 48 INT PSEUDO +1 REG1 REG1=EIP SUPPRESSED W V 16 2 1 16 INT IP +2 MEM0 (see below) SUPPRESSED R SPW3 48 6 1 48 INT INVALID +3 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 6 +FLAGS: + reads-rflags id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm nt mask=0x27000 + written: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX SCALABLE STACKPOP0 +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00408/cmd b/tests/tests-base/test-00408/cmd new file mode 100644 index 0000000..f7e92c3 --- /dev/null +++ b/tests/tests-base/test-00408/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 CF diff --git a/tests/tests-base/test-00408/codes b/tests/tests-base/test-00408/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00408/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00408/retcode.reference b/tests/tests-base/test-00408/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00408/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00408/stderr.reference b/tests/tests-base/test-00408/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00408/stdout.reference b/tests/tests-base/test-00408/stdout.reference new file mode 100644 index 0000000..018a4f0 --- /dev/null +++ b/tests/tests-base/test-00408/stdout.reference @@ -0,0 +1,28 @@ +Attempting to decode: cf +iclass IRETD category RET ISA-extension BASE ISA-set I386 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name IRETD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R SPW3 96 12 1 96 INT PSEUDO +1 REG1 REG1=EIP SUPPRESSED W V 32 4 1 32 INT IP +2 MEM0 (see below) SUPPRESSED R SPW3 96 12 1 96 INT INVALID +3 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= SS BASE= ESP/GPR ASZ0=32 + MemopBytes = 12 +FLAGS: + reads-rflags id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm nt mask=0x27000 + written: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX SCALABLE STACKPOP0 +ISA SET: [I386] diff --git a/tests/tests-base/test-00409/cmd b/tests/tests-base/test-00409/cmd new file mode 100644 index 0000000..371d31d --- /dev/null +++ b/tests/tests-base/test-00409/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 48CF diff --git a/tests/tests-base/test-00409/codes b/tests/tests-base/test-00409/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00409/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00409/retcode.reference b/tests/tests-base/test-00409/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00409/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00409/stderr.reference b/tests/tests-base/test-00409/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00409/stdout.reference b/tests/tests-base/test-00409/stdout.reference new file mode 100644 index 0000000..bd3223a --- /dev/null +++ b/tests/tests-base/test-00409/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: 48 cf +iclass IRETQ category RET ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name IRETQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=STACKPOP SUPPRESSED R SPW3 192 24 1 192 INT PSEUDO +1 REG1 REG1=RIP SUPPRESSED W V 64 8 1 64 INT IP +2 MEM0 (see below) SUPPRESSED R SPW3 192 24 1 192 INT INVALID +3 BASE0 BASE0=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR +4 REG2 REG2=RFLAGS SUPPRESSED RW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSP/GPR ASZ0=64 + MemopBytes = 24 +FLAGS: + reads-rflags id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop + read: iopl vm nt mask=0x27000 + written: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX SCALABLE STACKPOP0 +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00410/cmd b/tests/tests-base/test-00410/cmd new file mode 100644 index 0000000..ecdd915 --- /dev/null +++ b/tests/tests-base/test-00410/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 FC diff --git a/tests/tests-base/test-00410/codes b/tests/tests-base/test-00410/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00410/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00410/retcode.reference b/tests/tests-base/test-00410/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00410/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00410/stderr.reference b/tests/tests-base/test-00410/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00410/stdout.reference b/tests/tests-base/test-00410/stdout.reference new file mode 100644 index 0000000..d315055 --- /dev/null +++ b/tests/tests-base/test-00410/stdout.reference @@ -0,0 +1,23 @@ +Attempting to decode: fc +iclass CLD category FLAGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name CLD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags df-0 + read: mask=0x0 + written: df mask=0x400 + undefined: mask=0x0 +ATTRIBUTES: NOTSX_COND +ISA SET: [I86] diff --git a/tests/tests-base/test-00411/cmd b/tests/tests-base/test-00411/cmd new file mode 100644 index 0000000..050d316 --- /dev/null +++ b/tests/tests-base/test-00411/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 FD diff --git a/tests/tests-base/test-00411/codes b/tests/tests-base/test-00411/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00411/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00411/retcode.reference b/tests/tests-base/test-00411/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00411/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00411/stderr.reference b/tests/tests-base/test-00411/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00411/stdout.reference b/tests/tests-base/test-00411/stdout.reference new file mode 100644 index 0000000..364b1e9 --- /dev/null +++ b/tests/tests-base/test-00411/stdout.reference @@ -0,0 +1,23 @@ +Attempting to decode: fd +iclass STD category FLAGOP ISA-extension BASE ISA-set I86 +instruction-length 1 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name STD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags df-1 + read: mask=0x0 + written: df mask=0x400 + undefined: mask=0x0 +ATTRIBUTES: NOTSX_COND +ISA SET: [I86] diff --git a/tests/tests-base/test-00412/cmd b/tests/tests-base/test-00412/cmd new file mode 100644 index 0000000..e014a18 --- /dev/null +++ b/tests/tests-base/test-00412/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 0F05 diff --git a/tests/tests-base/test-00412/codes b/tests/tests-base/test-00412/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00412/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00412/retcode.reference b/tests/tests-base/test-00412/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00412/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00412/stderr.reference b/tests/tests-base/test-00412/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00412/stdout.reference b/tests/tests-base/test-00412/stdout.reference new file mode 100644 index 0000000..4f2b861 --- /dev/null +++ b/tests/tests-base/test-00412/stdout.reference @@ -0,0 +1,26 @@ +Attempting to decode: 0f 05 +iclass SYSCALL category SYSCALL ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 2 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name SYSCALL +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RIP SUPPRESSED W V 64 8 1 64 INT IP +1 REG1 REG1=RFLAGS SUPPRESSED W Y 64 8 1 64 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod + read: mask=0x0 + written: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + undefined: mask=0x0 +ATTRIBUTES: NOTSX +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00413/cmd b/tests/tests-base/test-00413/cmd new file mode 100644 index 0000000..960e552 --- /dev/null +++ b/tests/tests-base/test-00413/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 480F07 diff --git a/tests/tests-base/test-00413/codes b/tests/tests-base/test-00413/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00413/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00413/retcode.reference b/tests/tests-base/test-00413/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00413/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00413/stderr.reference b/tests/tests-base/test-00413/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00413/stdout.reference b/tests/tests-base/test-00413/stdout.reference new file mode 100644 index 0000000..cf89fae --- /dev/null +++ b/tests/tests-base/test-00413/stdout.reference @@ -0,0 +1,28 @@ +Attempting to decode: 48 0f 07 +iclass SYSRET category SYSRET ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name SYSRET +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RIP SUPPRESSED W Q 64 8 1 64 INT IP +1 REG1 REG1=RFLAGS SUPPRESSED W Y 64 8 1 64 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod + read: mask=0x0 + written: of sf zf af pf cf df vif iopl if ac rf nt tf id vip mask=0x3d7fd5 + undefined: mask=0x0 +ATTRIBUTES: NOTSX PROTECTED_MODE RING0 +RING0 only +Number of legacy prefixes: 1 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00414/cmd b/tests/tests-base/test-00414/cmd new file mode 100644 index 0000000..d7120a7 --- /dev/null +++ b/tests/tests-base/test-00414/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 0FAA diff --git a/tests/tests-base/test-00414/codes b/tests/tests-base/test-00414/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00414/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00414/retcode.reference b/tests/tests-base/test-00414/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00414/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00414/stderr.reference b/tests/tests-base/test-00414/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00414/stdout.reference b/tests/tests-base/test-00414/stdout.reference new file mode 100644 index 0000000..d8fcaff --- /dev/null +++ b/tests/tests-base/test-00414/stdout.reference @@ -0,0 +1,24 @@ +Attempting to decode: 0f aa +iclass RSM category SYSRET ISA-extension BASE ISA-set I486 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name RSM +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EIP SUPPRESSED W V 32 4 1 32 INT IP +1 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS +Memory Operands + MemopBytes = 0 +FLAGS: + must-write-rflags id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod + read: mask=0x0 + written: of sf zf af pf cf df vif iopl if ac vm rf nt tf id vip mask=0x3f7fd5 + undefined: mask=0x0 +ATTRIBUTES: NOTSX +ISA SET: [I486] diff --git a/tests/tests-base/test-00415/cmd b/tests/tests-base/test-00415/cmd new file mode 100644 index 0000000..0cfb523 --- /dev/null +++ b/tests/tests-base/test-00415/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6C diff --git a/tests/tests-base/test-00415/codes b/tests/tests-base/test-00415/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00415/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00415/retcode.reference b/tests/tests-base/test-00415/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00415/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00415/stderr.reference b/tests/tests-base/test-00415/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00415/stdout.reference b/tests/tests-base/test-00415/stdout.reference new file mode 100644 index 0000000..6f1a4d6 --- /dev/null +++ b/tests/tests-base/test-00415/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6c +iclass REP_INSB category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_INSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: INSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I186] diff --git a/tests/tests-base/test-00416/cmd b/tests/tests-base/test-00416/cmd new file mode 100644 index 0000000..8dc8ba3 --- /dev/null +++ b/tests/tests-base/test-00416/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 666D diff --git a/tests/tests-base/test-00416/codes b/tests/tests-base/test-00416/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00416/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00416/retcode.reference b/tests/tests-base/test-00416/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00416/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00416/stderr.reference b/tests/tests-base/test-00416/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00416/stdout.reference b/tests/tests-base/test-00416/stdout.reference new file mode 100644 index 0000000..ea1cb71 --- /dev/null +++ b/tests/tests-base/test-00416/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 66 6d +iclass REP_INSW category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_INSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: INSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I186] diff --git a/tests/tests-base/test-00417/cmd b/tests/tests-base/test-00417/cmd new file mode 100644 index 0000000..36a2d3b --- /dev/null +++ b/tests/tests-base/test-00417/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6D diff --git a/tests/tests-base/test-00417/codes b/tests/tests-base/test-00417/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00417/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00417/retcode.reference b/tests/tests-base/test-00417/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00417/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00417/stderr.reference b/tests/tests-base/test-00417/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00417/stdout.reference b/tests/tests-base/test-00417/stdout.reference new file mode 100644 index 0000000..7d98ae9 --- /dev/null +++ b/tests/tests-base/test-00417/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6d +iclass REP_INSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_INSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: INSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00418/cmd b/tests/tests-base/test-00418/cmd new file mode 100644 index 0000000..36a2d3b --- /dev/null +++ b/tests/tests-base/test-00418/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6D diff --git a/tests/tests-base/test-00418/codes b/tests/tests-base/test-00418/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00418/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00418/retcode.reference b/tests/tests-base/test-00418/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00418/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00418/stderr.reference b/tests/tests-base/test-00418/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00418/stdout.reference b/tests/tests-base/test-00418/stdout.reference new file mode 100644 index 0000000..7d98ae9 --- /dev/null +++ b/tests/tests-base/test-00418/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6d +iclass REP_INSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_INSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: INSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00419/cmd b/tests/tests-base/test-00419/cmd new file mode 100644 index 0000000..f84ad70 --- /dev/null +++ b/tests/tests-base/test-00419/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6E diff --git a/tests/tests-base/test-00419/codes b/tests/tests-base/test-00419/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00419/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00419/retcode.reference b/tests/tests-base/test-00419/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00419/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00419/stderr.reference b/tests/tests-base/test-00419/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00419/stdout.reference b/tests/tests-base/test-00419/stdout.reference new file mode 100644 index 0000000..e313e4d --- /dev/null +++ b/tests/tests-base/test-00419/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6e +iclass REP_OUTSB category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_OUTSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: OUTSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I186] diff --git a/tests/tests-base/test-00420/cmd b/tests/tests-base/test-00420/cmd new file mode 100644 index 0000000..b612a1d --- /dev/null +++ b/tests/tests-base/test-00420/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 666F diff --git a/tests/tests-base/test-00420/codes b/tests/tests-base/test-00420/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00420/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00420/retcode.reference b/tests/tests-base/test-00420/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00420/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00420/stderr.reference b/tests/tests-base/test-00420/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00420/stdout.reference b/tests/tests-base/test-00420/stdout.reference new file mode 100644 index 0000000..9b10e60 --- /dev/null +++ b/tests/tests-base/test-00420/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 66 6f +iclass REP_OUTSW category IOSTRINGOP ISA-extension BASE ISA-set I186 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_OUTSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: OUTSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I186] diff --git a/tests/tests-base/test-00421/cmd b/tests/tests-base/test-00421/cmd new file mode 100644 index 0000000..b5b62e8 --- /dev/null +++ b/tests/tests-base/test-00421/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6F diff --git a/tests/tests-base/test-00421/codes b/tests/tests-base/test-00421/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00421/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00421/retcode.reference b/tests/tests-base/test-00421/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00421/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00421/stderr.reference b/tests/tests-base/test-00421/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00421/stdout.reference b/tests/tests-base/test-00421/stdout.reference new file mode 100644 index 0000000..3c3cc9c --- /dev/null +++ b/tests/tests-base/test-00421/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6f +iclass REP_OUTSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_OUTSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: OUTSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00422/cmd b/tests/tests-base/test-00422/cmd new file mode 100644 index 0000000..b5b62e8 --- /dev/null +++ b/tests/tests-base/test-00422/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 6F diff --git a/tests/tests-base/test-00422/codes b/tests/tests-base/test-00422/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00422/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00422/retcode.reference b/tests/tests-base/test-00422/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00422/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00422/stderr.reference b/tests/tests-base/test-00422/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00422/stdout.reference b/tests/tests-base/test-00422/stdout.reference new file mode 100644 index 0000000..3c3cc9c --- /dev/null +++ b/tests/tests-base/test-00422/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 6f +iclass REP_OUTSD category IOSTRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_OUTSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=DX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags iopl-tst df-tst + read: df iopl mask=0x3400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 NOTSX REP +REAL REP corresponding no-rep iclass: OUTSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00423/cmd b/tests/tests-base/test-00423/cmd new file mode 100644 index 0000000..810f049 --- /dev/null +++ b/tests/tests-base/test-00423/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 A4 diff --git a/tests/tests-base/test-00423/codes b/tests/tests-base/test-00423/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00423/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00423/retcode.reference b/tests/tests-base/test-00423/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00423/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00423/stderr.reference b/tests/tests-base/test-00423/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00423/stdout.reference b/tests/tests-base/test-00423/stdout.reference new file mode 100644 index 0000000..53caefa --- /dev/null +++ b/tests/tests-base/test-00423/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 a4 +iclass REP_MOVSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_MOVSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: MOVSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00424/cmd b/tests/tests-base/test-00424/cmd new file mode 100644 index 0000000..7e1c819 --- /dev/null +++ b/tests/tests-base/test-00424/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 66A5 diff --git a/tests/tests-base/test-00424/codes b/tests/tests-base/test-00424/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00424/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00424/retcode.reference b/tests/tests-base/test-00424/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00424/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00424/stderr.reference b/tests/tests-base/test-00424/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00424/stdout.reference b/tests/tests-base/test-00424/stdout.reference new file mode 100644 index 0000000..ad1b13e --- /dev/null +++ b/tests/tests-base/test-00424/stdout.reference @@ -0,0 +1,35 @@ +Attempting to decode: f3 66 a5 +iclass REP_MOVSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_MOVSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: MOVSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00425/cmd b/tests/tests-base/test-00425/cmd new file mode 100644 index 0000000..3ec97b7 --- /dev/null +++ b/tests/tests-base/test-00425/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 A5 diff --git a/tests/tests-base/test-00425/codes b/tests/tests-base/test-00425/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00425/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00425/retcode.reference b/tests/tests-base/test-00425/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00425/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00425/stderr.reference b/tests/tests-base/test-00425/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00425/stdout.reference b/tests/tests-base/test-00425/stdout.reference new file mode 100644 index 0000000..b217192 --- /dev/null +++ b/tests/tests-base/test-00425/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 a5 +iclass REP_MOVSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_MOVSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + 1 read SEG= DS BASE= ESI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: MOVSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00426/cmd b/tests/tests-base/test-00426/cmd new file mode 100644 index 0000000..7fd4da7 --- /dev/null +++ b/tests/tests-base/test-00426/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 48A5 diff --git a/tests/tests-base/test-00426/codes b/tests/tests-base/test-00426/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00426/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00426/retcode.reference b/tests/tests-base/test-00426/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00426/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00426/stderr.reference b/tests/tests-base/test-00426/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00426/stdout.reference b/tests/tests-base/test-00426/stdout.reference new file mode 100644 index 0000000..d960973 --- /dev/null +++ b/tests/tests-base/test-00426/stdout.reference @@ -0,0 +1,35 @@ +Attempting to decode: f3 48 a5 +iclass REP_MOVSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REP_MOVSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +2 MEM1 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +3 BASE1 BASE1=RSI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG0 REG0=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +5 REG1 REG1=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 written BASE= RDI/GPR ASZ0=64 + 1 read BASE= RSI/GPR ASZ1=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: MOVSQ +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00427/cmd b/tests/tests-base/test-00427/cmd new file mode 100644 index 0000000..8a6a0f6 --- /dev/null +++ b/tests/tests-base/test-00427/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 A6 diff --git a/tests/tests-base/test-00427/codes b/tests/tests-base/test-00427/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00427/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00427/retcode.reference b/tests/tests-base/test-00427/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00427/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00427/stderr.reference b/tests/tests-base/test-00427/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00427/stdout.reference b/tests/tests-base/test-00427/stdout.reference new file mode 100644 index 0000000..4096878 --- /dev/null +++ b/tests/tests-base/test-00427/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f2 a6 +iclass REPNE_CMPSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSB +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00428/cmd b/tests/tests-base/test-00428/cmd new file mode 100644 index 0000000..211cc38 --- /dev/null +++ b/tests/tests-base/test-00428/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 66A7 diff --git a/tests/tests-base/test-00428/codes b/tests/tests-base/test-00428/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00428/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00428/retcode.reference b/tests/tests-base/test-00428/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00428/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00428/stderr.reference b/tests/tests-base/test-00428/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00428/stdout.reference b/tests/tests-base/test-00428/stdout.reference new file mode 100644 index 0000000..e03b79b --- /dev/null +++ b/tests/tests-base/test-00428/stdout.reference @@ -0,0 +1,36 @@ +Attempting to decode: f2 66 a7 +iclass REPNE_CMPSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSW +F2 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00429/cmd b/tests/tests-base/test-00429/cmd new file mode 100644 index 0000000..6f1aacf --- /dev/null +++ b/tests/tests-base/test-00429/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 A7 diff --git a/tests/tests-base/test-00429/codes b/tests/tests-base/test-00429/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00429/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00429/retcode.reference b/tests/tests-base/test-00429/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00429/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00429/stderr.reference b/tests/tests-base/test-00429/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00429/stdout.reference b/tests/tests-base/test-00429/stdout.reference new file mode 100644 index 0000000..4baa86b --- /dev/null +++ b/tests/tests-base/test-00429/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f2 a7 +iclass REPNE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00430/cmd b/tests/tests-base/test-00430/cmd new file mode 100644 index 0000000..bc9db8d --- /dev/null +++ b/tests/tests-base/test-00430/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f2 48A7 diff --git a/tests/tests-base/test-00430/codes b/tests/tests-base/test-00430/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00430/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00430/retcode.reference b/tests/tests-base/test-00430/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00430/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00430/stderr.reference b/tests/tests-base/test-00430/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00430/stdout.reference b/tests/tests-base/test-00430/stdout.reference new file mode 100644 index 0000000..76d369d --- /dev/null +++ b/tests/tests-base/test-00430/stdout.reference @@ -0,0 +1,36 @@ +Attempting to decode: f2 48 a7 +iclass REPNE_CMPSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REPNE_CMPSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RSI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +2 MEM1 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +3 BASE1 BASE1=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG0 REG0=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +5 REG1 REG1=RFLAGS SUPPRESSED RCW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSI/GPR ASZ0=64 + 1 read BASE= RDI/GPR ASZ1=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSQ +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00431/cmd b/tests/tests-base/test-00431/cmd new file mode 100644 index 0000000..52bb744 --- /dev/null +++ b/tests/tests-base/test-00431/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 A6 diff --git a/tests/tests-base/test-00431/codes b/tests/tests-base/test-00431/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00431/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00431/retcode.reference b/tests/tests-base/test-00431/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00431/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00431/stderr.reference b/tests/tests-base/test-00431/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00431/stdout.reference b/tests/tests-base/test-00431/stdout.reference new file mode 100644 index 0000000..5791cff --- /dev/null +++ b/tests/tests-base/test-00431/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f3 a6 +iclass REPE_CMPSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: BYTEOP FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00432/cmd b/tests/tests-base/test-00432/cmd new file mode 100644 index 0000000..fd23b7c --- /dev/null +++ b/tests/tests-base/test-00432/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 66A7 diff --git a/tests/tests-base/test-00432/codes b/tests/tests-base/test-00432/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00432/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00432/retcode.reference b/tests/tests-base/test-00432/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00432/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00432/stderr.reference b/tests/tests-base/test-00432/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00432/stdout.reference b/tests/tests-base/test-00432/stdout.reference new file mode 100644 index 0000000..9df9595 --- /dev/null +++ b/tests/tests-base/test-00432/stdout.reference @@ -0,0 +1,36 @@ +Attempting to decode: f3 66 a7 +iclass REPE_CMPSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00433/cmd b/tests/tests-base/test-00433/cmd new file mode 100644 index 0000000..ee28fc1 --- /dev/null +++ b/tests/tests-base/test-00433/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 A7 diff --git a/tests/tests-base/test-00433/codes b/tests/tests-base/test-00433/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00433/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00433/retcode.reference b/tests/tests-base/test-00433/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00433/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00433/stderr.reference b/tests/tests-base/test-00433/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00433/stdout.reference b/tests/tests-base/test-00433/stdout.reference new file mode 100644 index 0000000..883d1e2 --- /dev/null +++ b/tests/tests-base/test-00433/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f3 a7 +iclass REPE_CMPSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_CMPSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +1 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 MEM1 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +3 BASE1 BASE1=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG0 REG0=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +5 REG1 REG1=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + 1 read SEG= ES BASE= EDI/GPR ASZ1=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00434/cmd b/tests/tests-base/test-00434/cmd new file mode 100644 index 0000000..65db327 --- /dev/null +++ b/tests/tests-base/test-00434/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 48A7 diff --git a/tests/tests-base/test-00434/codes b/tests/tests-base/test-00434/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00434/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00434/retcode.reference b/tests/tests-base/test-00434/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00434/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00434/stderr.reference b/tests/tests-base/test-00434/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00434/stdout.reference b/tests/tests-base/test-00434/stdout.reference new file mode 100644 index 0000000..394553b --- /dev/null +++ b/tests/tests-base/test-00434/stdout.reference @@ -0,0 +1,36 @@ +Attempting to decode: f3 48 a7 +iclass REPE_CMPSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REPE_CMPSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RSI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +2 MEM1 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +3 BASE1 BASE1=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG0 REG0=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +5 REG1 REG1=RFLAGS SUPPRESSED RCW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSI/GPR ASZ0=64 + 1 read BASE= RDI/GPR ASZ1=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 FIXED_BASE1 REP +REAL REP corresponding no-rep iclass: CMPSQ +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00435/cmd b/tests/tests-base/test-00435/cmd new file mode 100644 index 0000000..f255c0e --- /dev/null +++ b/tests/tests-base/test-00435/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AA diff --git a/tests/tests-base/test-00435/codes b/tests/tests-base/test-00435/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00435/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00435/retcode.reference b/tests/tests-base/test-00435/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00435/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00435/stderr.reference b/tests/tests-base/test-00435/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00435/stdout.reference b/tests/tests-base/test-00435/stdout.reference new file mode 100644 index 0000000..b6d6c6f --- /dev/null +++ b/tests/tests-base/test-00435/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 aa +iclass REP_STOSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_STOSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW B 8 1 1 8 UINT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=AL SUPPRESSED R B 8 1 1 8 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: STOSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00436/cmd b/tests/tests-base/test-00436/cmd new file mode 100644 index 0000000..f17b52c --- /dev/null +++ b/tests/tests-base/test-00436/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 66AB diff --git a/tests/tests-base/test-00436/codes b/tests/tests-base/test-00436/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00436/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00436/retcode.reference b/tests/tests-base/test-00436/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00436/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00436/stderr.reference b/tests/tests-base/test-00436/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00436/stdout.reference b/tests/tests-base/test-00436/stdout.reference new file mode 100644 index 0000000..53b008d --- /dev/null +++ b/tests/tests-base/test-00436/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 66 ab +iclass REP_STOSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_STOSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW W 16 2 1 16 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=AX SUPPRESSED R W 16 2 1 16 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: STOSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00437/cmd b/tests/tests-base/test-00437/cmd new file mode 100644 index 0000000..de2a9b7 --- /dev/null +++ b/tests/tests-base/test-00437/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AB diff --git a/tests/tests-base/test-00437/codes b/tests/tests-base/test-00437/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00437/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00437/retcode.reference b/tests/tests-base/test-00437/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00437/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00437/stderr.reference b/tests/tests-base/test-00437/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00437/stdout.reference b/tests/tests-base/test-00437/stdout.reference new file mode 100644 index 0000000..412905d --- /dev/null +++ b/tests/tests-base/test-00437/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 ab +iclass REP_STOSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_STOSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW D 32 4 1 32 INT INVALID +1 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +2 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 written SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: STOSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00438/cmd b/tests/tests-base/test-00438/cmd new file mode 100644 index 0000000..7e33cf4 --- /dev/null +++ b/tests/tests-base/test-00438/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 48AB diff --git a/tests/tests-base/test-00438/codes b/tests/tests-base/test-00438/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00438/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00438/retcode.reference b/tests/tests-base/test-00438/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00438/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00438/stderr.reference b/tests/tests-base/test-00438/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00438/stdout.reference b/tests/tests-base/test-00438/stdout.reference new file mode 100644 index 0000000..764a441 --- /dev/null +++ b/tests/tests-base/test-00438/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 48 ab +iclass REP_STOSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REP_STOSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 MEM0 (see below) SUPPRESSED CW Q 64 8 1 64 INT INVALID +1 BASE0 BASE0=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +2 REG0 REG0=RAX SUPPRESSED R Q 64 8 1 64 INT GPR +3 REG1 REG1=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG2 REG2=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 written BASE= RDI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: STOSQ +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00439/cmd b/tests/tests-base/test-00439/cmd new file mode 100644 index 0000000..f2dddc9 --- /dev/null +++ b/tests/tests-base/test-00439/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AC diff --git a/tests/tests-base/test-00439/codes b/tests/tests-base/test-00439/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00439/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00439/retcode.reference b/tests/tests-base/test-00439/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00439/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00439/stderr.reference b/tests/tests-base/test-00439/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00439/stdout.reference b/tests/tests-base/test-00439/stdout.reference new file mode 100644 index 0000000..c96302a --- /dev/null +++ b/tests/tests-base/test-00439/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 ac +iclass REP_LODSB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_LODSB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL SUPPRESSED CW B 8 1 1 8 INT GPR +1 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: BYTEOP FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: LODSB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00440/cmd b/tests/tests-base/test-00440/cmd new file mode 100644 index 0000000..d5d5a9e --- /dev/null +++ b/tests/tests-base/test-00440/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 66AD diff --git a/tests/tests-base/test-00440/codes b/tests/tests-base/test-00440/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00440/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00440/retcode.reference b/tests/tests-base/test-00440/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00440/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00440/stderr.reference b/tests/tests-base/test-00440/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00440/stdout.reference b/tests/tests-base/test-00440/stdout.reference new file mode 100644 index 0000000..b33e388 --- /dev/null +++ b/tests/tests-base/test-00440/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 66 ad +iclass REP_LODSW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_LODSW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AX SUPPRESSED CW W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: LODSW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00441/cmd b/tests/tests-base/test-00441/cmd new file mode 100644 index 0000000..7ecedce --- /dev/null +++ b/tests/tests-base/test-00441/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AD diff --git a/tests/tests-base/test-00441/codes b/tests/tests-base/test-00441/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00441/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00441/retcode.reference b/tests/tests-base/test-00441/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00441/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00441/stderr.reference b/tests/tests-base/test-00441/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00441/stdout.reference b/tests/tests-base/test-00441/stdout.reference new file mode 100644 index 0000000..28e4a31 --- /dev/null +++ b/tests/tests-base/test-00441/stdout.reference @@ -0,0 +1,31 @@ +Attempting to decode: f3 ad +iclass REP_LODSD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REP_LODSD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED CW D 32 4 1 32 INT GPR +1 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +2 BASE0 BASE0=ESI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= DS BASE= ESI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: LODSD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00442/cmd b/tests/tests-base/test-00442/cmd new file mode 100644 index 0000000..d605a64 --- /dev/null +++ b/tests/tests-base/test-00442/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 48AD diff --git a/tests/tests-base/test-00442/codes b/tests/tests-base/test-00442/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00442/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00442/retcode.reference b/tests/tests-base/test-00442/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00442/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00442/stderr.reference b/tests/tests-base/test-00442/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00442/stdout.reference b/tests/tests-base/test-00442/stdout.reference new file mode 100644 index 0000000..77555d0 --- /dev/null +++ b/tests/tests-base/test-00442/stdout.reference @@ -0,0 +1,33 @@ +Attempting to decode: f3 48 ad +iclass REP_LODSQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REP_LODSQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX SUPPRESSED CW Q 64 8 1 64 INT GPR +1 MEM0 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RSI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +3 REG1 REG1=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG2 REG2=RFLAGS SUPPRESSED R Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RSI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags df-tst + read: df mask=0x400 + written: mask=0x0 + undefined: mask=0x0 +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: LODSQ +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00443/cmd b/tests/tests-base/test-00443/cmd new file mode 100644 index 0000000..ffa90fb --- /dev/null +++ b/tests/tests-base/test-00443/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AE diff --git a/tests/tests-base/test-00443/codes b/tests/tests-base/test-00443/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00443/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00443/retcode.reference b/tests/tests-base/test-00443/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00443/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00443/stderr.reference b/tests/tests-base/test-00443/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00443/stdout.reference b/tests/tests-base/test-00443/stdout.reference new file mode 100644 index 0000000..bdea114 --- /dev/null +++ b/tests/tests-base/test-00443/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: f3 ae +iclass REPE_SCASB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_SCASB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL SUPPRESSED R B 8 1 1 8 INT GPR +1 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: BYTEOP FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASB +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00444/cmd b/tests/tests-base/test-00444/cmd new file mode 100644 index 0000000..f8759ce --- /dev/null +++ b/tests/tests-base/test-00444/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 66AF diff --git a/tests/tests-base/test-00444/codes b/tests/tests-base/test-00444/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00444/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00444/retcode.reference b/tests/tests-base/test-00444/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00444/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00444/stderr.reference b/tests/tests-base/test-00444/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00444/stdout.reference b/tests/tests-base/test-00444/stdout.reference new file mode 100644 index 0000000..c1e779f --- /dev/null +++ b/tests/tests-base/test-00444/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f3 66 af +iclass REPE_SCASW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_SCASW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASW +F3 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00445/cmd b/tests/tests-base/test-00445/cmd new file mode 100644 index 0000000..3fe41e0 --- /dev/null +++ b/tests/tests-base/test-00445/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f3 AF diff --git a/tests/tests-base/test-00445/codes b/tests/tests-base/test-00445/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00445/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00445/retcode.reference b/tests/tests-base/test-00445/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00445/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00445/stderr.reference b/tests/tests-base/test-00445/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00445/stdout.reference b/tests/tests-base/test-00445/stdout.reference new file mode 100644 index 0000000..6e98fb1 --- /dev/null +++ b/tests/tests-base/test-00445/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: f3 af +iclass REPE_SCASD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPE_SCASD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +1 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASD +F3 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00446/cmd b/tests/tests-base/test-00446/cmd new file mode 100644 index 0000000..88122dc --- /dev/null +++ b/tests/tests-base/test-00446/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f3 48AF diff --git a/tests/tests-base/test-00446/codes b/tests/tests-base/test-00446/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00446/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00446/retcode.reference b/tests/tests-base/test-00446/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00446/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00446/stderr.reference b/tests/tests-base/test-00446/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00446/stdout.reference b/tests/tests-base/test-00446/stdout.reference new file mode 100644 index 0000000..4c6af40 --- /dev/null +++ b/tests/tests-base/test-00446/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f3 48 af +iclass REPE_SCASQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REPE_SCASQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX SUPPRESSED R Q 64 8 1 64 INT GPR +1 MEM0 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +3 REG1 REG1=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG2 REG2=RFLAGS SUPPRESSED RCW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RDI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASQ +F3 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00447/cmd b/tests/tests-base/test-00447/cmd new file mode 100644 index 0000000..304e8e1 --- /dev/null +++ b/tests/tests-base/test-00447/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 AE diff --git a/tests/tests-base/test-00447/codes b/tests/tests-base/test-00447/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00447/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00447/retcode.reference b/tests/tests-base/test-00447/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00447/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00447/stderr.reference b/tests/tests-base/test-00447/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00447/stdout.reference b/tests/tests-base/test-00447/stdout.reference new file mode 100644 index 0000000..ca0bdb5 --- /dev/null +++ b/tests/tests-base/test-00447/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: f2 ae +iclass REPNE_SCASB category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 2 +operand-width 8 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_SCASB +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AL SUPPRESSED R B 8 1 1 8 INT GPR +1 MEM0 (see below) SUPPRESSED CR B 8 1 1 8 UINT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 1 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: BYTEOP FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASB +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I86] diff --git a/tests/tests-base/test-00448/cmd b/tests/tests-base/test-00448/cmd new file mode 100644 index 0000000..53255c9 --- /dev/null +++ b/tests/tests-base/test-00448/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 66AF diff --git a/tests/tests-base/test-00448/codes b/tests/tests-base/test-00448/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00448/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00448/retcode.reference b/tests/tests-base/test-00448/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00448/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00448/stderr.reference b/tests/tests-base/test-00448/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00448/stdout.reference b/tests/tests-base/test-00448/stdout.reference new file mode 100644 index 0000000..7fe9ebe --- /dev/null +++ b/tests/tests-base/test-00448/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f2 66 af +iclass REPNE_SCASW category STRINGOP ISA-extension BASE ISA-set I86 +instruction-length 3 +operand-width 16 +effective-operand-width 16 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_SCASW +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=AX SUPPRESSED R W 16 2 1 16 INT GPR +1 MEM0 (see below) SUPPRESSED CR W 16 2 1 16 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 2 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASW +F2 PREFIX +66-OSZ PREFIX +ANY 66 PREFIX +Number of legacy prefixes: 2 +ISA SET: [I86] diff --git a/tests/tests-base/test-00449/cmd b/tests/tests-base/test-00449/cmd new file mode 100644 index 0000000..b1dd7df --- /dev/null +++ b/tests/tests-base/test-00449/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 f2 AF diff --git a/tests/tests-base/test-00449/codes b/tests/tests-base/test-00449/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00449/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00449/retcode.reference b/tests/tests-base/test-00449/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00449/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00449/stderr.reference b/tests/tests-base/test-00449/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00449/stdout.reference b/tests/tests-base/test-00449/stdout.reference new file mode 100644 index 0000000..39de155 --- /dev/null +++ b/tests/tests-base/test-00449/stdout.reference @@ -0,0 +1,32 @@ +Attempting to decode: f2 af +iclass REPNE_SCASD category STRINGOP ISA-extension BASE ISA-set I386 +instruction-length 2 +operand-width 32 +effective-operand-width 32 +effective-address-width 32 +stack-address-width 32 +iform-enum-name REPNE_SCASD +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=EAX SUPPRESSED R D 32 4 1 32 INT GPR +1 MEM0 (see below) SUPPRESSED CR D 32 4 1 32 INT INVALID +2 BASE0 BASE0=EDI SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +3 REG1 REG1=ECX SUPPRESSED RCW ASZ 32 4 1 32 INT GPR +4 REG2 REG2=EFLAGS SUPPRESSED RCW Y 32 4 1 32 INT FLAGS +Memory Operands + 0 read SEG= ES BASE= EDI/GPR ASZ0=32 + MemopBytes = 4 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASD +F2 PREFIX +Number of legacy prefixes: 1 +ISA SET: [I386] diff --git a/tests/tests-base/test-00450/cmd b/tests/tests-base/test-00450/cmd new file mode 100644 index 0000000..b87ba0f --- /dev/null +++ b/tests/tests-base/test-00450/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex1 -64 f2 48AF diff --git a/tests/tests-base/test-00450/codes b/tests/tests-base/test-00450/codes new file mode 100644 index 0000000..3d4f1b1 --- /dev/null +++ b/tests/tests-base/test-00450/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00450/retcode.reference b/tests/tests-base/test-00450/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00450/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00450/stderr.reference b/tests/tests-base/test-00450/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00450/stdout.reference b/tests/tests-base/test-00450/stdout.reference new file mode 100644 index 0000000..00685fd --- /dev/null +++ b/tests/tests-base/test-00450/stdout.reference @@ -0,0 +1,34 @@ +Attempting to decode: f2 48 af +iclass REPNE_SCASQ category STRINGOP ISA-extension LONGMODE ISA-set LONGMODE +instruction-length 3 +operand-width 64 +effective-operand-width 64 +effective-address-width 64 +stack-address-width 64 +iform-enum-name REPNE_SCASQ +iform-enum-name-dispatch (zero based) 0 +iclass-max-iform-dispatch 1 +Operands +# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS +# ==== ======= === == === ==== ===== ===== ====== ======== ======== +0 REG0 REG0=RAX SUPPRESSED R Q 64 8 1 64 INT GPR +1 MEM0 (see below) SUPPRESSED CR Q 64 8 1 64 INT INVALID +2 BASE0 BASE0=RDI SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +3 REG1 REG1=RCX SUPPRESSED RCW ASZ 64 8 1 64 INT GPR +4 REG2 REG2=RFLAGS SUPPRESSED RCW Y 64 8 1 64 INT FLAGS +Memory Operands + 0 read BASE= RDI/GPR ASZ0=64 + MemopBytes = 8 +FLAGS: + reads-rflags of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst + read: zf df mask=0x440 + written: of sf zf af pf cf mask=0x8d5 + undefined: mask=0x0 +READS ZF +ATTRIBUTES: FIXED_BASE0 REP +REAL REP corresponding no-rep iclass: SCASQ +F2 PREFIX +Number of legacy prefixes: 2 +ISA SET: [LONGMODE] +0 CPUID BIT NAME: [INTEL64] + Leaf 0x80000001, subleaf 0x00000000, EDX[29] diff --git a/tests/tests-base/test-00451/cmd b/tests/tests-base/test-00451/cmd new file mode 100644 index 0000000..291c925 --- /dev/null +++ b/tests/tests-base/test-00451/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d C5EC58CB diff --git a/tests/tests-base/test-00451/codes b/tests/tests-base/test-00451/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00451/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00451/retcode.reference b/tests/tests-base/test-00451/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00451/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00451/stderr.reference b/tests/tests-base/test-00451/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00451/stdout.reference b/tests/tests-base/test-00451/stdout.reference new file mode 100644 index 0000000..49acd7b --- /dev/null +++ b/tests/tests-base/test-00451/stdout.reference @@ -0,0 +1,3 @@ +C5EC58CB +ICLASS: VADDPS CATEGORY: AVX EXTENSION: AVX IFORM: VADDPS_YMMqq_YMMqq_YMMqq ISA_SET: AVX +SHORT: vaddps ymm1, ymm2, ymm3 diff --git a/tests/tests-base/test-00452/cmd b/tests/tests-base/test-00452/cmd new file mode 100644 index 0000000..c92d323 --- /dev/null +++ b/tests/tests-base/test-00452/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 66C5EC58CB diff --git a/tests/tests-base/test-00452/codes b/tests/tests-base/test-00452/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00452/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00452/retcode.reference b/tests/tests-base/test-00452/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00452/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00452/stderr.reference b/tests/tests-base/test-00452/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00452/stdout.reference b/tests/tests-base/test-00452/stdout.reference new file mode 100644 index 0000000..40767bc --- /dev/null +++ b/tests/tests-base/test-00452/stdout.reference @@ -0,0 +1,2 @@ +66C5EC58CB +ERROR: BAD_LEGACY_PREFIX Could not decode at offset: 0x0 PC: 0x0: [66C5EC58CB00000000000000000000] diff --git a/tests/tests-base/test-00453/cmd b/tests/tests-base/test-00453/cmd new file mode 100644 index 0000000..ac0a401 --- /dev/null +++ b/tests/tests-base/test-00453/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 vaddps ymm1 ymm2 ymm3 diff --git a/tests/tests-base/test-00453/codes b/tests/tests-base/test-00453/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00453/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00453/retcode.reference b/tests/tests-base/test-00453/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00453/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00453/stderr.reference b/tests/tests-base/test-00453/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00453/stdout.reference b/tests/tests-base/test-00453/stdout.reference new file mode 100644 index 0000000..ec46160 --- /dev/null +++ b/tests/tests-base/test-00453/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VADDPS MODE:1, REG0:YMM1, REG1:YMM2, REG2:YMM3, SMODE:1 +OPERAND ORDER: REG0 REG1 REG2 + +Encodable! C5EC58CB diff --git a/tests/tests-base/test-00454/cmd b/tests/tests-base/test-00454/cmd new file mode 100644 index 0000000..2b97826 --- /dev/null +++ b/tests/tests-base/test-00454/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vpinsrb xmm1 xmm2 eax IMM:ff diff --git a/tests/tests-base/test-00454/codes b/tests/tests-base/test-00454/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00454/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00454/retcode.reference b/tests/tests-base/test-00454/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00454/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00454/stderr.reference b/tests/tests-base/test-00454/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00454/stdout.reference b/tests/tests-base/test-00454/stdout.reference new file mode 100644 index 0000000..3f05fc8 --- /dev/null +++ b/tests/tests-base/test-00454/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPINSRB IMM_WIDTH:8, IMM0:0xff, MODE:2, REG0:XMM1, REG1:XMM2, REG2:EAX, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 IMM0 + +Encodable! C4E36920C8FF diff --git a/tests/tests-base/test-00455/cmd b/tests/tests-base/test-00455/cmd new file mode 100644 index 0000000..305c160 --- /dev/null +++ b/tests/tests-base/test-00455/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vpinsrb/64 xmm1 xmm2 eax IMM:ff diff --git a/tests/tests-base/test-00455/codes b/tests/tests-base/test-00455/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00455/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00455/retcode.reference b/tests/tests-base/test-00455/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00455/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00455/stderr.reference b/tests/tests-base/test-00455/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00455/stdout.reference b/tests/tests-base/test-00455/stdout.reference new file mode 100644 index 0000000..c0b5742 --- /dev/null +++ b/tests/tests-base/test-00455/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPINSRB EOSZ:3, IMM_WIDTH:8, IMM0:0xff, MODE:2, REG0:XMM1, REG1:XMM2, REG2:EAX, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 IMM0 + +Encodable! C4E3E920C8FF diff --git a/tests/tests-base/test-00456/cmd b/tests/tests-base/test-00456/cmd new file mode 100644 index 0000000..365e060 --- /dev/null +++ b/tests/tests-base/test-00456/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4E36920C8FF diff --git a/tests/tests-base/test-00456/codes b/tests/tests-base/test-00456/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00456/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00456/retcode.reference b/tests/tests-base/test-00456/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00456/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00456/stderr.reference b/tests/tests-base/test-00456/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00456/stdout.reference b/tests/tests-base/test-00456/stdout.reference new file mode 100644 index 0000000..cdba8f1 --- /dev/null +++ b/tests/tests-base/test-00456/stdout.reference @@ -0,0 +1,3 @@ +C4E36920C8FF +ICLASS: VPINSRB CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRB_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrb xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00457/cmd b/tests/tests-base/test-00457/cmd new file mode 100644 index 0000000..ce38985 --- /dev/null +++ b/tests/tests-base/test-00457/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4 E3 E9 20C8FF diff --git a/tests/tests-base/test-00457/codes b/tests/tests-base/test-00457/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00457/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00457/retcode.reference b/tests/tests-base/test-00457/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00457/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00457/stderr.reference b/tests/tests-base/test-00457/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00457/stdout.reference b/tests/tests-base/test-00457/stdout.reference new file mode 100644 index 0000000..ad77566 --- /dev/null +++ b/tests/tests-base/test-00457/stdout.reference @@ -0,0 +1,3 @@ +C4E3E920C8FF +ICLASS: VPINSRB CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRB_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrb xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00458/cmd b/tests/tests-base/test-00458/cmd new file mode 100644 index 0000000..eb54bdc --- /dev/null +++ b/tests/tests-base/test-00458/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d C4 E3 E9 20C8FF diff --git a/tests/tests-base/test-00458/codes b/tests/tests-base/test-00458/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00458/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00458/retcode.reference b/tests/tests-base/test-00458/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00458/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00458/stderr.reference b/tests/tests-base/test-00458/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00458/stdout.reference b/tests/tests-base/test-00458/stdout.reference new file mode 100644 index 0000000..ad77566 --- /dev/null +++ b/tests/tests-base/test-00458/stdout.reference @@ -0,0 +1,3 @@ +C4E3E920C8FF +ICLASS: VPINSRB CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRB_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrb xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00459/cmd b/tests/tests-base/test-00459/cmd new file mode 100644 index 0000000..9039d78 --- /dev/null +++ b/tests/tests-base/test-00459/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d C4 E3 69 20C8FF diff --git a/tests/tests-base/test-00459/codes b/tests/tests-base/test-00459/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00459/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00459/retcode.reference b/tests/tests-base/test-00459/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00459/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00459/stderr.reference b/tests/tests-base/test-00459/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00459/stdout.reference b/tests/tests-base/test-00459/stdout.reference new file mode 100644 index 0000000..cdba8f1 --- /dev/null +++ b/tests/tests-base/test-00459/stdout.reference @@ -0,0 +1,3 @@ +C4E36920C8FF +ICLASS: VPINSRB CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRB_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrb xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00460/cmd b/tests/tests-base/test-00460/cmd new file mode 100644 index 0000000..cce60e8 --- /dev/null +++ b/tests/tests-base/test-00460/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vpinsrw xmm1 xmm2 eax IMM:ff diff --git a/tests/tests-base/test-00460/codes b/tests/tests-base/test-00460/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00460/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00460/retcode.reference b/tests/tests-base/test-00460/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00460/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00460/stderr.reference b/tests/tests-base/test-00460/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00460/stdout.reference b/tests/tests-base/test-00460/stdout.reference new file mode 100644 index 0000000..7d8cbb1 --- /dev/null +++ b/tests/tests-base/test-00460/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VPINSRW IMM_WIDTH:8, IMM0:0xff, MODE:2, REG0:XMM1, REG1:XMM2, REG2:EAX, SMODE:2 +OPERAND ORDER: REG0 REG1 REG2 IMM0 + +Encodable! C5E9C4C8FF diff --git a/tests/tests-base/test-00461/cmd b/tests/tests-base/test-00461/cmd new file mode 100644 index 0000000..2ffa38e --- /dev/null +++ b/tests/tests-base/test-00461/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C5E9C4C8FF diff --git a/tests/tests-base/test-00461/codes b/tests/tests-base/test-00461/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00461/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00461/retcode.reference b/tests/tests-base/test-00461/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00461/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00461/stderr.reference b/tests/tests-base/test-00461/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00461/stdout.reference b/tests/tests-base/test-00461/stdout.reference new file mode 100644 index 0000000..96c9175 --- /dev/null +++ b/tests/tests-base/test-00461/stdout.reference @@ -0,0 +1,3 @@ +C5E9C4C8FF +ICLASS: VPINSRW CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRW_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrw xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00462/cmd b/tests/tests-base/test-00462/cmd new file mode 100644 index 0000000..1c064b3 --- /dev/null +++ b/tests/tests-base/test-00462/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4 E1 69 C4 C8 FF diff --git a/tests/tests-base/test-00462/codes b/tests/tests-base/test-00462/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00462/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00462/retcode.reference b/tests/tests-base/test-00462/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00462/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00462/stderr.reference b/tests/tests-base/test-00462/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00462/stdout.reference b/tests/tests-base/test-00462/stdout.reference new file mode 100644 index 0000000..eacb21a --- /dev/null +++ b/tests/tests-base/test-00462/stdout.reference @@ -0,0 +1,3 @@ +C4E169C4C8FF +ICLASS: VPINSRW CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRW_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrw xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00463/cmd b/tests/tests-base/test-00463/cmd new file mode 100644 index 0000000..a50eaca --- /dev/null +++ b/tests/tests-base/test-00463/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4 E1 E9 C4 C8 FF diff --git a/tests/tests-base/test-00463/codes b/tests/tests-base/test-00463/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00463/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00463/retcode.reference b/tests/tests-base/test-00463/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00463/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00463/stderr.reference b/tests/tests-base/test-00463/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00463/stdout.reference b/tests/tests-base/test-00463/stdout.reference new file mode 100644 index 0000000..3e172e3 --- /dev/null +++ b/tests/tests-base/test-00463/stdout.reference @@ -0,0 +1,3 @@ +C4E1E9C4C8FF +ICLASS: VPINSRW CATEGORY: AVX EXTENSION: AVX IFORM: VPINSRW_XMMdq_XMMdq_GPR32d_IMMb ISA_SET: AVX +SHORT: vpinsrw xmm1, xmm2, eax, 0xff diff --git a/tests/tests-base/test-00464/cmd b/tests/tests-base/test-00464/cmd new file mode 100644 index 0000000..992d3d7 --- /dev/null +++ b/tests/tests-base/test-00464/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vbroadcastss/32 xmm1 MEM4:rax diff --git a/tests/tests-base/test-00464/codes b/tests/tests-base/test-00464/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00464/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00464/retcode.reference b/tests/tests-base/test-00464/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00464/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00464/stderr.reference b/tests/tests-base/test-00464/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00464/stdout.reference b/tests/tests-base/test-00464/stdout.reference new file mode 100644 index 0000000..b6bdb0f --- /dev/null +++ b/tests/tests-base/test-00464/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VBROADCASTSS EOSZ:2, MEM_WIDTH:4, MEM0:dword ptr [RAX], MODE:2, REG0:XMM1, SMODE:2 +OPERAND ORDER: REG0 MEM0 + +Encodable! C4E2791808 diff --git a/tests/tests-base/test-00465/cmd b/tests/tests-base/test-00465/cmd new file mode 100644 index 0000000..1a72f66 --- /dev/null +++ b/tests/tests-base/test-00465/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vbroadcastss/64 xmm1 MEM4:rax diff --git a/tests/tests-base/test-00465/codes b/tests/tests-base/test-00465/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00465/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00465/retcode.reference b/tests/tests-base/test-00465/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00465/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00465/stderr.reference b/tests/tests-base/test-00465/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00465/stdout.reference b/tests/tests-base/test-00465/stdout.reference new file mode 100644 index 0000000..b66a644 --- /dev/null +++ b/tests/tests-base/test-00465/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VBROADCASTSS EOSZ:3, MEM_WIDTH:4, MEM0:dword ptr [RAX], MODE:2, REG0:XMM1, SMODE:2 +OPERAND ORDER: REG0 MEM0 + +Encodable! C4E2791808 diff --git a/tests/tests-base/test-00466/cmd b/tests/tests-base/test-00466/cmd new file mode 100644 index 0000000..bef64ab --- /dev/null +++ b/tests/tests-base/test-00466/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 67C4226D934CC500 diff --git a/tests/tests-base/test-00466/codes b/tests/tests-base/test-00466/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00466/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00466/retcode.reference b/tests/tests-base/test-00466/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00466/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00466/stderr.reference b/tests/tests-base/test-00466/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00466/stdout.reference b/tests/tests-base/test-00466/stdout.reference new file mode 100644 index 0000000..4e41df5 --- /dev/null +++ b/tests/tests-base/test-00466/stdout.reference @@ -0,0 +1,3 @@ +67C4226D934CC500 +ICLASS: VGATHERQPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherqps xmm9, xmmword ptr [ebp+ymm8*8], xmm2 diff --git a/tests/tests-base/test-00467/cmd b/tests/tests-base/test-00467/cmd new file mode 100644 index 0000000..e6b5bf9 --- /dev/null +++ b/tests/tests-base/test-00467/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 67C4E23593AC3ED8B2080A diff --git a/tests/tests-base/test-00467/codes b/tests/tests-base/test-00467/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00467/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00467/retcode.reference b/tests/tests-base/test-00467/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00467/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00467/stderr.reference b/tests/tests-base/test-00467/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00467/stdout.reference b/tests/tests-base/test-00467/stdout.reference new file mode 100644 index 0000000..895228b --- /dev/null +++ b/tests/tests-base/test-00467/stdout.reference @@ -0,0 +1,3 @@ +67C4E23593AC3ED8B2080A +ICLASS: VGATHERQPS CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vgatherqps xmm5, xmmword ptr [esi+ymm7*1+0xa08b2d8], xmm9 diff --git a/tests/tests-base/test-00468/cmd b/tests/tests-base/test-00468/cmd new file mode 100644 index 0000000..1b9d660 --- /dev/null +++ b/tests/tests-base/test-00468/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4A23D91043D00000000 diff --git a/tests/tests-base/test-00468/codes b/tests/tests-base/test-00468/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00468/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00468/retcode.reference b/tests/tests-base/test-00468/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00468/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00468/stderr.reference b/tests/tests-base/test-00468/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00468/stdout.reference b/tests/tests-base/test-00468/stdout.reference new file mode 100644 index 0000000..10268a1 --- /dev/null +++ b/tests/tests-base/test-00468/stdout.reference @@ -0,0 +1,3 @@ +C4A23D91043D00000000 +ICLASS: VPGATHERQD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherqd xmm0, xmmword ptr [ymm15*1], xmm8 diff --git a/tests/tests-base/test-00469/cmd b/tests/tests-base/test-00469/cmd new file mode 100644 index 0000000..05fc428 --- /dev/null +++ b/tests/tests-base/test-00469/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C462159124058076ED5E diff --git a/tests/tests-base/test-00469/codes b/tests/tests-base/test-00469/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00469/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00469/retcode.reference b/tests/tests-base/test-00469/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00469/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00469/stderr.reference b/tests/tests-base/test-00469/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00469/stdout.reference b/tests/tests-base/test-00469/stdout.reference new file mode 100644 index 0000000..235b56b --- /dev/null +++ b/tests/tests-base/test-00469/stdout.reference @@ -0,0 +1,3 @@ +C462159124058076ED5E +ICLASS: VPGATHERQD CATEGORY: AVX2GATHER EXTENSION: AVX2GATHER IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 ISA_SET: AVX2GATHER +SHORT: vpgatherqd xmm12, xmmword ptr [ymm0*1+0x5eed7680], xmm13 diff --git a/tests/tests-base/test-00470/cmd b/tests/tests-base/test-00470/cmd new file mode 100644 index 0000000..081754c --- /dev/null +++ b/tests/tests-base/test-00470/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vgatherdps ymm1 MEM32:RAX,YMM2,2 YMM3 diff --git a/tests/tests-base/test-00470/codes b/tests/tests-base/test-00470/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00470/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00470/retcode.reference b/tests/tests-base/test-00470/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00470/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00470/stderr.reference b/tests/tests-base/test-00470/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00470/stdout.reference b/tests/tests-base/test-00470/stdout.reference new file mode 100644 index 0000000..df1e163 --- /dev/null +++ b/tests/tests-base/test-00470/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPS MEM_WIDTH:32, MEM0:ymmword ptr [RAX+YMM2*2], MODE:2, REG0:YMM1, REG1:YMM3, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E265920C50 diff --git a/tests/tests-base/test-00471/cmd b/tests/tests-base/test-00471/cmd new file mode 100644 index 0000000..e4b8ece --- /dev/null +++ b/tests/tests-base/test-00471/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex3 -64 vgatherdps ymm1 MEM32:RBP,YMM2,2 YMM3 diff --git a/tests/tests-base/test-00471/codes b/tests/tests-base/test-00471/codes new file mode 100644 index 0000000..8d3025b --- /dev/null +++ b/tests/tests-base/test-00471/codes @@ -0,0 +1 @@ +ENC AVX diff --git a/tests/tests-base/test-00471/retcode.reference b/tests/tests-base/test-00471/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00471/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00471/stderr.reference b/tests/tests-base/test-00471/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00471/stdout.reference b/tests/tests-base/test-00471/stdout.reference new file mode 100644 index 0000000..867e665 --- /dev/null +++ b/tests/tests-base/test-00471/stdout.reference @@ -0,0 +1,5 @@ +Encode request: +VGATHERDPS MEM_WIDTH:32, MEM0:ymmword ptr [RBP+YMM2*2], MODE:2, REG0:YMM1, REG1:YMM3, SMODE:2 +OPERAND ORDER: REG0 MEM0 REG1 + +Encodable! C4E265924C5500 diff --git a/tests/tests-base/test-00472/cmd b/tests/tests-base/test-00472/cmd new file mode 100644 index 0000000..cff6686 --- /dev/null +++ b/tests/tests-base/test-00472/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d 0fbc00 diff --git a/tests/tests-base/test-00472/codes b/tests/tests-base/test-00472/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00472/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00472/retcode.reference b/tests/tests-base/test-00472/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00472/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00472/stderr.reference b/tests/tests-base/test-00472/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00472/stdout.reference b/tests/tests-base/test-00472/stdout.reference new file mode 100644 index 0000000..e988e2c --- /dev/null +++ b/tests/tests-base/test-00472/stdout.reference @@ -0,0 +1,3 @@ +0FBC00 +ICLASS: BSF CATEGORY: BITBYTE EXTENSION: BASE IFORM: BSF_GPRv_MEMv ISA_SET: I386 +SHORT: bsf eax, dword ptr [eax] diff --git a/tests/tests-base/test-00473/cmd b/tests/tests-base/test-00473/cmd new file mode 100644 index 0000000..7ecb73d --- /dev/null +++ b/tests/tests-base/test-00473/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d f30fbc00 diff --git a/tests/tests-base/test-00473/codes b/tests/tests-base/test-00473/codes new file mode 100644 index 0000000..fdfd99c --- /dev/null +++ b/tests/tests-base/test-00473/codes @@ -0,0 +1 @@ +DEC HSW diff --git a/tests/tests-base/test-00473/retcode.reference b/tests/tests-base/test-00473/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00473/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00473/stderr.reference b/tests/tests-base/test-00473/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00473/stdout.reference b/tests/tests-base/test-00473/stdout.reference new file mode 100644 index 0000000..a4ad920 --- /dev/null +++ b/tests/tests-base/test-00473/stdout.reference @@ -0,0 +1,3 @@ +F30FBC00 +ICLASS: TZCNT CATEGORY: BMI1 EXTENSION: BMI1 IFORM: TZCNT_GPRv_MEMv ISA_SET: BMI1 +SHORT: tzcnt eax, dword ptr [eax] diff --git a/tests/tests-base/test-00474/cmd b/tests/tests-base/test-00474/cmd new file mode 100644 index 0000000..dbb16e7 --- /dev/null +++ b/tests/tests-base/test-00474/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check HASWELL -d f30fbc00 diff --git a/tests/tests-base/test-00474/codes b/tests/tests-base/test-00474/codes new file mode 100644 index 0000000..fdfd99c --- /dev/null +++ b/tests/tests-base/test-00474/codes @@ -0,0 +1 @@ +DEC HSW diff --git a/tests/tests-base/test-00474/retcode.reference b/tests/tests-base/test-00474/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00474/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00474/stderr.reference b/tests/tests-base/test-00474/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00474/stdout.reference b/tests/tests-base/test-00474/stdout.reference new file mode 100644 index 0000000..c03226f --- /dev/null +++ b/tests/tests-base/test-00474/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to HASWELL +F30FBC00 +ICLASS: TZCNT CATEGORY: BMI1 EXTENSION: BMI1 IFORM: TZCNT_GPRv_MEMv ISA_SET: BMI1 +SHORT: tzcnt eax, dword ptr [eax] diff --git a/tests/tests-base/test-00475/cmd b/tests/tests-base/test-00475/cmd new file mode 100644 index 0000000..51d1bbc --- /dev/null +++ b/tests/tests-base/test-00475/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check IVYBRIDGE -d f30fbc00 diff --git a/tests/tests-base/test-00475/codes b/tests/tests-base/test-00475/codes new file mode 100644 index 0000000..fdfd99c --- /dev/null +++ b/tests/tests-base/test-00475/codes @@ -0,0 +1 @@ +DEC HSW diff --git a/tests/tests-base/test-00475/retcode.reference b/tests/tests-base/test-00475/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00475/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00475/stderr.reference b/tests/tests-base/test-00475/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00475/stdout.reference b/tests/tests-base/test-00475/stdout.reference new file mode 100644 index 0000000..23f3fba --- /dev/null +++ b/tests/tests-base/test-00475/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to IVYBRIDGE +F30FBC00 +ICLASS: BSF CATEGORY: BITBYTE EXTENSION: BASE IFORM: BSF_GPRv_MEMv ISA_SET: I386 +SHORT: bsf eax, dword ptr [eax] diff --git a/tests/tests-base/test-00476/cmd b/tests/tests-base/test-00476/cmd new file mode 100644 index 0000000..6693f4f --- /dev/null +++ b/tests/tests-base/test-00476/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check HASWELL -d 0fbc00 diff --git a/tests/tests-base/test-00476/codes b/tests/tests-base/test-00476/codes new file mode 100644 index 0000000..fdfd99c --- /dev/null +++ b/tests/tests-base/test-00476/codes @@ -0,0 +1 @@ +DEC HSW diff --git a/tests/tests-base/test-00476/retcode.reference b/tests/tests-base/test-00476/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00476/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00476/stderr.reference b/tests/tests-base/test-00476/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00476/stdout.reference b/tests/tests-base/test-00476/stdout.reference new file mode 100644 index 0000000..c28b835 --- /dev/null +++ b/tests/tests-base/test-00476/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to HASWELL +0FBC00 +ICLASS: BSF CATEGORY: BITBYTE EXTENSION: BASE IFORM: BSF_GPRv_MEMv ISA_SET: I386 +SHORT: bsf eax, dword ptr [eax] diff --git a/tests/tests-base/test-00477/cmd b/tests/tests-base/test-00477/cmd new file mode 100644 index 0000000..6d07960 --- /dev/null +++ b/tests/tests-base/test-00477/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check QUARK -d F2E100 diff --git a/tests/tests-base/test-00477/codes b/tests/tests-base/test-00477/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00477/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00477/retcode.reference b/tests/tests-base/test-00477/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00477/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00477/stderr.reference b/tests/tests-base/test-00477/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00477/stdout.reference b/tests/tests-base/test-00477/stdout.reference new file mode 100644 index 0000000..b65b028 --- /dev/null +++ b/tests/tests-base/test-00477/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to QUARK +F2E100 +ICLASS: LOOPE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPE_RELBRb ISA_SET: I86 +SHORT: loope 0x3 diff --git a/tests/tests-base/test-00478/cmd b/tests/tests-base/test-00478/cmd new file mode 100644 index 0000000..b0589f7 --- /dev/null +++ b/tests/tests-base/test-00478/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check QUARK -d E100 diff --git a/tests/tests-base/test-00478/codes b/tests/tests-base/test-00478/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00478/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00478/retcode.reference b/tests/tests-base/test-00478/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00478/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00478/stderr.reference b/tests/tests-base/test-00478/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00478/stdout.reference b/tests/tests-base/test-00478/stdout.reference new file mode 100644 index 0000000..481e55f --- /dev/null +++ b/tests/tests-base/test-00478/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to QUARK +E100 +ICLASS: LOOPE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPE_RELBRb ISA_SET: I86 +SHORT: loope 0x2 diff --git a/tests/tests-base/test-00479/cmd b/tests/tests-base/test-00479/cmd new file mode 100644 index 0000000..71e1781 --- /dev/null +++ b/tests/tests-base/test-00479/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check QUARK -d F3E100 diff --git a/tests/tests-base/test-00479/codes b/tests/tests-base/test-00479/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00479/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00479/retcode.reference b/tests/tests-base/test-00479/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00479/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00479/stderr.reference b/tests/tests-base/test-00479/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00479/stdout.reference b/tests/tests-base/test-00479/stdout.reference new file mode 100644 index 0000000..57982f6 --- /dev/null +++ b/tests/tests-base/test-00479/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to QUARK +F3E100 +ICLASS: LOOPE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPE_RELBRb ISA_SET: I86 +SHORT: loope 0x3 diff --git a/tests/tests-base/test-00480/cmd b/tests/tests-base/test-00480/cmd new file mode 100644 index 0000000..86c24b8 --- /dev/null +++ b/tests/tests-base/test-00480/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check PENTIUM -d F2E100 diff --git a/tests/tests-base/test-00480/codes b/tests/tests-base/test-00480/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00480/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00480/retcode.reference b/tests/tests-base/test-00480/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00480/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00480/stderr.reference b/tests/tests-base/test-00480/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00480/stdout.reference b/tests/tests-base/test-00480/stdout.reference new file mode 100644 index 0000000..937b3e3 --- /dev/null +++ b/tests/tests-base/test-00480/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to PENTIUM +F2E100 +ICLASS: LOOPNE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPNE_RELBRb ISA_SET: I86 +SHORT: loopne 0x3 diff --git a/tests/tests-base/test-00481/cmd b/tests/tests-base/test-00481/cmd new file mode 100644 index 0000000..4bfc448 --- /dev/null +++ b/tests/tests-base/test-00481/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check PENTIUM -d E100 diff --git a/tests/tests-base/test-00481/codes b/tests/tests-base/test-00481/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00481/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00481/retcode.reference b/tests/tests-base/test-00481/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00481/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00481/stderr.reference b/tests/tests-base/test-00481/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00481/stdout.reference b/tests/tests-base/test-00481/stdout.reference new file mode 100644 index 0000000..60f9365 --- /dev/null +++ b/tests/tests-base/test-00481/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to PENTIUM +E100 +ICLASS: LOOPE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPE_RELBRb ISA_SET: I86 +SHORT: loope 0x2 diff --git a/tests/tests-base/test-00482/cmd b/tests/tests-base/test-00482/cmd new file mode 100644 index 0000000..6e696e3 --- /dev/null +++ b/tests/tests-base/test-00482/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -chip-check PENTIUM -d F3E100 diff --git a/tests/tests-base/test-00482/codes b/tests/tests-base/test-00482/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00482/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00482/retcode.reference b/tests/tests-base/test-00482/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00482/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00482/stderr.reference b/tests/tests-base/test-00482/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00482/stdout.reference b/tests/tests-base/test-00482/stdout.reference new file mode 100644 index 0000000..9ff398d --- /dev/null +++ b/tests/tests-base/test-00482/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to PENTIUM +F3E100 +ICLASS: LOOPE CATEGORY: COND_BR EXTENSION: BASE IFORM: LOOPE_RELBRb ISA_SET: I86 +SHORT: loope 0x3 diff --git a/tests/tests-base/test-00483/cmd b/tests/tests-base/test-00483/cmd new file mode 100644 index 0000000..eefce23 --- /dev/null +++ b/tests/tests-base/test-00483/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de f266440f38f1fa diff --git a/tests/tests-base/test-00483/codes b/tests/tests-base/test-00483/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00483/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00483/retcode.reference b/tests/tests-base/test-00483/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00483/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00483/stderr.reference b/tests/tests-base/test-00483/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00483/stdout.reference b/tests/tests-base/test-00483/stdout.reference new file mode 100644 index 0000000..8e11085 --- /dev/null +++ b/tests/tests-base/test-00483/stdout.reference @@ -0,0 +1,5 @@ +F266440F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 r15d, dx +Encodable! F266440F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00484/cmd b/tests/tests-base/test-00484/cmd new file mode 100644 index 0000000..1c434e6 --- /dev/null +++ b/tests/tests-base/test-00484/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de f2480f38f1fa diff --git a/tests/tests-base/test-00484/codes b/tests/tests-base/test-00484/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00484/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00484/retcode.reference b/tests/tests-base/test-00484/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00484/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00484/stderr.reference b/tests/tests-base/test-00484/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00484/stdout.reference b/tests/tests-base/test-00484/stdout.reference new file mode 100644 index 0000000..350f738 --- /dev/null +++ b/tests/tests-base/test-00484/stdout.reference @@ -0,0 +1,5 @@ +F2480F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 rdi, rdx +Encodable! F2480F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00485/cmd b/tests/tests-base/test-00485/cmd new file mode 100644 index 0000000..6a9cdc3 --- /dev/null +++ b/tests/tests-base/test-00485/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de f2440f38f1fa diff --git a/tests/tests-base/test-00485/codes b/tests/tests-base/test-00485/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00485/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00485/retcode.reference b/tests/tests-base/test-00485/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00485/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00485/stderr.reference b/tests/tests-base/test-00485/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00485/stdout.reference b/tests/tests-base/test-00485/stdout.reference new file mode 100644 index 0000000..c37f8b4 --- /dev/null +++ b/tests/tests-base/test-00485/stdout.reference @@ -0,0 +1,5 @@ +F2440F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 r15d, edx +Encodable! F2440F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00486/cmd b/tests/tests-base/test-00486/cmd new file mode 100644 index 0000000..2bb7ecb --- /dev/null +++ b/tests/tests-base/test-00486/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -de f20f38f1fa diff --git a/tests/tests-base/test-00486/codes b/tests/tests-base/test-00486/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00486/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00486/retcode.reference b/tests/tests-base/test-00486/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00486/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00486/stderr.reference b/tests/tests-base/test-00486/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00486/stdout.reference b/tests/tests-base/test-00486/stdout.reference new file mode 100644 index 0000000..d731b9a --- /dev/null +++ b/tests/tests-base/test-00486/stdout.reference @@ -0,0 +1,5 @@ +F20F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 edi, edx +Encodable! F20F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00487/cmd b/tests/tests-base/test-00487/cmd new file mode 100644 index 0000000..5705e9a --- /dev/null +++ b/tests/tests-base/test-00487/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -de f2660f38f1fa diff --git a/tests/tests-base/test-00487/codes b/tests/tests-base/test-00487/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00487/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00487/retcode.reference b/tests/tests-base/test-00487/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00487/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00487/stderr.reference b/tests/tests-base/test-00487/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00487/stdout.reference b/tests/tests-base/test-00487/stdout.reference new file mode 100644 index 0000000..2d761da --- /dev/null +++ b/tests/tests-base/test-00487/stdout.reference @@ -0,0 +1,5 @@ +F2660F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 edi, dx +Encodable! F2660F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00488/cmd b/tests/tests-base/test-00488/cmd new file mode 100644 index 0000000..86b7559 --- /dev/null +++ b/tests/tests-base/test-00488/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de f20f38f1fa diff --git a/tests/tests-base/test-00488/codes b/tests/tests-base/test-00488/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00488/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00488/retcode.reference b/tests/tests-base/test-00488/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00488/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00488/stderr.reference b/tests/tests-base/test-00488/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00488/stdout.reference b/tests/tests-base/test-00488/stdout.reference new file mode 100644 index 0000000..d38c8ba --- /dev/null +++ b/tests/tests-base/test-00488/stdout.reference @@ -0,0 +1,5 @@ +F20F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 edi, dx +Encodable! F20F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00489/cmd b/tests/tests-base/test-00489/cmd new file mode 100644 index 0000000..8449974 --- /dev/null +++ b/tests/tests-base/test-00489/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -de f2660f38f1fa diff --git a/tests/tests-base/test-00489/codes b/tests/tests-base/test-00489/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00489/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00489/retcode.reference b/tests/tests-base/test-00489/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00489/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00489/stderr.reference b/tests/tests-base/test-00489/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00489/stdout.reference b/tests/tests-base/test-00489/stdout.reference new file mode 100644 index 0000000..93315d3 --- /dev/null +++ b/tests/tests-base/test-00489/stdout.reference @@ -0,0 +1,5 @@ +F2660F38F1FA +ICLASS: CRC32 CATEGORY: SSE EXTENSION: SSE4 IFORM: CRC32_GPRyy_GPRv ISA_SET: SSE42 +SHORT: crc32 edi, edx +Encodable! F2660F38F1FA +Identical re-encoding diff --git a/tests/tests-base/test-00490/cmd b/tests/tests-base/test-00490/cmd new file mode 100644 index 0000000..958b394 --- /dev/null +++ b/tests/tests-base/test-00490/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -chip-check SANDYBRIDGE -d 0fae30 diff --git a/tests/tests-base/test-00490/codes b/tests/tests-base/test-00490/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00490/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00490/retcode.reference b/tests/tests-base/test-00490/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00490/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00490/stderr.reference b/tests/tests-base/test-00490/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00490/stdout.reference b/tests/tests-base/test-00490/stdout.reference new file mode 100644 index 0000000..c2687b4 --- /dev/null +++ b/tests/tests-base/test-00490/stdout.reference @@ -0,0 +1,4 @@ +Setting chip to SANDYBRIDGE +0FAE30 +ICLASS: XSAVEOPT CATEGORY: XSAVEOPT EXTENSION: XSAVEOPT IFORM: XSAVEOPT_MEMmxsave ISA_SET: XSAVEOPT +SHORT: xsaveopt ptr [rax] diff --git a/tests/tests-base/test-00491/cmd b/tests/tests-base/test-00491/cmd new file mode 100644 index 0000000..7742f76 --- /dev/null +++ b/tests/tests-base/test-00491/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f2 f0 01 03 diff --git a/tests/tests-base/test-00491/codes b/tests/tests-base/test-00491/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00491/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00491/retcode.reference b/tests/tests-base/test-00491/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00491/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00491/stderr.reference b/tests/tests-base/test-00491/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00491/stdout.reference b/tests/tests-base/test-00491/stdout.reference new file mode 100644 index 0000000..bc24246 --- /dev/null +++ b/tests/tests-base/test-00491/stdout.reference @@ -0,0 +1,5 @@ +F2F00103 +ICLASS: ADD_LOCK CATEGORY: BINARY EXTENSION: BASE IFORM: ADD_LOCK_MEMv_GPRv ISA_SET: I86 +SHORT: xacquire lock add dword ptr [ebx], eax +Encodable! F2F00103 +Identical re-encoding diff --git a/tests/tests-base/test-00492/cmd b/tests/tests-base/test-00492/cmd new file mode 100644 index 0000000..3e62456 --- /dev/null +++ b/tests/tests-base/test-00492/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e movsd_xmm xmm0 MEM4:eax diff --git a/tests/tests-base/test-00492/codes b/tests/tests-base/test-00492/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00492/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00492/retcode.reference b/tests/tests-base/test-00492/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00492/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00492/stderr.reference b/tests/tests-base/test-00492/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00492/stdout.reference b/tests/tests-base/test-00492/stdout.reference new file mode 100644 index 0000000..1c2e23f --- /dev/null +++ b/tests/tests-base/test-00492/stdout.reference @@ -0,0 +1,5 @@ +Request: MOVSD_XMM EASZ:2, MEM_WIDTH:4, MEM0:dword ptr [EAX], MODE:1, REG0:XMM0, SMODE:1 +OPERAND ORDER: REG0 MEM0 +Could not encode: movsd_xmm xmm0 MEM4:eax +Error code was: GENERAL_ERROR +[XED CLIENT ERROR] Dying diff --git a/tests/tests-base/test-00493/cmd b/tests/tests-base/test-00493/cmd new file mode 100644 index 0000000..7d83d7b --- /dev/null +++ b/tests/tests-base/test-00493/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de f30f5100 diff --git a/tests/tests-base/test-00493/codes b/tests/tests-base/test-00493/codes new file mode 100644 index 0000000..3fa1ffc --- /dev/null +++ b/tests/tests-base/test-00493/codes @@ -0,0 +1 @@ +DEC END diff --git a/tests/tests-base/test-00493/retcode.reference b/tests/tests-base/test-00493/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00493/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00493/stderr.reference b/tests/tests-base/test-00493/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00493/stdout.reference b/tests/tests-base/test-00493/stdout.reference new file mode 100644 index 0000000..4160780 --- /dev/null +++ b/tests/tests-base/test-00493/stdout.reference @@ -0,0 +1,5 @@ +F30F5100 +ICLASS: SQRTSS CATEGORY: SSE EXTENSION: SSE IFORM: SQRTSS_XMMss_MEMss ISA_SET: SSE +SHORT: sqrtss xmm0, dword ptr [eax] +Encodable! F30F5100 +Identical re-encoding diff --git a/tests/tests-base/test-00494/cmd b/tests/tests-base/test-00494/cmd new file mode 100644 index 0000000..c244772 --- /dev/null +++ b/tests/tests-base/test-00494/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e sqrtss xmm0 mem4:eax diff --git a/tests/tests-base/test-00494/codes b/tests/tests-base/test-00494/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00494/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00494/retcode.reference b/tests/tests-base/test-00494/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00494/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00494/stderr.reference b/tests/tests-base/test-00494/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00494/stdout.reference b/tests/tests-base/test-00494/stdout.reference new file mode 100644 index 0000000..aabea46 --- /dev/null +++ b/tests/tests-base/test-00494/stdout.reference @@ -0,0 +1,4 @@ +Request: SQRTSS EASZ:2, MEM_WIDTH:4, MEM0:dword ptr [EAX], MODE:1, REG0:XMM0, SMODE:1 +OPERAND ORDER: REG0 MEM0 +Encodable! F30F5100 +.byte 0xf3,0x0f,0x51,0x00 diff --git a/tests/tests-base/test-00495/cmd b/tests/tests-base/test-00495/cmd new file mode 100644 index 0000000..b893ccd --- /dev/null +++ b/tests/tests-base/test-00495/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -16 -d 36 C4 E2 68 F3 0C diff --git a/tests/tests-base/test-00495/codes b/tests/tests-base/test-00495/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00495/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00495/retcode.reference b/tests/tests-base/test-00495/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00495/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00495/stderr.reference b/tests/tests-base/test-00495/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00495/stdout.reference b/tests/tests-base/test-00495/stdout.reference new file mode 100644 index 0000000..fd53f6f --- /dev/null +++ b/tests/tests-base/test-00495/stdout.reference @@ -0,0 +1,3 @@ +36C4E268F30C +ICLASS: BLSR CATEGORY: BMI1 EXTENSION: BMI1 IFORM: BLSR_VGPR32d_MEMd ISA_SET: BMI1 +SHORT: blsr edx, dword ptr ss:[si] diff --git a/tests/tests-base/test-00496/cmd b/tests/tests-base/test-00496/cmd new file mode 100644 index 0000000..7cd066e --- /dev/null +++ b/tests/tests-base/test-00496/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -d 65 C4 E3 7B F0 BC 35 79 4A B6 0D 67 diff --git a/tests/tests-base/test-00496/codes b/tests/tests-base/test-00496/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00496/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00496/retcode.reference b/tests/tests-base/test-00496/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00496/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00496/stderr.reference b/tests/tests-base/test-00496/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00496/stdout.reference b/tests/tests-base/test-00496/stdout.reference new file mode 100644 index 0000000..8c6e02e --- /dev/null +++ b/tests/tests-base/test-00496/stdout.reference @@ -0,0 +1,3 @@ +65C4E37BF0BC35794AB60D67 +ICLASS: RORX CATEGORY: BMI2 EXTENSION: BMI2 IFORM: RORX_VGPR32d_MEMd_IMMb ISA_SET: BMI2 +SHORT: rorx edi, dword ptr gs:[ebp+esi*1+0xdb64a79], 0x67 diff --git a/tests/tests-base/test-00497/cmd b/tests/tests-base/test-00497/cmd new file mode 100644 index 0000000..0dd410a --- /dev/null +++ b/tests/tests-base/test-00497/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -32 -d 65 C4 E3 FB F0 BC 35 79 4A B6 0D 67 diff --git a/tests/tests-base/test-00497/codes b/tests/tests-base/test-00497/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00497/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00497/retcode.reference b/tests/tests-base/test-00497/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00497/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00497/stderr.reference b/tests/tests-base/test-00497/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00497/stdout.reference b/tests/tests-base/test-00497/stdout.reference new file mode 100644 index 0000000..9b5f6b8 --- /dev/null +++ b/tests/tests-base/test-00497/stdout.reference @@ -0,0 +1,3 @@ +65C4E3FBF0BC35794AB60D67 +ICLASS: RORX CATEGORY: BMI2 EXTENSION: BMI2 IFORM: RORX_VGPR32d_MEMd_IMMb ISA_SET: BMI2 +SHORT: rorx edi, dword ptr gs:[ebp+esi*1+0xdb64a79], 0x67 diff --git a/tests/tests-base/test-00498/cmd b/tests/tests-base/test-00498/cmd new file mode 100644 index 0000000..b0e91ff --- /dev/null +++ b/tests/tests-base/test-00498/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 65 C4 E3 7B F0 BC 35 79 4A B6 0D 67 diff --git a/tests/tests-base/test-00498/codes b/tests/tests-base/test-00498/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00498/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00498/retcode.reference b/tests/tests-base/test-00498/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00498/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00498/stderr.reference b/tests/tests-base/test-00498/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00498/stdout.reference b/tests/tests-base/test-00498/stdout.reference new file mode 100644 index 0000000..54def5f --- /dev/null +++ b/tests/tests-base/test-00498/stdout.reference @@ -0,0 +1,3 @@ +65C4E37BF0BC35794AB60D67 +ICLASS: RORX CATEGORY: BMI2 EXTENSION: BMI2 IFORM: RORX_VGPR32d_MEMd_IMMb ISA_SET: BMI2 +SHORT: rorx edi, dword ptr gs:[rbp+rsi*1+0xdb64a79], 0x67 diff --git a/tests/tests-base/test-00499/cmd b/tests/tests-base/test-00499/cmd new file mode 100644 index 0000000..98614e1 --- /dev/null +++ b/tests/tests-base/test-00499/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 65 C4 E3 FB F0 BC 35 79 4A B6 0D 67 diff --git a/tests/tests-base/test-00499/codes b/tests/tests-base/test-00499/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00499/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00499/retcode.reference b/tests/tests-base/test-00499/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00499/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00499/stderr.reference b/tests/tests-base/test-00499/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00499/stdout.reference b/tests/tests-base/test-00499/stdout.reference new file mode 100644 index 0000000..10da926 --- /dev/null +++ b/tests/tests-base/test-00499/stdout.reference @@ -0,0 +1,3 @@ +65C4E3FBF0BC35794AB60D67 +ICLASS: RORX CATEGORY: BMI2 EXTENSION: BMI2 IFORM: RORX_VGPR64q_MEMq_IMMb ISA_SET: BMI2 +SHORT: rorx rdi, qword ptr gs:[rbp+rsi*1+0xdb64a79], 0x67 diff --git a/tests/tests-base/test-00500/cmd b/tests/tests-base/test-00500/cmd new file mode 100644 index 0000000..6cd8b92 --- /dev/null +++ b/tests/tests-base/test-00500/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex-cpuid f3 0f bc 00 diff --git a/tests/tests-base/test-00500/codes b/tests/tests-base/test-00500/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00500/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00500/retcode.reference b/tests/tests-base/test-00500/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00500/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00500/stderr.reference b/tests/tests-base/test-00500/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00500/stdout.reference b/tests/tests-base/test-00500/stdout.reference new file mode 100644 index 0000000..c6d2cfe --- /dev/null +++ b/tests/tests-base/test-00500/stdout.reference @@ -0,0 +1,2 @@ +PARSING BYTES: f3 0f bc 00 +DISASM tzcnt eax, dword ptr [eax] diff --git a/tests/tests-base/test-00501/cmd b/tests/tests-base/test-00501/cmd new file mode 100644 index 0000000..a4d2a69 --- /dev/null +++ b/tests/tests-base/test-00501/cmd @@ -0,0 +1 @@ + BUILDDIR/xed-ex-cpuid -nobmi f3 0f bc 00 diff --git a/tests/tests-base/test-00501/codes b/tests/tests-base/test-00501/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00501/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00501/retcode.reference b/tests/tests-base/test-00501/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00501/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00501/stderr.reference b/tests/tests-base/test-00501/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00501/stdout.reference b/tests/tests-base/test-00501/stdout.reference new file mode 100644 index 0000000..115b697 --- /dev/null +++ b/tests/tests-base/test-00501/stdout.reference @@ -0,0 +1,2 @@ +PARSING BYTES: f3 0f bc 00 +DISASM bsf eax, dword ptr [eax] diff --git a/tests/tests-base/test-00502/cmd b/tests/tests-base/test-00502/cmd new file mode 100644 index 0000000..72be9c2 --- /dev/null +++ b/tests/tests-base/test-00502/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -d c4 e2 b1 92 12 diff --git a/tests/tests-base/test-00502/codes b/tests/tests-base/test-00502/codes new file mode 100644 index 0000000..8b6eb6a --- /dev/null +++ b/tests/tests-base/test-00502/codes @@ -0,0 +1 @@ +DEC AVX diff --git a/tests/tests-base/test-00502/retcode.reference b/tests/tests-base/test-00502/retcode.reference new file mode 100644 index 0000000..d00491f --- /dev/null +++ b/tests/tests-base/test-00502/retcode.reference @@ -0,0 +1 @@ +1 diff --git a/tests/tests-base/test-00502/stderr.reference b/tests/tests-base/test-00502/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00502/stdout.reference b/tests/tests-base/test-00502/stdout.reference new file mode 100644 index 0000000..22bb872 --- /dev/null +++ b/tests/tests-base/test-00502/stdout.reference @@ -0,0 +1,2 @@ +C4E2B19212 +ERROR: GENERAL_ERROR Could not decode at offset: 0x0 PC: 0x0: [C4E2B1921200000000000000000000] diff --git a/tests/tests-base/test-00503/cmd b/tests/tests-base/test-00503/cmd new file mode 100644 index 0000000..8255d51 --- /dev/null +++ b/tests/tests-base/test-00503/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -e JRCXZ 'BRDISP:1E' diff --git a/tests/tests-base/test-00503/codes b/tests/tests-base/test-00503/codes new file mode 100644 index 0000000..0464f53 --- /dev/null +++ b/tests/tests-base/test-00503/codes @@ -0,0 +1 @@ +ENC diff --git a/tests/tests-base/test-00503/retcode.reference b/tests/tests-base/test-00503/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00503/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00503/stderr.reference b/tests/tests-base/test-00503/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00503/stdout.reference b/tests/tests-base/test-00503/stdout.reference new file mode 100644 index 0000000..e10d7fc --- /dev/null +++ b/tests/tests-base/test-00503/stdout.reference @@ -0,0 +1,4 @@ +Request: JRCXZ BRDISP_WIDTH:8, MODE:2, RELBR:0x1e, SMODE:2 +OPERAND ORDER: RELBR +Encodable! E31E +.byte 0xe3,0x1e diff --git a/tests/tests-base/test-00504/cmd b/tests/tests-base/test-00504/cmd new file mode 100644 index 0000000..40f2ec6 --- /dev/null +++ b/tests/tests-base/test-00504/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de e31e diff --git a/tests/tests-base/test-00504/codes b/tests/tests-base/test-00504/codes new file mode 100644 index 0000000..209ec74 --- /dev/null +++ b/tests/tests-base/test-00504/codes @@ -0,0 +1 @@ +DEC ENC diff --git a/tests/tests-base/test-00504/retcode.reference b/tests/tests-base/test-00504/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00504/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00504/stderr.reference b/tests/tests-base/test-00504/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00504/stdout.reference b/tests/tests-base/test-00504/stdout.reference new file mode 100644 index 0000000..ccbc646 --- /dev/null +++ b/tests/tests-base/test-00504/stdout.reference @@ -0,0 +1,5 @@ +E31E +ICLASS: JRCXZ CATEGORY: COND_BR EXTENSION: BASE IFORM: JRCXZ_RELBRb ISA_SET: LONGMODE +SHORT: jrcxz 0x20 +Encodable! E31E +Identical re-encoding diff --git a/tests/tests-base/test-00505/cmd b/tests/tests-base/test-00505/cmd new file mode 100644 index 0000000..faba533 --- /dev/null +++ b/tests/tests-base/test-00505/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d e31e diff --git a/tests/tests-base/test-00505/codes b/tests/tests-base/test-00505/codes new file mode 100644 index 0000000..10759ce --- /dev/null +++ b/tests/tests-base/test-00505/codes @@ -0,0 +1 @@ +DEC diff --git a/tests/tests-base/test-00505/retcode.reference b/tests/tests-base/test-00505/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-base/test-00505/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-base/test-00505/stderr.reference b/tests/tests-base/test-00505/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-base/test-00505/stdout.reference b/tests/tests-base/test-00505/stdout.reference new file mode 100644 index 0000000..00d05ea --- /dev/null +++ b/tests/tests-base/test-00505/stdout.reference @@ -0,0 +1,3 @@ +E31E +ICLASS: JRCXZ CATEGORY: COND_BR EXTENSION: BASE IFORM: JRCXZ_RELBRb ISA_SET: LONGMODE +SHORT: jrcxz 0x20 diff --git a/tests/tests-knc/test-00000/cmd b/tests/tests-knc/test-00000/cmd new file mode 100644 index 0000000..1356624 --- /dev/null +++ b/tests/tests-knc/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62F279081815C0C23200 diff --git a/tests/tests-knc/test-00000/codes b/tests/tests-knc/test-00000/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00000/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00000/retcode.reference b/tests/tests-knc/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00000/stderr.reference b/tests/tests-knc/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00000/stdout.reference b/tests/tests-knc/test-00000/stdout.reference new file mode 100644 index 0000000..f4a5bd7 --- /dev/null +++ b/tests/tests-knc/test-00000/stdout.reference @@ -0,0 +1,5 @@ +62F279081815C0C23200 +ICLASS: VBROADCASTSS CATEGORY: BROADCAST EXTENSION: KNCE IFORM: VBROADCASTSS_ZMMzf32_MASK1mskw_MEMzv ISA_SET: KNCE +SHORT: vbroadcastss zmm2, k0, dword ptr [rip+0x32c2c0] +Encodable! 62F279081815C0C23200 +Identical re-encoding diff --git a/tests/tests-knc/test-00001/cmd b/tests/tests-knc/test-00001/cmd new file mode 100644 index 0000000..c4eb4b3 --- /dev/null +++ b/tests/tests-knc/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 626279585A2588223D00 diff --git a/tests/tests-knc/test-00001/codes b/tests/tests-knc/test-00001/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00001/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00001/retcode.reference b/tests/tests-knc/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00001/stderr.reference b/tests/tests-knc/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00001/stdout.reference b/tests/tests-knc/test-00001/stdout.reference new file mode 100644 index 0000000..4db90c5 --- /dev/null +++ b/tests/tests-knc/test-00001/stdout.reference @@ -0,0 +1,5 @@ +626279585A2588223D00 +ICLASS: VBROADCASTI32X4 CATEGORY: BROADCAST EXTENSION: KNCE IFORM: VBROADCASTI32X4_ZMMzd_MASK1mskw_MEMzv ISA_SET: KNCE +SHORT: vbroadcasti32x4 zmm28, k0, dword ptr [rip+0x3d2288]{sint8} +Encodable! 626279585A2588223D00 +Identical re-encoding diff --git a/tests/tests-knc/test-00002/cmd b/tests/tests-knc/test-00002/cmd new file mode 100644 index 0000000..ace5d7d --- /dev/null +++ b/tests/tests-knc/test-00002/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62F1782B28C1 diff --git a/tests/tests-knc/test-00002/codes b/tests/tests-knc/test-00002/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00002/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00002/retcode.reference b/tests/tests-knc/test-00002/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00002/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00002/stderr.reference b/tests/tests-knc/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00002/stdout.reference b/tests/tests-knc/test-00002/stdout.reference new file mode 100644 index 0000000..3f53fe6 --- /dev/null +++ b/tests/tests-knc/test-00002/stdout.reference @@ -0,0 +1,5 @@ +62F1782B28C1 +ICLASS: VMOVAPS CATEGORY: DATAXFER EXTENSION: KNCE IFORM: VMOVAPS_ZMMzf32_MASK1mskw_ZMMzf32 ISA_SET: KNCE +SHORT: vmovaps zmm0, k3, zmm1{badc} +Encodable! 62F1782B28C1 +Identical re-encoding diff --git a/tests/tests-knc/test-00003/cmd b/tests/tests-knc/test-00003/cmd new file mode 100644 index 0000000..1cdd756 --- /dev/null +++ b/tests/tests-knc/test-00003/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62F17808295C2404 diff --git a/tests/tests-knc/test-00003/codes b/tests/tests-knc/test-00003/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00003/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00003/retcode.reference b/tests/tests-knc/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00003/stderr.reference b/tests/tests-knc/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00003/stdout.reference b/tests/tests-knc/test-00003/stdout.reference new file mode 100644 index 0000000..635c73d --- /dev/null +++ b/tests/tests-knc/test-00003/stdout.reference @@ -0,0 +1,5 @@ +62F17808295C2404 +ICLASS: VMOVAPS CATEGORY: DATAXFER EXTENSION: KNCE IFORM: VMOVAPS_MEMzv_MASK1mskw_ZMMzf32 ISA_SET: KNCE +SHORT: vmovaps ptr [rsp+0x100], k0, zmm3 +Encodable! 62F17808295C2404 +Identical re-encoding diff --git a/tests/tests-knc/test-00004/cmd b/tests/tests-knc/test-00004/cmd new file mode 100644 index 0000000..99f44cb --- /dev/null +++ b/tests/tests-knc/test-00004/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62F2F90AD14598 diff --git a/tests/tests-knc/test-00004/codes b/tests/tests-knc/test-00004/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00004/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00004/retcode.reference b/tests/tests-knc/test-00004/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00004/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00004/stderr.reference b/tests/tests-knc/test-00004/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00004/stdout.reference b/tests/tests-knc/test-00004/stdout.reference new file mode 100644 index 0000000..37d7804 --- /dev/null +++ b/tests/tests-knc/test-00004/stdout.reference @@ -0,0 +1,5 @@ +62F2F90AD14598 +ICLASS: VPACKSTORELPD CATEGORY: DATAXFER EXTENSION: KNCE IFORM: VPACKSTORELPD_MEMzv_MASK1mskw_ZMMzf64 ISA_SET: KNCE +SHORT: vpackstorelpd ptr [rbp-0x340], k2, zmm0 +Encodable! 62F2F90AD14598 +Identical re-encoding diff --git a/tests/tests-knc/test-00005/cmd b/tests/tests-knc/test-00005/cmd new file mode 100644 index 0000000..abafb7c --- /dev/null +++ b/tests/tests-knc/test-00005/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d C4E0687410 diff --git a/tests/tests-knc/test-00005/codes b/tests/tests-knc/test-00005/codes new file mode 100644 index 0000000..38630c4 --- /dev/null +++ b/tests/tests-knc/test-00005/codes @@ -0,0 +1 @@ +DEC KNC diff --git a/tests/tests-knc/test-00005/retcode.reference b/tests/tests-knc/test-00005/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00005/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00005/stderr.reference b/tests/tests-knc/test-00005/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00005/stdout.reference b/tests/tests-knc/test-00005/stdout.reference new file mode 100644 index 0000000..5463c39 --- /dev/null +++ b/tests/tests-knc/test-00005/stdout.reference @@ -0,0 +1,3 @@ +C4E0687410 +ICLASS: JKZD CATEGORY: COND_BR EXTENSION: KNCV IFORM: JKZD_MASKmskw_RELBRb_KNC ISA_SET: KNCJKBR +SHORT: jkzd k2, 0x15 diff --git a/tests/tests-knc/test-00006/cmd b/tests/tests-knc/test-00006/cmd new file mode 100644 index 0000000..d4f9761 --- /dev/null +++ b/tests/tests-knc/test-00006/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62E178082805F6412900 diff --git a/tests/tests-knc/test-00006/codes b/tests/tests-knc/test-00006/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00006/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00006/retcode.reference b/tests/tests-knc/test-00006/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00006/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00006/stderr.reference b/tests/tests-knc/test-00006/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00006/stdout.reference b/tests/tests-knc/test-00006/stdout.reference new file mode 100644 index 0000000..1f409ec --- /dev/null +++ b/tests/tests-knc/test-00006/stdout.reference @@ -0,0 +1,5 @@ +62E178082805F6412900 +ICLASS: VMOVAPS CATEGORY: DATAXFER EXTENSION: KNCE IFORM: VMOVAPS_ZMMzf32_MASK1mskw_MEMzv ISA_SET: KNCE +SHORT: vmovaps zmm16, k0, ptr [rip+0x2941f6] +Encodable! 62E178082805F6412900 +Identical re-encoding diff --git a/tests/tests-knc/test-00007/cmd b/tests/tests-knc/test-00007/cmd new file mode 100644 index 0000000..ae5b7fb --- /dev/null +++ b/tests/tests-knc/test-00007/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de C5F8182D79022900 diff --git a/tests/tests-knc/test-00007/codes b/tests/tests-knc/test-00007/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00007/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00007/retcode.reference b/tests/tests-knc/test-00007/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00007/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00007/stderr.reference b/tests/tests-knc/test-00007/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00007/stdout.reference b/tests/tests-knc/test-00007/stdout.reference new file mode 100644 index 0000000..c9dafad --- /dev/null +++ b/tests/tests-knc/test-00007/stdout.reference @@ -0,0 +1,5 @@ +C5F8182D79022900 +ICLASS: VPREFETCHE0 CATEGORY: PREFETCH EXTENSION: KNC IFORM: VPREFETCHE0_MEMmprefetch ISA_SET: KNCV +SHORT: vprefetche0 ptr [rip+0x290279] +Encodable! C5F8182D79022900 +Identical re-encoding diff --git a/tests/tests-knc/test-00008/cmd b/tests/tests-knc/test-00008/cmd new file mode 100644 index 0000000..60bf723 --- /dev/null +++ b/tests/tests-knc/test-00008/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -d 62B2F98D901CE580136900 diff --git a/tests/tests-knc/test-00008/codes b/tests/tests-knc/test-00008/codes new file mode 100644 index 0000000..38630c4 --- /dev/null +++ b/tests/tests-knc/test-00008/codes @@ -0,0 +1 @@ +DEC KNC diff --git a/tests/tests-knc/test-00008/retcode.reference b/tests/tests-knc/test-00008/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00008/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00008/stderr.reference b/tests/tests-knc/test-00008/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00008/stdout.reference b/tests/tests-knc/test-00008/stdout.reference new file mode 100644 index 0000000..bfcdada --- /dev/null +++ b/tests/tests-knc/test-00008/stdout.reference @@ -0,0 +1,3 @@ +62B2F98D901CE580136900 +ICLASS: VPGATHERDQ CATEGORY: KNC EXTENSION: KNCE IFORM: VPGATHERDQ_ZMMzq_MASK1mskw_MEMzv ISA_SET: KNCE +SHORT: vpgatherdq zmm3, k5, qword ptr [zmm12*8+0x691380]{eh} diff --git a/tests/tests-knc/test-00009/cmd b/tests/tests-knc/test-00009/cmd new file mode 100644 index 0000000..de216b9 --- /dev/null +++ b/tests/tests-knc/test-00009/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 62D2790AA29C950023AE00 diff --git a/tests/tests-knc/test-00009/codes b/tests/tests-knc/test-00009/codes new file mode 100644 index 0000000..6d7871f --- /dev/null +++ b/tests/tests-knc/test-00009/codes @@ -0,0 +1 @@ +DEC ENC KNC diff --git a/tests/tests-knc/test-00009/retcode.reference b/tests/tests-knc/test-00009/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-knc/test-00009/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-knc/test-00009/stderr.reference b/tests/tests-knc/test-00009/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-knc/test-00009/stdout.reference b/tests/tests-knc/test-00009/stdout.reference new file mode 100644 index 0000000..209a70f --- /dev/null +++ b/tests/tests-knc/test-00009/stdout.reference @@ -0,0 +1,5 @@ +62D2790AA29C950023AE00 +ICLASS: VSCATTERDPS CATEGORY: KNC EXTENSION: KNCE IFORM: VSCATTERDPS_MEMzv_MASK1mskw_ZMMzf32 ISA_SET: KNCE +SHORT: vscatterdps dword ptr [r13+zmm2*4+0xae2300], k2, zmm3 +Encodable! 62D2790AA29C950023AE00 +Identical re-encoding diff --git a/tests/tests-xop/test-00000/cmd b/tests/tests-xop/test-00000/cmd new file mode 100644 index 0000000..18ebf5b --- /dev/null +++ b/tests/tests-xop/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e vpshaw xmm7 MEM16:ecx xmm6 diff --git a/tests/tests-xop/test-00000/codes b/tests/tests-xop/test-00000/codes new file mode 100644 index 0000000..7624f09 --- /dev/null +++ b/tests/tests-xop/test-00000/codes @@ -0,0 +1 @@ +ENC AVX XOP diff --git a/tests/tests-xop/test-00000/retcode.reference b/tests/tests-xop/test-00000/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-xop/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-xop/test-00000/stderr.reference b/tests/tests-xop/test-00000/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-xop/test-00000/stdout.reference b/tests/tests-xop/test-00000/stdout.reference new file mode 100644 index 0000000..ea89a8d --- /dev/null +++ b/tests/tests-xop/test-00000/stdout.reference @@ -0,0 +1,4 @@ +Request: VPSHAW EASZ:2, MEM_WIDTH:16, MEM0:xmmword ptr [ECX], MODE:1, REG0:XMM7, REG1:XMM6, SMODE:1 +OPERAND ORDER: REG0 MEM0 REG1 +Encodable! 8FE9489939 +.byte 0x8f,0xe9,0x48,0x99,0x39 diff --git a/tests/tests-xop/test-00001/cmd b/tests/tests-xop/test-00001/cmd new file mode 100644 index 0000000..b9b5ad6 --- /dev/null +++ b/tests/tests-xop/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 8f e9 48 99 39 diff --git a/tests/tests-xop/test-00001/codes b/tests/tests-xop/test-00001/codes new file mode 100644 index 0000000..65341bb --- /dev/null +++ b/tests/tests-xop/test-00001/codes @@ -0,0 +1 @@ +ENC AVX XOP DEC diff --git a/tests/tests-xop/test-00001/retcode.reference b/tests/tests-xop/test-00001/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-xop/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-xop/test-00001/stderr.reference b/tests/tests-xop/test-00001/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-xop/test-00001/stdout.reference b/tests/tests-xop/test-00001/stdout.reference new file mode 100644 index 0000000..f97be71 --- /dev/null +++ b/tests/tests-xop/test-00001/stdout.reference @@ -0,0 +1,5 @@ +8FE9489939 +ICLASS: VPSHAW CATEGORY: XOP EXTENSION: XOP IFORM: VPSHAW_XMMdq_MEMdq_XMMdq ISA_SET: XOP +SHORT: vpshaw xmm7, xmmword ptr [ecx], xmm6 +Encodable! 8FE9489939 +Identical re-encoding diff --git a/tests/tests-xop/test-00002/cmd b/tests/tests-xop/test-00002/cmd new file mode 100644 index 0000000..c9f182d --- /dev/null +++ b/tests/tests-xop/test-00002/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -e vpmadcswd xmm7 xmm1 xmm0 xmm3 diff --git a/tests/tests-xop/test-00002/codes b/tests/tests-xop/test-00002/codes new file mode 100644 index 0000000..7624f09 --- /dev/null +++ b/tests/tests-xop/test-00002/codes @@ -0,0 +1 @@ +ENC AVX XOP diff --git a/tests/tests-xop/test-00002/retcode.reference b/tests/tests-xop/test-00002/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-xop/test-00002/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-xop/test-00002/stderr.reference b/tests/tests-xop/test-00002/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-xop/test-00002/stdout.reference b/tests/tests-xop/test-00002/stdout.reference new file mode 100644 index 0000000..fa22235 --- /dev/null +++ b/tests/tests-xop/test-00002/stdout.reference @@ -0,0 +1,4 @@ +Request: VPMADCSWD MODE:1, REG0:XMM7, REG1:XMM1, REG2:XMM0, REG3:XMM3, SMODE:1 +OPERAND ORDER: REG0 REG1 REG2 REG3 +Encodable! 8FE870B6F830 +.byte 0x8f,0xe8,0x70,0xb6,0xf8,0x30 diff --git a/tests/tests-xop/test-00003/cmd b/tests/tests-xop/test-00003/cmd new file mode 100644 index 0000000..dce2ba5 --- /dev/null +++ b/tests/tests-xop/test-00003/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -de 8FE870B6F830 diff --git a/tests/tests-xop/test-00003/codes b/tests/tests-xop/test-00003/codes new file mode 100644 index 0000000..65341bb --- /dev/null +++ b/tests/tests-xop/test-00003/codes @@ -0,0 +1 @@ +ENC AVX XOP DEC diff --git a/tests/tests-xop/test-00003/retcode.reference b/tests/tests-xop/test-00003/retcode.reference new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/tests-xop/test-00003/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-xop/test-00003/stderr.reference b/tests/tests-xop/test-00003/stderr.reference new file mode 100644 index 0000000..e69de29 diff --git a/tests/tests-xop/test-00003/stdout.reference b/tests/tests-xop/test-00003/stdout.reference new file mode 100644 index 0000000..aaac956 --- /dev/null +++ b/tests/tests-xop/test-00003/stdout.reference @@ -0,0 +1,5 @@ +8FE870B6F830 +ICLASS: VPMADCSWD CATEGORY: XOP EXTENSION: XOP IFORM: VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq ISA_SET: XOP +SHORT: vpmadcswd xmm7, xmm1, xmm0, xmm3 +Encodable! 8FE870B6F830 +Identical re-encoding diff --git a/xed_build_common.py b/xed_build_common.py new file mode 100755 index 0000000..a972f80 --- /dev/null +++ b/xed_build_common.py @@ -0,0 +1,597 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +#Copyright (c) 2004-2015, Intel Corporation. All rights reserved. +# +#Redistribution and use in source and binary forms, with or without +#modification, are permitted provided that the following conditions are +#met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +#"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +#LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +#A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +#OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +#SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +#LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +#DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +#THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +#OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#END_LEGAL + +import sys +import os +import re +import shutil +import copy +import time +import glob +import types +import optparse +import mbuild + +############################################################################ +class xed_exception_t(Exception): + def __init__(self,kind,value,msg=""): + self.kind = kind + self.value = value + self.msg = msg + def __str__(self): + return "KIND: %s VALUE: %d MSG: %s" % (kind, value, msg) + +def handle_exception_and_die(e): + if hasattr(e,'kind'): + if e.kind == 'die': + sys.stderr.write('ABORT: ' + e.msg + '\n') + sys.exit(e.value) + elif e.kind == 'exit': + sys.stderr.write('EXITING\n') + sys.exit(e.value) + else: + print str(e) + sys.exit(1) + +def cdie(s): + raise xed_exception_t("die", 1, s) +def cexit(r=0): + raise xed_exception_t("exit", r) + +def add_to_flags(env,s): + env.add_to_var('CCFLAGS',s) + env.add_to_var('CXXFLAGS',s) + +def compile_with_pin_crt_lin_mac_common_cplusplus(env): + env.add_to_var('LINKFLAGS','-lstlport-dynamic') + env.add_to_var('CXXFLAGS','-fno-exceptions') + env.add_to_var('CXXFLAGS', '-fno-rtti') + +def _compile_with_pin_crt_lin_mac_common(env): + env.add_system_include_dir('%(pin_root)s/extras/stlport/include') + env.add_system_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_system_include_dir('%(pin_root)s/extras/crt/include') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + env.add_to_var('LINKFLAGS','-nostdlib') + env.add_to_var('LINKFLAGS','-lc-dynamic') + env.add_to_var('LINKFLAGS','-lm-dynamic') + env.add_to_var('LINKFLAGS','-L%(pin_crt_dir)s') + + # FIXME: if we ever support kits with Pin CRT, we'll need to copy + # the PINCRT to the XED kit and use a different rpath. + env.add_to_var('example_linkflags','-Wl,-rpath,%(pin_crt_dir)s') + + # -lpin3dwarf FIXME + + if env['shared']: + # when building dynamic libary + env['first_lib'] = '%(pin_crt_dir)s/crtbeginS%(OBJEXT)s' + env['first_example_lib'] = '%(pin_crt_dir)s/crtbegin%(OBJEXT)s' + + _add_to_flags(env,'-funwind-tables') + +def _compile_with_pin_crt_lin(env): + _compile_with_pin_crt_lin_mac_common(env) + env.add_define('TARGET_LINUX') + if env['shared']: + env['last_lib'] = '%(pin_crt_dir)s/crtendS%(OBJEXT)s' + env['last_example_lib'] = '%(pin_crt_dir)s/crtend%(OBJEXT)s' + +def _compile_with_pin_crt_mac(env): + _compile_with_pin_crt_lin_mac_common(env) + env.add_define('TARGET_MAC') + env.add_to_var('LINKFLAGS','-Wl,-no_new_main') + +def _compile_with_pin_crt_win(env): + env.add_include_dir('%(pin_root)s/extras/stlport/include') + env.add_include_dir('%(pin_root)s/extras') + env.add_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_include_dir('%(pin_root)s/extras/crt/include') + env.add_include_dir('%(pin_root)s/extras/crt') + env.add_include_dir('%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + env.add_to_var('LINKFLAGS','/NODEFAULTLIB') + env.add_to_var('LINKFLAGS','stlport-static.lib') + env.add_to_var('LINKFLAGS','m-static.lib') + env.add_to_var('LINKFLAGS','c-static.lib') + env.add_to_var('LINKFLAGS','os-apis.lib') + env.add_to_var('LINKFLAGS','ntdll-%(arch)s.lib') + env.add_to_var('LINKFLAGS','/IGNORE:4210') + env.add_to_var('LINKFLAGS','/IGNORE:4049') + env.add_to_var('LINKFLAGS','/LIBPATH:%(pin_crt_dir)s') + env.add_to_var('LINKFLAGS','/LIBPATH:%(pin_root)s/%(pin_arch)s/lib-ext') + + # for DLLs + if env['shared']: + env['first_lib'] = '%(pin_crt_dir)s/crtbeginS%(OBJEXT)s' + + # for EXEs + env['first_example_lib'] = '%(pin_crt_dir)s/crtbegin%(OBJEXT)s' + + _add_to_flags(env,'/GR-') + _add_to_flags(env,'/GS-') + + env['original_windows_h_path'] = mbuild.join( + os.environ['WindowsSdkDir'], 'Include','um') + env.add_define('_WINDOWS_H_PATH_="%(original_windows_h_path)s"') + _add_to_flags(env,'/FIinclude/msvc_compat.h') + env.add_define('TARGET_WINDOWS') + +def _compile_with_pin_crt(env): + if env['arch'] == '32': + env['pin_arch'] = 'ia32' + env['bionic_arch'] = 'x86' + env.add_define('TARGET_IA32') + else: + env['pin_arch'] = 'intel64' + env['bionic_arch'] = 'x86_64' + env.add_define('TARGET_IA32E') + + env['pin_root'] = env['pin_crt'] + env['pin_crt_dir'] = '%(pin_root)s/%(pin_arch)s/runtime/pincrt' + env.add_define('__PIN__=1') + env.add_define('PIN_CRT=1') + + env.add_include_dir('%(pin_root)s/extras/stlport/include') + env.add_include_dir('%(pin_root)s/extras') + env.add_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_include_dir('%(pin_root)s/extras/crt/include') + env.add_include_dir('%(pin_root)s/extras/crt') + env.add_include_dir('%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + if get_arch(env) == '32': + env.add_define('__i386__') + else: + env.add_define('__LP64__') + + if env.on_linux(): + _compile_with_pin_crt_lin(env) + elif env.on_mac(): + _compile_with_pin_crt_mac(env) + elif env.on_windows(): + _compile_with_pin_crt_win(env) + +def _greater_than_gcc(env,amaj,amin,aver): + gcc = env.expand('%(CC)s') + vstr = mbuild.get_gcc_version(gcc) + mbuild.msgb("GCC VERSION", vstr) + try: + (vmaj, vmin, vver) = vstr.split('.') + except: + return False + if vmaj > amaj: + return True + if vmaj == amaj and vmin > amin: + return True + if vmaj == amaj and vmin == amin and vver >= aver: + return True + return False + +def set_env_gnu(env): + """Example of setting up the GNU GCC environment for compilation""" + env['LINK'] = env['CC'] + + flags = '' + + #coverage testing using the local compiler + #flags += ' -fprofile-arcs -ftest-coverage' + #env['LIBS'] += ' -lgcov' + + flags += ' -Wall' + + # 2014-06-23: tried out address sanitizer. it did not find any + # issues. + if 0: + address_santizer = ' -fsanitize=address -g' + flags += address_santizer + env['LINKFLAGS'] += address_santizer + + if env['use_werror']: + flags += ' -Werror' + if env['compiler'] != 'icc': + flags += ' -Wno-long-long' + flags += ' -Wno-unknown-pragmas' + flags += ' -fmessage-length=0' + flags += ' -pipe' + + # -pg is incompatible with -fomit-frame-pointer + if (re.search(r' -pg', env['CXXFLAGS']) == None and + re.search(r' -pg', env['CCFLAGS']) == None and + (env['compiler'] != 'icc' or env['icc_version'] not in ['7','8'])): + flags += ' -fomit-frame-pointer' + + if env['compiler'] != 'icc' or (env['compiler'] == 'icc' and + env['icc_version'] != '7'): + flags += ' -fno-exceptions' + + # required for gcc421 xcode (I have v 3.2.5) to avoid + # undefined symbols when linking tools. + if env.on_mac(): + flags += ' -fno-common' + + if env['build_os'] == 'win': + # gcc3.4.4 on windows has problems with %x for xed_int32_t. + flags += ' -Wno-format' + + if env['compiler'] != 'icc': + # c99 is required for c++ style comments. + env['CSTD'] = 'c99' + env['CCFLAGS'] += ' -std=%(CSTD)s ' + if env['pedantic']: + env['CCFLAGS'] += ' -pedantic ' + + if env['shared']: + if not env.on_windows(): + # -fvisibility=hidden only works on gcc>4. If not gcc, + # assume it works. Really only a problem for older icc + # compilers. + _greater_than_gcc(env,4,0,0) + if env['compiler'] != 'gcc' or _greater_than_gcc(env,4,0,0): + hidden = ' -fvisibility=hidden' + env['LINKFLAGS'] += hidden + flags += hidden + + env['CCFLAGS'] += flags + env['CCFLAGS'] += ' -Wstrict-prototypes' + env['CCFLAGS'] += ' -Wwrite-strings' + if env['compiler'] != 'icc': + env['CCFLAGS'] += ' -Wredundant-decls' + + # Disabled the following. Generates too many silly errors/warnings + #env['CCFLAGS'] += ' -Wmissing-prototypes' + + env['CXXFLAGS'] += flags + +def set_env_clang(env): + set_env_gnu(env) + +def set_env_ms(env): + """Set up the MSVS environment for compilation""" + flags = '' + cxxflags = '' + if env['clr']: + flags += ' /TP /clr ' + # linker fail suggested libcmt was a problem for CLR. 2007-07-17 + env['LINKFLAGS'] += ' /NODEFAULTLIB:libcmt' + + # remove dead code from executable + env['LINKFLAGS'] += ' /OPT:REF /OPT:ICF=3' + + # enable security features + if env['msvs_version'] and int(env['msvs_version']) >= 8: # MSVS2005 + env.add_to_var('LINKFLAGS','/NXCOMPAT') + env.add_to_var('LINKFLAGS','/DYNAMICBASE') + + + if env['msvs_version'] == '6': + flags += ' /w' # disable warnings + else: + #cxxflags += ' /wd4530'# disable warning on unhandled exceptions + #flags += ' /wd4214' # disable /W4 warning on nonstd typed-bitfields + if not env['clr']: + cxxflags += ' /EHsc' # use windows exceptions + if not env['clr']: + cxxflags += ' /GR-' # do not use RTTI + if env['msvs_version'] != '6': + flags += ' /W4' # Maximum warning level. + flags += ' /WX' # Warnings as errors. + flags += ' /wd4091' # disable dbghelp.h warning in msvs2015 + # Disable warnings about conditional expression is constant + # used by xed_assert()'s "while(0)" and + # a few other "if (1)..." things. + flags += ' /wd4127' + flags += ' /wd4505' # Disable warnings about unused functions. + flags += ' /wd4702' # Disable warnings about unreachable code + # (shows up in generated code). FIXME + flags += ' /wd4244' # Disable warnings about changing widths. + # Disable warnings about compiler limit in MSVC7(.NET / 2003) + flags += ' /wd4292' + + # /Zm200 is required on VC98 for xed-decode.cpp to avoid + # internal compiler error + #flags += ' /Zm200' + env['CCFLAGS'] += flags + env['CXXFLAGS'] += cxxflags + " " + flags + +def intel_compiler_disables(env): + """Return a comma separated string of compile warning number disables + for ICC/ICL.""" + disables = [] + disables.append( 810 ) # loss of precision + # value copied to temporary, reference to temporary used. + disables.append( 383 ) + disables.append( 108 ) # signed bit fields of 1 bit length + disables.append( 111 ) # statement is unreachable + disables.append( 1419 ) # external declaration in primary source file + disables.append( 981 ) # operands are evaluated in unspecified order + if env['icc_version'] != '7': + # function "strncat" or "strcpy" (etc.) was declared + # "deprecated" # NOT ON ECL7 + disables.append( 1478 ) + disables.append( 188 ) # enumerated type mixed with another type + disables.append( 310 ) # old-style parameter list (anachronism) + disables.append( 592 ) # variable "c" is used before its value is set + disables.append( 1418 ) # external definition with no prior declaration + disables.append( 186 ) # pointless comparison of unsigned integer with zero + disables.append( 279 ) # controlling expression is constant + disables.append( 128 ) # loop is not reachable from preceding code + disables.append( 177 ) # function was declared but never referenced + + # Explicit conversion of a 64-bit integral type to a smaller integral type. + #disables.append( 1683 ) + + if env['icc_version'] not in ['7','8','9']: + # non-pointer conversion/lose significant bits, ICL11 + disables.append( 2259 ) + return ",".join(map(str,disables)) + +def set_env_icc(env): + set_env_gnu(env) + env['CCFLAGS'] += ' -wd' + intel_compiler_disables(env) + env['CXXFLAGS'] += ' -wd' + intel_compiler_disables(env) + +def set_env_icl(env): + set_env_ms(env) + env['CCFLAGS'] += ' /Qwd' + intel_compiler_disables(env) + env['CXXFLAGS'] += ' /Qwd' + intel_compiler_disables(env) + +########################################################################### + +def xed_remove_files_glob(env): + """Clean up""" + mbuild.msgb("CLEANING") + try: + if 'build_dir' in env: + path = env['build_dir'] + if path != '.' and path != '..': + mbuild.remove_tree(path) + return + except: + cdie("clean failed") + +########################################################################### + + +def set_xed_defaults(env): + """External entry point: Users must call set_xed_defaults() or + xed_args(). This post-processes the environment""" + env.process_user_settings() + +def init_once(env): + p = os.path.join(env['src_dir'], 'scripts') + if os.path.exists(p): + sys.path.insert(0, p) + +def init(env): + # we make the python command contingent upon the mfile itself to catch + # build changes. + env['mfile'] = env.src_dir_join('mfile.py') + env['arch'] = get_arch(env) + + if env['compiler'] == 'gnu': + set_env_gnu(env) + elif env['compiler'] == 'clang': + set_env_clang(env) + elif env['compiler'] == 'ms': + set_env_ms(env) + elif env['compiler'] == 'icc': + set_env_icc(env) + elif env['compiler'] == 'icl': + set_env_icl(env) + else: + cdie("Unknown compiler: " + env['compiler']) + + if env['pin_crt']: + _compile_with_pin_crt(env) + + if env['xed_messages']: + env.add_define('XED_MESSAGES') + if env['xed_asserts']: + env.add_define("XED_ASSERTS") + +def strip_file(env,fn,options=''): + if env.on_windows(): + return + fne = env.expand(fn) + mbuild.msgb("STRIPPING", fne) + strip_cmd = " ".join([env['strip'], options, fne]) + mbuild.msgb("STRIP CMD", strip_cmd) + (retcode,stdout,stderr) = mbuild.run_command(strip_cmd) + if retcode != 0: + dump_lines("strip stdout", stdout) + dump_lines("strip stderr", stderr) + cdie("Could not strip " + fne) + +def src_dir_join(env, lst): + return map(lambda x: mbuild.join(env['src_dir'],'src',x), lst) + +def build_dir_join(env, lst): + return map(lambda x: mbuild.join(env['build_dir'],x), lst) + +def make_lib_dll(env,base): + """Return the static or link lib and shared-lib name. For a given + base we return base.lib and base.dll on windows. base.so and + base.so on non-windows. Users link against the link lib.""" + + dll = env.shared_lib_name(base) + static_lib = env.static_lib_name(base) + + if env['shared']: + if env.on_windows(): + link_lib = static_lib + else: + link_lib = dll + else: + link_lib = static_lib + + return link_lib, dll + +def _xed_lib_dir_join(env, s): + return mbuild.join(env['xed_lib_dir'],s) + +def get_libxed_names(env,work_queue): + libxed_lib, libxed_dll = make_lib_dll(env,'xed') + env['link_libxed'] = _xed_lib_dir_join(env,libxed_lib) + env['shd_libxed'] = _xed_lib_dir_join(env,libxed_dll) + + lib,dll = make_lib_dll(env,'xed-ild') + env['link_libild'] = _xed_lib_dir_join(env,lib) + env['shd_libild'] = _xed_lib_dir_join(env,dll) + +def installing(env): + if 'install' in env['targets'] or 'zip' in env['targets']: + return True + return False + +def _modify_search_path_mac(env, fn): + """Make example tools refer to the libxed.so from the lib directory + if doing and install. Mac only.""" + if not env['shared']: + return + if not env.on_mac(): + return + if not installing(env): + return + env['odll'] = '%(build_dir)s/libxed.dylib' + env['ndll'] = '"@loader_path/../lib/libxed.dylib"' + cmd = 'install_name_tool -change %(odll)s %(ndll)s ' + fn + cmd = env.expand(cmd) + env['odll'] = None + env['ndll'] = None + + mbuild.msgb("SHDOBJ SEARCH PATH", cmd) + (retcode,stdout,stderr) = mbuild.run_command(cmd) + if retcode != 0: + dump_lines("install_name_tool stdout", stdout) + dump_lines("install_name_tool stderr", stderr) + cdie("Could not modify dll path: " + cmd) + + +def get_arch(env): + if env['host_cpu'] == 'ia32': + arch = '32' + else: + arch = '64' + return arch + + +def dump_lines(s,lines): + if lines: + print "========" + print s + ":" + for line in lines: + print line.strip() + print "========" + + +def prep(env): + mbuild.msgb("PYTHON VERSION", "%d.%d.%d" % + (mbuild.get_python_version_tuple())) + + +########################################################################### +# ELF/DWARF (linux only) + +def _use_elf_dwarf(env): + """Do not call this directly. See cond_add_elf_dwarf. Tell the + build we want to use libelf and libdwarf. Some systems have these + libraries installed and this is sufficient for those systems.""" + + env['LIBS'] += ' -lelf' + env.add_define('XED_DWARF') + env['LIBS'] += ' -ldwarf' + +def _add_elf_dwarf_precompiled(env): + """Do not call this directly. See cond_add_elf_dwarf. Set up to + use our precompiled libelf/libdwarf. """ + + # not using src_dir here because examples have different src_dir + env.add_include_dir('%(xed_dir)s/external/include') + env.add_include_dir('%(xed_dir)s/external/include/libelf') + + env['extern_lib_dir'] = '%(xed_dir)s/external/lin/lib%(arch)s' + + env['libdwarf'] = '%(extern_lib_dir)s/libdwarf.so' + env['libelf'] = env.expand('%(extern_lib_dir)s/libelf.so.0.8.13') + env['libelf_symlink'] = 'libelf.so.0' + env['libelf_license'] = env.expand('%(extern_lib_dir)s/EXTLICENSE.txt') + if env.on_freebsd(): + env['LINKFLAGS'] += " -Wl,-z,origin" + + env['LINKFLAGS'] += " -L%(extern_lib_dir)s" + if installing(env): + env['LINKFLAGS'] += " -Wl,-rpath,'$ORIGIN/../extlib'" + else: + # this case is a little ambiguous. If not making a kit we + # just use a full path to the source tree. + p = os.path.abspath(env.expand("%(extern_lib_dir)s")) + env['LINKFLAGS'] += " -Wl,-rpath," + p + + env['ext_libs' ].append(env['libelf']) + env['ext_libs' ].append(env['libdwarf']) + +def cond_add_elf_dwarf(env): + "Set up for using libelf/libdwarf on linux." + + if 'ext_libs' not in env: + env['ext_libs'] = [] + + if env['use_elf_dwarf']: + if not env.on_linux(): + die("No libelf/dwarf for this platform") + else: + return + + mbuild.msgb("ADDING ELF/DWARF") + # set up the preprocessor define and linker requirements. + _use_elf_dwarf(env) + + if not env['use_elf_dwarf_precompiled']: + # presumably the user is supplying their own & setting rpaths, etc. + return + mbuild.msgb("ADDING ELF/DWARF PRECOMPILED") + _add_elf_dwarf_precompiled(env) + +# +########################################################################### diff --git a/xed_mbuild.py b/xed_mbuild.py new file mode 100755 index 0000000..6921594 --- /dev/null +++ b/xed_mbuild.py @@ -0,0 +1,2149 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2016 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +############################################################################ +#See the execute() and work() functions down at the bottom of the file +#for the main routine. +############################################################################ + +## START OF IMPORTS SETUP +import sys +import os +import re +import shutil +import copy +import time +import glob +import types +import optparse +import collections + +def _fatal(m): + sys.stderr.write("\n\nXED ERROR: %s\n\n" % (m) ) + sys.exit(1) + +try: + import mbuild +except: + _fatal("xed_mbuild.py could not find/import mbuild." + + " Should be a sibling of the xed directory.") +try: + import xed_build_common as xbc +except: + _fatal("xed_mbuild.py could not import xed_build_common.py") + + +## END OF IMPORTS SETUP +############################################################################ + +def aq(s): + t = mbuild.cond_add_quotes(s) + return t + +def check_mbuild_file(mbuild_file, sig_file): + if os.path.exists(sig_file): + old_hash = file(sig_file).readline().strip() + else: + old_hash = '' + hash = mbuild.hash_list(file(sys.argv[0]).readlines()) + f = open(sig_file, 'w') + f.write(hash) + f.close() + + if hash == old_hash: + retval = False + mbuild.msgb("MBUILD INPUT FILE", "does not appear to have changes.") + else: + retval = True + mbuild.msgb("MBUILD INPUT FILE", "appears to have changes.") + return retval + +def _write_file(fn, stream): + """Write stream to fn""" + mbuild.msgb("WRITING", fn) + f = open(fn,'w') + f.writelines(stream) + f.close() + +########################################################################### +# generators + +class generator_inputs_t(object): + def __init__(self, build_dir, + amd_enabled=True, + limit_strings=False): + self.fields = ['dec-spine', + 'dec-instructions', + 'enc-instructions', + 'dec-patterns', + 'enc-patterns', + 'enc-dec-patterns', # decode patterns used for encode + 'fields', + 'state', + 'registers', + 'widths', + 'extra-widths', + 'pointer-names', + 'element-types', + 'element-type-base', + 'chip-models', + 'conversion-table', + 'ild-scanners', + 'ild-getters', + 'cpuid' + ] + self.files = {} # lists of input files per field type + self.priority = {} # field type -> int + + # output file names. We concatenate all the input files of a + # given type. These get used in the command are internal to the + # execution of the generator. + self.file_name = {} + for fld in self.fields: + self.files[fld] = [] # list of input files + self.file_name[fld] = 'all-' + fld + '.txt' + + self.renamed = False + self.intermediate_dir = None + self.set_intermediate_dir(build_dir) + self.use_intermediate_files() + self.amd_enabled = amd_enabled + self.limit_strings = limit_strings + + def add_file(self, file_type, file_name, priority=1): + """Add a specific type of file to the right list""" + + curp = 1 + if file_type in self.priority: + curp = self.priority[file_type] + + if curp > priority: + mbuild.msgb("Skipping low priority file for type %s: %s" % + (file_type, file_name)) + return + elif curp < priority: + # new higher priority file blows away the list of files for + # this file type. + mbuild.msgb("Clearing file list for type %s: [ %s ]" % + (file_type, + ", ".join(self.files[file_type]))) + self.files[file_type] = [] + self.priority[file_type]=priority + + if file_name in self.files[file_type]: + xbc.cdie('duplicate line: {}:{}'.format(file_type,file_name)) + self.files[file_type].append(file_name) + + def remove_file(self, file_type, file_name): + """Remove a specific file""" + try: + self.files[file_type].remove(file_name) + except: + xbc.cdie("Invalid type of file " + + "(%s) or file name (%s) not found: " % (file_type, + file_name) ) + + def clear_files(self,file_type): + """Remove a specific type of file""" + try: + self.files[file_type] = [] + mbuild.msgb("REMOVING FILE TYPE", file_type) + except: + xbc.cdie("Invalid type of file (%s) not found: " % + (file_type)) + + def all_input_files(self): + """Return a list of all the input file names so we can hook up + the dependences""" + fnames = [] + for flist in self.files.itervalues(): + fnames.extend(flist) + return fnames + + def set_intermediate_dir(self, build_dir): + self.intermediate_dir = mbuild.join(build_dir,'dgen') + mbuild.cmkdir(self.intermediate_dir) + + def use_intermediate_files(self): + """Prefix al the files by the intermediate directory name""" + # just do this once + if self.renamed: + return + self.renamed = True + + for f in self.fields: + ofn = mbuild.join(self.intermediate_dir,self.file_name[f]) + self.file_name[f] = ofn # update file name-- only call once! + + def concatenate_input_files(self,env): + """Concatenate all the files of each type""" + for f in self.fields: + self.concatenate_one_set_of_files(env, + self.file_name[f], + self.files[f]) + + def decode_command(self, xedsrc, extra_args=None, on_windows=False): + """Produce a decoder generator command""" + s = [] + s.append( '%(pythonarg)s' ) + # s.append("-3") # python3.0 compliance checking using python2.6 + s.append(aq(mbuild.join(xedsrc,'pysrc','generator.py'))) + if self.limit_strings: + s.append('--limit-enum-strings') + s.append('--spine ' + aq(self.file_name['dec-spine'])) + s.append('--isa ' + aq(self.file_name['dec-instructions'])) + s.append('--patterns ' + aq(self.file_name['dec-patterns'])) + s.append('--input-fields ' + aq(self.file_name['fields'])) + s.append('--input-state ' + aq(self.file_name['state'])) + s.append('--chip-models ' + aq(self.file_name['chip-models'])) + s.append('--ctables ' + aq(self.file_name['conversion-table'])) + s.append('--input-regs ' + aq(self.file_name['registers'])) + s.append('--input-widths ' + aq(self.file_name['widths'])) + s.append('--input-extra-widths ' + + aq(self.file_name['extra-widths'])) + s.append('--input-element-types ' + + aq(self.file_name['element-types'])) + s.append('--input-element-type-base ' + + aq(self.file_name['element-type-base'])) + s.append('--input-pointer-names ' + + aq(self.file_name['pointer-names'])) + s.append('--ild-scanners ' + + aq(self.file_name['ild-scanners'])) + s.append('--cpuid ' + + aq(self.file_name['cpuid'])) + if len(self.files['ild-getters']) > 0: + s.append('--ild-getters ' + + aq(self.file_name['ild-getters'])) + if extra_args: + s.append(extra_args) + return ' '.join(s) + + def encode_command(self, xedsrc, extra_args=None, on_windows=False, amd_enabled=True): + """Produce a decoder generator command""" + s = [] + s.append( '%(pythonarg)s' ) + # s.append("-3") # python3.0 compliance checking using python2.6 + s.append( aq(mbuild.join(xedsrc,'pysrc', 'read-encfile.py'))) + s.append('--isa %s' % aq(self.file_name['enc-instructions'])) + s.append('--enc-patterns %s' % aq(self.file_name['enc-patterns'])) + s.append('--enc-dec-patterns %s' % + aq(self.file_name['enc-dec-patterns'])) + s.append('--input-fields %s' % aq(self.file_name['fields'])) + s.append('--input-state %s' % aq(self.file_name['state'])) + s.append('--input-regs %s' % aq(self.file_name['registers'])) + if not amd_enabled: + s.append('--no-amd') + if extra_args: + s.append( extra_args) + return ' '.join(s) + + def concatenate_one_set_of_files(self, env, target, inputs): + """Concatenate input files creating the target file.""" + try: + mbuild.msgb("CONCAT", "%s <-\n\t\t%s" % (target , + '\n\t\t'.join(inputs))) + output = open(target,"w") + for f in inputs: + if os.path.exists(f): + output.write("\n\n###FILE: %s\n\n" % (f)) + for line in file(f).readlines(): + line = line.rstrip() + #replace the possible symbolic path %(cur_dir)s + #FIXME: could have used env's expand_string method, + #for src_dir and cur_dir. + file_dir = os.path.dirname(f) + line = line.replace('%(cur_dir)s', file_dir) + line = line.replace('%(xed_dir)s', env['src_dir']) + output.write(line + "\n") + else: + xbc.cdie("Could not read input file: " + f) + output.close() + except xbc.xed_exception_t as e: + raise # re-raise exception + except: + xbc.cdie("Could not write file %s from inputs: %s" % + ( target, ', '.join(inputs))) + +def run_generator_preparation(gc, env): + """Prepare to run the encode and decode table generators""" + if env == None: + return (1, ['no env!']) + + xedsrc = env['src_dir'] + build_dir = env['build_dir'] + gc.concatenate_input_files(env) + + mbuild.touch(env.build_dir_join('dummy-prep')) + return (0, [] ) + +def read_file_list(fn): + a = [] + for f in file(fn).readlines(): + a.append(f.rstrip()) + return a + +def run_decode_generator(gc, env): + """Run the decode table generator""" + if env == None: + return (1, ['no env!']) + + xedsrc = env.escape_string(env['src_dir']) + build_dir = env.escape_string(env['build_dir']) + debug = "" + other_args = " ".join(env['generator_options']) + gen_extra_args = "--gendir %s --xeddir %s %s %s" % (build_dir, + xedsrc, debug, + other_args) + if env['gen_ild_storage']: + gen_extra_args += ' --gen-ild-storage' + + if env['compress_operands']: + gen_extra_args += " --compress-operands" + + cmd = env.expand_string(gc.decode_command(xedsrc, + gen_extra_args, + env.on_windows())) + + if mbuild.verbose(2): + mbuild.msgb("DEC-GEN", cmd) + (retval, output, error_output) = mbuild.run_command(cmd, + separate_stderr=True) + oo = env.build_dir_join('DEC-OUT.txt') + oe = env.build_dir_join('DEC-ERR.txt') + _write_file(oo, output) + _write_file(oe, error_output) + + if retval == 0: + list_of_files = read_file_list(gc.dec_output_file) + mbuild.hash_files(list_of_files, + env.build_dir_join(".mbuild.hash.xeddecgen")) + + mbuild.msgb("DEC-GEN", "Return code: " + str(retval)) + return (retval, error_output ) + +def run_encode_generator(gc, env): + """Run the encoder table generator""" + if env == None: + return (1, ['no env!']) + + xedsrc = env.escape_string(env['src_dir']) + build_dir = env.escape_string(env['build_dir']) + + gen_extra_args = "--gendir %s --xeddir %s" % (build_dir, xedsrc) + cmd = env.expand_string(gc.encode_command(xedsrc, + gen_extra_args, + env.on_windows(), + env['amd_enabled'])) + if mbuild.verbose(2): + mbuild.msgb("ENC-GEN", cmd) + (retval, output, error_output) = mbuild.run_command(cmd, + separate_stderr=True) + oo = env.build_dir_join('ENC-OUT.txt') + oe = env.build_dir_join('ENC-ERR.txt') + _write_file(oo, output) + _write_file(oe, error_output) + + if retval == 0: + list_of_files = read_file_list(gc.enc_output_file) + mbuild.hash_files(list_of_files, + env.build_dir_join(".mbuild.hash.xedencgen")) + + mbuild.msgb("ENC-GEN", "Return code: " + str(retval)) + return (retval, [] ) + +def need_to_rebuild(fn,sigfile): + rebuild = False + if not os.path.exists(fn): + return True + + list_of_files = read_file_list(fn) + if mbuild.file_hashes_are_valid(list_of_files, sigfile): + return False + return True + +########################################################################### +# legal header tagging + +def legal_header_tagging(env): + if 'apply-header' not in env['targets']: + return + + public_source_files = [ + mbuild.join(env['src_dir'],'include', 'public', '*.h'), + mbuild.join(env['src_dir'],'examples','*.cpp'), + mbuild.join(env['src_dir'],'examples','*.c'), + mbuild.join(env['src_dir'],'examples','*.[hH]'), + mbuild.join(mbuild.join(env['build_dir'],'*.h')) ] + + private_source_files = [ + mbuild.join(env['src_dir'],'src','*.c'), + mbuild.join(env['src_dir'],'include', 'private','*.h') ] + + private_data_files = [ + mbuild.join(env['src_dir'],'scripts','*.py'), + mbuild.join(env['src_dir'],'pysrc','*.py')] + + # find and classify the files in datafiles directories + for root,dirs,files in os.walk( mbuild.join(env['src_dir'],'datafiles') ): + for f in files : + fn = mbuild.join(root,f) + if 'test' not in fn: + if re.search(r'[~]$',fn): + # skip backup files + continue + elif re.search(r'[.][ch]$',fn): + private_source_files.append(fn) + else: + private_data_files.append(fn) + + if env.on_windows(): + xbc.cdie("ERROR","TAGGING THE IN-USE PYTHON FILES DOES " + + "NOT WORK ON WINDOWS.") + + legal_header = file(mbuild.join(env['src_dir'],'misc', + 'apache-header.txt')).readlines() + header_tag_files(env,public_source_files, legal_header, + script_files=False) + header_tag_files(env,private_source_files, legal_header, + script_files=False) + header_tag_files(env, private_data_files, legal_header, + script_files=True) + mbuild.msgb("STOPPING", "after %s" % 'header tagging') + xbc.cexit(0) + +def header_tag_files(env, files, legal_header, script_files=False): + """Apply the legal_header to the list of files""" + try: + import apply_legal_header + except: + xbc.cdie("XED ERROR: mfile.py could not find scripts directory") + + for g in files: + print "G: ", g + for f in glob.glob(g): + print "F: ", f + if script_files: + apply_legal_header.apply_header_to_data_file(legal_header, f) + else: + apply_legal_header.apply_header_to_source_file(legal_header, f) +########################################################################### +# Doxygen build + +def doxygen_subs(env,api_ref=True): + subs = {} + subs['XED_TOPSRCDIR'] = aq(env['src_dir']) + subs['XED_KITDIR'] = aq(env['install_dir']) + subs['XED_GENDOC'] = aq(env['doxygen_install']) + if api_ref: + subs['XED_INPUT_TOP'] = aq(env.src_dir_join(mbuild.join('docsrc', + 'xed-doc-top.txt'))) + else: + subs['XED_INPUT_TOP'] = aq(env.src_dir_join(mbuild.join('docsrc', + 'xed-build.txt'))) + #subs['XED_HTML_HEADER'] = aq(env.src_dir_join(mbuild.join('docsrc', + # 'xed-doxygen-header.txt'))) + return subs + +def make_doxygen_build(env, work_queue): + """Make the doxygen how-to-build-xed manual""" + if 'doc-build' not in env['targets']: + return + mbuild.msgb("XED BUILDING 'build' DOCUMENTATION") + e2 = copy.deepcopy(env) + e2['doxygen_cmd']= e2['doxygen'] + + if e2['doxygen_install'] == '': + d= mbuild.join(e2['build_dir'],'doc') + else: + d = env['doxygen_install'] + e2['doxygen_install'] = mbuild.join(d, 'build-manual') + + mbuild.msgb("BUILDING BUILD MANUAL", e2['doxygen_install']) + mbuild.cmkdir(e2['doxygen_install']) + e2['doxygen_config'] = e2.src_dir_join(mbuild.join('docsrc', + 'Doxyfile.build')) + + subs = doxygen_subs(e2,api_ref=False) + e2['doxygen_top_src'] = subs['XED_INPUT_TOP'] + inputs = [ subs['XED_INPUT_TOP'] ] + inputs.append( e2['mfile'] ) + mbuild.doxygen_run(e2, inputs, subs, work_queue, 'dox-build') + +def make_doxygen_api(env, work_queue, install_dir): + """We may install in the kit or elsewhere using files from the kit""" + mbuild.msgb("XED BUILDING 'api' DOCUMENTATION") + e2 = copy.deepcopy(env) + e2['doxygen_cmd']= e2['doxygen'] + e2['doxygen_install'] = mbuild.join(install_dir,'ref-manual') + mbuild.cmkdir(e2['doxygen_install']) + e2['doxygen_config'] = e2.src_dir_join(mbuild.join('docsrc','Doxyfile')) + subs = doxygen_subs(e2,api_ref=True) + e2['doxygen_top_src'] = subs['XED_INPUT_TOP'] + inputs = [] + inputs.append(subs['XED_INPUT_TOP']) + inputs.extend( mbuild.glob(mbuild.join(e2['install_dir'], + 'include','*'))) + + inputs.extend( mbuild.glob(mbuild.join(e2['install_dir'], + 'examples','*.c'))) + inputs.extend( mbuild.glob(mbuild.join(e2['install_dir'], + 'examples','*.cpp'))) + inputs.extend( mbuild.glob(mbuild.join(e2['install_dir'], + 'examples','*.[Hh]'))) + inputs.append( e2['mfile'] ) + mbuild.doxygen_run(e2, inputs, subs, work_queue, 'dox-ref') + + +def mkenv(): + """External entry point: create the environment""" + if not mbuild.check_python_version(2,7): + xbc.cdie("Need python 2.7.x...") + + # create an environment, parse args + env = mbuild.env_t() + standard_defaults = dict( doxygen_install='', + doxygen='', + clean=False, + die_on_errors=True, + xed_messages=False, + xed_asserts=False, + pedantic=True, + clr=False, + use_werror=True, + gen_ild_storage=False, + show_dag=False, + ext=[], + extf=[], + xedext_dir='%(xed_dir)s/../xedext', + default_isa='', + avx=True, + knc=False, + xsaveopt=True, + ivbavx=True, + ivbint=True, + avxhsw=True, + mpx=True, + glm=True, + skl=True, + skx=True, + memory_future=True, + avx512_future=True, + future=True, + knl=True, + knm=True, + sha=True, + bdw=True, + fma=True, + dbghelp=False, + install_dir='', + kit_kind='base', + win=False, + amd_enabled=True, + encoder=True, + decoder=True, + dev=False, + generator_options=[], + legal_header=None, + pythonarg=None, + ld_library_path=[], + ld_library_path_for_tests=[], + use_elf_dwarf=False, + use_elf_dwarf_precompiled=False, + limit_strings=False, + strip='strip', + pti_test=False, + verbose = 1, + compress_operands=False, + test_perf=False, + example_linkflags='', + example_rpaths=[], + android=False, + copy_libc=False, + pin_crt='', + static_stripped=False) + + env['xed_defaults'] = standard_defaults + env.set_defaults(env['xed_defaults']) + return env + +def xed_args(env): + """For command line invocation: parse the arguments""" + env.parser.add_option("--android", + dest="android", + action="store_true", + help="Android build (avoid rpath for examples)") + env.parser.add_option("--copy-runtime-libs", + dest="copy_libc", + action="store_true", + help="Copy the libc to the kit." + + " Rarely necessary if building on old linux " + + "dev systems. Default: false") + env.parser.add_option("--example-linkflags", + dest="example_linkflags", + action="store", + help="Extra link flags for the examples") + env.parser.add_option("--example-rpath", + dest="example_rpaths", + action="append", + help="Extra rpath dirs for examples") + env.parser.add_option("--doxygen-install", + dest="doxygen_install", + action="store", + help="Doxygen installation directory") + env.parser.add_option("--doxygen", + dest="doxygen", + action="store", + help="Doxygen command name") + env.parser.add_option("-c","--clean", + dest="clean", + action="store_true", + help="Clean targets") + env.parser.add_option("--keep-going", '-k', + action="store_false", + dest="die_on_errors", + help="Keep going after errors occur when building") + env.parser.add_option("--messages", + action="store_true", + dest="xed_messages", + help="Enable use xed's debug messages") + env.parser.add_option("--no-pedantic", + action="store_false", + dest="pedantic", + help="Disable -pedantic (gnu/clang compilers).") + env.parser.add_option("--asserts", + action="store_true", + dest="xed_asserts", + help="Enable use xed's asserts") + env.parser.add_option("--clr", + action="store_true", + dest="clr", + help="Compile for Microsoft CLR") + env.parser.add_option("--no-werror", + action="store_false", + dest="use_werror", + help="Disable use of -Werror on GNU compiles") + env.parser.add_option("--gen-ild-storage", + action="store_true", + dest="gen_ild_storage", + help="Dump ILD storage data file.") + env.parser.add_option("--show-dag", + action="store_true", + dest="show_dag", + help="Show the dependence DAG") + + env.parser.add_option("--ext", + action="append", + dest="ext", + help="Add extension files of the form " + + "pattern-name:file-name.txt") + + env.parser.add_option("--extf", + action="append", + dest="extf", + help="Add extension configuration files " + + "that contain lines of form pattern-name:file-name.txt. All files " + + "references will be made relative to the directory in which the " + + "config file is located.") + + env.parser.add_option("--xedext-dir", + action="store", + dest="xedext_dir", + help="XED extension dir") + + env.parser.add_option("--default-isa-extf", + action="store", + dest="default_isa", + help="Override the default ISA files.cfg file") + + env.parser.add_option("--knc", + action="store_true", + dest="knc", + help="Include KNC support") + env.parser.add_option("--no-avx", + action="store_false", + dest="avx", + help="Do not include AVX") + env.parser.add_option("--no-xsaveopt", + action="store_false", + dest="xsaveopt", + help="Do not include XSAVEOPT") + env.parser.add_option("--no-ivbavx", + action="store_false", + dest="ivbavx", + help="Do not include AVX for IVB.") + env.parser.add_option("--no-ivbint", + action="store_false", + dest="ivbint", + help="Do not include integer (nonAVX) IVB NI.") + env.parser.add_option("--no-avxhsw", + action="store_false", + dest="avxhsw", + help="Do not include AVX for HSW.") + env.parser.add_option("--no-mpx", + action="store_false", + dest="mpx", + help="Do not include MPX.") + env.parser.add_option("--no-sha", + action="store_false", + dest="sha", + help="Do not include SHA.") + env.parser.add_option("--no-bdw", + action="store_false", + dest="bdw", + help="Do not include BDW NI.") + env.parser.add_option("--no-glm", + action="store_false", + dest="glm", + help="Do not include GLM.") + env.parser.add_option("--knl", + action="store_true", + dest="knl", + help="Include KNL AVX512{PF,ER} on top of " + + "AVX512{F,CD}. " + + "Default: Currently enabled.") + env.parser.add_option("--knm", + action="store_true", + dest="knm", + help="Include KNM AVX512{4FMAPS,4VNNIW} " + + "Default: Currently enabled.") + env.parser.add_option("--no-knl", + action="store_false", + dest="knl", + help="Do no include KNL AVX512{PF,ER}. " + + "Default: KNL enabled.") + env.parser.add_option("--no-skl", + action="store_false", + dest="skl", + help="Do not include SKL.") + env.parser.add_option("--no-skx", + action="store_false", + dest="skx", + help="Do not include SKX.") + env.parser.add_option("--no-memory-future", + action="store_false", + dest="memory_future", + help="Do not include future memory NI.") + env.parser.add_option("--no-future", + action="store_false", + dest="future", + help="Do not include future NI.") + env.parser.add_option("--no-avx512-future", + action="store_false", + dest="avx512_future", + help="Do not include future avx512 instructions.") + env.parser.add_option("--dbghelp", + action="store_true", + dest="dbghelp", + help="Use dbghelp.dll on windows.") + env.parser.add_option("--install-dir", + dest="install_dir", + action="store", + help="XED Install directory. " + + "Default: kits/xed-install-date-os-cpu") + env.parser.add_option("--kit-kind", + dest="kit_kind", + action="store", + help="Kit version string. " + + "The default is 'base'") + env.parser.add_option("--no-amd", + action="store_false", + dest="amd_enabled", + help="Disable AMD public instructions") + env.parser.add_option("--limit-strings", + action="store_true", + dest="limit_strings", + help="Remove some strings to save space.") + env.parser.add_option("--no-encoder", + action="store_false", + dest="encoder", + help="Disable the encoder") + env.parser.add_option("--no-decoder", + action="store_false", + dest="decoder", + help="Disable the decoder") + env.parser.add_option("--generator-options", + action="append", + dest="generator_options", + help="Options to pass through for " + + "the decode generator") + env.parser.add_option("--legal-header", + action="store", + dest="legal_header", + help="Use this special legal header " + + "on public header files and examples.") + env.parser.add_option("--python", + action="store", + dest="pythonarg", + help="Use a specific version of python " + + "for subprocesses.") + env.parser.add_option("--ld-library-path", + action="append", + dest="ld_library_path", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running ldd and making kits") + env.parser.add_option("--ld-library-path-for-tests", + action="append", + dest="ld_library_path_for_tests", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running the tests") + + # elf.h is different than libelf.h. + env.parser.add_option("--elf-dwarf", "--dwarf", + action="store_true", + dest="use_elf_dwarf", + help="Use libelf/libdwarf. (Linux only)") + env.parser.add_option('--dev', + action='store_true', + dest='dev', + help='Developer knob. Updates VERISON file') + env.parser.add_option("--elf-dwarf-precompiled", + action="store_true", + dest="use_elf_dwarf_precompiled", + help="Use precompiled libelf/libdwarf from " + + " the XED source distribution." + + " This is the currently required" + + " if you are installing a kit." + + " Implies the --elf-dwarf knob." + " (Linux only)") + env.parser.add_option("--strip", + action="store", + dest="strip", + help="Path to strip binary. (Linux only)") + env.parser.add_option("--pti-test", + action="store_true", + dest="pti_test", + help="INTERNAL TESTING OPTION.") + env.parser.add_option("--compress-operands", + action="store_true", + dest="compress_operands", + help="use bit-fields to compress the "+ + "operand storage.") + env.parser.add_option("--test-perf", + action="store_true", + dest="test_perf", + help="Do performance test (on linux). Requires" + + " specific external test binary.") + env.parser.add_option("--pin-crt", + action="store", + dest="pin_crt", + help="Compile for the Pin C-runtime. Specify" + + " path to pin kit") + env.parser.add_option("--static-stripped", + action="store_true", + dest="static_stripped", + help="Make a static libxed.a renaming internal symbols") + + env.parse_args(env['xed_defaults']) + +def init_once(env): + xbc.init_once(env) + if 'doc' in env['targets']: + if 'install' not in env['targets']: + xbc.cdie( "Doxygen API will not get built if not building a\n" + + """XED kit using the "install" command line target.""") + +def init(env): + if env['pythonarg']: + python_command = env['pythonarg'] + else: + python_command = sys.executable + # Avoid using cygwin python which may be in the PATH of + # noncygwin shells. + if env.on_windows() and python_command in ['/bin/python', + '/usr/bin/python']: + if env.on_cygwin() and env['compiler'] in ['ms','icl']: + xbc.cdie("Cannot build with cygwin python. " + + "Please install win32 python") + python_commands = [ 'c:/python27/python.exe', + 'c:/python26/python.exe', + 'c:/python25/python.exe' ] + python_command = None + for p in python_commands: + if os.path.exists(p): + python_command = p + break + if not python_command: + xbc.cdie("Could not find win32 python at these locations: %s" % + "\n\t" + "\n\t".join(python_commands)) + + env['pythonarg'] = env.escape_string(python_command) + if mbuild.verbose(2): + mbuild.msgb("PYTHON", env['pythonarg']) + + xbc.init(env) + + env.add_define('XED_GIT_VERSION="%(xed_git_version)s"') + if env['shared']: + env.add_define('XED_DLL') + + env.add_include_dir(mbuild.join(env['src_dir'],"include","private")) + env.add_include_dir(mbuild.join(env['src_dir'],"include","public")) + + valid_targets = [ 'clean', 'just-gen', + 'skip-gen', 'install', + 'apply-header', + 'skip-lib', + 'examples', 'cmdline', + 'doc', 'doc-build', + 'install', 'zip', + 'test' ] + for t in env['targets']: + if t not in valid_targets: + xbc.cdie("Invalid target supplied: " + t + + "\n Valid targets:\n\t" + + "\n\t".join(valid_targets)) + if 'test' in env['targets']: + if 'examples' not in env['targets']: + mbuild.msgb("INFO", + "added examples to target list since running tests") + env['targets'].append('examples') + +def _wk_show_errors_only(): + #True means show errors only when building. + if mbuild.verbose(1): + return False # show output + return True # show errors only. + +def build_xed_ild_library(env, lib_env, lib_dag): + # compile sources specific to ild + xed_ild_sources = ['xed-init-ild.c', 'xed-ild-support.c'] + ild_objs = lib_env.compile( lib_dag, xbc.src_dir_join(lib_env, + xed_ild_sources)) + # grab common sources compiled earlier + ild_objs += xbc.build_dir_join(lib_env, + lib_env.make_obj(['xed-ild.c', + 'xed-isa-set.c', + 'xed-chip-features.c', + 'xed-chip-features-table.c', + 'xed-chip-modes.c', + 'xed-ild-disp-l3.c', + 'xed-ild-eosz.c', + 'xed-ild-easz.c', + 'xed-ild-imm-l3.c'])) + + lib,dll = xbc.make_lib_dll(env,'xed-ild') + + if lib_env['shared']: + u = lib_env.dynamic_lib(ild_objs, dll, relocate=True) + else: + u = lib_env.static_lib(ild_objs, lib, relocate=True) + env['link_libild'] = lib_env.build_dir_join(lib) + env['shd_libild'] = lib_env.build_dir_join(dll) + lib_dag.add(lib_env,u) + + +def make_static_stripped_library(env, objs, obj_clean): + c = mbuild.plan_t(name='repack-and-clean', + command=repack_and_clean, + args=[obj_clean, objs], + env=env, + input=objs, + output=obj_clean) + return c + + +def repack_and_clean(args, env): + """Run ld -r foo.o objs... and then use objcopy --redefine-syms=file + to redefine the internal symbols. The renamed obj file is packed + in to a static library. The "file" is a list of old new pairs, one + per line. The public symbols come from the file + misc/API.SYMBOLS.txt every other non-external label is considered + internal and gets renamed.""" + + tobj_clean = args[0] + objs = args[1] + + + # step 1: ld -r + ldcmd = env['toolchain'] + 'ld' + tobj_dirty = env.expand(env.build_dir_join('xed-tobj-dirty%(OBJEXT)s')) + + repack_cmd = "{} -r -o {} {}".format(ldcmd, tobj_dirty, " ".join(objs)) + mbuild.run_command(repack_cmd) + + # step 2: extract a list of all symbols + nmcmd = env['toolchain'] + 'nm' + nm = "{} --defined-only {}".format(nmcmd, tobj_dirty) + all_syms_fn = env.build_dir_join('all-syms.txt') + mbuild.run_command_output_file(nm, output_file_name=all_syms_fn) + + # step 3: parse the all_syms_fn. + all_syms = file(all_syms_fn).readlines() + all_syms = map(lambda x: x.strip(), all_syms) + all_syms = set(map(lambda x: x.split(' ',2)[2], all_syms)) + + # step 4: subtract the public symbols + api_names_fn = env.src_dir_join(mbuild.join('misc','API.NAMES.txt')) + api_names = file(api_names_fn).readlines() + api_names = set(map(lambda x: x.strip(), api_names)) + + private_syms = all_syms - api_names + + # step 5: make rename file for the private symbols + redef_fn = env.build_dir_join('symbol-redef.txt') + f = open(redef_fn,"w") + for i,x in enumerate(private_syms): + f.write("{} xedint{}\n".format(x, i)) + f.close() + + # step 6: run objcopy, renaming the symbols + objcopy_cmd = env['toolchain'] + 'objcopy' + ocargs = "--redefine-syms={}".format(redef_fn) + ocmd = "{} {} {} {}".format(objcopy_cmd, ocargs, tobj_dirty, tobj_clean) + mbuild.run_command(ocmd) + return (0, ["success"]) + +def build_libxed(env,work_queue): + "Run the generator and build libxed" + + # create object that will assemble our command line. + gc = generator_inputs_t(env['build_dir'], + env['amd_enabled'], + env['limit_strings']) + + # if we are doing an extended XED then here we'd add more input files + # here. + + # these are individual extension files + for ext_files in env['ext']: + (ptype, fname) = ext_files.split(':') + gc.add_file(ptype,fname) + + # READ EACH EXTENSION FILE-of-FILES + comment_pattern = re.compile(r'[#].*$') + sources_to_remove = [] + sources_to_add = [] + sources = {} + source_prio = collections.defaultdict(int) + + if env['amd_enabled']: + env.add_define('XED_AMD_ENABLED') + + if env['avx']: + env.add_define('XED_AVX') + if not env['avx']: + mbuild.warn("No AVX -> Disabling KNM, KNL, SKX, Future AVX512\n\n\n") + env['knl'] = False + env['knm'] = False + env['skx'] = False + env['avx512_future'] = False + + if env['avx512_future']: + env['skx'] = True + + if env['knm'] or env['knl'] or env['skx'] or env['avx512_future']: + # this is also supplied by xed_interface.py + env.add_define('XED_SUPPORTS_AVX512') + if env['knc']: + env.add_define('XED_SUPPORTS_KNC') + if env['mpx']: + env.add_define('XED_MPX') + if env['sha']: + env.add_define('XED_SUPPORTS_SHA') + + if env['decoder']: + env.add_define('XED_DECODER') + if env['encoder']: + env.add_define('XED_ENCODER') + + #insert default isa files at the front of the extension list + newstuff = [] + if env['default_isa'] == '': + newstuff.append( env.src_dir_join(mbuild.join('datafiles', + 'files.cfg'))) + + # This has the NT definitions for things like XMM_B() which + # are needed for >= SSE-class machines. + newstuff.append( env.src_dir_join(mbuild.join('datafiles', + 'files-xregs.cfg'))) + if not env['avx']: + # this has the xmm reg and nesting for sse-class machines. + # not useful/appropriate for AVX1/2 or AVX512-class machines. + newstuff.append( env.src_dir_join(mbuild.join('datafiles', + 'files-xmm.cfg'))) + else: + newstuff.append( env['default_isa'] ) + + # add AMD stuff under knob control + if env['amd_enabled']: + newstuff.append( env.src_dir_join(mbuild.join('datafiles', + 'files-amd.cfg'))) + if env['avx']: + newstuff.append( env.src_dir_join(mbuild.join('datafiles', + 'amdxop', + 'files.cfg'))) + + def _add_normal_ext(tenv,x , y='files.cfg'): + e = tenv.src_dir_join(mbuild.join('datafiles', x, y)) + if e not in tenv['extf']: + tenv['extf'].append( e ) + + if env['knc']: + if env['knm'] or env['knl'] or env['skx']: + _add_normal_ext(env,'knc', 'files-with-avx512f.cfg') + else: + _add_normal_ext(env,'knc', 'files-no-avx512f.cfg') + + if env['xsaveopt']: + _add_normal_ext(env,'xsaveopt') + if env['mpx']: + _add_normal_ext(env,'mpx') + if env['sha']: + _add_normal_ext(env,'sha') + if env['ivbint']: + _add_normal_ext(env,'ivbint') + if env['glm']: # FIXME requires BDW (partly) and IVBINT and XSAVEOPT + _add_normal_ext(env,'glm') + _add_normal_ext(env,'xsaves') + _add_normal_ext(env,'xsavec') + + # Add avx and fma under control of a knob + if env['avx']: + _add_normal_ext(env,'avx') + if env['ivbavx']: + _add_normal_ext(env,'ivbavx') + if env['avxhsw']: + env.add_define('XED_SUPPORTS_LZCNT_TZCNT') + _add_normal_ext(env,'avxhsw') + if env['fma']: # FIXME on HSW, but announced w/SNB, could move them + _add_normal_ext(env, 'avx', 'files-fma.cfg') + if env['bdw']: + _add_normal_ext(env,'bdw') + if env['skl'] or env['skx']: # FIXME: requires MPX and BDW + _add_normal_ext(env,'skl') + _add_normal_ext(env,'sgx') + _add_normal_ext(env,'xsaves') + _add_normal_ext(env,'xsavec') + if env['skx']: + _add_normal_ext(env,'skx') + _add_normal_ext(env,'pku') + if env['memory_future']: + _add_normal_ext(env,'memory') + if env['future']: + _add_normal_ext(env,'pt') + if env['knl']: + _add_normal_ext(env,'knl') + if env['knm']: + _add_normal_ext(env,'knm') + _add_normal_ext(env,'4fmaps-512') + _add_normal_ext(env,'4vnniw-512') + _add_normal_ext(env,'vpopcntdq-512') + + if env['skx'] or env['knl'] or env['knm']: + _add_normal_ext(env,'avx512f','shared-files.cfg') + _add_normal_ext(env,'avx512f') + _add_normal_ext(env,'avx512cd') + if env['skx']: + _add_normal_ext(env,'avx512-skx') + if env['avx512_future']: + _add_normal_ext(env,'avx512-future') + _add_normal_ext(env,'avx512ifma') + _add_normal_ext(env,'avx512vbmi') + + env['extf'] = newstuff + env['extf'] + dup_check = {} + for ext_file in env['extf']: + mbuild.msgb("EXTF PROCESSING", ext_file) + if not os.path.exists(ext_file): + xbc.cdie("Cannot open extension configuration file: %s" % + ext_file) + if os.path.isdir(ext_file): + xbc.cdie("Please specify a file, not a directory " + + "for --extf option: %s" % ext_file) + + if ext_file in dup_check: + mbuild.warn("Ignoring duplicate extf file in list %s" % ext_file) + continue + dup_check[ext_file]=True + + dir = os.path.dirname(ext_file) + for line in file(ext_file).readlines(): + line = line.strip() + line = comment_pattern.sub('',line) + if len(line) > 0: + try: + wrds = line.split(':') + if len(wrds) == 4: + (cmd, ptype, fname, priority) = wrds + elif len(wrds) == 3: + (cmd, ptype, fname) = wrds + priority='1' + elif len(wrds) == 2: + (ptype, fname) = wrds + priority='1' + if ptype == 'define': + cmd = 'define' + definition = fname.strip() + else: + cmd = 'add' + else: + xbc.cdie("Malformed extension line. " + + "Need 2-4 tokens separated by " + + " colons: [%s]" % (line)) + ptype = ptype.strip() + fname = fname.strip() + cmd = cmd.strip() + priority = int(priority.strip()) + except xbc.xed_exception_t as e: + raise # re-raise exception + except: + xbc.cdie("Cannot split this line on a colon: [%s]" % line) + + if cmd == 'clear': + gc.clear_files(ptype) + continue + elif cmd == 'define': + env.add_define(definition) + continue + elif cmd == 'remove-source': + sources_to_remove.append(fname) + continue + + if re.search('%[(].*[)]',fname): + fname = env.expand(fname) + full_name = os.path.abspath(fname) + else: + full_name = mbuild.join(dir,fname) + + if not os.path.exists(full_name): + xbc.cdie("Cannot open extension file: %s" % full_name) + + if cmd == 'add': + gc.add_file(ptype,full_name, priority) + elif cmd == 'remove': + gc.remove_file(ptype,full_name) + elif cmd == 'add-source': + print "CONSIDERING SOURCE", full_name, ptype, priority + if source_prio[ptype] < priority: + print "ADDING SOURCE", full_name, ptype, priority + source_prio[ptype] = priority + sources[ptype] = full_name + else: + xbc.cdie("Invalid extension file cmd (1st token):" + + " [%s]\nMust be 'add' or 'remove'" % line) + + for v in sources.itervalues(): + sources_to_add.append(v) + + gen_dag = mbuild.dag_t('xedgen', env=env) + + prep_files = env.build_dir_join('prep-inputs') + f = open(prep_files,"w") + f.write( "\n".join(gc.all_input_files()) + "\n") + f.close() + + # must add all user-relevant defines before emitting defines + # header + emit_defines_header(env) + + #mbuild.msgb("PREP INPUTS", ", ".join(gc.all_input_files())) + c0 = mbuild.plan_t(name='decprep', + command=run_generator_preparation, + args=gc, + env=env, + input=gc.all_input_files() + [env['mfile'], prep_files], + output= env.build_dir_join('dummy-prep') ) + prep = gen_dag.add(env,c0) + + # Python imports used by the 2 generators. + # generated 2016-04-15 by importfinder.py: + # pysrc/importfinder.py generator pysrc + # pysrc/importfinder.py read-encfile pysrc + # importfinder.py is too slow to use on every build, over 20seconds/run. + + dec_py =['pysrc/actions.py', 'pysrc/genutil.py', + 'pysrc/ild_easz.py', 'pysrc/ild_codegen.py', 'pysrc/tup2int.py', + 'pysrc/encutil.py', 'pysrc/verbosity.py', 'pysrc/ild_eosz.py', + 'pysrc/xedhash.py', 'pysrc/ild_phash.py', + 'pysrc/actions_codegen.py', 'pysrc/patterns.py', + 'pysrc/operand_storage.py', 'pysrc/opnds.py', 'pysrc/hashlin.py', + 'pysrc/hashfks.py', 'pysrc/ild_info.py', 'pysrc/ild_cdict.py', + 'pysrc/xed3_nt.py', 'pysrc/codegen.py', 'pysrc/ild_nt.py', + 'pysrc/hashmul.py', 'pysrc/enumer.py', 'pysrc/enum_txt_writer.py', + 'pysrc/xed3_nt.py', 'pysrc/ild_disp.py', 'pysrc/ild_imm.py', + 'pysrc/ild_modrm.py', 'pysrc/ild_storage.py', + 'pysrc/ild_storage_data.py', 'pysrc/slash_expand.py', + 'pysrc/chipmodel.py', 'pysrc/flag_gen.py', 'pysrc/opnd_types.py', + 'pysrc/hlist.py', 'pysrc/ctables.py', 'pysrc/ild.py', + 'pysrc/refine_regs.py', 'pysrc/metaenum.py'] + + enc_py = ['pysrc/genutil.py', 'pysrc/encutil.py', + 'pysrc/verbosity.py', 'pysrc/patterns.py', 'pysrc/actions.py', + 'pysrc/operand_storage.py', 'pysrc/opnds.py', 'pysrc/ild_info.py', + 'pysrc/codegen.py', 'pysrc/ild_nt.py', 'pysrc/actions.py', + 'pysrc/ild_codegen.py', 'pysrc/tup2int.py', + 'pysrc/constraint_vec_gen.py', 'pysrc/xedhash.py', + 'pysrc/ild_phash.py', 'pysrc/actions_codegen.py', + 'pysrc/hashlin.py', 'pysrc/hashfks.py', 'pysrc/hashmul.py', + 'pysrc/func_gen.py', 'pysrc/refine_regs.py', + 'pysrc/slash_expand.py', 'pysrc/nt_func_gen.py', + 'pysrc/scatter.py', 'pysrc/ins_emit.py'] + + dec_py = env.src_dir_join(dec_py) + enc_py = env.src_dir_join(enc_py) + dec_py += mbuild.glob(env.src_dir_join('datafiles/*enum.txt')) + + dd = env.build_dir_join('DECGEN-OUTPUT-FILES.txt') + if os.path.exists(dd): + need_to_rebuild_dec = need_to_rebuild(dd, + env.build_dir_join(".mbuild.hash.xeddecgen")) + if need_to_rebuild_dec: + mbuild.remove_file(dd) + + gc.dec_output_file = dd + + dec_input_files = (gc.all_input_files() + prep.targets + + dec_py + [env['mfile']]) + c1 = mbuild.plan_t(name='decgen', + command=run_decode_generator, + args=gc, + env=env, + input=dec_input_files, + output= dd) + dec_cmd = gen_dag.add(env,c1) + + if env['encoder']: + ed = previous_output_fn = env.build_dir_join('ENCGEN-OUTPUT-FILES.txt') + if os.path.exists(ed): + need_to_rebuild_enc = need_to_rebuild(ed, + env.build_dir_join('.mbuild.hash.xedencgen')) + if need_to_rebuild_enc: + mbuild.remove_file(ed) + + gc.enc_output_file = ed + enc_input_files = (gc.all_input_files() + prep.targets + + enc_py + [env['mfile']]) + c2 = mbuild.plan_t(name='encgen', + command=run_encode_generator, + args=gc, + env=env, + input=enc_input_files, + output= ed) + enc_cmd = gen_dag.add(env,c2) + + phase = "DECODE/ENCODE GENERATORS" + if 'skip-gen' in env['targets']: + mbuild.msgb(phase, "SKIPPING!") + else: + okay = work_queue.build(dag=gen_dag, + show_progress=True, + show_output=True, + show_errors_only=_wk_show_errors_only()) + + if not okay: + xbc.cdie("[%s] failed. dying..." % phase) + if mbuild.verbose(2): + mbuild.msgb(phase, "succeeded") + + if 'just-gen' in env['targets']: + mbuild.msgb("STOPPING", "after %s" % phase) + xbc.cexit(1) + + ######################################################################### + # build libxed + + libxed_lib, libxed_dll = xbc.make_lib_dll(env,'xed') + if env['shared']: + env['shd_libxed'] = env.build_dir_join(libxed_dll) + env['link_libxed'] = env.build_dir_join(libxed_lib) + else: + env['shd_libxed'] = env.build_dir_join(libxed_lib) + env['link_libxed'] = env['shd_libxed'] # same + + + # pick up the generated header files in the header scans + env.add_include_dir(env['build_dir']) + env['private_generated_header_dir'] = mbuild.join(env['build_dir'], + 'include-private') + env.add_include_dir(env['private_generated_header_dir']) + + # collect up all the generated sources + generated_library_sources = mbuild.glob(mbuild.join(env['build_dir'],'*.c')) + nongen_lib_sources = mbuild.glob(mbuild.join(env['src_dir'],'src','*.c')) + + # remove the overridden sources and stuff that is not for libxed.* + sources_to_remove.extend(['xed-init-ild.c', + 'xed-ild-support.c']) # stuff for standalone ild + sources_to_remove = xbc.src_dir_join(env, sources_to_remove) + + generated_sources_to_remove = [] + if not env['decoder']: + decoder_sources_to_remove = [ + 'xed-inst.c', + 'xed-decode.c,' + 'xed-chip-features.c', + 'xed-enc-dec.c', + 'xed-iform-map.c', + 'xed-disas.c' + 'xed-decoded-inst.c', + 'xed-decoded-init.c', + 'xed-agen.c', + 'xed-ild.c', + 'xed3-dynamic-decode.c', + 'xed3-static-decode.c', + ] + sources_to_remove += xbc.src_dir_join(env, decoder_sources_to_remove) + generated_sources_to_remove += [ + env.build_dir_join('xed-iform-map-init.c') + ] + if not env['encoder']: + encoder_sources_to_remove = [ + 'xed-encode.c', + 'xed-enc-dec.c', + 'xed-encode-isa-functions.c', + 'xed-encoder-hl.c'] + sources_to_remove += xbc.src_dir_join(env, encoder_sources_to_remove) + + nongen_lib_sources = list( set(nongen_lib_sources) - set(sources_to_remove)) + generated_library_sources = list( set(generated_library_sources) - + set(generated_sources_to_remove) ) + # add the replacement sources + nongen_lib_sources.extend(sources_to_add) + + lib_dag = mbuild.dag_t('xedlib', env=env) + lib_env = copy.deepcopy(env) + lib_env.add_cc_define("XED_BUILD") + + lib_objs = [] + # first_lib and last_lib are for supporting compilations using + # custom C runtimes. + if 'first_lib' in env: + lib_objs.append(env['first_lib']) + lib_objs += lib_env.compile( lib_dag, generated_library_sources) + lib_objs += lib_env.compile( lib_dag, nongen_lib_sources) + if 'last_lib' in env: + lib_objs.append(env['last_lib']) + + if lib_env['shared']: + # use gcc for making the shared object + lib_env['CXX_COMPILER']= lib_env['CC_COMPILER'] + + # libxed + if lib_env['shared']: + u = lib_env.dynamic_lib(lib_objs, env['shd_libxed']) + elif env.on_linux() and lib_env['static_stripped']: + tobj_clean = env.expand(env.build_dir_join('xed-tobj-clean%(OBJEXT)s')) + u = make_static_stripped_library(lib_env, lib_objs, tobj_clean) + lib_dag.add(lib_env,u) + u = lib_env.static_lib([tobj_clean], env['link_libxed']) + else: + u = lib_env.static_lib(lib_objs, env['link_libxed']) + lib_dag.add(lib_env,u) + + # libxed-ild + if env['decoder'] and not lib_env['static_stripped']: + build_xed_ild_library(env, lib_env, lib_dag) + + + if lib_dag.cycle_check(): + xbc.cdie("Circularities in dag...") + if 'skip-lib' in env['targets']: + mbuild.msgb("SKIPPING LIBRARY BUILD") + else: + okay = work_queue.build(lib_dag, + die_on_errors=lib_env['die_on_errors'], + show_progress=True, + show_output=True, + show_errors_only=_wk_show_errors_only()) + + if okay and env['shared'] and not env['debug']: + xbc.strip_file(env, env['shd_libxed'], '-x') + xbc.strip_file(lib_env, env['shd_libild'], '-x') + if not okay: + xbc.cdie("Library build failed") + if mbuild.verbose(2): + mbuild.msgb("LIBRARY", "build succeeded") + + del lib_env + +def _modify_search_path_mac(env, fn): + """Make example tools refer to the libxed.so from the lib directory + if doing and install. Mac only.""" + if not env['shared']: + return + if not env.on_mac(): + return + if not xbc.installing(env): + return + env['odll'] = '%(build_dir)s/libxed.dylib' + env['ndll'] = '"@loader_path/../lib/libxed.dylib"' + cmd = 'install_name_tool -change %(odll)s %(ndll)s ' + fn + cmd = env.expand(cmd) + env['odll'] = None + env['ndll'] = None + + mbuild.msgb("SHDOBJ SEARCH PATH", cmd) + (retcode,stdout,stderr) = mbuild.run_command(cmd) + if retcode != 0: + xbc.dump_lines("install_name_tool stdout", stdout) + xbc.dump_lines("install_name_tool stderr", stderr) + xbc.cdie("Could not modify dll path: " + cmd) + +def _test_perf(env): + """Performance test. Should compile with -O3 or higher. Linux + only. Requires a specific test binary.""" + if not env.on_linux(): + return + if not env['test_perf']: + return + + # find the XED command line tool binary + xed = None + for exe in env['example_exes']: + if 'xed' == os.path.basename(exe): + xed = exe + if not xed: + xbc.cdie("Could not find the xed command line tool for perf test") + + import perftest + args = perftest.mkargs() + args.xed = xed + r = perftest.work(args) # 2016-04-22 FIXME: need to update interface + if r != 0: + # perf test failed. Although calling xbc.cexit() avoids saving + # mbuild hash state and causes rebuilds. + xbc.cdie( "perf test failed") + +def _get_xed_min_size(env): + if not env.on_linux(): + return + + xed_min = None + #check if we have xed-min test + for exe in env['example_exes']: + if 'xed-min' in exe: + xed_min = exe + + if not xed_min: + return + + xbc.strip_file(env,xed_min) + + #get the size in MB + size_bytes = os.path.getsize(xed_min) + size_meg = size_bytes / (1024*1024.0) + mbuild.msgb("XED-MIN SIZE", "%d = %.2fMB" % (size_bytes,size_meg)) + + import elf_sizes + d = elf_sizes.work(xed_min,die_on_errors=False) + if d: + elf_sizes.print_table(d) + +def build_examples(env): + env['example_exes'] = [] + if not set(['examples','cmdline']).intersection(env['targets']): + return + + sys.path.insert(0, mbuild.join(env['src_dir'],'examples')) + import xed_examples_mbuild + env_ex = copy.deepcopy(env) + env_ex['CPPPATH'] = [] # clear out libxed-build headers. + env_ex['src_dir'] = mbuild.join(env['src_dir'], 'examples') + env_ex['xed_lib_dir'] = env['build_dir'] + env_ex['xed_inc_dir'] = env['build_dir'] + + try: + retval = xed_examples_mbuild.examples_work(env_ex) + except Exception, e: + xbc.handle_exception_and_die(e) + if 'example_exes' in env_ex: + env['example_exes'] = env_ex['example_exes'] + _get_xed_min_size(env_ex) + _test_perf(env_ex) + + +def copy_dynamic_libs_to_kit(env, kitdir): + """Copy *all* the dynamic libs that ldd finds to the extlib dir in the + kit""" + import external_libs + + if not env.on_linux() and not env.on_freebsd(): + return + + kit_ext_lib_dir = mbuild.join(kitdir,'extlib') + bindir = mbuild.join(kitdir,'bin') + executables = glob.glob(mbuild.join(bindir,'*')) + mbuild.cmkdir(kit_ext_lib_dir) + if 'extern_lib_dir' not in env: + env['extern_lib_dir'] = '%(xed_dir)s/external/lin/lib%(arch)s' + + extra_ld_library_paths = (env['ld_library_path'] + + [ env.expand('%(extern_lib_dir)s')]) + + # run LDD to find the shared libs and do the copies + okay = external_libs.copy_system_libraries(env, + kit_ext_lib_dir, + executables, + extra_ld_library_paths) + if not okay: + mbuild.warn("There was a problem running LDD when making the kit") + + # copy the libelf/dwarf license + if env['use_elf_dwarf_precompiled']: + env2 = copy.deepcopy(env) + xbc.cond_add_elf_dwarf(env2) + mbuild.copy_file(env2['libelf_license'], kit_ext_lib_dir) + + +def copy_ext_libs_to_kit(env,dest): # 2014-12-02: currently unused + if not env['use_elf_dwarf_precompiled']: + return + + extlib = mbuild.join(dest,"extlib") + mbuild.cmkdir(extlib) + + env2 = copy.deepcopy(env) + xbc.cond_add_elf_dwarf(env2) + + for f in env2['ext_libs']: + mbuild.copy_file(env2.expand(f),extlib) + existing_file_name = os.path.basename(env2['libelf']) + dest_path_and_link = mbuild.join(extlib,env2['libelf_symlink']) + if os.path.exists(dest_path_and_link): + mbuild.remove_file(dest_path_and_link) + mbuild.symlink(env, existing_file_name, dest_path_and_link) + mbuild.copy_file(env2['libelf_license'], extlib) + +def apply_legal_header2(fn, legal_header): + + def _c_source(x): + t = x.lower() + for y in ['.c', '.h', '.cpp']: + if t.endswith(y): + return True + return False + + try: + import apply_legal_header + except: + xbc.cdie("XED ERROR: mfile.py could not find scripts directory") + + if mbuild.verbose(2): + mbuild.msgb("HEADER TAG", fn) + + if _c_source(fn): + apply_legal_header.apply_header_to_source_file(legal_header,fn) + else: + apply_legal_header.apply_header_to_data_file(legal_header,fn) + + + +def build_kit(env, work_queue): + "Build the XED kit" + if not xbc.installing(env): + return + + # add a default legal header if we are building a kit and none is + # specified. + + if env['legal_header'] == 'default' or env['legal_header'] == None: + env['legal_header'] = mbuild.join(env['src_dir'],'misc', + 'apache-header.txt') + legal_header = file(env['legal_header']).readlines() + + if env['install_dir'] == '': + date = time.strftime("%Y-%m-%d") + sd = 'xed-install-%s-%s-%s-%s' % ( env['kit_kind'], + date, + env['build_os'], + env['host_cpu'] ) + mbuild.cmkdir('kits') + env['install_dir'] = os.path.join('kits', sd) + + dest = env['install_dir'] + + if os.path.exists(dest): # start clean + mbuild.remove_tree(dest) + + if mbuild.verbose(2): + mbuild.msgb("INSTALL DIR", dest) + include = mbuild.join(dest,"include") + lib = mbuild.join(dest,"lib") + examples = mbuild.join(dest,"examples") + bin_dir = mbuild.join(dest,"bin") + doc = mbuild.join(dest,"doc") + misc = mbuild.join(dest,"misc") + mbld = mbuild.join(dest,"mbuild") + mbld2 = mbuild.join(mbld,'mbuild') + + for d in [dest,lib,include,examples,bin_dir,misc,mbld, mbld2]: + mbuild.cmkdir(d) + + boilerplate = env.src_dir_join([ 'README.md' ]) + boilerplate.append(mbuild.join(env['src_dir'],'LICENSE')) + for f in boilerplate: + if os.path.exists(f): + mbuild.copy_file(f,dest) + else: + mbuild.warn("Could not find %s" % (f)) + + # copy the miscellaneous files to the misc directory + idata =mbuild.join(env['build_dir'],'idata.txt') + mbuild.copy_file(idata, misc) + apply_legal_header2(mbuild.join(misc,'idata.txt'), legal_header) + + # copy mbuild to kit + msrc = mbuild.join(env['src_dir'], '..', 'mbuild') + for fn in glob.glob(mbuild.join(msrc,'mbuild','*.py')): + mbuild.copy_file(fn, mbld2) + dfn = mbuild.join(mbld2,os.path.basename(fn)) + apply_legal_header2(dfn, legal_header) + + # copy the common build file to the examples dir of the kits + common =mbuild.join(env['src_dir'],'xed_build_common.py') + mbuild.copy_file(common, examples) + apply_legal_header2(mbuild.join(examples,'xed_build_common.py'), + legal_header) + + # copy the examples that we just built + example_exes = env['example_exes'] + copied = False + if len(example_exes) > 0: + for f in example_exes: + if os.path.exists(f): + if not env['debug']: + xbc.strip_file(env,f) + mbuild.copy_file(f,bin_dir) + copied=True + _modify_search_path_mac(env, + mbuild.join( bin_dir, + os.path.basename(f))) + if copied: + copy_dynamic_libs_to_kit(env, dest) + + # copy dbghelp.dll to the bin on windows + if env['dbghelp'] and env.on_windows(): + # locate src sibling directory dbghelp + dbghelp = mbuild.join(mbuild.posix_slashes(os.path.dirname( + os.path.abspath(env['src_dir']))),'dbghelp') + mbuild.msgb("Trying dbghelp", dbghelp) + if os.path.exists(dbghelp): + dll = mbuild.join(dbghelp,env['arch'],'dbghelp.dll') + mbuild.msgb("trying to find dll", dll) + if os.path.exists(dll): + mbuild.copy_file(dll,bin_dir) + + + # copy the libraries. (DLL goes in bin) + libnames_template = [ 'lib%(base_lib)s.a', + 'lib%(base_lib)s.so', + '%(base_lib)s.lib', + '%(base_lib)s.dll', + 'lib%(base_lib)s.dylib' ] + libnames = [] + for base_lib in ['xed', 'xed-ild']: + env['base_lib']=base_lib + libnames.extend(env.expand(libnames_template)) + + libs = map(lambda x: mbuild.join(env['build_dir'], x), + libnames) + libs = filter(lambda x: os.path.exists(x), libs) + if len(libs) == 0: + xbc.cdie("No libraries found for install") + for f in libs: + print f + if f.find('.dll') != -1: + mbuild.copy_file(f, bin_dir) + else: + mbuild.copy_file(f, lib) + + # copy any *.pdb files if one exists + copy_pdb_files = False + if copy_pdb_files: + pdb_files = mbuild.glob(mbuild.join(env['build_dir'],'*.pdb')) + for pdb in pdb_files: + if os.path.exists(pdb): + mbuild.copy_file(pdb,lib) + + # copy non-generated headers + src_inc = mbuild.join(env['src_dir'],'include',"public",'*.h') + incs= mbuild.glob(src_inc) + if len(incs) == 0: + xbc.cdie("No standard include headers found for install") + for h in incs: + mbuild.copy_file(h,include) + + # copy examples source + for ext in ['*.[Hh]', '*.c', '*.cpp', '*.py', 'README.txt']: + esrc = mbuild.glob(mbuild.join(env['src_dir'],'examples',ext)) + if len(esrc) == 0: + xbc.cdie( "No standard examples to install") + for s in esrc: + mbuild.copy_file(s,examples) + + # legal header stuff + base = os.path.basename(s) + tgt = mbuild.join(examples,base) + if 'LICENSE' not in tgt: + apply_legal_header2(tgt, legal_header) + + # copy the generated headers + gen_inc = mbuild.join(mbuild.join(env['build_dir'],'*.[Hh]')) + gincs= mbuild.glob(gen_inc) + if len(gincs) == 0: + xbc.cdie("No generated include headers found for install") + for h in gincs: + mbuild.copy_file(h,include) + + # apply legal header to all headers (generanted and nongenerated) + # in the include directory. + for h in mbuild.glob(mbuild.join(include,'*.[Hh]')): + if mbuild.verbose(2): + mbuild.msgb("HEADER TAG", h) + apply_legal_header2(h, legal_header) + + + # After applying the legal header, create the doxygen from the kit + # files, and place the output right in the kit. + if 'doc' in env['targets']: + mbuild.cmkdir(doc) + make_doxygen_api(env, work_queue, doc) + # for the web... + if env['doxygen_install']: + make_doxygen_api(env, work_queue, env['doxygen_install']) + + # build a zip file + if 'zip' in env['targets']: + wfiles = os.walk( env['install_dir']) + zip_files = [] + for (path,dirs,files) in wfiles: + zip_files.extend( map(lambda x: mbuild.join(path,x), files) ) + import zipfile + archive = env['install_dir'] + '.zip' + z = zipfile.ZipFile(archive,'w') + for f in zip_files: + z.write(f) + z.close() + mbuild.msgb("ZIPFILE", archive) + env['kit_zip_file']=archive + mbuild.msgb("XED KIT BUILD COMPLETE") + +def get_git_cmd(env): + git = 'git' + if 'GITCMD' in os.environ: + gite = os.environ['GITCMD'] + if os.path.exists(gite): + git = gite + return git + +def autodev(env): + if env['dev']: + return True + if os.path.exists(mbuild.join(env['src_dir'],".developer")): + return True + return False + +def get_git_version(env): + fn = mbuild.join(env['src_dir'],'VERSION') + # are we in a GIT repo? + if os.path.exists(mbuild.join(env['src_dir'],'.git')): + cmd = get_git_cmd(env) + ' describe --tags' + (retcode, stdout, stderr) = mbuild.run_command(cmd, + directory=env['src_dir']) + if retcode == 0: + # git worked, update VERSION file + line = stdout[0].strip() + # update the VERSION file conditionally. It will mess up nightly + # machines to modify a tracked file on every build. + if autodev(env): + f = open(fn,'w') + f.write(line + "\n") + f.close() + + return line + else: + xbc.dump_lines("git description stdout", stdout) + xbc.dump_lines("git description stderr", stderr) + + # not a git repo or git failed or was not found. + try: + lines = file(fn).readlines() + line = lines[0].strip() + return line + except: + xbc.cdie("Could not find VERSION file, git or git repo") + +def emit_defines_header(env): + """Grab all the XED_* defines and the model name and emit a header file""" + + def _emit_define(s): + short = s + short = re.sub(r'[=].*','',s) + + # grab right hand side of equals sign, if any + rhs = None + if '=' in s: + rhs = re.sub(r'.*[=]','',s) + + klist = [] + klist.append( "# if !defined(%s)" % (short)) + if rhs: + klist.append( "# define %s %s" % (short,rhs)) + else: + klist.append( "# define %s" % (short)) + klist.append( "# endif") + return klist + output_file_name = "xed-build-defines.h" + + klist = [] + klist.append("#if !defined(_XED_BUILD_DEFINES_H_)") + klist.append("# define _XED_BUILD_DEFINES_H_\n") + + kys = env['DEFINES'].keys() + kys.sort() + for d in kys: + if re.match(r'^XED_',d): + define = env.expand(d) + klist.extend(_emit_define(define)) + klist.append("#endif") + + klist = map(lambda x: x+'\n', klist) + + fn = env.build_dir_join(output_file_name) + if mbuild.hash_list(klist) != mbuild.hash_file(fn): + mbuild.msgb("EMIT BUILD DEFINES HEADER FILE") + f = open(fn,"w") + for line in klist: + f.write(line) + f.close() + else: + mbuild.msgb("REUSING BUILD DEFINES HEADER FILE") + +def update_version(env): + new_rev = get_git_version(env) + date = time.strftime("%Y-%m-%d") + if new_rev: + mbuild.msgb("GIT VERSION", new_rev) + else: + new_rev = "000" + mbuild.warn("Could not find GIT revision number") + + # For developer builds, include the date in the git version. For + # non developer builds, do not include the date. The git version + # gets put in the xed-build-defines.h file. If the git version + # includes the date, it would trigger rebuilds on a daily basis. + + if autodev(env): + env['xed_git_version'] = new_rev + " " + date + else: + env['xed_git_version'] = new_rev + +def _test_setup(env): + osenv = None + if 'ld_library_path_for_tests' in env and env['ld_library_path_for_tests']: + osenv = copy.deepcopy(os.environ) + s = None + if 'LD_LIBRARY_PATH' in osenv: + s = osenv['LD_LIBRARY_PATH'] + osenv['LD_LIBRARY_PATH'] = ":".join(env['ld_library_path_for_tests']) + if s: + osenv['LD_LIBRARY_PATH'] += ":" + s + + if env.on_windows() and env['shared']: + # copy the xed.dll to the env['build_dir']/examples dir so + # that it is found by the executable tests. + mbuild.copy_file( env.expand( env.build_dir_join( env.shared_lib_name('xed'))), + env.build_dir_join('examples')) + return osenv + +def _test_cmdline_decoder(env,osenv): + """Disassemble something with the command line decoder to make sure it + works. Returns 0 on success, and nonzero on failure.""" + + output_file = env.build_dir_join('CMDLINE.OUT.txt') + cmd = "%(build_dir)s/examples/xed -n 1000 -i %(build_dir)s/examples/xed%(OBJEXT)s" + cmd = env.expand_string(cmd) + (retval, output, oerror) = mbuild.run_command_output_file(cmd, + output_file, + osenv=osenv) + if retval: + mbuild.msgb("XED CMDLINE TEST", "failed. retval={}".format(retval)) + if output: + xbc.dump_lines("[STDOUT]", output) + if oerror: + xbc.dump_lines("[STDERR]", oerror) + else: + mbuild.msgb("XED CMDLINE TEST", "passed") + + return retval + +def _run_canned_tests(env,osenv): + """Run the tests from the tests subdirectory""" + retval = 0 # success + env['test_dir'] = env.escape_string(mbuild.join(env['src_dir'],'tests')) + cmd = "%(python)s %(test_dir)s/run-cmd.py --build-dir %(build_dir)s/examples " + + dirs = ['tests-base', 'tests-knc', 'tests-avx512', 'tests-xop'] + for d in dirs: + x = env.escape_string(mbuild.join(env['test_dir'],d)) + cmd += " --tests %s " % (x) + + # add test restriction/subetting codes + codes = [] + if env['encoder']: + codes.append('ENC') + if env['decoder']: + codes.append('DEC') + if env['avx']: + codes.append('AVX') + if env['knc']: + codes.append('KNC') + if env['skx']: + codes.append('AVX512X') + if env['knm'] or env['knl']: + codes.append('AVX512PF') + if env['avxhsw']: # hack misnomer for BSF/BSR/TZCNT/LZCNT tests + codes.append('HSW') + if env['amd_enabled'] and env['avx']: + codes.append('XOP') + for c in codes: + cmd += ' -c ' + c + + output_file = env.build_dir_join('TEST.OUT.txt') + cmd = env.expand_string(cmd) + if mbuild.verbose(2): + mbuild.msgb("TEST COMMAND", "%s > %s" %(cmd,str(output_file))) + (retcode, stdout, stderr) = mbuild.run_command_output_file(cmd, + output_file, + osenv=osenv) + if retcode == 1: + for l in stdout: + print l.rstrip() + + for l in stdout: + l = l.rstrip() + if re.search(r'^[[](TESTS|ERRORS|SKIPPED|PASS_PCT|FAIL)[]]',l): + mbuild.msgb("TESTSUMMARY", l) + if retcode == 0: + mbuild.msgb("CANNED TESTS", "PASSED") + else: + mbuild.msgb("CANNED TESTS", "FAILED") + retval = 1 # failure + + return retval + +def run_tests(env): + """Run the tests""" + + if 'test' not in env['targets']: + return 0 # success + mbuild.msgb("RUNNING TESTS") + osenv = _test_setup(env) + + retval_cmdline = 0 + if env['decoder']: + retval_cmdline = _test_cmdline_decoder(env,osenv) + retval_canned = _run_canned_tests(env,osenv) + if retval_canned or retval_cmdline: + mbuild.msgb("OVERALL TESTING", "failed") + return 1 # failure + return 0 # success + +def verify_args(env): + if not env['avx']: + env['avxhsw']=False + env['ivbavx']=False + env['fma']=False + + if not env['ivbavx']: + env['avxhsw'] = False + env['fma']=False + + if not env['avxhsw']: + env['fma']=False + + if env['knc']: + mbuild.warn("Disabling AVX512, MEMORY-FUTURE for KNC build\n\n\n") + env['knl'] = False + env['knm'] = False + env['skx'] = False + env['avx512_future'] = False + env['memory_future'] = False + env['future'] = False + + if not env['future']: + env['avx512_future'] = False + env['memory_future'] = False + + if not env['skx'] and not env['skl'] and not env['glm']: + env['mpx'] = False + + # SKX implies SKL + if env['skx']: + env['skl'] = True + + # no SKL implies no SKX (order matters w/the previous) + if not env['skl']: + env['skx'] = False + + if not env['glm']: + env['sha'] = False + + if env['use_elf_dwarf_precompiled']: + env['use_elf_dwarf'] = True + +def work(env): + """External entry point for non-command line invocations. + Initialize the environment, build libxed, the examples, the kit + and run the tests""" + + xbc.prep(env) + env['xed_dir'] = env['src_dir'] + verify_args(env) + start_time=mbuild.get_time() + update_version(env) + init_once(env) + init(env) + if 'clean' in env['targets'] or env['clean']: + xbc.xed_remove_files_glob(env) + if len(env['targets'])<=1: + xbc.cexit(0) + + mbuild.cmkdir(env['build_dir']) + mbuild.cmkdir(mbuild.join(env['build_dir'], 'include-private')) + work_queue = mbuild.work_queue_t(env['jobs']) + + build_libxed(env, work_queue) + legal_header_tagging(env) + build_examples(env) + build_kit(env,work_queue) + make_doxygen_build(env,work_queue) + retval = run_tests(env) + + end_time=mbuild.get_time() + mbuild.msgb("ELAPSED TIME", mbuild.get_elapsed_time(start_time, + end_time)) + mbuild.msgb("RETVAL={}".format(retval)) + return retval + +# for compatibility with older user script conventions +def set_xed_defaults(env): + xbc.set_xed_defaults(env) + +def execute(): + """Main external entry point for command line invocations""" + env = mkenv() + # xed_args() is skip-able for remote (import) invocation. The env + # from mkenv can be updated programmatically. One must call + # xbc.set_xed_defaults(env) if not calling xed_args(env) + xed_args(env) # parse command line knobs + retval = work(env) + return retval +