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c31ccf70bd
* adding PREFETCHW to silvermont and broadwell avoids issue with CPUID bit referring to non-exising isa-set in --no-amd builds. PREFETCHW opcode was previously a NOP on pentium-pro-and-later so no chip-check violation. * A little bit of a stroke of luck here: the ISA_SET PREFETCHW shows up in the isa-set enum and in the chip hierarchy, but there are no instructions in the PREFETCHW ISA_SET. The PREFETCHW instruction is in the PREFETCH_NOP ISA_SET and is checked for validity that way. The only major downside of this approach is that the cpuid bit for PREFETCHW is not displayed properly when queried. Change-Id: Ic20f9dc86d2a43367cc623794b21ce51811f91b0 (cherry picked from commit 2a030ad113265e3b71633c59dc0084d0bf609edd)
37 lines
1.1 KiB
INI
37 lines
1.1 KiB
INI
#BEGIN_LEGAL
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#
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#Copyright (c) 2017 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# AMD extensions
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dec-instructions : xed-amd-3dnow.txt
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enc-instructions : xed-amd-3dnow.txt
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dec-instructions : xed-amd-base.txt
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enc-instructions : xed-amd-base.txt
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dec-instructions : xed-amd-svm.txt
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enc-instructions : xed-amd-svm.txt
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enc-instructions : xed-amd-sse4a.txt
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dec-instructions : xed-amd-sse4a.txt
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enc-instructions : xed-amd-clzero.txt
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dec-instructions : xed-amd-clzero.txt
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chip-models : xed-amd-chips.txt
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cpuid : cpuid-amd.xed.txt
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