mirror of
https://github.com/RPCSX/xed.git
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Change-Id: I166833daaa56c33eca01bdf7b9aa6e74a490ba9a (cherry picked from commit 1212ba962dff6dfbfa0bd2469327ff447ce59058)
194 lines
6.3 KiB
Python
194 lines
6.3 KiB
Python
#!/usr/bin/env python
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# -*- python -*-
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#BEGIN_LEGAL
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#
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#Copyright (c) 2017 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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from __future__ import print_function
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import re
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from patterns import *
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from genutil import *
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import enumer
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# $$ reg_info_t
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class reg_info_t(object):
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def __init__(self, name, type, width,
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max_enclosing_reg,
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ordinal,
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hreg=False,
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max_enclosing_reg_32=None,
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display_str=None):
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self.name = name.upper()
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if display_str:
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self.display_str = display_str
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else:
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self.display_str = self.name
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self.type = type.upper()
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self.width = width
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self.max_enclosing_reg = max_enclosing_reg
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self.max_enclosing_reg_32 = max_enclosing_reg_32
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self.ordinal = ordinal
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self.hreg = hreg # the AH,BH,CH,DH registers
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if self.type == 'GPR':
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if self.hreg:
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self.rtype = self.type + str(self.width) + self.hreg
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else:
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self.rtype = self.type + str(self.width)
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else:
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self.rtype = self.type
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def refine_regs_input(lines):
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"""Return a list of reg_info_t. Skip comments and blank lines"""
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global comment_pattern
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all_ri = []
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reg_width_dict = {}
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for line in lines:
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pline = comment_pattern.sub('',line).strip()
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if pline == '':
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continue
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wrds = pline.split()
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n = len(wrds)
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# if there are only 3 fields, duplicate the first field as the 4th field
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if n == 3:
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n = 4
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first = wrds[0]
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wrds.append(first)
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if n == 6 and (wrds[5] not in [ 'h', '-']):
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die("regs-read: Illegal final token on line: " + line)
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if n < 4 or n > 7:
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die("regs-read: Bad number of tokens on line: " + line)
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name = wrds[0]
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rtype = wrds[1]
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width = wrds[2]
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max_enclosing_reg = wrds[3]
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max_enclosing_reg_32 = None
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if '/' in max_enclosing_reg:
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(max_enclosing_reg, max_enclosing_reg_32) = max_enclosing_reg.split('/')
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ordinal = 0
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if n >= 5:
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ordinal = int(wrds[4])
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hreg = None
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if n >= 6:
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hreg = wrds[5]
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if hreg != 'h':
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hreg = None
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# 7th operand is a display string to replace the name in the enumerations
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display_str = None
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if n >= 7:
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display_str = wrds[6]
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ri = reg_info_t(name,
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rtype,
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width,
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max_enclosing_reg,
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ordinal,
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hreg,
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max_enclosing_reg_32,
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display_str)
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all_ri.append(ri)
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# CR/DR regs have slashes in the width for 32/64b mode. They
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# are not relevant for the register enclosing computation that
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# this code is facilitating.
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if width == 'NA':
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# the pseudo registers use NA as their width. We do not
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# care about the enclosing register computation for them.
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short_width = '1'
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elif '/' in width:
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short_width = re.sub(r'/.*','',width)
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else:
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short_width = width
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iw = int(short_width)
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if name in reg_width_dict:
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if reg_width_dict[name] < iw:
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reg_width_dict[name] = iw
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else:
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reg_width_dict[name] = iw
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regs_name_list = []
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regs_dict = {}
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for ri in all_ri:
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# add name to list to preserve original order
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if ri.name not in regs_dict:
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regs_dict[ri.name] = ri
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regs_name_list.append(ri.name)
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elif regs_dict[ri.name].width < ri.width: # replace narrower
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regs_dict[ri.name] = ri
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else:
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old_enclosing = regs_dict[ri.name].max_enclosing_reg
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a = reg_width_dict[old_enclosing]
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b = reg_width_dict[ri.max_enclosing_reg]
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print("LER: Comparing {} and {} for {}".format(old_enclosing,
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ri.max_enclosing_reg,
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ri.name))
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if a < b:
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# take the wider enclosing registers
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print("\ttaking new wider version")
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regs_dict[ri.name] = ri
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# return a list resembling the original order
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regs_list = []
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for nm in regs_name_list:
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regs_list.append(regs_dict[nm])
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return regs_list
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def _key_reg_ordinal(x):
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return x.ordinal
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def _reg_cmp(a,b): # FIXME:2017-06-10: PY3 port, no longer used
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if a.ordinal < b.ordinal:
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return -1
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elif a.ordinal > b.ordinal:
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return 1
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return 0
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def rearrange_regs(regs_list):
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"""Return a list of enumer.enumer_values_t objects to be passed to
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enum_txt_writer"""
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groups = uniqueify( [ x.rtype for x in regs_list])
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msgb("RGROUPS", str(groups))
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enumvals = []
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for g in groups:
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k = list(filter(lambda x: x.rtype == g, regs_list))
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k.sort(key=_key_reg_ordinal)
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first = '%s_FIRST' % (g)
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last = '%s_LAST' % (g)
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# first
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enumvals.append(enumer.enumer_value_t(k[0].name,
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display_str=k[0].display_str))
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enumvals.append(enumer.enumer_value_t(first,
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value=k[0].name,
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doxygen='//< PSEUDO'))
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# everything in the middle
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if len(k) > 1:
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enumvals.extend(
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[ enumer.enumer_value_t(x.name,
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display_str=x.display_str) for x in k[1:] ] )
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#last
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enumvals.append(enumer.enumer_value_t(last,
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value=k[-1].name,
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doxygen='//<PSEUDO'))
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return enumvals
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