mirror of
https://github.com/RPCSX/xed.git
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236 lines
7.3 KiB
Plaintext
236 lines
7.3 KiB
Plaintext
#BEGIN_LEGAL
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#
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#Copyright (c) 2016 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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xed_reg_enum_t XMM_SE()::
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mode16 | OUTREG=XMM_SE32()
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mode32 | OUTREG=XMM_SE32()
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mode64 | OUTREG=XMM_SE64()
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xed_reg_enum_t XMM_SE64()::
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ESRC=0x0 | OUTREG=XED_REG_XMM0
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ESRC=0x1 | OUTREG=XED_REG_XMM1
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ESRC=0x2 | OUTREG=XED_REG_XMM2
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ESRC=0x3 | OUTREG=XED_REG_XMM3
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ESRC=0x4 | OUTREG=XED_REG_XMM4
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ESRC=0x5 | OUTREG=XED_REG_XMM5
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ESRC=0x6 | OUTREG=XED_REG_XMM6
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ESRC=0x7 | OUTREG=XED_REG_XMM7
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ESRC=0x8 | OUTREG=XED_REG_XMM8
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ESRC=0x9 | OUTREG=XED_REG_XMM9
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ESRC=0xA | OUTREG=XED_REG_XMM10
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ESRC=0xB | OUTREG=XED_REG_XMM11
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ESRC=0xC | OUTREG=XED_REG_XMM12
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ESRC=0xD | OUTREG=XED_REG_XMM13
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ESRC=0xE | OUTREG=XED_REG_XMM14
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ESRC=0xF | OUTREG=XED_REG_XMM15
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xed_reg_enum_t XMM_SE32()::
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ESRC=0 | OUTREG=XED_REG_XMM0 enc
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ESRC=1 | OUTREG=XED_REG_XMM1 enc
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ESRC=2 | OUTREG=XED_REG_XMM2 enc
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ESRC=3 | OUTREG=XED_REG_XMM3 enc
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ESRC=4 | OUTREG=XED_REG_XMM4 enc
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ESRC=5 | OUTREG=XED_REG_XMM5 enc
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ESRC=6 | OUTREG=XED_REG_XMM6 enc
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ESRC=7 | OUTREG=XED_REG_XMM7 enc
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# ignoring the high bit in non64b modes. Really just 0...7
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ESRC=0x8 | OUTREG=XED_REG_XMM0
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ESRC=0x9 | OUTREG=XED_REG_XMM1
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ESRC=0xA | OUTREG=XED_REG_XMM2
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ESRC=0xB | OUTREG=XED_REG_XMM3
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ESRC=0xC | OUTREG=XED_REG_XMM4
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ESRC=0xD | OUTREG=XED_REG_XMM5
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ESRC=0xE | OUTREG=XED_REG_XMM6
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ESRC=0xF | OUTREG=XED_REG_XMM7
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xed_reg_enum_t YMM_SE()::
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mode16 | OUTREG=YMM_SE32()
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mode32 | OUTREG=YMM_SE32()
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mode64 | OUTREG=YMM_SE64()
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xed_reg_enum_t YMM_SE64()::
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ESRC=0x0 | OUTREG=XED_REG_YMM0
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ESRC=0x1 | OUTREG=XED_REG_YMM1
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ESRC=0x2 | OUTREG=XED_REG_YMM2
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ESRC=0x3 | OUTREG=XED_REG_YMM3
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ESRC=0x4 | OUTREG=XED_REG_YMM4
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ESRC=0x5 | OUTREG=XED_REG_YMM5
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ESRC=0x6 | OUTREG=XED_REG_YMM6
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ESRC=0x7 | OUTREG=XED_REG_YMM7
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ESRC=0x8 | OUTREG=XED_REG_YMM8
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ESRC=0x9 | OUTREG=XED_REG_YMM9
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ESRC=0xA | OUTREG=XED_REG_YMM10
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ESRC=0xB | OUTREG=XED_REG_YMM11
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ESRC=0xC | OUTREG=XED_REG_YMM12
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ESRC=0xD | OUTREG=XED_REG_YMM13
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ESRC=0xE | OUTREG=XED_REG_YMM14
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ESRC=0xF | OUTREG=XED_REG_YMM15
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xed_reg_enum_t YMM_SE32()::
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ESRC=0 | OUTREG=XED_REG_YMM0 enc
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ESRC=1 | OUTREG=XED_REG_YMM1 enc
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ESRC=2 | OUTREG=XED_REG_YMM2 enc
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ESRC=3 | OUTREG=XED_REG_YMM3 enc
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ESRC=4 | OUTREG=XED_REG_YMM4 enc
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ESRC=5 | OUTREG=XED_REG_YMM5 enc
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ESRC=6 | OUTREG=XED_REG_YMM6 enc
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ESRC=7 | OUTREG=XED_REG_YMM7 enc
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# ignoring the high bit in non64b modes. Really just 0...7
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ESRC=0x8 | OUTREG=XED_REG_YMM0
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ESRC=0x9 | OUTREG=XED_REG_YMM1
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ESRC=0xA | OUTREG=XED_REG_YMM2
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ESRC=0xB | OUTREG=XED_REG_YMM3
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ESRC=0xC | OUTREG=XED_REG_YMM4
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ESRC=0xD | OUTREG=XED_REG_YMM5
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ESRC=0xE | OUTREG=XED_REG_YMM6
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ESRC=0xF | OUTREG=XED_REG_YMM7
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xed_reg_enum_t XMM_N()::
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mode16 | OUTREG=XMM_N_32():
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mode32 | OUTREG=XMM_N_32():
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mode64 | OUTREG=XMM_N_64():
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xed_reg_enum_t XMM_N_32()::
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VEXDEST210=7 | OUTREG=XED_REG_XMM0
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VEXDEST210=6 | OUTREG=XED_REG_XMM1
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VEXDEST210=5 | OUTREG=XED_REG_XMM2
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VEXDEST210=4 | OUTREG=XED_REG_XMM3
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VEXDEST210=3 | OUTREG=XED_REG_XMM4
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VEXDEST210=2 | OUTREG=XED_REG_XMM5
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VEXDEST210=1 | OUTREG=XED_REG_XMM6
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VEXDEST210=0 | OUTREG=XED_REG_XMM7
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xed_reg_enum_t XMM_N_64()::
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VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
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VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
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VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
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VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
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VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
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VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
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VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
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VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7
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VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
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VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
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VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
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VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
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VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
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VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
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VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
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VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15
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xed_reg_enum_t YMM_N()::
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mode16 | OUTREG=YMM_N_32():
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mode32 | OUTREG=YMM_N_32():
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mode64 | OUTREG=YMM_N_64():
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xed_reg_enum_t YMM_N_32()::
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VEXDEST210=7 | OUTREG=XED_REG_YMM0
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VEXDEST210=6 | OUTREG=XED_REG_YMM1
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VEXDEST210=5 | OUTREG=XED_REG_YMM2
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VEXDEST210=4 | OUTREG=XED_REG_YMM3
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VEXDEST210=3 | OUTREG=XED_REG_YMM4
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VEXDEST210=2 | OUTREG=XED_REG_YMM5
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VEXDEST210=1 | OUTREG=XED_REG_YMM6
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VEXDEST210=0 | OUTREG=XED_REG_YMM7
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xed_reg_enum_t YMM_N_64()::
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VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
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VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
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VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
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VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
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VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
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VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
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VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
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VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
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VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
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VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
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VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
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VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
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VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
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VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
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VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
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VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15
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xed_reg_enum_t YMM_R()::
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mode16 | OUTREG=YMM_R_32():
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mode32 | OUTREG=YMM_R_32():
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mode64 | OUTREG=YMM_R_64():
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xed_reg_enum_t YMM_R_32()::
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REG=0 | OUTREG=XED_REG_YMM0
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REG=1 | OUTREG=XED_REG_YMM1
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REG=2 | OUTREG=XED_REG_YMM2
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REG=3 | OUTREG=XED_REG_YMM3
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REG=4 | OUTREG=XED_REG_YMM4
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REG=5 | OUTREG=XED_REG_YMM5
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REG=6 | OUTREG=XED_REG_YMM6
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REG=7 | OUTREG=XED_REG_YMM7
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xed_reg_enum_t YMM_R_64()::
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REXR=0 REG=0 | OUTREG=XED_REG_YMM0
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REXR=0 REG=1 | OUTREG=XED_REG_YMM1
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REXR=0 REG=2 | OUTREG=XED_REG_YMM2
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REXR=0 REG=3 | OUTREG=XED_REG_YMM3
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REXR=0 REG=4 | OUTREG=XED_REG_YMM4
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REXR=0 REG=5 | OUTREG=XED_REG_YMM5
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REXR=0 REG=6 | OUTREG=XED_REG_YMM6
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REXR=0 REG=7 | OUTREG=XED_REG_YMM7
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REXR=1 REG=0 | OUTREG=XED_REG_YMM8
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REXR=1 REG=1 | OUTREG=XED_REG_YMM9
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REXR=1 REG=2 | OUTREG=XED_REG_YMM10
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REXR=1 REG=3 | OUTREG=XED_REG_YMM11
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REXR=1 REG=4 | OUTREG=XED_REG_YMM12
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REXR=1 REG=5 | OUTREG=XED_REG_YMM13
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REXR=1 REG=6 | OUTREG=XED_REG_YMM14
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REXR=1 REG=7 | OUTREG=XED_REG_YMM15
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xed_reg_enum_t YMM_B()::
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mode16 | OUTREG=YMM_B_32():
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mode32 | OUTREG=YMM_B_32():
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mode64 | OUTREG=YMM_B_64():
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xed_reg_enum_t YMM_B_32()::
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RM=0 | OUTREG=XED_REG_YMM0
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RM=1 | OUTREG=XED_REG_YMM1
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RM=2 | OUTREG=XED_REG_YMM2
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RM=3 | OUTREG=XED_REG_YMM3
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RM=4 | OUTREG=XED_REG_YMM4
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RM=5 | OUTREG=XED_REG_YMM5
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RM=6 | OUTREG=XED_REG_YMM6
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RM=7 | OUTREG=XED_REG_YMM7
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xed_reg_enum_t YMM_B_64()::
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REXB=0 RM=0 | OUTREG=XED_REG_YMM0
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REXB=0 RM=1 | OUTREG=XED_REG_YMM1
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REXB=0 RM=2 | OUTREG=XED_REG_YMM2
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REXB=0 RM=3 | OUTREG=XED_REG_YMM3
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REXB=0 RM=4 | OUTREG=XED_REG_YMM4
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REXB=0 RM=5 | OUTREG=XED_REG_YMM5
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REXB=0 RM=6 | OUTREG=XED_REG_YMM6
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REXB=0 RM=7 | OUTREG=XED_REG_YMM7
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REXB=1 RM=0 | OUTREG=XED_REG_YMM8
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REXB=1 RM=1 | OUTREG=XED_REG_YMM9
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REXB=1 RM=2 | OUTREG=XED_REG_YMM10
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REXB=1 RM=3 | OUTREG=XED_REG_YMM11
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REXB=1 RM=4 | OUTREG=XED_REG_YMM12
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REXB=1 RM=5 | OUTREG=XED_REG_YMM13
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REXB=1 RM=6 | OUTREG=XED_REG_YMM14
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REXB=1 RM=7 | OUTREG=XED_REG_YMM15
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