mirror of
https://github.com/RPCSX/xed.git
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28056 lines
885 KiB
Plaintext
28056 lines
885 KiB
Plaintext
#BEGIN_LEGAL
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#
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#Copyright (c) 2016 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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#
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#
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#
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# ***** GENERATED FILE -- DO NOT EDIT! *****
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# ***** GENERATED FILE -- DO NOT EDIT! *****
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# ***** GENERATED FILE -- DO NOT EDIT! *****
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#
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#
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#
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EVEX_INSTRUCTIONS()::
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# EMITTING VADDPD (VADDPD-128-1)
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{
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ICLASS: VADDPD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MASKOP_EVEX
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PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
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OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
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IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
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}
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{
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ICLASS: VADDPD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
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IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
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}
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# EMITTING VADDPD (VADDPD-256-1)
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{
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ICLASS: VADDPD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MASKOP_EVEX
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PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
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OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
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IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
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}
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{
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ICLASS: VADDPD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
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IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
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}
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# EMITTING VADDPS (VADDPS-128-1)
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{
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ICLASS: VADDPS
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MASKOP_EVEX
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PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
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OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
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IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
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}
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{
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ICLASS: VADDPS
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
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IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
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}
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# EMITTING VADDPS (VADDPS-256-1)
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{
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ICLASS: VADDPS
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MASKOP_EVEX
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PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
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OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
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IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
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}
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{
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ICLASS: VADDPS
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E2
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REAL_OPCODE: Y
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ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
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IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
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}
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# EMITTING VALIGND (VALIGND-128-1)
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{
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ICLASS: VALIGND
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
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OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
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IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
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}
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{
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ICLASS: VALIGND
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
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IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
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}
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# EMITTING VALIGND (VALIGND-256-1)
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{
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ICLASS: VALIGND
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
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OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
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IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
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}
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{
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ICLASS: VALIGND
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
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IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
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}
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# EMITTING VALIGNQ (VALIGNQ-128-1)
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{
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ICLASS: VALIGNQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
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OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
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IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
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}
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{
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ICLASS: VALIGNQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_128
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
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IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
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}
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# EMITTING VALIGNQ (VALIGNQ-256-1)
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{
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ICLASS: VALIGNQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
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OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
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IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
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}
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{
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ICLASS: VALIGNQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_256
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
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IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
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}
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# EMITTING VANDNPD (VANDNPD-128-1)
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_128
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
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OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
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IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
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}
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_128
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
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IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
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}
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# EMITTING VANDNPD (VANDNPD-256-1)
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_256
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
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OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
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IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
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}
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_256
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
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IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
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}
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# EMITTING VANDNPD (VANDNPD-512-1)
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
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OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
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IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
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}
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{
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ICLASS: VANDNPD
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CPL: 3
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CATEGORY: LOGICAL_FP
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512DQ_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
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IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
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}
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# EMITTING VANDNPS (VANDNPS-128-1)
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{
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|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPS (VANDNPS-256-1)
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPS (VANDNPS-512-1)
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-128-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-256-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-512-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-128-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-256-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-512-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPD (VBLENDMPD-128-1)
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPD (VBLENDMPD-256-1)
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPS (VBLENDMPS-128-1)
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPS (VBLENDMPS-256-1)
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32
|
|
IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X8
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32
|
|
IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64
|
|
IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64
|
|
IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32
|
|
IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32
|
|
IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32
|
|
IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X8
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32
|
|
IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64
|
|
IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64
|
|
IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-256-1)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-256-2)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-128-1)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-128-2)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-256-1)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-256-2)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPD (VCMPPD-128-1)
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPD (VCMPPD-256-1)
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPS (VCMPPS-128-1)
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPS (VCMPPS-256-1)
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PS (VCVTPD2PS-128-1)
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PS (VCVTPD2PS-256-1)
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PS (VCVTPH2PS-128-1)
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16
|
|
IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PS (VCVTPH2PS-256-1)
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16
|
|
IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PD (VCVTPS2PD-128-1)
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PD (VCVTPS2PD-256-1)
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-128-1)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-128-2)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-256-1)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-256-2)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-128-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-256-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-512-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPD (VDIVPD-128-1)
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPD (VDIVPD-256-1)
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPS (VDIVPS-128-1)
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPS (VDIVPS-256-1)
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-128-1)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-128-2)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-256-1)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-256-2)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-128-1)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-128-2)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-256-1)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-256-2)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PD (VFMADD132PD-128-1)
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PD (VFMADD132PD-256-1)
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PS (VFMADD132PS-128-1)
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PS (VFMADD132PS-256-1)
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PD (VFMADD213PD-128-1)
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PD (VFMADD213PD-256-1)
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PS (VFMADD213PS-128-1)
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PS (VFMADD213PS-256-1)
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PD (VFMADD231PD-128-1)
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PD (VFMADD231PD-256-1)
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PS (VFMADD231PS-128-1)
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PS (VFMADD231PS-256-1)
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PD (VFMSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PD (VFMSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PS (VFMSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PS (VFMSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PD (VFMSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PD (VFMSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PS (VFMSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PS (VFMSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PD (VFMSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PD (VFMSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PS (VFMSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PS (VFMSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PD (VFNMADD132PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PD (VFNMADD132PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PS (VFNMADD132PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PS (VFNMADD132PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PD (VFNMADD213PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PD (VFNMADD213PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PS (VFNMADD213PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PS (VFNMADD213PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PD (VFNMADD231PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PD (VFNMADD231PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PS (VFNMADD231PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PS (VFNMADD231PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-128-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-256-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-512-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-128-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-256-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-512-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSSD (VFPCLASSSD-128-1)
|
|
{
|
|
ICLASS: VFPCLASSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSSS (VFPCLASSSS-128-1)
|
|
{
|
|
ICLASS: VFPCLASSSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPD (VGATHERDPD-128-1)
|
|
{
|
|
ICLASS: VGATHERDPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64
|
|
IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPD (VGATHERDPD-256-1)
|
|
{
|
|
ICLASS: VGATHERDPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64
|
|
IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPS (VGATHERDPS-128-1)
|
|
{
|
|
ICLASS: VGATHERDPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32
|
|
IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPS (VGATHERDPS-256-1)
|
|
{
|
|
ICLASS: VGATHERDPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32
|
|
IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPD (VGATHERQPD-128-1)
|
|
{
|
|
ICLASS: VGATHERQPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64
|
|
IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPD (VGATHERQPD-256-1)
|
|
{
|
|
ICLASS: VGATHERQPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64
|
|
IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPS (VGATHERQPS-128-1)
|
|
{
|
|
ICLASS: VGATHERQPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:q:f32
|
|
IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPS (VGATHERQPS-256-1)
|
|
{
|
|
ICLASS: VGATHERQPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32
|
|
IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPD (VGETEXPPD-128-1)
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPD (VGETEXPPD-256-1)
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPS (VGETEXPPS-128-1)
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPS (VGETEXPPS-256-1)
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPD (VGETMANTPD-128-1)
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPD (VGETMANTPD-256-1)
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPS (VGETMANTPS-128-1)
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPS (VGETMANTPS-256-1)
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1)
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1)
|
|
{
|
|
ICLASS: VINSERTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1)
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1)
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1)
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1)
|
|
{
|
|
ICLASS: VINSERTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1)
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1)
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPD (VMAXPD-128-1)
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPD (VMAXPD-256-1)
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPS (VMAXPS-128-1)
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPS (VMAXPS-256-1)
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPD (VMINPD-128-1)
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPD (VMINPD-256-1)
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPS (VMINPS-128-1)
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPS (VMINPS-256-1)
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-1)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-2)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-3)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-1)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-2)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-3)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-1)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-2)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-3)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-1)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-2)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-3)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDDUP (VMOVDDUP-128-1)
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
|
|
IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDDUP (VMOVDDUP-256-1)
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-1)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-2)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-3)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-1)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-2)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-3)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-1)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-2)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-3)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-1)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-2)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-3)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-1)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-2)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-3)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-1)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-2)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-3)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-1)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-2)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-3)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-1)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-2)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-3)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQ (VMOVNTDQ-128-1)
|
|
{
|
|
ICLASS: VMOVNTDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32
|
|
IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQ (VMOVNTDQ-256-1)
|
|
{
|
|
ICLASS: VMOVNTDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32
|
|
IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQA (VMOVNTDQA-128-1)
|
|
{
|
|
ICLASS: VMOVNTDQA
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQA (VMOVNTDQA-256-1)
|
|
{
|
|
ICLASS: VMOVNTDQA
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPD (VMOVNTPD-128-1)
|
|
{
|
|
ICLASS: VMOVNTPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64
|
|
IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPD (VMOVNTPD-256-1)
|
|
{
|
|
ICLASS: VMOVNTPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64
|
|
IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPS (VMOVNTPS-128-1)
|
|
{
|
|
ICLASS: VMOVNTPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32
|
|
IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPS (VMOVNTPS-256-1)
|
|
{
|
|
ICLASS: VMOVNTPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32
|
|
IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSHDUP (VMOVSHDUP-128-1)
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSHDUP (VMOVSHDUP-256-1)
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSLDUP (VMOVSLDUP-128-1)
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSLDUP (VMOVSLDUP-256-1)
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-1)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-2)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-3)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-1)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-2)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-3)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-1)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-2)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-3)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-1)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-2)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-3)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPD (VMULPD-128-1)
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPD (VMULPD-256-1)
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPS (VMULPS-128-1)
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPS (VMULPS-256-1)
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-128-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-256-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-512-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-128-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-256-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-512-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-128-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-256-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-512-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8
|
|
IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8
|
|
IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSD (VPABSD-128-1)
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSD (VPABSD-256-1)
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSQ (VPABSQ-128-1)
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64
|
|
IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSQ (VPABSQ-256-1)
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64
|
|
IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-128-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-256-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
|
|
IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
|
|
IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-512-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
|
|
IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16
|
|
IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-128-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-256-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-512-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
|
|
IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-128-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-256-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-512-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-128-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-256-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-512-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-128-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-256-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-512-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-128-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-256-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-512-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDD (VPADDD-128-1)
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDD (VPADDD-256-1)
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDQ (VPADDQ-128-1)
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDQ (VPADDQ-256-1)
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-128-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-256-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-512-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-128-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-256-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-512-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-128-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-256-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-512-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-128-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-256-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-512-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-128-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-256-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-512-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-128-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-256-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-512-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDD (VPANDD-128-1)
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDD (VPANDD-256-1)
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDND (VPANDND-128-1)
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDND (VPANDND-256-1)
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDNQ (VPANDNQ-128-1)
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDNQ (VPANDNQ-256-1)
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDQ (VPANDQ-128-1)
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDQ (VPANDQ-256-1)
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-128-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-256-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-512-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-128-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-256-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-512-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-128-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-256-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-512-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMD (VPBLENDMD-128-1)
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMD (VPBLENDMD-256-1)
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMQ (VPBLENDMQ-128-1)
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMQ (VPBLENDMQ-256-1)
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-128-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-256-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-512-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-3)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-3)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTMB2Q
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8
|
|
IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTMB2Q
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8
|
|
IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTMW2D
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16
|
|
IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTMW2D
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-128-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-256-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-512-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPD (VPCMPD-128-1)
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPD (VPCMPD-256-1)
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-128-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-256-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-512-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQD (VPCMPEQD-128-1)
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQD (VPCMPEQD-256-1)
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQQ (VPCMPEQQ-128-1)
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQQ (VPCMPEQQ-256-1)
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-128-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-256-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-512-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-128-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-256-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-512-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTD (VPCMPGTD-128-1)
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTD (VPCMPGTD-256-1)
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTQ (VPCMPGTQ-128-1)
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTQ (VPCMPGTQ-256-1)
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-128-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-256-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-512-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPQ (VPCMPQ-128-1)
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPQ (VPCMPQ-256-1)
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-128-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-256-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-512-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUD (VPCMPUD-128-1)
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUD (VPCMPUD-256-1)
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUQ (VPCMPUQ-128-1)
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUQ (VPCMPUQ-256-1)
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-128-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-256-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-512-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-128-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-256-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-512-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTD (VPCONFLICTD-128-1)
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTD (VPCONFLICTD-256-1)
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1)
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1)
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMD (VPERMD-256-1)
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2D (VPERMI2D-128-1)
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2D (VPERMI2D-256-1)
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PD (VPERMI2PD-128-1)
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PD (VPERMI2PD-256-1)
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PS (VPERMI2PS-128-1)
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PS (VPERMI2PS-256-1)
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2Q (VPERMI2Q-128-1)
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2Q (VPERMI2Q-256-1)
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-128-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-256-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-512-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-128-1)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-128-2)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-256-1)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-256-2)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-128-1)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-128-2)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-256-1)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-256-2)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-256-1)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-256-2)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPS (VPERMPS-256-1)
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-256-1)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-256-2)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2D (VPERMT2D-128-1)
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2D (VPERMT2D-256-1)
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PD (VPERMT2PD-128-1)
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PD (VPERMT2PD-256-1)
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PS (VPERMT2PS-128-1)
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PS (VPERMT2PS-256-1)
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2Q (VPERMT2Q-128-1)
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2Q (VPERMT2Q-256-1)
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-128-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-256-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-512-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-128-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-256-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-512-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-128-1)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-128-2)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-256-1)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-256-2)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-128-1)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-128-2)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-256-1)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-256-2)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRB (VPEXTRB-128-1)
|
|
{
|
|
ICLASS: VPEXTRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE
|
|
PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE()
|
|
OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRD (VPEXTRD-128-1)
|
|
{
|
|
ICLASS: VPEXTRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRQ (VPEXTRQ-128-1)
|
|
{
|
|
ICLASS: VPEXTRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRW (VPEXTRW-128-1)
|
|
{
|
|
ICLASS: VPEXTRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD
|
|
PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD()
|
|
OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRW (VPEXTRW-128-2)
|
|
{
|
|
ICLASS: VPEXTRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDD (VPGATHERDD-128-1)
|
|
{
|
|
ICLASS: VPGATHERDD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32
|
|
IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDD (VPGATHERDD-256-1)
|
|
{
|
|
ICLASS: VPGATHERDD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32
|
|
IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDQ (VPGATHERDQ-128-1)
|
|
{
|
|
ICLASS: VPGATHERDQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64
|
|
IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDQ (VPGATHERDQ-256-1)
|
|
{
|
|
ICLASS: VPGATHERDQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64
|
|
IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQD (VPGATHERQD-128-1)
|
|
{
|
|
ICLASS: VPGATHERQD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:q:u32
|
|
IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQD (VPGATHERQD-256-1)
|
|
{
|
|
ICLASS: VPGATHERQD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32
|
|
IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQQ (VPGATHERQQ-128-1)
|
|
{
|
|
ICLASS: VPGATHERQQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64
|
|
IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQQ (VPGATHERQQ-256-1)
|
|
{
|
|
ICLASS: VPGATHERQQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64
|
|
IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRB (VPINSRB-128-1)
|
|
{
|
|
ICLASS: VPINSRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b
|
|
IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER_BYTE
|
|
PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b
|
|
IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRD (VPINSRD-128-1)
|
|
{
|
|
ICLASS: VPINSRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRQ (VPINSRQ-128-1)
|
|
{
|
|
ICLASS: VPINSRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b
|
|
IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b
|
|
IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRW (VPINSRW-128-1)
|
|
{
|
|
ICLASS: VPINSRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b
|
|
IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER_WORD
|
|
PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b
|
|
IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTD (VPLZCNTD-128-1)
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTD (VPLZCNTD-256-1)
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTQ (VPLZCNTQ-128-1)
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTQ (VPLZCNTQ-256-1)
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-128-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-256-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-512-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-128-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-256-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-512-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-128-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-256-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-512-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSD (VPMAXSD-128-1)
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSD (VPMAXSD-256-1)
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSQ (VPMAXSQ-128-1)
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSQ (VPMAXSQ-256-1)
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-128-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-256-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-512-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-128-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-256-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-512-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUD (VPMAXUD-128-1)
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUD (VPMAXUD-256-1)
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUQ (VPMAXUQ-128-1)
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUQ (VPMAXUQ-256-1)
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-128-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-256-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-512-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-128-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-256-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-512-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSD (VPMINSD-128-1)
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSD (VPMINSD-256-1)
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSQ (VPMINSQ-128-1)
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSQ (VPMINSQ-256-1)
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-128-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-256-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-512-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-128-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-256-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-512-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUD (VPMINUD-128-1)
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUD (VPMINUD-256-1)
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUQ (VPMINUQ-128-1)
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUQ (VPMINUQ-256-1)
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-128-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-256-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-512-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-128-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8
|
|
IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-256-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8
|
|
IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-512-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8
|
|
IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-128-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32
|
|
IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-256-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32
|
|
IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-512-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32
|
|
IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-128-1)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-128-2)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-256-1)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-256-2)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-128-1)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-128-2)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-256-1)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-256-2)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-128-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-256-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-512-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-128-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-256-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-512-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-128-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-256-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-512-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-128-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-256-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-512-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-128-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64
|
|
IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-256-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64
|
|
IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-512-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64
|
|
IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-128-1)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-128-2)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-256-1)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-256-2)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-128-1)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-128-2)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-256-1)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-256-2)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-128-1)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-128-2)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-256-1)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-256-2)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-128-1)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-128-2)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-256-1)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-256-2)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-128-1)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-128-2)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-256-1)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-256-2)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-128-1)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-128-2)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-256-1)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-256-2)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-128-1)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-128-2)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-256-1)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-256-2)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-128-1)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-128-2)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-256-1)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-256-2)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-128-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16
|
|
IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-128-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-256-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16
|
|
IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-256-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-512-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16
|
|
IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-512-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBD (VPMOVSXBD-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBD (VPMOVSXBD-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8
|
|
IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-512-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32
|
|
IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32
|
|
IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWD (VPMOVSXWD-128-1)
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWD (VPMOVSXWD-256-1)
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16
|
|
IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-128-1)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-128-2)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-256-1)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-256-2)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-512-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-512-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-128-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16
|
|
IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-256-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16
|
|
IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-512-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16
|
|
IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-128-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-128-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-256-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-256-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-512-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-512-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBD (VPMOVZXBD-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBD (VPMOVZXBD-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8
|
|
IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-512-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32
|
|
IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32
|
|
IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWD (VPMOVZXWD-128-1)
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWD (VPMOVZXWD-256-1)
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16
|
|
IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULDQ (VPMULDQ-128-1)
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULDQ (VPMULDQ-256-1)
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-128-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-256-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-512-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-128-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-256-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-512-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-128-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-256-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-512-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLD (VPMULLD-128-1)
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLD (VPMULLD-256-1)
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-128-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-256-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-512-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-128-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-256-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-512-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULUDQ (VPMULUDQ-128-1)
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULUDQ (VPMULUDQ-256-1)
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORD (VPORD-128-1)
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORD (VPORD-256-1)
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORQ (VPORQ-128-1)
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORQ (VPORQ-256-1)
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLD (VPROLD-128-1)
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLD (VPROLD-256-1)
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLQ (VPROLQ-128-1)
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLQ (VPROLQ-256-1)
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVD (VPROLVD-128-1)
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVD (VPROLVD-256-1)
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVQ (VPROLVQ-128-1)
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVQ (VPROLVQ-256-1)
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORD (VPRORD-128-1)
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORD (VPRORD-256-1)
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORQ (VPRORQ-128-1)
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORQ (VPRORQ-256-1)
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVD (VPRORVD-128-1)
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVD (VPRORVD-256-1)
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVQ (VPRORVQ-128-1)
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVQ (VPRORVQ-256-1)
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-128-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8
|
|
IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-256-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8
|
|
IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-512-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8
|
|
IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDD (VPSCATTERDD-128-1)
|
|
{
|
|
ICLASS: VPSCATTERDD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDD (VPSCATTERDD-256-1)
|
|
{
|
|
ICLASS: VPSCATTERDD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1)
|
|
{
|
|
ICLASS: VPSCATTERDQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1)
|
|
{
|
|
ICLASS: VPSCATTERDQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQD (VPSCATTERQD-128-1)
|
|
{
|
|
ICLASS: VPSCATTERQD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQD (VPSCATTERQD-256-1)
|
|
{
|
|
ICLASS: VPSCATTERQD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1)
|
|
{
|
|
ICLASS: VPSCATTERQQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1)
|
|
{
|
|
ICLASS: VPSCATTERQQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-128-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-256-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-512-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFD (VPSHUFD-128-1)
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFD (VPSHUFD-256-1)
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-128-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-256-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-512-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-128-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-256-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-512-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-128-1)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-128-3)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-256-1)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-256-3)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-128-2)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-256-2)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-512-1)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-128-1)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-128-3)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-256-1)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-256-3)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVD (VPSLLVD-128-1)
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVD (VPSLLVD-256-1)
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVQ (VPSLLVQ-128-1)
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVQ (VPSLLVQ-256-1)
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-128-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-256-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-512-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-128-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-128-3)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-256-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-256-3)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-512-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-512-2)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-128-1)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-128-3)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-256-1)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-256-3)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-128-1)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-128-2)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-256-1)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-256-2)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVD (VPSRAVD-128-1)
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVD (VPSRAVD-256-1)
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVQ (VPSRAVQ-128-1)
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVQ (VPSRAVQ-256-1)
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-128-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-256-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-512-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-128-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-128-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-256-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-256-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-512-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-512-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-128-1)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-128-2)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-256-1)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-256-2)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-128-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-256-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-512-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-128-1)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-128-2)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-256-1)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-256-2)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVD (VPSRLVD-128-1)
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVD (VPSRLVD-256-1)
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVQ (VPSRLVQ-128-1)
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVQ (VPSRLVQ-256-1)
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-128-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-256-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-512-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-128-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-128-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-256-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-256-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-512-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-512-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-128-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-256-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-512-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBD (VPSUBD-128-1)
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBD (VPSUBD-256-1)
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBQ (VPSUBQ-128-1)
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBQ (VPSUBQ-256-1)
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-128-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-256-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-512-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-128-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-256-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-512-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-128-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-256-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-512-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-128-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-256-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-512-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-128-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-256-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-512-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGD (VPTERNLOGD-128-1)
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGD (VPTERNLOGD-256-1)
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1)
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1)
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-128-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-256-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-512-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMD (VPTESTMD-128-1)
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMD (VPTESTMD-256-1)
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMQ (VPTESTMQ-128-1)
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMQ (VPTESTMQ-256-1)
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-128-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-256-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-512-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-128-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-256-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-512-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMD (VPTESTNMD-128-1)
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMD (VPTESTNMD-256-1)
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMQ (VPTESTNMQ-128-1)
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMQ (VPTESTNMQ-256-1)
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-128-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-256-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-512-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORD (VPXORD-128-1)
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORD (VPXORD-256-1)
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORQ (VPXORQ-128-1)
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORQ (VPXORQ-256-1)
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-128-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-256-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-512-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-128-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-256-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-512-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGESD (VRANGESD-128-1)
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGESS (VRANGESS-128-1)
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PD (VRCP14PD-128-1)
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PD (VRCP14PD-256-1)
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PS (VRCP14PS-128-1)
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PS (VRCP14PS-256-1)
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-128-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-256-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-512-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-128-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-256-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-512-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCESD (VREDUCESD-128-1)
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCESS (VREDUCESS-128-1)
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1)
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1)
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1)
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1)
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PD (VRSQRT14PD-128-1)
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PD (VRSQRT14PD-256-1)
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PS (VRSQRT14PS-128-1)
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PS (VRSQRT14PS-256-1)
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPD (VSCALEFPD-128-1)
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPD (VSCALEFPD-256-1)
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPS (VSCALEFPS-128-1)
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPS (VSCALEFPS-256-1)
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPD (VSCATTERDPD-128-1)
|
|
{
|
|
ICLASS: VSCATTERDPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPD (VSCATTERDPD-256-1)
|
|
{
|
|
ICLASS: VSCATTERDPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPS (VSCATTERDPS-128-1)
|
|
{
|
|
ICLASS: VSCATTERDPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPS (VSCATTERDPS-256-1)
|
|
{
|
|
ICLASS: VSCATTERDPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPD (VSCATTERQPD-128-1)
|
|
{
|
|
ICLASS: VSCATTERQPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPD (VSCATTERQPD-256-1)
|
|
{
|
|
ICLASS: VSCATTERQPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPS (VSCATTERQPS-128-1)
|
|
{
|
|
ICLASS: VSCATTERQPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPS (VSCATTERQPS-256-1)
|
|
{
|
|
ICLASS: VSCATTERQPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1)
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1)
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1)
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1)
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPD (VSHUFPD-128-1)
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPD (VSHUFPD-256-1)
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPS (VSHUFPS-128-1)
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPS (VSHUFPS-256-1)
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPD (VSQRTPD-128-1)
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPD (VSQRTPD-256-1)
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPS (VSQRTPS-128-1)
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPS (VSQRTPS-256-1)
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPD (VSUBPD-128-1)
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPD (VSUBPD-256-1)
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPS (VSUBPS-128-1)
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPS (VSUBPS-256-1)
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPD (VUNPCKHPD-128-1)
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPD (VUNPCKHPD-256-1)
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPS (VUNPCKHPS-128-1)
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPS (VUNPCKHPS-256-1)
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPD (VUNPCKLPD-128-1)
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPD (VUNPCKLPD-256-1)
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPS (VUNPCKLPS-128-1)
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPS (VUNPCKLPS-256-1)
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-128-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-256-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-512-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-128-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-256-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-512-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING KADDB (KADDB-256-1)
|
|
{
|
|
ICLASS: KADDB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDD (KADDD-256-1)
|
|
{
|
|
ICLASS: KADDD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDQ (KADDQ-256-1)
|
|
{
|
|
ICLASS: KADDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDW (KADDW-256-1)
|
|
{
|
|
ICLASS: KADDW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDB (KANDB-256-1)
|
|
{
|
|
ICLASS: KANDB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDD (KANDD-256-1)
|
|
{
|
|
ICLASS: KANDD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDNB (KANDNB-256-1)
|
|
{
|
|
ICLASS: KANDNB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDND (KANDND-256-1)
|
|
{
|
|
ICLASS: KANDND
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDNQ (KANDNQ-256-1)
|
|
{
|
|
ICLASS: KANDNQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDQ (KANDQ-256-1)
|
|
{
|
|
ICLASS: KANDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-1)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8
|
|
IFORM: KMOVB_MASKmskw_MASKu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8
|
|
IFORM: KMOVB_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-2)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR
|
|
OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVB_MEMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-3)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVB_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-4)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVB_GPR32u32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-1)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32
|
|
IFORM: KMOVD_MASKmskw_MASKu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32
|
|
IFORM: KMOVD_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-2)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVD_MEMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-3)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVD_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-4)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVD_GPR32u32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-1)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64
|
|
IFORM: KMOVQ_MASKmskw_MASKu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64
|
|
IFORM: KMOVQ_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-2)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVQ_MEMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-3)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64
|
|
IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-4)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTB (KNOTB-128-1)
|
|
{
|
|
ICLASS: KNOTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTD (KNOTD-128-1)
|
|
{
|
|
ICLASS: KNOTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTQ (KNOTQ-128-1)
|
|
{
|
|
ICLASS: KNOTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORB (KORB-256-1)
|
|
{
|
|
ICLASS: KORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORD (KORD-256-1)
|
|
{
|
|
ICLASS: KORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORQ (KORQ-256-1)
|
|
{
|
|
ICLASS: KORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTB (KORTESTB-128-1)
|
|
{
|
|
ICLASS: KORTESTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTD (KORTESTD-128-1)
|
|
{
|
|
ICLASS: KORTESTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTQ (KORTESTQ-128-1)
|
|
{
|
|
ICLASS: KORTESTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLB (KSHIFTLB-128-1)
|
|
{
|
|
ICLASS: KSHIFTLB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLD (KSHIFTLD-128-1)
|
|
{
|
|
ICLASS: KSHIFTLD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLQ (KSHIFTLQ-128-1)
|
|
{
|
|
ICLASS: KSHIFTLQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRB (KSHIFTRB-128-1)
|
|
{
|
|
ICLASS: KSHIFTRB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRD (KSHIFTRD-128-1)
|
|
{
|
|
ICLASS: KSHIFTRD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRQ (KSHIFTRQ-128-1)
|
|
{
|
|
ICLASS: KSHIFTRQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTB (KTESTB-128-1)
|
|
{
|
|
ICLASS: KTESTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTD (KTESTD-128-1)
|
|
{
|
|
ICLASS: KTESTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTQ (KTESTQ-128-1)
|
|
{
|
|
ICLASS: KTESTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTW (KTESTW-128-1)
|
|
{
|
|
ICLASS: KTESTW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTW_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KUNPCKDQ (KUNPCKDQ-256-1)
|
|
{
|
|
ICLASS: KUNPCKDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KUNPCKWD (KUNPCKWD-256-1)
|
|
{
|
|
ICLASS: KUNPCKWD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORB (KXNORB-256-1)
|
|
{
|
|
ICLASS: KXNORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORD (KXNORD-256-1)
|
|
{
|
|
ICLASS: KXNORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORQ (KXNORQ-256-1)
|
|
{
|
|
ICLASS: KXNORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORB (KXORB-256-1)
|
|
{
|
|
ICLASS: KXORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORD (KXORD-256-1)
|
|
{
|
|
ICLASS: KXORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORQ (KXORQ-256-1)
|
|
{
|
|
ICLASS: KXORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|