mirror of
https://github.com/RPCSX/xed.git
synced 2026-01-31 01:05:17 +01:00
175 lines
7.3 KiB
Plaintext
175 lines
7.3 KiB
Plaintext
#BEGIN_LEGAL
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#
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#Copyright (c) 2016 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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xed_reg_enum_t XMM_N3()::
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mode16 | OUTREG=XMM_N3_32()
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mode32 | OUTREG=XMM_N3_32()
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mode64 | OUTREG=XMM_N3_64()
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xed_reg_enum_t XMM_N3_32()::
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VEXDEST210=7 | OUTREG=XED_REG_XMM0
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VEXDEST210=6 | OUTREG=XED_REG_XMM1
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VEXDEST210=5 | OUTREG=XED_REG_XMM2
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VEXDEST210=4 | OUTREG=XED_REG_XMM3
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VEXDEST210=3 | OUTREG=XED_REG_XMM4
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VEXDEST210=2 | OUTREG=XED_REG_XMM5
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VEXDEST210=1 | OUTREG=XED_REG_XMM6
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VEXDEST210=0 | OUTREG=XED_REG_XMM7
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xed_reg_enum_t XMM_N3_64()::
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31
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xed_reg_enum_t YMM_N3()::
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mode16 | OUTREG=YMM_N3_32()
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mode32 | OUTREG=YMM_N3_32()
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mode64 | OUTREG=YMM_N3_64()
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xed_reg_enum_t YMM_N3_32()::
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VEXDEST210=7 | OUTREG=XED_REG_YMM0
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VEXDEST210=6 | OUTREG=XED_REG_YMM1
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VEXDEST210=5 | OUTREG=XED_REG_YMM2
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VEXDEST210=4 | OUTREG=XED_REG_YMM3
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VEXDEST210=3 | OUTREG=XED_REG_YMM4
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VEXDEST210=2 | OUTREG=XED_REG_YMM5
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VEXDEST210=1 | OUTREG=XED_REG_YMM6
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VEXDEST210=0 | OUTREG=XED_REG_YMM7
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xed_reg_enum_t YMM_N3_64()::
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31
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xed_reg_enum_t ZMM_N3()::
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mode16 | OUTREG=ZMM_N3_32()
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mode32 | OUTREG=ZMM_N3_32()
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mode64 | OUTREG=ZMM_N3_64()
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xed_reg_enum_t ZMM_N3_32()::
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VEXDEST210=7 | OUTREG=XED_REG_ZMM0
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VEXDEST210=6 | OUTREG=XED_REG_ZMM1
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VEXDEST210=5 | OUTREG=XED_REG_ZMM2
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VEXDEST210=4 | OUTREG=XED_REG_ZMM3
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VEXDEST210=3 | OUTREG=XED_REG_ZMM4
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VEXDEST210=2 | OUTREG=XED_REG_ZMM5
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VEXDEST210=1 | OUTREG=XED_REG_ZMM6
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VEXDEST210=0 | OUTREG=XED_REG_ZMM7
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xed_reg_enum_t ZMM_N3_64()::
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6
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VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14
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VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22
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VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30
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VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31
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