RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-01 07:30:31 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
0f320a4f3b
llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

35 lines
1.4 KiB
LLVM
Raw Normal View History

[Mips] Return false for isFPCloseToIncomingSP() On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237153 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 17:14:05 +00:00
; Check that register scavenging spill slot is close to $fp.
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265949 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-11 15:24:23 +00:00
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
[Mips] Return false for isFPCloseToIncomingSP() On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237153 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 17:14:05 +00:00
[mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 12:39:33 +00:00
; CHECK: sw ${{.*}}, 8($sp)
; CHECK: lw ${{.*}}, 8($sp)
[Mips] Return false for isFPCloseToIncomingSP() On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237153 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 17:14:05 +00:00
[mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 12:39:33 +00:00
define i32 @main(i32 signext %argc, i8** %argv) #0 {
[Mips] Return false for isFPCloseToIncomingSP() On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237153 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 17:14:05 +00:00
entry:
%retval = alloca i32, align 4
%argc.addr = alloca i32, align 4
%argv.addr = alloca i8**, align 4
%v0 = alloca <16 x i8>, align 16
%.compoundliteral = alloca <16 x i8>, align 16
%v1 = alloca <16 x i8>, align 16
%.compoundliteral1 = alloca <16 x i8>, align 16
%unused_variable = alloca [16384 x i32], align 4
%result = alloca <16 x i8>, align 16
store i32 0, i32* %retval
store i32 %argc, i32* %argc.addr, align 4
store i8** %argv, i8*** %argv.addr, align 4
store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
store <16 x i8> %0, <16 x i8>* %v0, align 16
store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
store <16 x i8> %1, <16 x i8>* %v1, align 16
%2 = load <16 x i8>, <16 x i8>* %v0, align 16
%3 = load <16 x i8>, <16 x i8>* %v1, align 16
%mul = mul <16 x i8> %2, %3
store <16 x i8> %mul, <16 x i8>* %result, align 16
ret i32 0
}
[mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 12:39:33 +00:00
Have 'optnone' respect the -fast-isel=false option. This is primarily useful for debugging optnone v. ISel issues. Differential Revision: http://reviews.llvm.org/D14792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254335 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-30 21:56:16 +00:00
attributes #0 = { noinline "no-frame-pointer-elim"="true" }
Reference in New Issue Copy Permalink