llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll

; RUN: llc < %s -march=arm -mcpu=arm1136jf-s
; Radar 7854640

define void @test() nounwind {
bb:
  br i1 undef, label %bb9, label %bb10

bb9:
  %tmp63 = bitcast <4 x float> zeroinitializer to i128
  %tmp64 = trunc i128 %tmp63 to i32
  br label %bb10

bb10:
  %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
  ret void
}
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8 2010-04-14 20:45:23 +00:00			`; RUN: llc < %s -march=arm -mcpu=arm1136jf-s`
			`; Radar 7854640`

Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8 2010-06-17 15:18:27 +00:00			`define void @test() nounwind {`
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8 2010-04-14 20:45:23 +00:00			`bb:`
			`br i1 undef, label %bb9, label %bb10`

			`bb9:`
			`%tmp63 = bitcast <4 x float> zeroinitializer to i128`
			`%tmp64 = trunc i128 %tmp63 to i32`
			`br label %bb10`

			`bb10:`
			`%0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]`
			`ret void`
			`}`